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  • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
  • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
  • B81C1/00222—Integrating an electronic processing unit with a micromechanical structure
  • B81C1/00238—Joining a substrate with an electronic processing unit and a substrate with a micromechanical structure
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  • B81—MICROSTRUCTURAL TECHNOLOGY
  • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
  • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
  • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
  • B81C1/00222—Integrating an electronic processing unit with a micromechanical structure
  • B81C1/00246—Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
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  • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
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  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
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  • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
  • H10P90/19—Preparing inhomogeneous wafers
  • H10P90/1904—Preparing vertically inhomogeneous wafers
  • H10P90/1906—Preparing SOI wafers
  • H10P90/1914—Preparing SOI wafers using bonding
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  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
  • H10W10/10—Isolation regions comprising dielectric materials
  • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
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  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
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  • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
  • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
  • H10W20/0234—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes that stop on pads or on electrodes
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  • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
  • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
  • H10W20/0242—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes from the back sides of the chips, wafers or substrates
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  • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
  • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
  • H10W20/0253—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising forming the through-semiconductor vias after stacking of the chips, wafers or substrates
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  • H10W20/00—Interconnections in chips, wafers or substrates
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  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
  • H10W20/211—Through-semiconductor vias, e.g. TSVs
  • H10W20/213—Cross-sectional shapes or dispositions
  • H10W20/2134—TSVs extending from the semiconductor wafer into back-end-of-line layers
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  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
  • H10W20/211—Through-semiconductor vias, e.g. TSVs
  • H10W20/218—Through-semiconductor vias, e.g. TSVs in silicon-on-insulator [SOI] wafers
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  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
  • H10W20/481—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes on the rear surfaces of the wafers or substrates
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B81—MICROSTRUCTURAL TECHNOLOGY
  • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
  • B81C2203/00—Forming microstructural systems
  • B81C2203/07—Integrating an electronic processing unit with a micromechanical structure
  • B81C2203/0707—Monolithic integration, i.e. the electronic processing unit is formed on or in the same substrate as the micromechanical structure
  • B81C2203/0728—Pre-CMOS, i.e. forming the micromechanical structure before the CMOS circuit
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B81—MICROSTRUCTURAL TECHNOLOGY
  • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
  • B81C2203/00—Forming microstructural systems
  • B81C2203/07—Integrating an electronic processing unit with a micromechanical structure
  • B81C2203/0707—Monolithic integration, i.e. the electronic processing unit is formed on or in the same substrate as the micromechanical structure
  • B81C2203/0735—Post-CMOS, i.e. forming the micromechanical structure after the CMOS circuit
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B81—MICROSTRUCTURAL TECHNOLOGY
  • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
  • B81C2203/00—Forming microstructural systems
  • B81C2203/07—Integrating an electronic processing unit with a micromechanical structure
  • B81C2203/0707—Monolithic integration, i.e. the electronic processing unit is formed on or in the same substrate as the micromechanical structure
  • B81C2203/0757—Topology for facilitating the monolithic integration
  • B81C2203/0778—Topology for facilitating the monolithic integration not provided for in B81C2203/0764 - B81C2203/0771
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B81—MICROSTRUCTURAL TECHNOLOGY
  • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
  • B81C2203/00—Forming microstructural systems
  • B81C2203/07—Integrating an electronic processing unit with a micromechanical structure
  • B81C2203/0785—Transfer and j oin technology, i.e. forming the electronic processing unit and the micromechanical structure on separate substrates and joining the substrates
  • B81C2203/0792—Forming interconnections between the electronic processing unit and the micromechanical structure
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  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
  • H10D84/02—Manufacture or treatment characterised by using material-based technologies
  • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
  • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
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  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D88/00—Three-dimensional [3D] integrated devices
  • H10D88/01—Manufacture or treatment
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  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/851—Dispositions of multiple connectors or interconnections
  • H10W72/874—On different surfaces
  • H10W72/884—Die-attach connectors and bond wires

Definitions

• Integrated circuits (ICs) vertical integration techniques utilize multiple active/device layers on a single die. These techniques allows for a significant increase in the number of components per IC without increasing the required die area. The die thickness may be increased, but it is the die area that is usually more of a limiting design consideration, and the overall result can be a reduced total die volume and IC package weight.
• the development of vertical integration techniques is, thus, of paramount importance for technologies in which electronic devices must be relatively small and lightweight, e.g. cell/smart phones, notebook/tablet PCs, etc.
• Embodiments of the present invention involve a semiconductor structure with multiple active layers formed from an SOI wafer.
• the typical SOI wafer has an insulator layer (e.g. a buried oxide) between a substrate layer and a semiconductor layer.
• a first active layer is formed in and on the semiconductor layer.
• a second active layer is formed in and on the substrate layer.
• a handle wafer is bonded to the SOI wafer, and the substrate layer is thinned before forming the second active layer.
• a third active layer may be formed in the substrate of the handle wafer.
• the first and second active layers include a MEMS device in one of these layers and a CMOS device in the other.
• FIG. 1 is a simplified cross-section of a semiconductor structure
• FIGs. 2-5 are simplified cross-sections of semiconductor structures at intermediate stages in the fabrication of the semiconductor structure shown in Fig. 1 in accordance with embodiments of the present invention.
• FIG. 6 is a simplified cross-section of an alternative semiconductor structure incorporating an embodiment of the present invention.
• the present invention achieves vertical integration of active layers in a monolithically formed IC semiconductor structure (e.g. semiconductor structure 100 of Fig. 1 ) using a semiconductor-on-insulator (SOI) wafer.
• SOI semiconductor-on-insulator
• the SOI wafer is inverted, and a second active layer is formed in and on the underlying substrate, as described in more detail below.
• This technique generally enables a relatively compact vertical integration of a variety of types of active layers with a significant reduction of die area and an increase in die per wafer.
• the multiple active layers may enable the integration of CMOS devices in the same monolithic semiconductor structure with other types of devices, such as film bulk acoustic resonators, surface acoustic wave devices, film plate acoustic resonators (FPAR), acoustic filters, RF switches, passive components, and other microelectromechanical systems (MEMS) devices.
• CMOS devices in the same monolithic semiconductor structure with other types of devices, such as film bulk acoustic resonators, surface acoustic wave devices, film plate acoustic resonators (FPAR), acoustic filters, RF switches, passive components, and other microelectromechanical systems (MEMS) devices.
• MEMS microelectromechanical systems
• the semiconductor structure 100 generally has an inverted SOI wafer 101 bonded with a handle wafer 102.
• the SOI wafer 1 01 generally has two active layers 103 and 104 on both opposite sides (i.e. top/bottom or upper/lower) of an insulator layer 105 (e.g. a buried oxide).
• the first active layer 103 is formed in and on the conventional semiconductor layer 106 of the SOI wafer 101 .
• the second active layer 104 is formed in and on the underlying conventional substrate layer 107 of the SOI wafer 101 , or the portion that remains after thinning the original substrate layer 107.
• the components that are shown within the active layers 103 and 104 are provided for illustrative purposes only and do not necessarily depict limitations on the present invention.
• the SOI wafer 101 generally includes interconnect layers 108 and 109, through which electrical connections may be made between the various components of the active layers 103 and 104.
• the components that are shown within the interconnect layers 108 and 109 are provided for illustrative purposes only and do not necessarily depict limitations on the present invention.
• one of the active layers e.g. 104 may include an RF/MEMS device 1 1 0 (among other components), and the other active layer (e.g. 103) may include CMOS devices 1 1 1 (among other components) for circuitry that controls operation of the MEMS device 1 10.
• the handle wafer 1 02 generally includes a handle substrate layer 1 12, a bonding layer 1 13, and an optional trap rich layer (TRL) 1 14.
• the handle wafer 102 is bonded to a top surface of the SOI wafer 1 01 (inverted as shown) after the formation of the first active layer 103 and the first interconnect layer 108.
• the handle wafer 102 is generally used to provide structural stability for the semiconductor structure 1 00 while processing the substrate layer 1 07 of the SOI wafer 101 and the formation of the second active layer 104 and second interconnect layer 1 09.
• the structural stability aspect enables the substrate layer 1 07 of the SOI wafer 101 to be thinned before formation of the second active layer 104.
• the first and second active layers 103 and 104 and the first and second interconnect layers 108 and 109 are described herein as being built up both into and onto the semiconductor layer 106 and substrate layer 1 07, respectively.
• This type of fabrication technique is known as a "monolithic" style of fabrication.
• a different technique of active layer fabrication is known as a "layer transfer" style, which involves the formation of the active layers in and on multiple separate wafers, followed by transferring one of the active layers onto the wafer of the other.
• the monolithic style for example, generally requires serial processing for each of the manufacturing steps; whereas, the layer transfer style allows for parallel processing of the multiple wafers, thereby potentially reducing the overall time to manufacture the final semiconductor structure.
• the monolithic style generally does not require the expense of multiple substrates, does not require wafer bonding or wafer cleavage steps, does not require significant grinding or etching back steps, does not require precision wafer-aligning for bonding, and does not require a capital investment for fabrication machines that can perform the wafer-bonding-related steps.
• Some general exceptions to these advantages may occur in some situations, such as the wafer bonding of the handle wafer 102.
• the handle wafer 102 does not have additional circuitry prior to bonding, there is no need for a high-precision alignment of the wafers 1 01 and 1 02.
• the bonding step for the handle wafer 102 can be relatively simple and cheap compared to approaches where multiple active layers on multiple wafers are integrated via a layer transfer process.
• FIG. 2-5 A simplified example manufacturing process, according to some embodiments for forming the semiconductor structure 1 00 of Fig. 1 , is shown by Figs. 2-5.
• the process generally starts with the SOI wafer 1 01 having the insulator layer 1 05 (e.g. a buried oxide) between the semiconductor layer 106 and substrate layer 1 07 as shown in Fig. 2.
• the first active layer 103 is then formed into and onto the "top" or "upper" surface of the semiconductor layer 106 using mostly
• the SOI wafer 101 may include a TRL formed as disclosed in U.S. Pat. App. / filed on the same day as the present application with attorney docket number IOSEP009CIP4. The disclosure of which is incorporated by reference herein in its entirety.
• the first interconnect layer 108 is then formed on the "top” or “upper” surface of the first active layer 103. Since the SOI wafer 101 is subsequently inverted from the orientation shown in Fig. 2, for the benefit of consistency in description, the portion of the SOI wafer 101 referred to as the "top” (or “upper” or “front") with respect to Fig. 2 will continue to be referred to herein as the “top” (or “upper” or “front"), and the portion of the SOI wafer 1 01 referred to as the "bottom” (or “lower” or “back") will continue to be referred to herein as the “bottom” (or “lower” or “back”), even after the SOI wafer 1 01 has been inverted. Therefore, in Fig.
• the "top” of the overall semiconductor structure 100 is considered the same as the “bottom” of the SOI wafer 101 . Also, when the top of the overall semiconductor structure 1 00 is being processed, it is considered “back side” processing for the SOI wafer 101 .
• the added material or layers are considered to become part of the wafer.
• the removed material or layers are no longer considered to be part of the wafer. Therefore, for example, the element designated as the SOI wafer 101 or the handle wafer 102 in the Figs, may increase or decrease in size or thickness as it is being processed.
• a surface referred to as the "top surface” or “bottom surface” of a wafer may change during processing when material or layers are added to or removed from the wafer.
• the first active layer 103 is formed by front side processing in and on the top surface of the SOI wafer 101 , but the material that is placed on the SOI wafer 101 creates a new top surface.
• the first interconnect layer 1 08 is formed on the new top surface. Then when the handle wafer 102 is bonded to the SOI wafer 101 , it is bonded to yet another new top surface thereof.
• TSVs semiconductor vias
• the simplified example manufacturing process continues with the formation of the handle wafer 102 as shown in Fig. 3.
• the bonding layer 1 13, and the TRL 1 14 are formed on the handle substrate layer 1 12.
• the handle substrate layer 1 12 is generally thick enough to provide structural stability or strength to the semiconductor structure 100.
• the TRL 1 14 is formed by any appropriate technique, e.g. implanting ions of high energy particles (e.g. a noble gas, Silicon, Oxygen, Carbon, Germanium, etc.), irradiating the handle wafer 1 02, depositing high resistivity material, damaging the exposed surfaces of the handle substrate layer 1 12, etc.
• the TRL 1 14 is formed as disclosed in U.S. Pat.
• the bonding layer 1 13 may be any appropriate material that can be bonded to the material at the top surface of the SOI wafer 101 . Other bonding techniques for other embodiments with or without the bonding layer 1 13 may also be used. In some embodiments, the bonding layer 1 13 may be combined with the TRL 1 14. In some embodiments, the entire handle wafer 102 will be the TRL 1 14.
• SOI wafer 101 of Fig. 2 is bonded to the handle wafer 102 of Fig. 3.
• the SOI wafer 101 is inverted in Fig. 4 relative to its orientation in Fig. 2.
• the surface of the SOI wafer 101 to which the handle wafer 1 02 is bonded is the top surface, which is opposite the insulator layer from the substrate layer 1 07. This step leaves the bottom or back side of the SOI wafer 101 exposed for processing.
• the handle wafer 102 provides structural stability during this processing.
• a portion of the substrate layer 107 is removed, thereby thinning the substrate layer 107, as shown in Fig. 5.
• the remaining portion of the substrate layer 107 is sufficiently thick to be used as a new semiconductor layer for the formation of a second active layer, such as the second active layer 104 in Fig. 1 .
• a cavity 1 15 may be formed in the substrate layer 107.
• the cavity 1 15 at least partly surrounds the MEMS device 1 10.
• the cavity 1 15 may be formed by any appropriate technique, e.g. orientation dependent etch, anisotropic etch, isotropic etch, etc.
• the cavity 1 15 provides isolation, improved thermal performance and/or a material for release of the MEMS device 1 1 0.
• a fill material is then placed inside the cavity 1 15 and planarized, e.g. by CMP.
• the fill material may be selective to the material that forms second active layer 104, so the fill material can be removed later to release the MEMS device 1 10.
• the cavity 1 15 may extend into the insulator layer 105, so the fill material may have to be selective to the insulator material.
• the second active layer 104 is then formed in and on the remaining portion of the substrate layer 1 07.
• fabrication of the MEMS device 1 10 within the second active layer 104 is done in reverse order from the conventional process. This reverse process may aid in simplifying the bonding and interconnection for low temperatures (e.g. less than 200 ° C ).
• the second interconnect layer 109 is then formed on the second active layer 1 04 (and through the two active layers 1 03 and 104) to produce the
• some of the electrical connections between the two active layers 103 and 1 04 may be formed with a buried contact, e.g. forming TSVs early in the overall fabrication process. Electrical connection pads 1 16 and a redistribution layer (not shown) may also be formed for external electrical connections. Electrical interconnects, e.g. TSVs, that pass through more than one layer may provide electrical connections between any two or more components in the two interconnect layers 108 and 109 and the active layers 103 and 104, e.g. a TSV interconnect between metallization in the
• interconnect layers 108 and 109 or a TSV interconnect between metallization in one of the interconnect layers 1 08 or 109 and an active device (e.g. source, drain or gate region) in one of the active layers 108 or 1 09.
• an active device e.g. source, drain or gate region
• FIG. 6 An alternative semiconductor structure 200 incorporating an alternative embodiment of the present invention is shown in Fig. 6.
• many of the elements are similar to those of the embodiment shown in Fig. 1 , because this embodiment may be built up from the semiconductor structure 100.
• a portion of the handle substrate layer 1 12 is removed, thereby thinning the handle substrate layer 1 12.
• the remaining portion of the handle substrate layer 1 12 is sufficiently thick to be used as a new semiconductor layer for the formation of a third active layer 201 , thereby monolithically forming yet another active layer.
• another handle wafer (not shown) may be bonded to the
• semiconductor structure 1 00 to provide structural stability during subsequent processing if the existing thickness of the semiconductor structure 100 does not provide sufficient structural stability.
• a MEMS device 202 is formed in the third active layer 201 , such that a cavity 203 may need to be formed in the handle substrate layer 1 12.
• the cavity 203 may be formed by any appropriate technique, e.g. orientation dependent etch, anisotropic etch, isotropic etch, etc.
• the cavity 203 provides isolation, improved thermal performance and/or a material for release of the MEMS device 202.
• a fill material is then placed inside the cavity 203 and planarized, e.g. by CMP.
• the fill material may be selective to the material of third active layer 201 , so the fill material can be removed later to release the MEMS device 202.
• the third active layer 201 is then formed in and on the remaining portion of the handle substrate layer 1 12.
• a third interconnect layer 204 is then formed on the third active layer 201 (and through to the first active layer 103) to produce the semiconductor structure 200 shown in Fig. 6.
• some of the electrical connections between the first and third active layers 103 and 201 may be formed with a buried contact, e.g. forming TSVs early in the overall fabrication process.
• the third active layer 201 may also be connected to the second active layer 1 04 via contacts between those layers and a common circuit node in interconnect layer 1 08.
• Electrical connection pads (not shown) and a redistribution layer (not shown) may also be formed for external electrical connections on the bottom side of the alternative semiconductor structure 200.
• electrical connection pads 1 16 and a redistribution layer may also be formed for external electrical

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• 2014
  • 2014-08-07 US US14/454,262 patent/US20160043108A1/en not_active Abandoned
• 2015
  • 2015-07-23 CN CN201580042310.2A patent/CN106716620B/zh not_active Expired - Fee Related
  • 2015-07-23 EP EP15829048.6A patent/EP3180802B1/en active Active
  • 2015-07-23 JP JP2017505838A patent/JP2017526178A/ja active Pending
  • 2015-07-23 KR KR1020177002990A patent/KR20170040226A/ko not_active Withdrawn
  • 2015-07-23 WO PCT/US2015/041769 patent/WO2016022302A1/en not_active Ceased
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