WO2016019908A1 - 一种快速启动数字输出缓冲器及其控制方法 - Google Patents

一种快速启动数字输出缓冲器及其控制方法 Download PDF

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Publication number
WO2016019908A1
WO2016019908A1 PCT/CN2015/086398 CN2015086398W WO2016019908A1 WO 2016019908 A1 WO2016019908 A1 WO 2016019908A1 CN 2015086398 W CN2015086398 W CN 2015086398W WO 2016019908 A1 WO2016019908 A1 WO 2016019908A1
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switch tube
switch
switched capacitor
capacitor array
voltage
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PCT/CN2015/086398
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English (en)
French (fr)
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陈锋
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王玮冰
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements

Definitions

  • the present invention relates to the field of digital output buffer technologies, and in particular, to a fast start digital output buffer and a control method thereof.
  • the sensor With the rise of sensors, the transmission of wired signals between sensors and hosts has become more complex.
  • the sensor In some ultra-low power applications, the sensor is in standby for most of the time, and only one sensor and data output is completed in a very short time.
  • the sensor outputs data through a digital output buffer.
  • the digital output buffer consumes a large amount of power when it buffers the output of the data. Therefore, it is necessary to design a digital output buffer that reduces power consumption.
  • Chinese Patent Publication No. CN103269217 published on Aug. 28, 2013, the name of the invention is an output buffer
  • the application discloses an output buffer comprising first and second transistors and a self-biasing circuit, first The transistor has a control electrode, an input electrode coupled to the output end, and an output electrode, and the second transistor has a control electrode, an input electrode coupled to the output electrode of the first transistor, and an output electrode coupled to the reference voltage, and the self-bias circuit is coupled to the output end And a control electrode of the first transistor.
  • the downside is that the output buffer consumes a lot of power.
  • the object of the present invention is to overcome the technical problem of large power consumption of the existing digital output buffer, and to provide a fast start digital output buffer capable of reducing power consumption and a control method thereof.
  • a fast-start digital output buffer of the present invention includes a timing generator, a capacitance mismatch detector, a capacitor array controller, a switched capacitor array, a current detector, an inductor L, a load capacitor CL, and a first switch SW1
  • the first conducting end of the tube SW4 is electrically connected to the first conducting end of the fifth switching tube SW5, the second conducting end of the fourth switching tube SW4 is electrically connected to the power source VDD, and the second conducting end of the fifth switching tube SW5 is electrically connected.
  • the second conduction end of the third switch tube SW3 is electrically connected to the end of the inductor L.
  • the other end of the inductor L and the upper plate of the load capacitor CL and the first switch tube SW1 are electrically connected.
  • the first conduction end, the first conduction end of the second switch tube SW2 and the detection end of the capacitance mismatch detector are electrically connected, and the second plate of the load capacitance CL and the second switch tube SW2 are electrically connected.
  • the terminals are both grounded, and the second conductive end of the first switch SW1 is electrically connected to the power source VDD.
  • the output end of the capacitive mismatch detector is electrically connected to the input end of the capacitor array controller, and the capacitor array controller is further electrically connected to the control end of the switched capacitor array, and the control end of the first switch tube SW1 and the second switch tube SW2 a control end, a control end of the third switch SW3, a control end of the fourth switch SW4, a control end of the fifth switch SW5, a capacitance mismatch detector, and a current detector are respectively electrically connected to the timing generator,
  • the two detecting ends of the current detector are respectively electrically connected to the first conducting end and the second conducting end of the third switching transistor SW3, and the input end of the timing generator is a signal input end of the digital output buffer,
  • the upper plate of the load capacitor CL is the signal output of the digital output buffer.
  • the timing generator, the switched capacitor array, the inductor L, the load capacitor CL, the first switch tube SW1, the second switch tube SW2, the third switch tube SW3, the fourth switch tube SW4, and the fifth switch tube SW5 The main circuit that constitutes the fast-start digital output buffer, its function is Controlling the LC oscillation by controlling the first switching transistor SW1, the second switching transistor SW2, the third switching transistor SW3, the fourth switching transistor SW4, and the fifth switching transistor SW5, the charge on the switched capacitor array is non-destructively moved according to the input signal Din Load capacitor CL, and strengthen the upper plate of the load capacitor CL to the voltage of the power supply VDD, or transfer the charge on the CL to the switched capacitor array according to the input signal Din, and put the upper plate of the load capacitor CL Strengthen to the ground, so that the output Dout can realize the conversion from low level to high level and strengthen and convert from high level to low level, and realize the data lossless buffer drive from Din to Dout.
  • the first switch tube SW1 and the second switch tube SW2 enhance the level of the digital output port Dout, and maintain Dout at a low level or a low level of low resistance.
  • the fourth switch tube SW4 and the fifth switch tube SW5 enhance the level of the first conductive end of the switched capacitor array, and maintain the first conductive end of the switched capacitor array at a low resistance high level or a low resistance low level Level.
  • the fast start digital output buffer operation is divided into four stages of T1, T2, T3 and T4.
  • the timing generator controls the first switching transistor SW1, the second switching transistor SW2, the third switching transistor SW3, the fourth switching transistor SW4, and the fifth switching transistor SW5 to operate.
  • the T1 interval is entered, and the third switch tube SW3 is turned on, the first switch tube SW1, the second switch tube SW2, the fourth switch tube SW4, and the fifth switch tube SW5. Disconnected, the charge stored in the switched capacitor array is supplied to the inductor L via the third switch SW3. Since the inductor L and the load capacitor CL form a series resonant circuit, the load capacitor CL is charged with voltage due to resonance, and the voltage of the upper plate can be Freely oscillate to VDD. In the T1 interval, the current in the inductor L increases from 0 to the positive direction. After reaching the peak value, the voltage of the plate on the load capacitor CL oscillates to the highest point, and the current in the inductor L returns to zero.
  • the current in the inductor L returns to 0, which is the end point of the T1 interval, and is the starting point of the T2 interval.
  • the first switch tube SW1 and the fifth switch tube SW5 are turned on, the second switch tube SW2, the third switch tube SW3 and the fourth switch tube SW4 are disconnected, and the upper plate of the load capacitor CL is boosted to VDD via the first switch tube SW1.
  • the voltage of the upper plate of the load capacitor CL reaches VDD, the output port Dout outputs a high level, and the first conduction end of the switched capacitor array is strengthened to GND via the fifth switch SW5, and the first conduction end of the switched capacitor array is maintained. At low level.
  • the T3 section When the input signal Din transitions from a high level to a low level, the T3 section is entered, and the third switch tube SW3 is turned on, the first switch tube SW1, the second switch tube SW2, the fourth switch tube SW4, and the fifth switch tube SW5. disconnect.
  • the charge on the load capacitor CL passes through the inductor L, and the third switch SW3 is recovered by the switched capacitor array. In this process, the voltage on the load capacitor CL oscillates freely from VDD to 0, and the current in the inductor L increases from 0 to the maximum point and then returns to 0.
  • the current in the inductor L returns to 0, which is the end point of the T3 interval, and is the starting point of the T4 interval.
  • the second switch tube SW2 and the fourth switch tube SW4 are turned on, and the first switch tube SW1, the third switch tube SW3, and the fifth switch tube SW5 are turned off.
  • the upper plate of the load capacitor CL is reinforced to GND via the second switch SW2, the output port Dout outputs a low level, and the first conductive end of the switched capacitor array is boosted to VDD via the fourth switch SW4, and the first lead of the switched capacitor array
  • the terminal is maintained at a high level.
  • the current detector provides negative feedback to the main circuit. Since the T1 phase and the T3 phase need to end when the current in the inductor L just becomes 0, the power consumption is reduced, and the circuit noise is generated by avoiding the high-frequency oscillation of the residual current in the inductor L. It is therefore important that the timing generator controls the duration of the T1 phase and the T3 phase.
  • the durations of the T1 phase and the T3 phase are the same, both being time T.
  • the initial value of the time T is preset in the timing generator.
  • the timing generator controls the third switch SW3 to turn on T time, that is, when the third switch SW3 is turned off, the current detector detects the residual current in the inductor L.
  • the Dcmp value is output to the timing generator, the Dcmp value reflects the direction of the residual current, or the Dcmp value reflects the direction and magnitude of the residual current, and the timing generator adjusts the value of the time T according to the received Dcmp value.
  • the third switch SW3 When the third switch SW3 is turned off, if the current detector detects that residual current flows from the inductor L to the load capacitor CL, the time T value increases, and if the current detector detects that residual current flows from the load capacitor CL to the inductor L, Then the time T value decreases.
  • the capacitor mismatch detector and the capacitor array controller form an auxiliary control circuit for the fast-start switching capacitor array.
  • the timing generator controls the third switching transistor SW3 to turn on T time, that is, when the third switching transistor SW3 is turned off, the capacitor is mismatched before the first switching transistor SW1 and the fifth switching transistor SW5 are turned on.
  • the detector detects the voltage V of the plate on the load capacitor CL, compares the voltage V with the voltage of the power supply VDD, and sends the comparison result to the capacitor array controller, and the capacitor array controller controls each switch in the switched capacitor array according to the received data.
  • the capacitor circuit is turned on and off.
  • the on/off state of each switched capacitor circuit in the switched capacitor array is unchanged; if the voltage V is less than the power supply VDD voltage, the on/off state of the corresponding switched capacitor circuit in the switched capacitor array is adjusted, so that the switched capacitor The effective capacitance Ca of the array is increased; if the voltage V is greater than the power supply VDD voltage, the on-off state of the corresponding switched capacitor circuit in the switched capacitor array is adjusted, so that the effective capacitance Ca of the switched capacitor array is reduced.
  • the capacitor mismatch detects the voltage V of the plate on the load capacitor CL, and compares the voltage V and 0. The size is sent to the capacitor array controller, and the capacitor array controller controls the turn-on and turn-off of each of the switched capacitor circuits in the switched capacitor array based on the received data.
  • the on/off state of each switched capacitor circuit in the switched capacitor array is unchanged; if the voltage V is less than 0, the on/off state of the corresponding switched capacitor circuit in the switched capacitor array is adjusted, so that the effective capacitance of the switched capacitor array The capacity Ca is decreased; if the voltage V is greater than 0, the on-off state of the corresponding switched capacitor circuit in the switched capacitor array is adjusted, so that the effective capacitance Ca of the switched capacitor array is increased.
  • the effective capacitance Ca of the switched capacitor array is matched with the capacitance of the load capacitor CL, so that a large storage capacitor is not required, and no huge storage capacitor is needed for circuit establishment.
  • Long-term charging saves power and allows the digital output buffer to start up quickly due to less charging time on the switched capacitor array.
  • the capacitance mismatch detector comprises a data processing module and a voltage detecting module, wherein the detecting end of the voltage detecting module is electrically connected to the upper plate of the load capacitor CL, and the data output end of the voltage detecting module and the data processing The input terminals of the module are electrically connected, and the data processing module is also electrically connected to the timing generator and the capacitor array controller, respectively.
  • the voltage detecting module detects the voltage of the plate on the load capacitor CL, and the data processing module processes the data detected by the voltage detecting module, and exchanges information with the timing generator and the capacitor array controller.
  • the switched capacitor array comprises a plurality of parallel switched capacitor circuits, the switched capacitor circuit comprising a capacitor and a switch module controlled by a capacitor array controller, the capacitor and the switch module being connected in series, the control terminal of the switch module Electrically connected to the capacitor array controller.
  • the capacitor array controller controls the switched capacitor power through a switch module in each switched capacitor circuit
  • the on and off of the circuit adjusts the effective capacitance Ca of the switched capacitor array by controlling the turn-on and turn-off of the respective switched capacitor circuits.
  • a method for controlling a fast-start digital output buffer of the present invention comprises the following steps:
  • step S1 the timing generator reads the input signal Din, when the input signal Din jumps from a low level to a high level, then step S2 is performed, when the input signal Din jumps from a high level to a low level, then step S4 is performed;
  • the timing generator controls the third switch tube SW3 to turn on T time, and controls the first switch tube SW1, the second switch tube SW2, the fourth switch tube SW4, and the fifth switch tube SW5 to be turned off for T time;
  • the timing generator controls the second switch tube SW2, the third switch tube SW3 and the fourth switch tube SW4 to be disconnected, and the control capacitor mismatch detector detects the load capacitor CL upper plate in the third switch tube SW3
  • the voltage V at the time of disconnection after the detection is completed, the timing generator controls the first switch tube SW1 and the fifth switch tube SW5 to be turned on, the capacitance mismatch detector compares the voltage V with the power supply VDD voltage, and sends the comparison result to
  • the capacitor array controller controls the on and off of each switch capacitor circuit in the switched capacitor array according to the received data, so that the effective capacitance Ca of the switched capacitor array matches the capacitance of the load capacitor CL;
  • the timing generator controls the third switch tube SW3 to be turned on for T time, and controls the first switch tube SW1, the second switch tube SW2, the fourth switch tube SW4, and the fifth switch tube SW5 to be turned off for T time;
  • the timing controller controls the first switch tube SW1, the third switch tube SW3, and the fifth switch tube SW5 to be turned off, and controls the second switch tube SW2 and the fourth switch tube SW4 to be turned on;
  • the initial value of the time T is preset in the timing generator.
  • the timing generator controls the third switch SW3 to turn on T time, that is, when the third switch SW3 is turned off, the current detector detects the residual current in the inductor L. , output Dcmp value to the timing generator, Dcmp value reacts residual electricity The direction of the flow, or the Dcmp value reflects the direction and magnitude of the residual current, and the timing generator adjusts the value of the time T according to the received Dcmp value.
  • the method for adjusting the value of the time T according to the received Dcmp value by the timing generator comprises the following steps: the timing generator is provided with a Dsgm value corresponding to the time value, and the time value corresponding to the initial value of the Dsgm value is time The initial value of T, the timing generator integrates the Dsgm value and the received Dcmp value to obtain the latest Dsgm value, and the time value corresponding to the latest Dsgm value is taken as the latest value of the time T.
  • the method for controlling the on and off of each switched capacitor circuit in the switched capacitor array according to the received data in the step S3 comprises the following steps: if the voltage V is equal to the power supply VDD voltage, the switched capacitor array The on/off state of each switched capacitor circuit is unchanged; if the voltage V is less than the power supply VDD voltage, the on/off state of the corresponding switched capacitor circuit in the switched capacitor array is adjusted, so that the effective capacitance Ca of the switched capacitor array is increased; if the voltage V is When the voltage is greater than the power supply VDD, the on/off state of the corresponding switched capacitor circuit in the switched capacitor array is adjusted, so that the effective capacitance Ca of the switched capacitor array is reduced.
  • the step S5 comprises the following steps: at the end of the T time, the timing controller controls the first switch tube SW1, the third switch tube SW3 and the fifth switch tube SW5 to be disconnected, and the capacitance mismatch detector detects the load capacitance CL.
  • the method for controlling the on and off of each switched capacitor circuit in the switched capacitor array according to the received data in the step S5 comprises the following steps: if the voltage V is equal to 0, each of the switched capacitor arrays The on/off state of the switched capacitor circuit is unchanged; if the voltage V is less than 0, the on/off state of the corresponding switched capacitor circuit in the switched capacitor array is adjusted, so that the effective capacitance Ca of the switched capacitor array is reduced; if the voltage V is greater than 0, then Adjusting the on/off state of the corresponding switched capacitor circuit in the switched capacitor array increases the effective capacitance Ca of the switched capacitor array.
  • the substantial effects of the present invention are: (1) effectively reducing the power consumption of the digital output buffer. (2) Start fast, establish a stable transmission path at once, and have extremely fast response capability to changes in load capacitance. (3) Avoid circuit noise caused by high-frequency oscillation of residual current in inductor L. (4) Capacitance matching technology is adopted, which is effective from the first data transmitted. If a large capacitor is used, the integrity of the data will be destroyed during the establishment process, and the data will be valid for a long time. . (5) Since the capacitances in the switched capacitor array are small capacitors, it is convenient to integrate the switched capacitor array into the chip.
  • FIG. 1 is a block diagram of a circuit principle connection of the present invention
  • FIG. 2 is a block diagram of a circuit principle connection of a capacitance mismatch detector
  • timing generator 1, capacitor mismatch detector, 3, capacitor array controller, 4, switched capacitor array, 5, current detector, 6, data processing module, 7, voltage detection module, 8, Capacitor, 9, switch module.
  • a fast-start digital output buffer of the present invention includes a timing generator 1, a capacitance mismatch detector 2, a capacitor array controller 3, a switched capacitor array 4, a current detector 5,
  • the first conduction end of the switch tube SW3, the first conduction end of the fourth switch tube SW4 and the first conduction end of the fifth switch tube SW5 are electrically connected, and the second conduction end of the fourth switch tube SW4 is connected to the power supply VDD.
  • the second conductive end of the fifth switch SW5 and the second conductive end of the switched capacitor array 4 are grounded, and the second conductive end of the third switch SW3 is electrically connected to one end of the inductor L, and the other end of the inductor L Connected to the upper plate of the load capacitor CL, the first conduction end of the first switch tube SW1, the first conduction end of the second switch tube SW2, and the detection end of the capacitance mismatch detector 2, under the load capacitance CL
  • the second conductive end of the second switch tube and the second switch tube SW2 are grounded, and the second conductive end of the first switch tube SW1 is electrically connected VDD is electrically connected, the output end of the capacitor mismatch detector 2 is electrically connected to the input end of the capacitor array controller 3, and the capacitor array controller 3 is also electrically connected to the control end of the switched capacitor array 4, and the control end of the first switch tube SW1 a control end of the second switch SW2, a control end of the third switch SW3, a control end of the fourth switch SW4, a
  • the capacitance mismatch detector 2 includes a data processing module 6 and a voltage detecting module 7.
  • the detecting end of the voltage detecting module 7 is electrically connected to the upper plate of the load capacitor CL, and the data output terminal of the voltage detecting module 7 is The input terminals of the data processing module 6 are electrically connected, and the data processing module 6 is also electrically connected to the timing generator 1 and the capacitor array controller 3, respectively.
  • the data processing module 6 is a bidirectional integrator controlled by the timing generator 1, the voltage detecting module 7 detects the voltage of the plate on the load capacitor CL, and the data processing module 6 processes the data detected by the voltage detecting module 7 and processes the result. Send to capacitor array controller 3.
  • the switched capacitor array 4 includes a plurality of parallel switched capacitor circuits.
  • the switched capacitor circuit includes a capacitor 8 and a switch module 9 controlled by the capacitor array controller 3.
  • the capacitor 8 and the switch module 9 are connected in series, and the control terminal and the capacitor array of the switch module 9 are controlled.
  • the device 3 is electrically connected.
  • the capacitor array controller 3 controls the on/off of the switched capacitor circuit through the switch module 9 in each switched capacitor circuit, and adjusts the effective capacitance Ca of the switched capacitor array 4 by controlling the turn-on and turn-off of the respective switched capacitor circuits.
  • the timing generator 1, the switched capacitor array 4, the inductor L, the load capacitor CL, the first switch transistor SW1, the second switch transistor SW2, the third switch transistor SW3, the fourth switch transistor SW4, and the fifth switch transistor SW5 form a quick start
  • the main circuit of the digital output buffer has a function of controlling the LC oscillation to control the switching capacitor array by controlling the first switching transistor SW1, the second switching transistor SW2, the third switching transistor SW3, the fourth switching transistor SW4, and the fifth switching transistor SW5.
  • the charge on 4 is non-destructively transferred to the load capacitor CL according to the input signal Din, and the upper plate of the load capacitor CL is boosted to the voltage of the power supply VDD, or the charge on the CL is non-destructively transferred to the switched capacitor according to the input signal Din.
  • Array 4 and strengthen the upper plate of the load capacitance CL to the ground, so that the output port Dout can be
  • the low-to-high transition and enhanced and high-to-low transitions and enhancements enable data lossless buffering from Din to Dout.
  • the first switch tube SW1 and the second switch tube SW2 enhance the level of the digital output port Dout, and maintain Dout at a low level or a low level of low resistance.
  • the fourth switch tube SW4 and the fifth switch tube SW5 enhance the level of the first conductive end of the switched capacitor array 4, and maintain the first conductive end of the switched capacitor array 4 at a low resistance high level or low resistance. On the low level.
  • the fast start digital output buffer is divided into T1, T2, and T3. And four stages of T4, the timing generator 1 controls the first switching transistor SW1, the second switching transistor SW2, the third switching transistor SW3, the fourth switching transistor SW4, and the fifth switching transistor SW5 to operate.
  • the T1 interval is entered, and the third switch tube SW3 is turned on, the first switch tube SW1, the second switch tube SW2, the fourth switch tube SW4, and the fifth switch tube SW5. Disconnected, the charge stored in the switched capacitor array 4 is supplied to the inductor L via the third switch SW3. Since the inductor L and the load capacitor CL form a series resonant circuit, the load capacitor CL is charged with voltage due to resonance, and the voltage of the upper plate is charged. It can swing freely to VDD. In the T1 interval, the current in the inductor L increases from 0 to the positive direction. After reaching the peak value, the voltage of the plate on the load capacitor CL oscillates to the highest point, and the current in the inductor L returns to zero.
  • the current in the inductor L returns to 0, which is the end point of the T1 interval, and is the starting point of the T2 interval.
  • the first switch tube SW1 and the fifth switch tube SW5 are turned on, the second switch tube SW2, the third switch tube SW3 and the fourth switch tube SW4 are disconnected, and the upper plate of the load capacitor CL is boosted to VDD via the first switch tube SW1.
  • the voltage of the upper plate of the load capacitor CL reaches To VDD
  • the output port Dout outputs a high level
  • the first conduction end of the switched capacitor array 4 is boosted to GND via the fifth switch SW5, and the first conduction end of the switched capacitor array 4 is maintained at a low level.
  • the T3 section When the input signal Din transitions from a high level to a low level, the T3 section is entered, and the third switch tube SW3 is turned on, the first switch tube SW1, the second switch tube SW2, the fourth switch tube SW4, and the fifth switch tube SW5. disconnect.
  • the charge on the load capacitance CL is recovered via the inductance L, and the third switch SW3 is recovered by the switched capacitor array 4.
  • the voltage on the load capacitor CL oscillates freely from VDD to 0, and the current in the inductor L increases from 0 to the maximum point and then returns to 0.
  • the current in the inductor L returns to 0, which is the end point of the T3 interval, and is the starting point of the T4 interval.
  • the second switch tube SW2 and the fourth switch tube SW4 are turned on, and the first switch tube SW1, the third switch tube SW3, and the fifth switch tube SW5 are turned off.
  • the upper plate of the load capacitor CL is reinforced to GND via the second switch SW2, and the output port Dout outputs a low level.
  • the first conductive end of the switched capacitor array 4 is reinforced to VDD via the fourth switch SW4, and the second of the switched capacitor array 4 A conduction terminal is maintained at a high level.
  • the current detector 5 provides negative feedback to the main circuit. Since the T1 phase and the T3 phase need to end when the current in the inductor L just becomes 0, the power consumption is reduced, and the circuit noise is generated by avoiding high frequency oscillation of the residual current in the inductor L. It is therefore important that the timing generator 1 controls the duration of the T1 phase and the T3 phase.
  • the durations of the T1 phase and the T3 phase are the same, both being time T.
  • the initial value of the time T is preset in the timing generator 1.
  • the timing generator controls the third switch SW3 to turn on T, that is, when the third switch SW3 is turned off, the current detector 5 detects the inductance L. Residual current, output Dcmp value to the timing generator, Dcmp value reflects the direction of residual current, or Dcmp value reflects the direction and magnitude of residual current, timing generator 1 adjusts according to the received Dcmp value The value of T between.
  • the third switch SW3 When the third switch SW3 is turned off, if the current detector 5 detects that residual current flows from the inductor L to the load capacitor CL, the time T value increases, and if the current detector 5 detects residual current flowing from the load capacitor CL to the inductor L, then the time T value decreases.
  • the capacitor mismatch detector 2 and the capacitor array controller 3 constitute an auxiliary control circuit for the fast-start switching capacitor array 4.
  • the timing generator 1 controls the third switching transistor SW3 to turn on T time, that is, when the third switching transistor SW3 is turned off, the first switching transistor SW1 and the fifth switching transistor SW5 are simultaneously Before the turn-on, the voltage detecting module 7 detects the voltage V of the plate on the load capacitor CL, and the data processing module 6 compares the voltage V with the power VDD voltage, and sends the comparison result to the capacitor array controller 3, and the capacitor array controller 3
  • the on and off of the respective switched capacitor circuits in the switched capacitor array 4 are controlled according to the received data.
  • the value Ctrl output from the data processing module 6 to the capacitor array controller 3 remains unchanged, and the on/off states of the respective switched capacitor circuits in the switched capacitor array 4 remain unchanged, and the effective capacitance Ca remains unchanged.
  • the value Ctrl output from the data processing module 6 to the capacitor array controller 3 is increased, and the on/off state of the corresponding switched capacitor circuit in the switched capacitor array 4 is adjusted, and the effective capacitance Ca is increased;
  • the value Ctrl output from the data processing module 6 to the capacitor array controller 3 is decreased, and the on-off state of the corresponding switched capacitor circuit in the switched capacitor array 4 is adjusted, and the effective capacitance Ca is decreased.
  • the timing generator 1 controls the third switching transistor SW3 to turn on T time, that is, when the third switching transistor SW3 is turned off, and before the second switching transistor SW2 and the fourth switching transistor SW4 are turned on
  • the voltage detecting module 7 detects the load.
  • the voltage V of the plate on the capacitor CL, the data processing module 6 compares the voltage V With the size of 0, and the comparison result is sent to the capacitor array controller 3, the capacitor array controller 3 controls the on and off of the respective switched capacitor circuits in the switched capacitor array 4 based on the received data.
  • the value Ctrl outputted by the data processing module 6 to the capacitor array controller 3 remains unchanged, and the on/off state of each switched capacitor circuit in the switched capacitor array 4 remains unchanged, and the effective capacitance Ca remains unchanged;
  • the value Ctrl output from the data processing module 6 to the capacitor array controller 3 is decreased, and the on/off state of the corresponding switched capacitor circuit in the switched capacitor array 4 is adjusted, and the effective capacitance Ca is decreased; if the voltage V is greater than 0
  • the value Ctrl output from the data processing module 6 to the capacitor array controller 3 is increased, the on-off state of the corresponding switched capacitor circuit in the switched capacitor array 4 is adjusted, and the effective capacitance Ca is increased.
  • the effective capacitance Ca of the switched capacitor array 4 is matched with the capacitance of the load capacitor CL, thereby eliminating the need for a large storage capacitor and eliminating the need for large energy storage for circuit establishment.
  • the capacitor is charged for a long time, which saves power consumption, and the digital output buffer can be quickly started due to the less charging time of the switched capacitor array 4.
  • the invention relates to a fast start digital output buffer control method suitable for the above-mentioned fast start digital output buffer, comprising the following steps:
  • step S1 the timing generator reads the input signal Din, when the input signal Din jumps from a low level to a high level, then step S2 is performed, when the input signal Din jumps from a high level to a low level, then step S4 is performed;
  • the timing generator controls the third switch tube SW3 to turn on T time, and controls the first switch tube SW1, the second switch tube SW2, the fourth switch tube SW4, and the fifth switch tube SW5 to be turned off for T time;
  • the charge stored in the switched capacitor array is supplied to the inductor L via the third switch SW3. Since the inductor L and the load capacitor CL form a series resonant circuit, the load capacitor CL is charged with voltage due to resonance, and the voltage of the upper plate can be freely oscillated to VDD. In this process, the current in the inductor L increases from 0 to the positive direction. After reaching the peak value, the voltage of the plate on the load capacitor CL oscillates to the highest point, and the current in the inductor L returns to zero.
  • the timing generator controls the second switch tube SW2, the third switch tube SW3 and the fourth switch tube SW4 to be disconnected, and the control capacitor mismatch detector detects the load capacitor CL upper plate in the third switch tube SW3
  • the voltage V at the time of disconnection after the detection is completed, the timing generator controls the first switch tube SW1 and the fifth switch tube SW5 to be turned on, the capacitance mismatch detector compares the voltage V with the power supply VDD voltage, and sends the comparison result to
  • the capacitor array controller controls the on and off of each switch capacitor circuit in the switched capacitor array according to the received data, so that the effective capacitance Ca of the switched capacitor array matches the capacitance of the load capacitor CL;
  • the upper plate of the load capacitor CL is boosted to VDD via the first switch SW1, the voltage of the upper plate of the load capacitor CL reaches VDD, the output port Dout outputs a high level, and the first conduction end of the switched capacitor array is connected to the fifth switch.
  • the tube SW5 is boosted to GND, and the first conduction end of the switched capacitor array is maintained at a low level.
  • the timing generator controls the third switch tube SW3 to be turned on for T time, and controls the first switch tube SW1, the second switch tube SW2, the fourth switch tube SW4, and the fifth switch tube SW5 to be turned off for T time;
  • the charge on the load capacitance CL is recovered via the inductance L, and the third switch SW3 is recovered by the switched capacitor array 4.
  • the voltage on the load capacitor CL oscillates freely from VDD to 0, and the current in the inductor L increases from 0 to the maximum point and then returns to 0.
  • the timing controller controls the first switch tube SW1, the third switch tube SW3, and the fifth switch tube SW5 to be disconnected, and the capacitor mismatch detector detects that the upper plate of the load capacitor CL is disconnected at the third switch tube SW3.
  • the timing generator controls the second switch tube SW2 and the fourth switch tube SW4 to be turned on, the capacitance mismatch detector compares the magnitudes of the voltages V and 0, and sends the comparison result to the capacitor array control.
  • the capacitor array controller controls the on and off of each of the switched capacitor circuits in the switched capacitor array according to the received data, so that the effective capacitance Ca of the switched capacitor array matches the capacitance of the load capacitor CL;
  • the upper plate of the load capacitor CL is reinforced to GND via the second switch SW2, the output port Dout outputs a low level, and the first conductive end of the switched capacitor array is boosted to VDD via the fourth switch SW4, and the first lead of the switched capacitor array The terminal is maintained at a high level.
  • the initial value of the time T is preset in the timing generator.
  • the timing generator controls the third switch SW3 to turn on T time, that is, when the third switch SW3 is turned off, the current detector detects the residual current in the inductor L.
  • the Dcmp value is output to the timing generator, the Dcmp value reflects the direction of the residual current, or the Dcmp value reflects the direction and magnitude of the residual current, and the timing generator adjusts the value of the time T according to the received Dcmp value.
  • the third switch SW3 When the third switch SW3 is turned off, if the current detector detects that residual current flows from the inductor L to the load capacitor CL, the time T value increases, and if the current detector detects that residual current flows from the load capacitor CL to the inductor L, Then the time T value decreases.
  • the timing generator adjusts the value of the time T according to the received Dcmp value.
  • the method includes the following steps: the timing generator is provided with a Dsgm value corresponding to the time value, and the time value corresponding to the initial value of the Dsgm value is an initial value of the time T, and the timing is generated. To the Dsgm value and the received Dcmp value The line is integrated to obtain the latest Dsgm value, and the time value corresponding to the latest Dsgm value is taken as the latest value of the time T.
  • the method for controlling the on and off of each switched capacitor circuit in the switched capacitor array according to the received data in step S3 includes the following steps: if the voltage V is equal to the power supply VDD voltage, each switched capacitor circuit in the switched capacitor array The on/off state is unchanged; if the voltage V is less than the power supply VDD voltage, the on/off state of the corresponding switched capacitor circuit in the switched capacitor array is adjusted, so that the effective capacitance of the switched capacitor array is increased; if the voltage V is greater than the power supply VDD voltage, the adjustment is made.
  • the on-off state of the corresponding switched capacitor circuit in the switched capacitor array reduces the effective capacitance of the switched capacitor array.
  • the method for controlling the on and off of each of the switched capacitor circuits in the switched capacitor array according to the received data in the step S5 includes the following steps: if the voltage V is equal to 0, the switching capacitor circuits in the switched capacitor array are connected. The off state is unchanged; if the voltage V is less than 0, the on/off state of the corresponding switched capacitor circuit in the switched capacitor array is adjusted, so that the effective capacitance of the switched capacitor array is reduced; if the voltage V is greater than 0, the corresponding switch in the switched capacitor array is adjusted. The on-off state of the capacitor circuit increases the effective capacitance of the switched capacitor array.

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Abstract

一种快速启动数字输出缓冲器及其控制方法。该数字输出缓冲器包括时序产生器（1）、电容失配探测器（2）、电容阵列控制器（3）、开关电容阵列（4）、电流探测器（5）、电感L、负载电容CL、第一开关管SW1、第二开关管SW2、第三开关管SW3、第四开关管SW4和第五开关管SW5，时序产生器（1）、开关电容阵列（4）、电感L、负载电容CL、第一开关管SW1、第二开关管SW2、第三开关管SW3、第四开关管SW4和第五开关管SW5组成了主电路，电流探测器（5）给主电路提供负反馈，电容失配探测器（2）和电容阵列控制器（3）组成了快速启动开关电容阵列的控制电路。该数字输出缓冲器的功耗降低，启动快速，对于负载电容的变化具有极快的响应能力。

Description

一种快速启动数字输出缓冲器及其控制方法 技术领域
本发明涉及数字输出缓冲器技术领域，尤其涉及一种快速启动数字输出缓冲器及其控制方法。
背景技术
随着传感器的兴起，传感器与主机间有线信号传输情况越来越复杂。在一些超低功耗应用场合，传感器大部分时间都是处于待机状态，只在极短时间内完成一次传感及数据输出。传感器通过数字输出缓冲器将数据输出，随着数字信号频率的上升，数字输出缓冲器对数据进行输出缓冲时需要消耗大量功率。因此，有必要设计一种降低功耗的数字输出缓冲器。
中国专利公开号CN103269217，公开日2013年8月28日，发明的名称为输出缓冲器，该申请案公开了一种输出缓冲器，它包括第一与第二晶体管及自偏压电路，第一晶体管具有控制电极、耦接输出端的输入电极及输出电极，第二晶体管具有控制电极、耦接第一晶体管的输出电极的输入电极及耦接参考电压的输出电极，自偏压电路耦接输出端及第一晶体管的控制电极。其不足之处是，该输出缓冲器的功耗较大。
发明内容
本发明的目的是克服现有数字输出缓冲器功耗较大的技术问题，提供了一种能够降低功耗的快速启动数字输出缓冲器及其控制方法。
为了解决上述问题，本发明采用以下技术方案予以实现：
本发明的一种快速启动数字输出缓冲器，包括时序产生器、电容失配探测器、电容阵列控制器、开关电容阵列、电流探测器、电感L、负载电容CL、第一开关管SW1、第二开关管SW2、第三开关管SW3、第四开关管SW4和第五开关管SW5，所述开关电容阵列的第一导通端与第三开关管SW3的第一导通端、第四开关管SW4的第一导通端和第五开关管SW5的第一导通端电连接，第四开关管SW4的第二导通端与电源VDD电连接，第五开关管SW5的第二导通端与开关电容阵列的第二导通端都接地，第三开关管SW3的第二导通端与电感L一端电连接，电感L另一端与负载电容CL的上极板、第一开关管SW1的第一导通端、第二开关管SW2的第一导通端和电容失配探测器的检测端电连接，所述负载电容CL的下极板和第二开关管SW2的第二导通端都接地，所述第一开关管SW1的第二导通端与电源VDD电连接，电容失配探测器的输出端与电容阵列控制器的输入端电连接，电容阵列控制器还与开关电容阵列的控制端电连接，所述第一开关管SW1的控制端、第二开关管SW2的控制端、第三开关管SW3的控制端、第四开关管SW4的控制端、第五开关管SW5的控制端、电容失配探测器和电流探测器分别与时序产生器电连接，所述电流探测器的两个检测端分别与第三开关管SW3的第一导通端和第二导通端电连接，所述时序产生器的输入端为数字输出缓冲器的信号输入端，所述负载电容CL的上极板为数字输出缓冲器的信号输出端。
在本技术方案中，时序产生器、开关电容阵列、电感L、负载电容CL、第一开关管SW1、第二开关管SW2、第三开关管SW3、第四开关管SW4和第五开关管SW5组成了快速启动数字输出缓冲器的主体电路，其功能是 通过控制第一开关管SW1、第二开关管SW2、第三开关管SW3、第四开关管SW4和第五开关管SW5来控制LC振荡把开关电容阵列上的电荷按照输入信号Din无损地搬到负载电容CL上，并把负载电容CL的上极板加强到电源VDD的电压，或者是把CL上的电荷按照输入信号Din无损地搬到开关电容阵列上，并把负载电容CL的上极板加强到地，这样在输出口Dout可以实现从低电平到高电平的转换并加强及从高电平到低电平的转换并加强，实现了从Din到Dout的数据无损缓冲驱动。
第一开关管SW1及第二开关管SW2实现对数字输出口Dout的电平的加强，把Dout维持在低阻的高电平或低阻的低电平上。第四开关管SW4及第五开关管SW5实现对开关电容阵列的第一导通端的电平的加强，把开关电容阵列的第一导通端维持在低阻的高电平或低阻的低电平上。
在输入信号Din从低电平跳变到高电平，再由高电平跳变到低电平的过程中，快速启动数字输出缓冲器工作分为T1、T2、T3和T4四个阶段，时序产生器控制第一开关管SW1、第二开关管SW2、第三开关管SW3、第四开关管SW4和第五开关管SW5工作。
当输入信号Din从低电平跳变到高电平时，进入T1区间，第三开关管SW3导通，第一开关管SW1、第二开关管SW2、第四开关管SW4和第五开关管SW5断开，开关电容阵列中储存的电荷经由第三开关管SW3提供给电感L，由于电感L与负载电容CL组成串联共振电路，负载电容CL由于共振而充入电压，其上极板的电压可以自由振荡到VDD。在T1区间，电感L中的电流从0开始往正向增大，到达峰值后，在负载电容CL上极板的电压振荡到最高点，电感L中电流又回到0。
接着进入T2区间，电感L中的电流回到0点，是T1区间的结束点，同时是T2区间的开始点。第一开关管SW1、第五开关管SW5导通，第二开关管SW2、第三开关管SW3和第四开关管SW4断开，负载电容CL的上极板经由第一开关管SW1加强到VDD，负载电容CL的上极板的电压达到VDD，输出口Dout输出高电平，开关电容阵列的第一导通端经由第五开关管SW5加强到GND，开关电容阵列的第一导通端维持在低电平。
当输入信号Din从高电平跳变到低电平时，进入T3区间，第三开关管SW3导通，第一开关管SW1、第二开关管SW2、第四开关管SW4和第五开关管SW5断开。负载电容CL上的电荷经由电感L，第三开关管SW3被开关电容阵列回收。这一过程，负载电容CL上的电压从VDD自由振荡到0，电感L中的电流从0开始反向增大到最大点，然后又回到0。
接着进入T4区间，电感L中的电流回到0点，是T3区间的结束点，同时是T4区间的开始点。第二开关管SW2和第四开关管SW4导通，第一开关管SW1、第三开关管SW3和第五开关管SW5断开。负载电容CL上极板经由第二开关管SW2加强到GND，输出口Dout输出低电平，开关电容阵列的第一导通端经由第四开关管SW4加强到VDD，开关电容阵列的第一导通端维持在高电平。
电流探测器给主体电路提供负反馈，由于T1阶段和T3阶段需要在电感L中的电流恰好变为0时结束，从而降低功耗，同时避免电感L中残余电流高频振荡产生电路噪声。因此时序产生器控制T1阶段和T3阶段的持续时间很重要。
T1阶段和T3阶段的持续时间相同，都为时间T。时序产生器内预先设有时间T的初始数值，当时序产生器控制第三开关管SW3导通T时间结束，即第三开关管SW3断开时，电流探测器探测到电感L中的残余电流，输出Dcmp值到时序产生器，Dcmp值反应残余电流的方向，或者Dcmp值反应残余电流的方向及大小，时序产生器根据接收到的Dcmp值调整时间T的数值。第三开关管SW3断开时，如果电流探测器检测到有残余电流从电感L流向负载电容CL，则时间T值增大，如果电流探测器检测到有残余电流从负载电容CL流向电感L，则时间T值减小。
电容失配探测器和电容阵列控制器组成了快速启动开关电容阵列的辅助控制电路。在T2区间，当时序产生器控制第三开关管SW3导通T时间结束，即第三开关管SW3断开时，同时在第一开关管SW1、第五开关管SW5导通前，电容失配探测器检测负载电容CL上极板的电压V，比较电压V与电源VDD电压的大小，并将比较结果发送到电容阵列控制器，电容阵列控制器根据接收到的数据控制开关电容阵列内各个开关电容电路的导通和关断。如果电压V等于电源VDD电压，则开关电容阵列内各个开关电容电路的通断状态不变；如果电压V小于电源VDD电压，则调整开关电容阵列内相应开关电容电路的通断状态，使得开关电容阵列的有效电容量Ca增大；如果电压V大于电源VDD电压，则调整开关电容阵列内相应开关电容电路的通断状态，使得开关电容阵列的有效电容量Ca减小。
在T4区间，当时序产生器控制第三开关管SW3导通T时间结束，即第三开关管SW3断开时，同时在第二开关管SW2、第四开关管SW4导通前，电容失配探测器检测负载电容CL上极板的电压V，比较电压V与0 的大小，并将比较结果发送到电容阵列控制器，电容阵列控制器根据接收到的数据控制开关电容阵列内各个开关电容电路的导通和关断。如果电压V等于0，则开关电容阵列内各个开关电容电路的通断状态不变；如果电压V小于0，则调整开关电容阵列内相应开关电容电路的通断状态，使得开关电容阵列的有效电容量Ca减小；如果电压V大于0，则调整开关电容阵列内相应开关电容电路的通断状态，使得开关电容阵列的有效电容量Ca增大。
通过实时调整各个开关电容电路的通断状态使开关电容阵列的有效电容量Ca与负载电容CL的电容量匹配，从而不需要使用巨大的储能电容，不用为了电路建立而对巨大的储能电容进行长时间充电，节省了功耗，同时由于对开关电容阵列的充电时间较少使得数字输出缓冲器能够快速启动。
作为优选，所述电容失配探测器包括数据处理模块和电压检测模块，所述电压检测模块的检测端与负载电容CL的上极板电连接，所述电压检测模块的数据输出端与数据处理模块的输入端电连接，所述数据处理模块还分别与时序产生器和电容阵列控制器电连接。电压检测模块检测负载电容CL上极板的电压，数据处理模块对电压检测模块检测到的数据进行处理，并且与时序产生器和电容阵列控制器进行信息交换。
作为优选，所述开关电容阵列包括若干个并联的开关电容电路，所述开关电容电路包括电容器以及受电容阵列控制器控制的开关模块，所述电容器和开关模块串联，所述开关模块的控制端与电容阵列控制器电连接。电容阵列控制器通过每个开关电容电路中的开关模块来控制该开关电容电 路的通断，通过控制各个开关电容电路的导通和关断来调整开关电容阵列的有效电容量Ca。
本发明的一种快速启动数字输出缓冲器的控制方法，包括以下步骤：
S1：时序产生器读取输入信号Din，当输入信号Din由低电平跳变至高电平时，则执行步骤S2，当输入信号Din由高电平跳变至低电平时，则执行步骤S4；
S2：时序产生器控制第三开关管SW3导通T时间，控制第一开关管SW1、第二开关管SW2、第四开关管SW4和第五开关管SW5断开T时间；
S3：T时间结束时，时序产生器控制第二开关管SW2、第三开关管SW3和第四开关管SW4断开，控制电容失配探测器检测负载电容CL上极板在第三开关管SW3断开时的电压V，检测完成后，时序产生器控制第一开关管SW1和第五开关管SW5导通，电容失配探测器比较电压V与电源VDD电压的大小，并将比较结果发送到电容阵列控制器，电容阵列控制器根据接收到的数据控制开关电容阵列内各个开关电容电路的导通和关断，使开关电容阵列的有效电容量Ca与负载电容CL的电容量匹配；
S4：时序产生器控制第三开关管SW3导通T时间，控制第一开关管SW1、第二开关管SW2、第四开关管SW4和第五开关管SW5断开T时间；
S5：T时间结束时，时序控制器控制第一开关管SW1、第三开关管SW3和第五开关管SW5断开，控制第二开关管SW2和第四开关管SW4导通；
时序产生器内预先设有时间T的初始数值，当时序产生器控制第三开关管SW3导通T时间结束，即第三开关管SW3断开时，电流探测器探测到电感L中的残余电流，输出Dcmp值到时序产生器，Dcmp值反应残余电 流的方向，或者Dcmp值反应残余电流的方向及大小，时序产生器根据接收到的Dcmp值调整时间T的数值。
作为优选，所述时序产生器根据接收到的Dcmp值调整时间T的数值的方法包括以下步骤：时序产生器设有一个与时间值对应的Dsgm值，Dsgm值的初始值对应的时间值为时间T的初始数值，时序产生器对Dsgm值和接收到的Dcmp值进行积分，得到最新的Dsgm值，将该最新的Dsgm值对应的时间值作为时间T的最新数值。
作为优选，所述步骤S3中电容阵列控制器根据接收到的数据控制开关电容阵列内各个开关电容电路的导通和关断的方法包括以下步骤：如果电压V等于电源VDD电压，则开关电容阵列内各个开关电容电路的通断状态不变；如果电压V小于电源VDD电压，则调整开关电容阵列内相应开关电容电路的通断状态，使得开关电容阵列的有效电容量Ca增大；如果电压V大于电源VDD电压，则调整开关电容阵列内相应开关电容电路的通断状态，使得开关电容阵列的有效电容量Ca减小。
作为优选，所述步骤S5包括以下步骤：T时间结束时，时序控制器控制第一开关管SW1、第三开关管SW3和第五开关管SW5断开，电容失配探测器检测负载电容CL上极板在第三开关管SW3断开时的电压V，检测完成后，时序产生器控制第二开关管SW2和第四开关管SW4导通，电容失配探测器比较电压V与0的大小，并将比较结果发送到电容阵列控制器，电容阵列控制器根据接收到的数据控制开关电容阵列内各个开关电容电路的导通和关断，使开关电容阵列的有效电容量Ca与负载电容CL的电容量匹配。
作为优选，所述步骤S5中电容阵列控制器根据接收到的数据控制开关电容阵列内各个开关电容电路的导通和关断的方法包括以下步骤：如果电压V等于0，则开关电容阵列内各个开关电容电路的通断状态不变；如果电压V小于0，则调整开关电容阵列内相应开关电容电路的通断状态，使得开关电容阵列的有效电容量Ca减小；如果电压V大于0，则调整开关电容阵列内相应开关电容电路的通断状态，使得开关电容阵列的有效电容量Ca增大。
本发明的实质性效果是：(1)有效降低了数字输出缓冲器的功耗。(2)启动快速，即刻建立起稳定传输路径，同时对于负载电容的变化具有极快的响应能力。(3)避免电感L中残余电流高频振荡产生电路噪声。(4)采用了电容匹配技术，从传输的第一个数据开始就是有效的，而采用大电容的话，在建立过程中，数据的完整性会得到破坏，要一个很长的时间数据才会有效。(5)由于开关电容阵列内的电容都是小电容，因此可以很方便把开关电容阵列集成到芯片内部。
附图说明
图1是本发明的一种电路原理连接框图；
图2是电容失配探测器的电路原理连接框图；
图3是本发明的一个工作周期的控制信号时序图；
图4是本发明的电容匹配时序图。
图中：1、时序产生器，2、电容失配探测器，3、电容阵列控制器，4、开关电容阵列，5、电流探测器，6、数据处理模块，7、电压检测模块，8、电容器，9、开关模块。
具体实施方式
下面通过实施例，并结合附图，对本发明的技术方案作进一步具体的说明。
实施例：本发明的一种快速启动数字输出缓冲器，如图1所示，包括时序产生器1、电容失配探测器2、电容阵列控制器3、开关电容阵列4、电流探测器5、电感L、负载电容CL、第一开关管SW1、第二开关管SW2、第三开关管SW3、第四开关管SW4和第五开关管SW5，开关电容阵列4的第一导通端与第三开关管SW3的第一导通端、第四开关管SW4的第一导通端和第五开关管SW5的第一导通端电连接，第四开关管SW4的第二导通端与电源VDD电连接，第五开关管SW5的第二导通端与开关电容阵列4的第二导通端都接地，第三开关管SW3的第二导通端与电感L一端电连接，电感L另一端与负载电容CL的上极板、第一开关管SW1的第一导通端、第二开关管SW2的第一导通端和电容失配探测器2的检测端电连接，负载电容CL的下极板和第二开关管SW2的第二导通端都接地，第一开关管SW1的第二导通端与电源VDD电连接，电容失配探测器2的输出端与电容阵列控制器3的输入端电连接，电容阵列控制器3还与开关电容阵列4的控制端电连接，第一开关管SW1的控制端、第二开关管SW2的控制端、第三开关管SW3的控制端、第四开关管SW4的控制端、第五开关管SW5的控制端、电容失配探测器2和电流探测器5分别与时序产生器1电连接，电流探测器5的两个检测端分别与第三开关管SW3的第一导通端和第二导通端电连接，时序产生器1的输入端为数字输出缓冲器的信号输入端，负载电容CL的上极板为数字输出缓冲器的信号输出端。
如图2所示，电容失配探测器2包括数据处理模块6和电压检测模块7，电压检测模块7的检测端与负载电容CL的上极板电连接，电压检测模块7的数据输出端与数据处理模块6的输入端电连接，数据处理模块6还分别与时序产生器1和电容阵列控制器3电连接。数据处理模块6为双向积分器，受时序产生器1控制，电压检测模块7检测负载电容CL上极板的电压，数据处理模块6对电压检测模块7检测到的数据进行处理，并将处理结果发送到电容阵列控制器3。
开关电容阵列4包括若干个并联的开关电容电路，开关电容电路包括电容器8以及受电容阵列控制器3控制的开关模块9，电容器8和开关模块9串联，开关模块9的控制端与电容阵列控制器3电连接。电容阵列控制器3通过每个开关电容电路中的开关模块9来控制该开关电容电路的通断，通过控制各个开关电容电路的导通和关断来调整开关电容阵列4的有效电容量Ca。
时序产生器1、开关电容阵列4、电感L、负载电容CL、第一开关管SW1、第二开关管SW2、第三开关管SW3、第四开关管SW4和第五开关管SW5组成了快速启动数字输出缓冲器的主体电路，其功能是通过控制第一开关管SW1、第二开关管SW2、第三开关管SW3、第四开关管SW4和第五开关管SW5来控制LC振荡把开关电容阵列4上的电荷按照输入信号Din无损地搬到负载电容CL上，并把负载电容CL的上极板加强到电源VDD的电压，或者是把CL上的电荷按照输入信号Din无损地搬到开关电容阵列4上，并把负载电容CL的上极板加强到地，这样在输出口Dout可 以实现从低电平到高电平的转换并加强及从高电平到低电平的转换并加强，实现了从Din到Dout的数据无损缓冲驱动。
第一开关管SW1及第二开关管SW2实现对数字输出口Dout的电平的加强，把Dout维持在低阻的高电平或低阻的低电平上。第四开关管SW4及第五开关管SW5实现对开关电容阵列4的第一导通端的电平的加强，把开关电容阵列4的第一导通端维持在低阻的高电平或低阻的低电平上。
如图3所示，在输入信号Din从低电平跳变到高电平，再由高电平跳变到低电平的过程中，快速启动数字输出缓冲器工作分为T1、T2、T3和T4四个阶段，时序产生器1控制第一开关管SW1、第二开关管SW2、第三开关管SW3、第四开关管SW4和第五开关管SW5工作。
当输入信号Din从低电平跳变到高电平时，进入T1区间，第三开关管SW3导通，第一开关管SW1、第二开关管SW2、第四开关管SW4和第五开关管SW5断开，开关电容阵列4中储存的电荷经由第三开关管SW3提供给电感L，由于电感L与负载电容CL组成串联共振电路，负载电容CL由于共振而充入电压，其上极板的电压可以自由振荡到VDD。在T1区间，电感L中的电流从0开始往正向增大，到达峰值后，在负载电容CL上极板的电压振荡到最高点，电感L中电流又回到0。
接着进入T2区间，电感L中的电流回到0点，是T1区间的结束点，同时是T2区间的开始点。第一开关管SW1、第五开关管SW5导通，第二开关管SW2、第三开关管SW3和第四开关管SW4断开，负载电容CL的上极板经由第一开关管SW1加强到VDD，负载电容CL的上极板的电压达 到VDD，输出口Dout输出高电平，开关电容阵列4的第一导通端经由第五开关管SW5加强到GND，开关电容阵列4的第一导通端维持在低电平。
当输入信号Din从高电平跳变到低电平时，进入T3区间，第三开关管SW3导通，第一开关管SW1、第二开关管SW2、第四开关管SW4和第五开关管SW5断开。负载电容CL上的电荷经由电感L，第三开关管SW3被开关电容阵列4回收。这一过程，负载电容CL上的电压从VDD自由振荡到0，电感L中的电流从0开始反向增大到最大点，然后又回到0。
接着进入T4区间，电感L中的电流回到0点，是T3区间的结束点，同时是T4区间的开始点。第二开关管SW2和第四开关管SW4导通，第一开关管SW1、第三开关管SW3和第五开关管SW5断开。负载电容CL上极板经由第二开关管SW2加强到GND，输出口Dout输出低电平，开关电容阵列4的第一导通端经由第四开关管SW4加强到VDD，开关电容阵列4的第一导通端维持在高电平。
电流探测器5给主体电路提供负反馈，由于T1阶段和T3阶段需要在电感L中的电流恰好变为0时结束，从而降低功耗，同时避免电感L中残余电流高频振荡产生电路噪声。因此时序产生器1控制T1阶段和T3阶段的持续时间很重要。
T1阶段和T3阶段的持续时间相同，都为时间T。时序产生器1内预先设有时间T的初始数值，当时序产生器控制第三开关管SW3导通T时间结束，即第三开关管SW3断开时，电流探测器5探测到电感L中的残余电流，输出Dcmp值到时序产生器，Dcmp值反应残余电流的方向，或者Dcmp值反应残余电流的方向及大小，时序产生器1根据接收到的Dcmp值调整时 间T的数值。第三开关管SW3断开时，如果电流探测器5检测到有残余电流从电感L流向负载电容CL，则时间T值增大，如果电流探测器5检测到有残余电流从负载电容CL流向电感L，则时间T值减小。
电容失配探测器2和电容阵列控制器3组成了快速启动开关电容阵列4的辅助控制电路。开关电容阵列4包括电容器C1、C2……Cn，电容器Cn的电容量Cn＝A×2n-1，n＝1，2，3……，A为常数。
如图4所示，在T2区间，当时序产生器1控制第三开关管SW3导通T时间结束，即第三开关管SW3断开时，同时在第一开关管SW1、第五开关管SW5导通前，电压检测模块7检测负载电容CL上极板的电压V，数据处理模块6比较电压V与电源VDD电压的大小，并将比较结果发送到电容阵列控制器3，电容阵列控制器3根据接收到的数据控制开关电容阵列4内各个开关电容电路的导通和关断。如果电压V等于电源VDD电压，数据处理模块6输出到电容阵列控制器3的数值Ctrl保持不变，则开关电容阵列4内各个开关电容电路的通断状态不变，有效电容量Ca保持不变；如果电压V小于电源VDD电压，数据处理模块6输出到电容阵列控制器3的数值Ctrl增大，则调整开关电容阵列4内相应开关电容电路的通断状态，有效电容量Ca增大；如果电压V大于电源VDD电压，数据处理模块6输出到电容阵列控制器3的数值Ctrl减小，则调整开关电容阵列4内相应开关电容电路的通断状态，有效电容量Ca减小。
当时序产生器1控制第三开关管SW3导通T时间结束，即第三开关管SW3断开时，同时在第二开关管SW2、第四开关管SW4导通前，电压检测模块7检测负载电容CL上极板的电压V，数据处理模块6比较电压V 与0的大小，并将比较结果发送到电容阵列控制器3，电容阵列控制器3根据接收到的数据控制开关电容阵列4内各个开关电容电路的导通和关断。如果电压V等于0，数据处理模块6输出到电容阵列控制器3的数值Ctrl保持不变，则开关电容阵列4内各个开关电容电路的通断状态不变，有效电容量Ca保持不变；如果电压V小于0，数据处理模块6输出到电容阵列控制器3的数值Ctrl减小，则调整开关电容阵列4内相应开关电容电路的通断状态，有效电容量Ca减小；如果电压V大于0，数据处理模块6输出到电容阵列控制器3的数值Ctrl增大，则调整开关电容阵列4内相应开关电容电路的通断状态，有效电容量Ca增大。
通过实时调整各个开关电容电路的通断状态使开关电容阵列4的有效电容量Ca与负载电容CL的电容量匹配，从而不需要使用巨大的储能电容，不用为了电路建立而对巨大的储能电容进行长时间充电，节省了功耗，同时由于对开关电容阵列4的充电时间较少使得数字输出缓冲器能够快速启动。
本发明的一种快速启动数字输出缓冲器的控制方法，适用于上述的一种快速启动数字输出缓冲器，包括以下步骤：
S1：时序产生器读取输入信号Din，当输入信号Din由低电平跳变至高电平时，则执行步骤S2，当输入信号Din由高电平跳变至低电平时，则执行步骤S4；
S2：时序产生器控制第三开关管SW3导通T时间，控制第一开关管SW1、第二开关管SW2、第四开关管SW4和第五开关管SW5断开T时间；
开关电容阵列中储存的电荷经由第三开关管SW3提供给电感L，由于电感L与负载电容CL组成串联共振电路，负载电容CL由于共振而充入电压，其上极板的电压可以自由振荡到VDD。这一过程，电感L中的电流从0开始往正向增大，到达峰值后，在负载电容CL上极板的电压振荡到最高点，电感L中电流又回到0。
S3：T时间结束时，时序产生器控制第二开关管SW2、第三开关管SW3和第四开关管SW4断开，控制电容失配探测器检测负载电容CL上极板在第三开关管SW3断开时的电压V，检测完成后，时序产生器控制第一开关管SW1和第五开关管SW5导通，电容失配探测器比较电压V与电源VDD电压的大小，并将比较结果发送到电容阵列控制器，电容阵列控制器根据接收到的数据控制开关电容阵列内各个开关电容电路的导通和关断，使开关电容阵列的有效电容量Ca与负载电容CL的电容量匹配；
负载电容CL的上极板经由第一开关管SW1加强到VDD，负载电容CL的上极板的电压达到VDD，输出口Dout输出高电平，开关电容阵列的第一导通端经由第五开关管SW5加强到GND，开关电容阵列的第一导通端维持在低电平。
S4：时序产生器控制第三开关管SW3导通T时间，控制第一开关管SW1、第二开关管SW2、第四开关管SW4和第五开关管SW5断开T时间；
负载电容CL上的电荷经由电感L，第三开关管SW3被开关电容阵列4回收。这一过程，负载电容CL上的电压从VDD自由振荡到0，电感L中的电流从0开始反向增大到最大点，然后又回到0。
S5：T时间结束时，时序控制器控制第一开关管SW1、第三开关管SW3和第五开关管SW5断开，电容失配探测器检测负载电容CL上极板在第三开关管SW3断开时的电压V，检测完成后，时序产生器控制第二开关管SW2和第四开关管SW4导通，电容失配探测器比较电压V与0的大小，并将比较结果发送到电容阵列控制器，电容阵列控制器根据接收到的数据控制开关电容阵列内各个开关电容电路的导通和关断，使开关电容阵列的有效电容量Ca与负载电容CL的电容量匹配；
负载电容CL上极板经由第二开关管SW2加强到GND，输出口Dout输出低电平，开关电容阵列的第一导通端经由第四开关管SW4加强到VDD，开关电容阵列的第一导通端维持在高电平。
时序产生器内预先设有时间T的初始数值，当时序产生器控制第三开关管SW3导通T时间结束，即第三开关管SW3断开时，电流探测器探测到电感L中的残余电流，输出Dcmp值到时序产生器，Dcmp值反应残余电流的方向，或者Dcmp值反应残余电流的方向及大小，时序产生器根据接收到的Dcmp值调整时间T的数值。
第三开关管SW3断开时，如果电流探测器检测到有残余电流从电感L流向负载电容CL，则时间T值增大，如果电流探测器检测到有残余电流从负载电容CL流向电感L，则时间T值减小。
时序产生器根据接收到的Dcmp值调整时间T的数值包括以下步骤：时序产生器设有一个与时间值对应的Dsgm值，Dsgm值的初始值对应的时间值为时间T的初始数值，时序产生器对Dsgm值和接收到的Dcmp值进 行积分，得到最新的Dsgm值，将该最新的Dsgm值对应的时间值作为时间T的最新数值。
步骤S3中电容阵列控制器根据接收到的数据控制开关电容阵列内各个开关电容电路的导通和关断的方法包括以下步骤：如果电压V等于电源VDD电压，则开关电容阵列内各个开关电容电路的通断状态不变；如果电压V小于电源VDD电压，则调整开关电容阵列内相应开关电容电路的通断状态，使得开关电容阵列的有效电容增大；如果电压V大于电源VDD电压，则调整开关电容阵列内相应开关电容电路的通断状态，使得开关电容阵列的有效电容减小。
步骤S5中电容阵列控制器根据接收到的数据控制开关电容阵列内各个开关电容电路的导通和关断的方法包括以下步骤：如果电压V等于0，则开关电容阵列内各个开关电容电路的通断状态不变；如果电压V小于0，则调整开关电容阵列内相应开关电容电路的通断状态，使得开关电容阵列的有效电容减小；如果电压V大于0，则调整开关电容阵列内相应开关电容电路的通断状态，使得开关电容阵列的有效电容增大。

Claims (8)

  1. 一种快速启动数字输出缓冲器，包括时序产生器(1)、电容失配探测器(2)、电容阵列控制器(3)、开关电容阵列(4)、电流探测器(5)、电感L、负载电容CL、第一开关管SW1、第二开关管SW2、第三开关管SW3、第四开关管SW4和第五开关管SW5，所述开关电容阵列(4)的第一导通端与第三开关管SW3的第一导通端、第四开关管SW4的第一导通端和第五开关管SW5的第一导通端电连接，第四开关管SW4的第二导通端与电源VDD电连接，第五开关管SW5的第二导通端与开关电容阵列(4)的第二导通端都接地，第三开关管SW3的第二导通端与电感L一端电连接，电感L另一端与负载电容CL的上极板、第一开关管SW1的第一导通端、第二开关管SW2的第一导通端和电容失配探测器(3)的检测端电连接，所述负载电容CL的下极板和第二开关管SW2的第二导通端都接地，所述第一开关管SW1的第二导通端与电源VDD电连接，电容失配探测器(2)的输出端与电容阵列控制器(3)的输入端电连接，电容阵列控制器(3)还与开关电容阵列(4)的控制端电连接，所述第一开关管SW1的控制端、第二开关管SW2的控制端、第三开关管SW3的控制端、第四开关管SW4的控制端、第五开关管SW5的控制端、电容失配探测器(2)和电流探测器(5)分别与时序产生器(1)电连接，所述电流探测器(5)的两个检测端分别与第三开关管SW3的第一导通端和第二导通端电连接，所述时序产生器(1)的输入端为数字输出缓冲器的信号输入端，所述负载电容CL的上极板为数字输出缓冲器的信号输出端。
  2. 根据权利要求1所述的快速启动数字输出缓冲器，其中，所述电容失配探测器(2)包括数据处理模块(6)和电压检测模块(7)，所述电压检测模块 (7)的检测端与负载电容CL的上极板电连接，所述电压检测模块(7)的数据输出端与数据处理模块(6)的输入端电连接，所述数据处理模块(6)还分别与时序产生器(1)和电容阵列控制器(3)电连接。
  3. 根据权利要求1或2所述的快速启动数字输出缓冲器，其中，所述开关电容阵列(4)包括若干个并联的开关电容电路，所述开关电容电路包括电容器(8)以及受电容阵列控制器(3)控制的开关模块(9)，所述电容器(8)和开关模块(9)串联，所述开关模块(9)的控制端与电容阵列控制器(3)电连接。
  4. 一种快速启动数字输出缓冲器的控制方法，包括以下步骤：
    S1：时序产生器读取输入信号Din，当输入信号Din由低电平跳变至高电平时，则执行步骤S2，当输入信号Din由高电平跳变至低电平时，则执行步骤S4；
    S2：时序产生器控制第三开关管SW3导通T时间，控制第一开关管SW1、第二开关管SW2、第四开关管SW4和第五开关管SW5断开T时间；
    S3：T时间结束时，时序产生器控制第二开关管SW2、第三开关管SW3和第四开关管SW4断开，控制电容失配探测器检测负载电容CL上极板在第三开关管SW3断开时的电压V，检测完成后，时序产生器控制第一开关管SW1和第五开关管SW5导通，电容失配探测器比较电压V与电源VDD电压的大小，并将比较结果发送到电容阵列控制器，电容阵列控制器根据接收到的数据控制开关电容阵列内各个开关电容电路的导通和关断，使开关电容阵列的有效电容量Ca与负载电容CL的电容量匹配；
    S4：时序产生器控制第三开关管SW3导通T时间，控制第一开关管SW1、第二开关管SW2、第四开关管SW4和第五开关管SW5断开T时间；
    S5：T时间结束时，时序控制器控制第一开关管SW1、第三开关管SW3和第五开关管SW5断开，控制第二开关管SW2和第四开关管SW4导通；
    时序产生器内预先设有时间T的初始数值，当时序产生器控制第三开关管SW3导通T时间结束，即第三开关管SW3断开时，电流探测器探测到电感L中的残余电流，输出Dcmp值到时序产生器，Dcmp值反应残余电流的方向，或者Dcmp值反应残余电流的方向及大小，时序产生器根据接收到的Dcmp值调整时间T的数值。
  5. 根据权利要求4所述的快速启动数字输出缓冲器的控制方法，其中，所述时序产生器根据接收到的Dcmp值调整时间T的数值的方法包括以下步骤：时序产生器设有一个与时间值对应的Dsgm值，Dsgm值的初始值对应的时间值为时间T的初始数值，时序产生器对Dsgm值和接收到的Dcmp值进行积分，得到最新的Dsgm值，将该最新的Dsgm值对应的时间值作为时间T的最新数值。
  6. 根据权利要求4或5所述的快速启动数字输出缓冲器的控制方法，其中，所述步骤S3中电容阵列控制器根据接收到的数据控制开关电容阵列内各个开关电容电路的导通和关断的方法包括以下步骤：如果电压V等于电源VDD电压，则开关电容阵列内各个开关电容电路的通断状态不变；如果电压V小于电源VDD电压，则调整开关电容阵列内相应开关电容电路的通断状态，使得开关电容阵列的有效电容量Ca增大；如果电压V大于电源VDD电压，则调整开关电容阵列内相应开关电容电路的通断状态，使得开关电容阵列的有效电容量Ca减小。
  7. 根据权利要求4或5所述的快速启动数字输出缓冲器的控制方法，其中，所述步骤S5包括以下步骤：T时间结束时，时序控制器控制第一开关管SW1、第三开关管SW3和第五开关管SW5断开，电容失配探测器检测负载电容CL上极板在第三开关管SW3断开时的电压V，检测完成后，时序产生器控制第二开关管SW2和第四开关管SW4导通，电容失配探测器比较电压V与0的大小，并将比较结果发送到电容阵列控制器，电容阵列控制器根据接收到的数据控制开关电容阵列内各个开关电容电路的导通和关断，使开关电容阵列的有效电容量Ca与负载电容CL的电容量匹配。
  8. 根据权利要求7所述的快速启动数字输出缓冲器的控制方法，其中，所述步骤S5中电容阵列控制器根据接收到的数据控制开关电容阵列内各个开关电容电路的导通和关断的方法包括以下步骤：如果电压V等于0，则开关电容阵列内各个开关电容电路的通断状态不变；如果电压V小于0，则调整开关电容阵列内相应开关电容电路的通断状态，使得开关电容阵列的有效电容量Ca减小；如果电压V大于0，则调整开关电容阵列内相应开关电容电路的通断状态，使得开关电容阵列的有效电容量Ca增大。
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