WO2016017024A1

WO2016017024A1 - Circuit substrate, electronic device and mounting structure

Info

Publication number: WO2016017024A1
Application number: PCT/JP2014/070312
Authority: WO
Inventors: 泰麿小宮
Original assignee: 株式会社日立製作所
Priority date: 2014-08-01
Filing date: 2014-08-01
Publication date: 2016-02-04

Abstract

A technique is provided that can reduce noise while cutting costs. This circuit substrate is provided with a substrate, a circuit provided on the substrate, a connector mounted on the substrate, and a shield. The shield is provided between the circuit and the connector so as to surround at least the connector, and electrically is directly connected to a conductive housing unit.

Description

Circuit board, electronic equipment and mounting structure

The present invention relates to a circuit board, an electronic device, and a mounting structure.

Patent Document 1 (Japanese Patent Application Laid-Open No. 2013-254759) discloses a circuit board, which is a circuit board GND that constitutes the upper and lower layers of the circuit board, a signal wiring provided in an inner layer of the circuit board, and the signal A GND pattern provided in a layer in which wiring is formed, and a GND via that connects the substrate GNDs on the upper and lower layers of the circuit board, and the GND pattern is connected to the substrate GND via the GND via. A circuit board characterized by electrical connection is described.

JP 2013-254759 A

The technique described in Patent Document 1 enables reduction of noise that propagates to the wiring when electrostatic noise is applied and reaches the IC. Therefore, it is necessary to include the substrate GND as the upper and lower layers of the circuit substrate, but such a substrate is expensive. Therefore, it is not suitable for a product that requires a strong cost reduction, such as a substrate for an automobile product. Further, for such products, further noise reduction is required.
The present invention has been made in view of such circumstances, and an object thereof is to provide a technique capable of reducing noise while reducing cost.

In order to solve the above problems, for example, the configuration described in the claims is adopted. The present application includes a plurality of means for solving the above-described problems. To give an example, a circuit board is a board, a circuit provided on the board, and a connector mounted on the board. And a shield, and the shield is provided between the circuit and the connector so as to surround at least the periphery of the connector, and is electrically connected directly to the conductive casing. .

According to the technology of the present invention, it is possible to reduce noise while further reducing costs. Problems, configurations, effects, and the like other than those described above will be clarified by the following description of embodiments.

It is an example of the structure outline | summary of the circuit board of 1st Embodiment. It is an example of sectional drawing of the circuit board of a 1st embodiment. It is a schematic diagram of the noise propagation state in the circuit board described in JP 2013-254759 A. It is a schematic diagram of the noise propagation situation in the circuit board of the first embodiment. An example of noise voltage is shown. It is an example of the external appearance of the electronic device containing a circuit board. It is an example of sectional drawing of the circuit board of a modification. It is an example of the structure outline | summary of the circuit board of a modification. It is an example of the structure outline | summary of the circuit board of a modification. It is an example of the structure outline | summary of the circuit board of a modification.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted. Further, in the following description, in the case of particularly distinguishing between components having the same function but different positions and ranges, for example, description will be given with reference numerals such as “A” and “B”.
[First embodiment]
FIG. 1 is an example of a schematic configuration of a circuit board according to the first embodiment. FIG. 2 is an example of a cross-sectional view of the circuit board according to the first embodiment. Note that FIG. 2 is an example of a cross-sectional view taken along line SS when the respective units shown in FIG. 1 are mounted, but a part of the configuration is omitted for simplification.

The connector 2 is mounted on the circuit board 1 and includes at least a part of the housing as will be described in detail later. Below, the part contained in the circuit board 1 among the housing | casing is demonstrated as the housing | casing part 31. FIG.

The circuit board 1 includes a board 10. A circuit 11, a connector pin via 12, a GND via 13, a GND pattern 14, a signal wiring 15, and the like are formed on the substrate 10.

The substrate 10 is composed of a plurality of layers. Here, the substrate 10 is described as having four layers, layer1 to layer4, but is not limited thereto.

The circuit 11 is a part that executes desired processing and the like, and includes, for example, an IC (Integrated Circuit) and signal wiring. Here, a description will be given assuming that the signal wiring of the circuit 11 is arranged in layer3, but the present invention is not limited to this.

The connector pin via 12 is provided so as not to overlap the range of the circuit 11. In FIG. 1, the connector pin via 12 is provided close to the outer periphery of the substrate 10. A connector pin 21 to be described later is inserted into the connector pin via 12 and the connector 2 is mounted.

The GND via 13 and the GND pattern 14 are provided between the connector 2 and the circuit 11 so as to surround at least the periphery where the connector 2 is provided. FIG. 1 shows an example in which the GND via 13 and the GND pattern 14 are provided along three sides of the periphery of the range where the connector 2 is provided and along the side closest to the connector 2 among the sides of the substrate 10. ing.

The inside of the GND via 13 is metalized or the like, and two or more GND patterns 14 are electrically connected. Although the number of the GND vias 13 is not particularly limited, it is effective to provide a plurality of GND vias so as to form a fence as illustrated. The distance between the GND vias 13 can be determined according to processing accuracy, desired performance, cost, and the like.

FIG. 1B is an example of the GND via 13 and the GND pattern 14. The GND pattern 14 is disposed so as to include the GND via 13 within the range. The GND pattern 14 is provided in each of at least two different layers. One is the lowermost layer of the substrate 10 and the outer side of the lowermost layer (the side not in contact with other layers). The other is a layer above the layer where the signal wiring of the circuit 11 is arranged. Hereinafter, when these GND patterns 14 are described separately, the former is referred to as a GND pattern 14-1, and the latter is referred to as a GND pattern 14-2. 1 and 2 show an example in which the GND pattern 14 is provided in layer 2 and layer 4.

The shape formed by the range of the two GND patterns 14 is not particularly limited as long as the GND via 13 can be included in the range. In FIG. 2, the GND pattern 14-1 is an example of a shape that surrounds the entire circumference of the range where the connector pin via 12 is provided and the side closest to the connector pin via 12 among the sides of the circuit board 1 in a band shape. It is. The GND pattern 14-2 is an example in which the GND pattern 14-2 is uniformly or almost uniformly formed on the entire surface of the substrate 10.

In addition, the lowest layer here is a layer opposite to the layer on which the connector 2 is mounted in the circuit board 1.

In FIG. 2, there is no great difference between the thickness of the layer and the thickness of the GND pattern 14, but this is for explanation, and the GND pattern 14 may actually be thinner or thicker than illustrated. . The same applies to other figures described later.

The technology for realizing the GND pattern 14 is not particularly limited. For example, it may be realized by applying a known conductive paste, or may be realized by masking and metallization. Further, the GND pattern 14-1 and the GND pattern 14-2 may be realized by different technologies. For example, the GND pattern 14-1 may be realized by a conductive paste, and the GND pattern 14-2 may be realized by masking and metallization. In this case, for the GND pattern 14-1, after the substrate 1 is manufactured, a conductive paste is applied to the outside of the lowermost layer of the substrate 10, and this applied portion comes into contact with a rim 311 (described later) of the housing portion 31. Thus, you may mount | assemble and mount to at least one among the housing | casing part 31 and a housing | casing.

The signal wiring 15 includes a signal wiring in the circuit 11. The signal wiring 15 is connected to the connector pin via 12. This signal wiring 15 is arranged to pass between the GND vias 13 so as not to contact the GND vias 13.

The connector 2 includes a connector pin 21 and a connector shell 22. The connector pin 21 is a linear GND pin bent at a right angle or a substantially right angle. The connector pins 21 penetrate the connector shell 22 and further penetrate the substrate 10.

At least a part of the housing portion 31 is formed of a conductive material such as metal, and the conductive material is configured to be in direct contact with the GND via 13 and the GND pattern 14. This eliminates the need to form the substrate GND as the upper and lower layers of the substrate, thereby reducing the cost and reducing noise.

In the present embodiment, the casing 31 itself is formed of a conductive material. The housing portion 31 includes a rim 311 that is a convex portion protruding in the direction of the substrate 10. FIG. 1C shows an example of the shape of the rim 311. The rim 311 includes a surface 312 at or near the vertex of the convex portion. The shape of the surface 312 may be the same as or substantially the same as the GND pattern 14-1. The surface 312 is formed so as to be in contact with at least a part, preferably the entire surface or almost the entire surface of the GND pattern 14-1. However, the contact mentioned here includes not only exact contact but also non-contact within a range where there is no problem in electrical connection.

By doing so, it is possible to control the parallelism of the substrate 10 to the housing portion 31 and to prevent the end of the connector pin 21 protruding from the substrate 10 from contacting the housing portion 31.

The GND via 13 and the GND pattern 14 configured as described above are electrically connected directly to the housing unit 31. By configuring in this way, it is possible to function these as a shield.

Further, in the housing part 31, the direct contact with the GND via 13 and the GND pattern 14 is on the opposite side of the surface of the substrate 10 to the surface on which the connector 2 is mounted. With this configuration, the shield can function so as to surround the layer direction of the substrate 10.

In addition, the shape of the housing | casing part 31 should just be in direct contact with the GND via | veer 13 and the GND pattern 14, and is not limited to what is illustrated. For example, a convex portion such as the rim 311 is not essential. Further, an edge may be provided around the casing 31 so as to function as a receiving structure such as a case described later.

FIG. 2 shows an example in which protrusions 131 are formed from the outer periphery of the GND via 13 so as to come into contact with both surfaces of the GND pattern 14. However, the protruding portion 131 is not necessarily formed, and the GND via 13 and the GND pattern 14 may be electrically connected. Such protrusions do not necessarily have to be formed on other circuit boards described below.
[Noise reduction]

The noise reduction by the circuit board having the above configuration will be described. FIG. 3 is a schematic diagram of a noise propagation state in a circuit board described in Japanese Patent Laid-Open No. 2013-254759. FIG. 4 is a schematic diagram of a noise propagation state in the circuit board according to the first embodiment.

One of the differences between the circuit board 1 </ b> A shown in FIG. 3 and the circuit board 1 shown in FIG. 4 is the positional relationship between the circuit 11, the contact pin via 12, and the GND via 13. As described above, in the circuit board 1, the GND via 13 is located between the circuit 11 and the contact pin via 12. On the other hand, in the circuit board 1 </ b> A, the contact pin via 12 is located between the circuit 11 and the GND via 13. Another difference is that in the circuit board 1A, the GND pattern 14 is not provided, but a GND layer 16 is provided instead.

When noise is applied from the casing 31 near the connector 2 of the circuit board 1A by the discharge gun G, an electromagnetic wave is generated around the tip of the discharge gun G, and the electromagnetic wave is generated between the connector 2 and the casing 31. It penetrates into the interlayer insulating film in the cross section of the substrate from the clearance. The connector pin 21 is coupled with the generated electromagnetic wave to generate noise on the connector pin 21. This noise generates electromagnetic noise inside the substrate via the connector pins 21 and is re-radiated.

The electromagnetic waves entering from the interlayer insulating film exposed at the edge of the substrate described above function as the electromagnetic wave shielding wall by the GND via 13 formed at the outer periphery of the edge of the substrate, and the internal penetration is suppressed and the strength is reduced. However, the electromagnetic waves generated and re-radiated inside the substrate via the connector pins 21 are not reduced in intensity and reach the signal wiring in the inner layer to generate induction noise. Such noise can be a cause of malfunction of an IC or the like.

As a known technique for reducing such various types of noise, there is mounting of a high frequency filter circuit or a noise suppression element. However, there is a problem that extra space is required to mount these configurations on the circuit board, and the cost increases accordingly.

Also for the circuit board 1 according to the present embodiment, the generation and re-radiation of electromagnetic noise are the same as described above. That is, when noise is applied from the casing 31 in the vicinity of the connector 2 by the discharge gun G, electromagnetic waves are generated around the tip of the discharge gun G. The connector pin 21 is coupled with the generated electromagnetic wave, and noise is generated on the connector pin 21. This noise generates electromagnetic noise inside the substrate via the connector pins 21 and is re-radiated.

However, in the case of the circuit board 1, the GND via 13 and the GND pattern 14 that are electrically connected directly to the housing portion 31 are provided between the circuit 11 and the contact pin via 12 as described above. Therefore, these can function as an electromagnetic wave shield. Thereby, the electromagnetic wave intensity of the noise re-radiated is reduced, and the noise induced in the signal wiring can be reduced.

FIG. 5 shows an example of noise voltage. A graph 500 shows an example of a result of simulating a noise waveform induced on the model substrate. Here, an in-vehicle electronic device is assumed as a model substrate for simulation. The model board is an FR4 board having a four-layer structure in which a connector is mounted at the board end, and a straight wiring having a characteristic impedance value of 50Ω is formed at a wiring distance of 35 mm and a wiring length of 20 mm from the board edge. The layer structure of the model board is layer1 to layer4 from the upper layer, the straight wiring is layer3, and the GND solid layer is Layer2.

When a waveform simulating discharge noise of a discharge voltage of 8 kV by an electrostatic tester is applied to such a model board at a position near the connector with respect to the housing under the circuit board, Induced noise waveform was obtained. In the graph 500, a line 511 indicates noise of a model board (hereinafter referred to as model board 1) provided with GND vias and GND patterns that are electrically connected directly to the casing as in the circuit board 1 described above. It is a waveform. Line 512 is a noise waveform of a model substrate (hereinafter referred to as model substrate 2) in which a contact pin via is located between the circuit and the GND via as in the circuit substrate 1A, and a GND layer is provided on the upper and lower sides of the substrate. .

As shown in the figure, a noise waveform having a maximum of 86 mV is generated on the line 512. In contrast, on line 511, the maximum noise amplitude is reduced to 64 mV. As described above, by adopting the configuration of the first embodiment, it is possible to reduce costs by eliminating the need for the substrate GND as the upper and lower layers of the circuit substrate, and at the same time, reduce the maximum noise voltage by 25%. .
[appearance]
FIG. 6 is an example of an external appearance of an electronic device including a circuit board. The electronic device 4 is for in-vehicle use, and includes a circuit board 1, a connector 2, a housing 3, and the like. Note that the electronic device here refers to a device including a circuit such as an IC and having a function of performing a desired process using the circuit.

The housing 3 includes a housing portion 31 and a case 32. In FIG. 6, a part of the circuit board 1 is included in the case 32 and is not shown. FIG. 6 is an example in which an edge is provided around the casing portion 31 to function as a receiving structure for the case 32. In this case, the rim 311 (not shown) may be realized as a convex portion obtained by processing a metal plate or the like.

The case 32 is configured to cover the circuit board 1 except for a part of the connector pins 21 and the shell 22 of the connector 2. The material of the case 32 is not particularly limited. When the case 32 is made of a conductive metal, it is possible to suppress static electricity failure and enhance the heat dissipation effect, while increasing the weight and the cost. When case 32 is resin, weight reduction and cost reduction can be achieved.

Due to design and manufacturing tolerances, a clearance C occurs between the outer periphery of the shell 22 and the housing 3, and thus the housing 3 has an opening. External electromagnetic noise enters the inside of the housing 3 from this opening.

By applying the structure of the above embodiment, when electrostatic noise flows from the connector 2, the generated electromagnetic wave penetrates from the opening of the housing 3, propagates in space on the surface of the substrate 10, and is diffracted at the end of the substrate 10. Electromagnetic noise that enters the interlayer insulating film can be reduced. Further, it is possible to reduce electromagnetic noise generated by coupling the generated electromagnetic wave with the connector pin 21 and re-radiating the noise into the substrate through the connector pin 21. As described above, in the above-described embodiment, it is possible to improve the static noise resistance in the packaged electronic device and reduce the cost.

Note that the appearance shown in FIG. 6 is an example, and the present invention is not limited to this. Appearance shape, size, dimensions, type and number of connectors to be mounted, and mounted components can be as desired. Further, the circuit board described here can be applied not only to electronic devices but also to any mounting structure including a circuit.

Further, the above-described configuration of each part is for convenience of description, and it is possible to divide the configuration into further configurations and to configure two or more configurations as one configuration. For example, the housing part and the case can be formed integrally, and the housing part and the case can be divided into further configurations. Therefore, the housing portion can include a case and other configurations not shown, and can be further divided.
[Modification 1]

FIG. 7 is an example of a cross-sectional view of the circuit board of the first modification. The circuit board 1B is different from the circuit board 1 in connector pins. The connector pin 21 is a GND pin, but the connector pin 21B is a signal pin. In this case, the connector pin 21B is arranged so as to be sufficiently isolated from the GND pattern 14 so that there is no electrical connection.
[Modification 2]

FIG. 8 is an example of a schematic configuration of the circuit board according to the second modification. The difference between the circuit board 1C and the circuit board 1 is a range in which a GND via and a GND pattern are provided. In the circuit board 1C, the GND via 13C and the GND pattern 14C are provided along the entire circumference of the range in which the connector pin via 12 is provided and the outer circumference of the board 10C.

FIG. 8B is an example of the GND via 13C and the GND pattern 14C. The GND pattern 14-1C has a shape surrounding the entire circumference of the range where the connector pin vias 12C are provided and all sides of the substrate 10C in a band shape. The GND pattern 14-2C is not particularly shown, but may be formed uniformly or substantially uniformly on the entire surface or substantially the entire surface of the substrate 10 as described above.

FIG. 8C shows an example of the rim 311C. The rim 311C has such a shape that it can be directly connected to at least a part, preferably all or almost all of the GND pattern 14-1C. That is, the rim 311C is a convex portion that surrounds the entire circumference of the range where the connector pin vias 12 are provided and all the sides of the substrate 10C in a band shape.

With the configuration described above, the shield functioning by the GND via and the GND pattern that are electrically connected directly to the housing portion forms a ring that seamlessly surrounds the entire circumference of the circuit. Therefore, it is possible to suppress electromagnetic waves that enter the inside of the substrate through the insulating layer from not only the end surface of the substrate on which the connector is mounted but also through the insulating layer, and to suppress noise that is induced to the signal wiring in the inner layer.
[Modification 3]

FIG. 9 is an example of a schematic configuration of the circuit board according to the third modification. The difference between the circuit board 1D and the circuit board 1C is the positional relationship in which the GND via is provided. In the circuit board 1 </ b> C, GND vias are provided in a straight line in one row with respect to the longitudinal direction of the strip-shaped GND pattern. On the other hand, in the circuit board 1D, the GND vias are provided in two rows along the longitudinal direction of the GND pattern in at least a part of the band-shaped GND pattern.

FIG. 9B is an example of the GND via 13D and the GND pattern 14D. The GND vias 13D are provided in a staggered manner within the range of the GND pattern 14-1D. Here, the staggered pattern means that each GND via 13D forms an angle other than 0 ° with respect to the other GND vias 13 adjacent in the width direction (for example, the W direction) of the GND pattern 14-1D. . This angle is not particularly limited, but when it is 45 degrees or in the vicinity thereof, the space can be used more efficiently. The GND pattern 14-2D is not particularly illustrated, but may be formed uniformly or substantially uniformly on the entire surface or substantially the entire surface of the substrate 10 as described above.

FIG. 9C shows an example of the rim 311D. The rim 311D has such a shape that it can be directly connected to at least a part, preferably all or almost all of the GND pattern 14-1D.

By configuring in this way, it becomes possible to arrange the distance between vias with respect to noise intrusion shorter than in the case where the GND vias are arranged linearly in one row, and the function as a shield for electromagnetic waves is further improved. It becomes possible.

In the case of FIG. 9, the GND vias 13 are arranged in a straight line for a part of the entire circumference of the GND pattern 14-1D (for example, the part 901 in FIG. 9B). This is because the signal wiring 15 from the connector pin via 13 passes through the GND via 13. However, two rows of GND vias 13 may be arranged in a zigzag pattern on the entire circumference of the GND pattern 14-1D. In this case, the signal wiring 15 is preferably drawn out at a predetermined angle other than 0 degrees with respect to the width direction of the GND pattern 14-1D.
In FIG. 9, the GND vias 13 are arranged in two rows in a staggered manner, but the number of rows is not limited to this and can be any number of two or more.
[Modification 4]

FIG. 10 is an example of a schematic configuration of the circuit board according to the fourth modification. The difference between the circuit board 1E and the circuit board 1C is the GND pattern 14. In the circuit board 1E, in addition to the GND pattern 14-1 and the GND pattern 14-2, one or more GND patterns 14-3 are provided.

FIG. 10C is an example of the GND pattern 14-3. The GND pattern 14-3 is configured to include the GND via 13E within the range. In addition, the GND pattern 14-3 forms an opening ring surrounding the circuit 11 with an opening (for example, an opening 1001) on at least a part of the entire circumference of the circuit 11. Through this opening, the signal wiring 15 from the connector pin via 13 is configured to pass between the GND vias 13. However, the position and shape of the opening are not limited to those illustrated.

The layer further provided with the GND pattern 14-3 is not particularly limited as long as it is not a layer provided with the GND pattern 14-1 and the GND pattern 14-2. In FIG. 10, layer 1 and layer 3 are assumed. That is, although the range is different, the GND pattern 14 is provided on all layers of the substrate 10E. However, the present invention is not limited to this, and the GND pattern 14 may be provided on a plurality, preferably three or more of the layers constituting the substrate.

FIG. 10B is an example of the GND via 13E and the GND pattern 14E. As shown in FIG. 10B, the GND pattern 14-1E may have the same configuration as described above. The GND pattern 14-2E is not particularly illustrated, but may be formed uniformly or substantially uniformly on the entire surface or substantially the entire surface of the substrate 10 as described above. The GND pattern 14-3 has a part of the opening as described above. However, the GND pattern 14-1E does not need to have such an opening and has the same shape as the GND pattern 14-1C. May be. Further, the rim 311E does not need to be provided with the opening, and may have the same shape as the rim 311C.

By forming in this way, it is possible to configure a shield function having a lattice shape in the vertical and horizontal directions of the entire end face of the substrate. Therefore, it is possible to further improve the electromagnetic wave shielding effect and suppress noise.

In FIG. 10, the GND pattern 14 encloses the entire circumference of the substrate 10 in an annular shape. However, the present invention is not limited to this, and only a part of the entire circumference of the substrate 10 is enclosed as shown in FIG. 1. It may be configured. Further, as shown in FIG. 9, the GND vias 13 may be arranged in a staggered manner.

With the above configuration, noise generated by coupling with electromagnetic noise in the connector mounted on the circuit board generates electromagnetic noise via the connector pin part inserted inside the board, and re-radiates inside the board. In addition, noise induced in the inner layer signal wiring can be reduced.

In the above description, the connector is provided near the end of the board. However, the connector is not limited to this, and can be provided at an arbitrary position on the board. Regardless of where it is provided on the board, at least as described above, by providing the GND pin and the GND pattern along the entire circumference of the range where the connector is mounted between the circuit and the connector, as described above. Effects can be obtained. Further, as described above, by further providing the GND pin and the GND pattern along the outer periphery of the substrate, a further noise suppression effect can be obtained.

As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above-described embodiments and examples, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, the above-described embodiments and examples are described in detail for easy understanding of the present invention, and are not necessarily limited to those having all the configurations described. A part of the configuration of an embodiment and an example can be replaced with the configuration of another embodiment and an example, and the configuration of an embodiment and an example can be replaced with that of another embodiment and an example. It is also possible to add a configuration. In addition, it is possible to add, delete, and replace other configurations for a part of the configurations of each embodiment and example.

1: circuit board, 10: board, 11: circuit, 12: connector pin, 13: GND via, 131: protrusion, 14: GND pattern, 15: signal wiring, 2: connector, 21: connector pin, 22: shell 3: casing, 31: casing, 311: rim, 32: case, 4: electronic device

Claims

A substrate,
A circuit provided on the substrate;
A connector mounted on the substrate;
A shield, and
The circuit board, wherein the shield is provided between the circuit and the connector so as to surround at least the periphery of the connector, and is electrically connected directly to a conductive casing.
The circuit board according to claim 1,
The circuit board characterized in that the shield includes a GND pattern and a GND via provided in the range of the GND pattern.
The circuit board according to claim 1,
The circuit board, wherein the shield is provided so as to surround at least a periphery of the connector in a layer direction of the board.
The circuit board according to claim 1,
The circuit board, wherein the shield is further provided along an outer periphery of the board.
The circuit board according to claim 2,
The circuit board, wherein the GND pattern is provided on an outer side of a layer constituting the substrate opposite to a layer on which the connector is mounted.
The circuit board according to claim 2,
The circuit board according to claim 1, wherein the GND vias are provided in a staggered manner within the range of the GND pattern.
The circuit board according to claim 2,
The circuit board according to claim 1, wherein the GND pattern is provided in three or more of the layers constituting the substrate.
The circuit board according to claim 1,
The housing part includes a convex part protruding in the substrate direction,
The shield is in contact with the substrate at the convex portion.
An electronic device including the circuit board according to claim 1.
A mounting structure including the circuit board according to claim 1.