WO2016009472A1 - Mémoire à changement de phase et dispositif à semi-conducteur - Google Patents

Mémoire à changement de phase et dispositif à semi-conducteur Download PDF

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Publication number
WO2016009472A1
WO2016009472A1 PCT/JP2014/068705 JP2014068705W WO2016009472A1 WO 2016009472 A1 WO2016009472 A1 WO 2016009472A1 JP 2014068705 W JP2014068705 W JP 2014068705W WO 2016009472 A1 WO2016009472 A1 WO 2016009472A1
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electrode
memory cell
wiring
phase change
memory
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PCT/JP2014/068705
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English (en)
Japanese (ja)
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田井　光春
高浦　則克
孝純 大柳
勝治 木下
貴博 森川
憲一 秋田
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株式会社日立製作所
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Priority to JP2016534005A priority Critical patent/JPWO2016009472A1/ja
Priority to PCT/JP2014/068705 priority patent/WO2016009472A1/fr
Publication of WO2016009472A1 publication Critical patent/WO2016009472A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching

Definitions

  • the present invention relates to a phase change memory and a semiconductor device.
  • the present invention relates to a nonvolatile semiconductor memory device that can store information using a substance whose current resistance value changes by passing a current through an element and can be electrically rewritten.
  • Tier 0 the storage tier that requires the highest data transfer speed
  • SSD solid state drive
  • HDD hard disk drive
  • magnetic tape has been commercialized for storage tiers (called Tier 1, 2,9) That do not require speed but have a very large data capacity.
  • Tier 0 The data transfer rate required for Tier 0 is increasing by about 40% per year.
  • SSDs using flash memory satisfy the specifications by operating multiple memory chips in parallel.
  • the disparity between the performance of memory chips and the required data transfer rate is increasing year by year, it is predicted that it will be extremely difficult to configure Tier 0 with SSDs using flash memory in the future. Development is desired.
  • phase change type memory As a next-generation solid-state storage, a resistance change type memory has been actively researched, and one of them is a phase change memory using a chalcogenide material as a recording material.
  • the basic structure of a phase change memory cell is one in which a phase change material as a recording material is sandwiched between metal electrodes.
  • the phase change memory cell stores information by utilizing the fact that the resistance value of a recording material made of a phase change material such as Ge 2 Sb 2 Te 5 is different between an amorphous state and a crystalline state.
  • the resistance is high in the amorphous state and low in the crystalline state. Therefore, reading is performed by applying a potential difference to both ends of the memory cell, measuring the current flowing through the memory cell, and determining the high resistance state / low resistance state of the memory cell.
  • phase change memory cell data is rewritten by changing the electrical resistance of the phase change film to a different state by Joule heat generated by current.
  • the reset operation that is, the operation of changing to a high-resistance amorphous state is performed by dissolving the phase change material with Joule heat generated by applying an electric current, and then rapidly decreasing and rapidly cooling the current.
  • the set operation that is, the operation of changing to a low-resistance crystalline state is performed by flowing a current sufficient for maintaining the phase change material at the crystallization temperature or higher for a long time.
  • R & D is a candidate for next-generation solid-state storage. Has been.
  • phase change memory cells Reducing the operating current and power of phase change memory cells is one of the important technological development elements.
  • a technique for realizing this there is a memory cell using a superlattice film in a phase change material portion.
  • the superlattice material is a metamaterial in which crystals of GeTe and Sb 2 Te 3 are alternately stacked.
  • phase change memory cells undergo state changes due to rearrangement of all constituent atoms
  • a memory cell using a superlattice film only Ge atoms near the GeTe / Sb 2 Te 3 interface are moved in a short range by charge injection without melting the material, causing a state change. Therefore, it is considered that the energy required for rewriting can be reduced by 1/20 or more compared to the conventional phase change memory cell.
  • An object of the present invention is to provide a phase change memory cell with a small current and power necessary for data rewriting. Another object of the present invention is to provide a phase change memory array using this memory cell with low power consumption and good data retention tolerance (retention).
  • a memory cell comprising a superlattice layer alternately stacked and a second electrode formed on the superlattice layer is stored, and information is stored by changing the resistance of the memory cell by supplying a rewrite current to the superlattice layer.
  • a direction of a rewrite current is defined in a direction from the base layer toward the superlattice layer.
  • a substrate In another embodiment, a substrate, a first electrode formed on the substrate, a base layer formed on the first electrode, a superlattice layer formed to be in contact with the base layer, a superlattice layer, A plurality of memory cells each formed of a second electrode formed on the lattice layer, and a selection element connected in series to the memory cells to selectively pass a current through the memory cells, the first electrode
  • This is a semiconductor device that stores information by setting a high potential on the side and a low potential on the second electrode side, passing a rewrite current through the superlattice layer, and changing its resistance value.
  • FIG. 3 is an element cross-sectional view showing one structure of a phase change memory cell of the present invention. It is element sectional drawing which shows another one structure of the phase change memory cell of this invention. It is a graph which shows the rewriting characteristic of the phase change memory cell of this invention.
  • 1 is a cross-sectional view showing a structure of a memory array employing a phase change memory cell of the present invention. It is sectional drawing which shows another one structure of the memory array which employ
  • FIG. 5 is a cross-sectional view of a connection example of CMOS, which is a component of a control circuit around a memory array, applicable to the semiconductor device of the present invention. It is sectional drawing which shows the connection method with the power supply wiring in the memory area
  • a phase change memory cell is formed so as to be in contact with a first electrode formed over a substrate, a base layer formed in contact with the first electrode, and a base layer is, GeTe, and Sb 2 Te 3 material is alternately laminated so-called super lattice layer made from the second electrode formed in contact with the superlattice layer, the superlattice direction of the current to be used for rewriting from the underlying layer It is defined in a direction toward the layer.
  • all the phase change memory cells in which the second electrode or a wiring electrically short-circuited to the second electrode constitutes the memory array Are electrically shorted between.
  • FIG. 1 is a cross-sectional view showing an example of a phase change memory cell of the present invention.
  • FIG. 2 is a cross-sectional view showing another example of the phase change memory cell of the present invention.
  • the phase change memory cell shown in FIGS. 1 and 2 has a lower electrode (first electrode) 103 on a lower wiring 102 formed through an interlayer insulating film 101 on a substrate omitted in the drawings. And a base layer 104 formed so as to be in contact with the lower electrode 103. Further, it has a superlattice layer 105 formed in contact with the base layer 104 and an upper electrode (second electrode) 106 formed in contact with the superlattice layer 105. In this embodiment, the superlattice layer 105 is formed by alternately laminating GeTe and Sb 2 Te 3 materials.
  • the superlattice layer is preferably formed directly on the underlayer.
  • the direction of the current used for rewriting is defined as the direction from the base layer 104 toward the superlattice layer 105.
  • the direction of current is indicated by an arrow 100 in the figure.
  • the substrate is not limited to a semiconductor substrate, an insulator substrate, and a conductor substrate.
  • the vertical relationship between the first electrode 103 and the second electrode 106 with respect to the substrate may be any, and the positional relationship between the base layer 104 and the superlattice layer 105 is important. That is, in FIGS. 1 and 2, it is defined that the current flows from the substrate side to the upper side of the substrate.
  • the current is defined in the direction from the base layer 104 toward the superlattice layer 105.
  • the upper wiring layer 107 is connected to the upper electrode 106.
  • Interlayer insulating films 108 and 109 exist above and below the upper wiring layer 107.
  • each layer constituting the memory cell is laminated in parallel to a substrate (not shown). Therefore, in an ideal model, the current flows in a direction perpendicular to the substrate and penetrates in the thickness direction of these layers.
  • the width of the base layer, the superlattice layer, and the upper electrode (second electrode) is different between the example of FIG. 1 and the example of FIG.
  • FIG. 3 shows data rewriting characteristics of the phase change memory cell having the structure shown in FIG.
  • the horizontal axis represents the amplitude of the pulse current density applied for rewriting, and the vertical axis represents the read resistance.
  • phase change memory cell Since data can be rewritten with low power, it is possible to provide a phase change memory cell with low current and power required for data rewriting by applying the phase change memory cell according to this embodiment. Further, by adopting the phase change memory array according to this embodiment, a semiconductor device with low operating power consumption can be provided. In addition, since the data rewrite current can be reduced, it is possible to provide a phase change memory array with good data retention tolerance (retention).
  • FIG. 4 is a diagram showing a cross section of a configuration example of one bit of a memory array using the phase change memory cell of the present invention (when the resistance change is binary. In principle, multi-value is also possible).
  • FIG. 4 includes a selection transistor 400 for selecting a bit and a phase change memory cell.
  • One side (right side in the figure) channel of the selection transistor is electrically short-circuited to the lower wiring (2) 401 via the via (2) 402, the lower wiring (1) 403, and the via (1) 404.
  • the gate 405 is electrically shorted to the bit line.
  • the other channel (the left side in the figure) of the selection transistor 400 includes a via (1) 404, a lower wiring (1) 403, a via (2) 402, a lower wiring (2) 401, a via (3) 406, a lower wiring ( 3) Electrically short-circuited to the underlying layer 104 via 102 and the lower electrode 103.
  • the upper wiring 107 is short-circuited to the superlattice layer 105 via the upper electrode 106.
  • the lower wiring (2) 401 is on the high voltage side and the upper wiring 107 is on the low voltage side.
  • the lower wiring (2) 401 is a word line and the upper electrode 106 is a source line.
  • Reference numerals 407 and 408 denote diffusion layers, and 409 denotes an STI region.
  • FIG. 5 is a diagram showing a cross section of another configuration example for one bit of the memory array using the phase change memory cell of the present invention.
  • FIG. 5 includes a selection diode 500 for selecting a bit and a phase change memory cell.
  • the rectification direction of the selection diode coincides with the current direction 100 of the phase change memory cell shown in FIG.
  • the selection diode 500 in FIG. 5 shows an example of a so-called pin-type diode comprising a p-type semiconductor layer 501, an intrinsic semiconductor layer 502, and an n-type semiconductor layer 503.
  • any device having a rectifying characteristic can be used as a selection element. Is possible.
  • the important point is that the commutation direction coincides with the current direction 100 of the memory array.
  • the power required for rewriting can be reduced.
  • the configuration shown in FIG. 5 it is possible to improve the data retention tolerance (retention) of the memory array.
  • FIG. 6 is an equivalent circuit diagram of an array portion for the memory array having the bit configuration shown in FIG. Memory cell 600 is shown as a resistor.
  • the second electrode (upper electrode) 106 since the second electrode (upper electrode) 106 is on the downstream side of the current, the voltage of the second electrode (upper electrode) 106 can be fixed as the source voltage in all bits.
  • the source line is shown as a ground potential (GND). Since a constant current source and a built-in circuit are not required, grounding is beneficial.
  • a memory array can be configured by short-circuiting the gate line 405 to the word lines W1, W2, W3, and W4 and the lower wiring (2) 401 to the bit lines B1, B2, and B3.
  • the second electrode or the wiring electrically short-circuited to the second electrode is electrically short-circuited between the phase change memory cells constituting the memory array. Since the applied voltage can be shared by the second electrodes 106 of all the bits, the source line does not need to be wired, and can be arranged in a plate shape in the entire array or several array blocks.
  • FIG. 7 is an array top view when the source lines 701 are arranged in a plate shape.
  • (a) is an example in which the entire array is covered in a plate shape
  • (b) is an example in which the entire array block is divided and covered in a plate shape.
  • the source line 701 is made of a metal material having a high thermal conductivity such as copper or aluminum which is a general wiring material.
  • a material having high thermal conductivity covers the phase change memory cell widely, so that Joule heat generated in the superlattice layer by current during data rewriting and reading is widely diffused to the periphery through the source line. As a result, a rise in the temperature of the memory cell can be suppressed, and a memory array that is resistant to retention due to heat generation can be realized.
  • the upper electrode (106 in FIG. 1 and the like) existing under the source line 701 is indicated by 702.
  • the merit of dividing the source line plate into array blocks in FIG. 7B is that processing defects are reduced when the damascene process is adopted in the wiring formation process.
  • FIG. 8A is a cross-sectional view showing the selection transistor 400 and the wiring layer formed on the silicon substrate 800. Components common to those in FIG. 4 are denoted by the same reference numerals. These are manufactured by the well-known LSI-CMOS, wiring formation process. In this step, peripheral circuits and selection transistors are formed. In FIG. 8, there are two wiring layers (401, 403), but the number of wiring layers may be selected according to circuit requirements.
  • a metal layer 801 to be the lower wiring 802 and the lower electrode 803 is formed.
  • the metal material may be different for the lower wiring 802 and the lower electrode 803, or the same material.
  • PVD physical vapor deposition
  • CVD chemical vapor deposition
  • the lower electrode 803 is processed by a photolithography process. If the metal material is different between the lower wiring 802 and the lower electrode 803, it is possible to perform highly accurate processing by employing an etching process in which the selection ratio of the two is different. Even in the case of the same material, it is possible to perform highly accurate processing by optimizing processing conditions such as processing time.
  • an interlayer insulating film 804 is formed by the CVD method, and the lower electrode 803 is once buried, and then flattened so as not to expose the upper surface of the lower electrode 803 by the CMP (Chemical-mechanical polishing) method. Then, the lower wiring 802 is processed by a photolithography process. During CMP, the lower electrode 803 may be exposed, but from the viewpoint of protecting the interface between the lower electrode 803 and the base layer, it is preferable to expose the upper surface of the lower electrode 803 only once in a later step.
  • CMP Chemical-mechanical polishing
  • an interlayer insulating film 805 is formed by the CVD method, and after the lower electrode 803 is buried again, the upper surface of the lower electrode 803 is exposed while being planarized by the CMP method.
  • the exposed upper surface of the lower electrode 803 is cleaned, and a base layer 806, a superlattice layer 807, and a metal layer 808 to be the upper electrode are sequentially formed by a PVD method or a CVD method.
  • the purpose of cleaning the upper surface of the lower electrode 803 is to remove the reaction film on the exposed surface. Wet cleaning may be used, but when the film is formed by the PVD method, reverse sputtering may be performed by a PVD apparatus to remove the reaction film on the surface.
  • the superlattice layer 807 has a structure in which crystal layers of GeTe and Sb 2 Te 3 are alternately stacked.
  • the PVD method employs a multi-sputtering method in which GeTe and Sb 2 Te 3 targets are sputtered alternately.
  • the underlayer 806 is an important film for stable formation of the superlattice layer 807.
  • Sb—Te and Bi—Te materials having a thickness of 5 nm or more are formed.
  • this film has a role of controlling the crystal orientation of the superlattice layer 807 formed thereon, and has the effect of flattening the surface roughness of the lower electrode under the underlayer.
  • FIG. 8 (g) three layers of the upper electrode 106, the superlattice layer 105, and the base layer 104 are processed by a photolithography process.
  • the lower electrode 803 (same as 103 in FIG. 4) and the three layers are processed so that the three layers have a likelihood (excessive) with respect to the lower electrode 803.
  • the processing edge of the superlattice layer 105 is considered so as not to affect the current characteristics, but if there is no concern that the processing edge affects the current characteristics, there is no need to give likelihood.
  • FIGS. 2 (a) and 2 (b) it is also possible to process into the same shape as shown in FIGS. 2 (a) and 2 (b). In that case, the processing of the lower electrode performed in FIG. 8C may be performed collectively in this step. In this case, the lower wiring is processed in the subsequent process.
  • the upper electrode 106, the superlattice layer 105, and the base layer 104 are buried with an interlayer insulating film 108 formed by a CVD method, and then the trench of the upper wiring layer is formed by a photolithography process.
  • the shape of the top surface of the trench in the array portion is the shape of the source line as exemplified in FIGS. 7 (a) and 7 (b).
  • the source line plate may be divided into array blocks to the extent that the heat dissipation effect is maintained, and the area of the trench may be divided to suppress the occurrence of defects.
  • a characteristic pattern may occur in the array due to the influence of the layout rule. For example, in the case of FIG. 7B, there is a structure in which a space is vacated every two vertical columns.
  • a pad via 810 is opened in a photolithography process, and a metal film for the pad is formed by a PVD method or a CVD method. Form a film. Further, a pad 811 is formed by a photolithography process, and the memory array is completed.
  • FIG. 9 is a block diagram showing a circuit configuration example of the memory of the present invention.
  • 900 is one memory cell (specific bit) in the memory array, 400 is a selection transistor, 600 is a resistance change element using a superlattice, B is a bit line, and W is a word line.
  • VDD is the drain side power supply voltage Do (Dorain Voltage) of the MOS element
  • VSS is the source side power supply voltage (Source Voltage) of the MOS element
  • VGATE is the gate voltage of the MOS element.
  • bitDATA indicates a signal to the bit line
  • wordDATA indicates a signal to the word line.
  • VWRITE is a rewrite voltage
  • VREAD is a read voltage.
  • a word line decoder 901 and a bit line decoder 902 for selecting a specific bit of the array, a decoder timing generation circuit 903, and a pulse waveform generation circuit 904 for generating a rewrite / read pulse.
  • a word line level shifter 905 for raising the signal wordDATA from the word line decoder 901 to the gate voltage VGATE required for the selection transistor operation.
  • the bit line B is connected to a bit line level shifter 906 that raises the signal bitDATA from the bit line decoder 902 to the rewrite voltage VWRITE / read voltage VREAD and forms it into a waveform generated by the pulse waveform generation circuit 904.
  • the plate-like source line 907 covers the upper part of the array.
  • the memory array is not limited to the configuration shown in FIG. 9, and the block configuration is increased or decreased depending on additional functions.
  • the configuration essential to this embodiment is a word line level shifter 905, a bit line level shifter 906, and a source line 907 that covers the upper portion of the array and their connection relation.
  • the source line is preferably plate-shaped, and a plate-shaped example will be described here.
  • the resistance change element 600 using a superlattice is directed from the selection transistor 400 toward the plate-like source line 907, corresponding to FIG. 4, the first electrode (lower electrode) 103, the base layer 104, and the superlattice layer.
  • the layers are configured in the order of 105 and the second electrode (upper electrode) 106.
  • the plate-like source line 907 (corresponding to 107 in FIG. 4) is fixed at a voltage lower than the voltage applied from the bit line shift register 906. For example, if VSS is the ground potential in FIG. 9, the relationship between VWRITE and VREAD is “VWRITE> VREAD> VSS”.
  • the ground potential is not limited to 0 V, but indicates that the ground potential is connected to a reference potential point, for example, a substrate potential. If VSS is 0 V, VWRITE and VREAD have the same polarity (both are positive) and have different absolute values.
  • the selection transistor 400 may adopt an n-type channel with high current driving capability, but since the electrode side not connected to the resistance change element has a high voltage, it is possible to adopt a p-type channel and perform stable operation. .
  • a memory array is configured by short-circuiting the gate line 405 of FIG. 4 to the word line W and the lower wiring (2) 401 to the bit line B. That is, the superlattice layer 105 and the base layer 104 are not electrically interposed between the lower electrode 103 and the level shifter circuits 905 and 906 that determine the voltage applied to the memory array.
  • the positional relationship of the bit line and the plate-like source line 907 with respect to the substrate is generally the order of the substrate, the bit line, and the plate-like source line from the order of the manufacturing process.
  • the order is the board, the plate-like source line, and the bit line.
  • the resistance change element 600 is directed from the selection transistor 400 toward the plate-like source line 907 in accordance with FIG. 4 in accordance with the first electrode (lower electrode) 103, the base layer 104, the superlattice layer 105, The order is the second electrode (upper electrode) 106.
  • Any array can provide a phase change memory array with low power consumption and good data retention tolerance (retention).
  • FIG. 10 is a cross-sectional view showing a connection relationship with a power source when a known phase change memory cell without using a superlattice layer and an underlayer is employed.
  • phase change material 1000 is rewritten by Joule heat generated by current application, an N-type MOS transistor capable of flowing more current is usually employed.
  • the side not connected to the MOS transistor is electrically connected to a high voltage wiring (HIGH) connected to a power supply for supplying a high voltage.
  • the side not connected to the phase change memory cell (CELL) is electrically connected to a low voltage wiring (LOW) connected to a power supply for supplying a low voltage.
  • LOW low voltage wiring
  • the current direction necessary for rewriting the phase change memory cell (CELL) may be either direction and that an N-type MOS transistor is used to secure the current.
  • the MOS transistor functions as a source on the low voltage supply wiring (LOW) side.
  • the switch has a fixed source voltage and functions as a stable switching element that can be controlled by the gate (G).
  • the side to which the phase change memory cell (CELL) is connected functions as the source.
  • the source side becomes an indefinite voltage, and control by the gate (G) is difficult.
  • the MOS transistor functions as an unstable switching element. Therefore, this connection is not usually adopted.
  • FIG. 11 shows a connection example of CMOS, which is a component of the control circuit around the memory array. This configuration is also used as a control circuit of a semiconductor device having the memory array of the present invention.
  • CMOS is generally used for a logic circuit and other circuits in a semiconductor control device in which a memory and a logic circuit or a circuit having other functions are mixedly mounted.
  • CMOS is widely known as it consists of an N-type MOS transistor and a P-type MOS transistor connected in series.
  • the N-type MOS transistor side is usually electrically connected to the low voltage wiring and the P-type MOS transistor side is electrically connected to the high voltage wiring.
  • the connection relationship between the transistors and the power supply wiring in the entire semiconductor device including the memory array and the control circuit is reasonable to unify the connection relationship between the transistors and the power supply wiring in the entire semiconductor device including the memory array and the control circuit. Therefore, when the circuit region is configured as shown in FIG. 11, even in a known phase change device that employs an N-type MOS transistor as a switching element, the N-type MOS transistor side is electrically connected to the low-voltage wiring instead of the phase-change memory cell side. It is reasonable to make a connection. That is, in both the memory area and the circuit area, the N-type MOS transistor side is usually connected to the low voltage wiring (LOW) side. For the above reasons, the connection shown in FIG. 10 is adopted in the known case, and there is no reason for the reverse connection.
  • LOW low voltage wiring
  • FIG. 12 is a cross-sectional view showing a connection method with the power supply wiring in the memory area of the present invention. Compared with FIGS. 10 and 11, the upper wiring is divided into a high voltage wiring (HIGH) and a low voltage wiring (LOW), which is different from the configuration of FIG. 4.
  • HGH high voltage wiring
  • LOW low voltage wiring
  • the direction 100 of current is defined as the direction from the underlayer 104 toward the superlattice layer 105. This is because when the phase change memory cell using the superlattice layer 105 and the underlayer 104 of the present invention is used, the current direction necessary for rewriting the phase change memory cell is that the current flows from the underlayer to the superlattice layer. Based on the finding that the flow is smaller.
  • phase change memory cell including the superlattice layer 105 and the base layer 104 when used, the effect of reducing the power consumption of the memory is remarkable, so the connection shown in FIG. 12 is adopted.
  • the MOS transistor When a P-type MOS transistor is used in the connection shown in FIG. 12, the MOS transistor functions as a source on the high voltage supply wiring (HIGH) side. That is, the switch has a fixed source voltage and functions as a stable switching element that can be controlled by the gate.
  • HGH high voltage supply wiring
  • the present invention is not limited to the above-described embodiment, and includes various modifications.
  • a part of the configuration of one embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of one embodiment.
  • source and drain of the transistor may be switched when a transistor with a different polarity is used or when the direction of current changes during circuit operation. Therefore, in this specification, the terms “source” and “drain” may be used interchangeably.
  • Electrode and “wiring” do not functionally limit these components.
  • an “electrode” may be used as part of a “wiring” and vice versa.
  • the terms “electrode” and “wiring” include a case where a plurality of “electrodes” and “wirings” are integrally formed.

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Abstract

La présente invention a pour but de fournir une cellule de mémoire à changement de phase ne nécessitant que peu de courant et de puissance électriques pour réécrire des données. De plus, la présente invention a pour but de fournir un réseau de mémoire à changement de phase utilisant ladite cellule de mémoire, consommant peu d'énergie électrique et ayant une bonne résistance de retenue de données (retenue). Pour atteindre ce but, l'invention concerne un élément qui est constitué pour comprendre une première électrode formée sur un substrat ; une couche de masse formée pour être en contact avec la première électrode, une couche de super-réseau, ainsi nommée, formée pour être en contact avec la couche de masse, des matières de GeTe et Sb2Te3 étant stratifiées en alternance ; une seconde électrode formée pour être en contact avec la couche de super-réseau. De plus, la direction du courant électrique utilisé pour la réécriture est spécifiée de façon à passer depuis la couche de masse vers la couche de super-réseau. De plus, dans un réseau de mémoire constitué à l'aide d'au moins deux desdites cellules de mémoire, les secondes électrodes ou les câblages électriquement court-circuités par les secondes électrodes court-circuitent électriquement entre toutes les cellules de mémoire à changement de phase constituant le réseau de mémoire.
PCT/JP2014/068705 2014-07-14 2014-07-14 Mémoire à changement de phase et dispositif à semi-conducteur WO2016009472A1 (fr)

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JP2016534005A JPWO2016009472A1 (ja) 2014-07-14 2014-07-14 相変化メモリおよび半導体装置
PCT/JP2014/068705 WO2016009472A1 (fr) 2014-07-14 2014-07-14 Mémoire à changement de phase et dispositif à semi-conducteur

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WO2020158531A1 (fr) * 2019-01-30 2020-08-06 日本電気株式会社 Dispositif de stockage et procédé de programmation

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