WO2016008224A1 - 薄膜晶体管、阵列基板及显示装置 - Google Patents

薄膜晶体管、阵列基板及显示装置 Download PDF

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WO2016008224A1
WO2016008224A1 PCT/CN2014/088896 CN2014088896W WO2016008224A1 WO 2016008224 A1 WO2016008224 A1 WO 2016008224A1 CN 2014088896 W CN2014088896 W CN 2014088896W WO 2016008224 A1 WO2016008224 A1 WO 2016008224A1
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semiconductor layer
film transistor
thin film
area
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French (fr)
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韩帅
张琨鹏
高鹏飞
王凤国
白妮妮
康峰
刘宇
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BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
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Ordos Yuansheng Optoelectronics Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/512—Disposition of the gate electrodes, e.g. buried gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the present disclosure relates to the field of thin film transistors, and in particular, to a thin film transistor, an array substrate, and a display device.
  • leakage current is one of the main reasons for the decrease in yield.
  • the LTPS TFT-LCD Thin Film Transistor-Liquid Crystal Display
  • LDD light-doped drain
  • This method requires ion doping, which may cause ion contamination, lattice distortion, etc. Doping also increases the process and raw materials (such as photoresist and doping ions), increasing production costs.
  • the present disclosure provides a thin film transistor, an array substrate, and a display device, which solves the problem of suppressing leakage of ions of a thin film transistor by using a lightly doped drain, which is highly costly.
  • the present disclosure provides a thin film transistor including: a gate electrode, a gate insulating layer, a semiconductor layer, a source electrode, and a drain electrode, wherein the gate electrode includes: a first region on a side of the source electrode a second region on the side of the drain electrode, and an intermediate region between the first region and the second region, wherein the intermediate region completely covers the semiconductor disposed corresponding to the intermediate region a layer, at least one of the first region and the second region covering a corresponding partial region of the semiconductor layer.
  • a width of the intermediate region in the first direction is greater than or equal to a width of the correspondingly disposed semiconductor layer in the first direction, the first direction being the source electrode and the leakage current
  • the length direction of the conductive channel formed between the poles is perpendicular to the direction.
  • the intermediate area is a rectangle, and the first area and the second area are both triangular.
  • the intermediate area is a rectangle, and the first area and the second area are both trapezoidal.
  • the semiconductor layer is a low temperature polysilicon semiconductor layer.
  • the semiconductor layer is an amorphous silicon semiconductor layer.
  • the present disclosure also provides an array substrate including the above thin film transistor.
  • the present disclosure also provides a display device including the above array substrate.
  • the edge portion of the semiconductor layer not covered by the gate electrode is not applied with a voltage, without applying a voltage
  • the edge portion of the semiconductor layer is equivalent to insulation, and its resistance is very large, so as to block the leakage current, so that the leakage current in the thin film transistor is very small, thereby improving the characteristics of the thin film transistor, and there is no ion doping.
  • the problem of ionic contamination is generated, and no process is required in the preparation process, which reduces the production cost.
  • FIG. 1 is a top plan view of a thin film transistor of an embodiment of the present disclosure.
  • FIG. 2 is a plan view of a gate electrode and a semiconductor layer of the thin film transistor of FIG. 1.
  • FIG 3 is a top plan view of a thin film transistor of another embodiment of the present disclosure.
  • the thin film transistor generally includes a gate electrode, a gate insulating layer, a semiconductor layer, a source electrode, and a drain electrode.
  • the gate electrode When the thin film transistor is turned on, the gate electrode is applied with a voltage, the gate voltage generates an electric field in the gate insulating layer, and the power line is directed from the gate electrode to the semiconductor layer. The surface, and generates an induced charge at the surface.
  • the gate voltage increases Add, the surface of the semiconductor layer will be transformed from a depletion layer to an electron accumulation layer to form an inversion layer.
  • a strong inversion type is reached (ie, when the on-voltage is reached), a voltage is applied between the source electrode and the drain electrode, and carriers are passed. Conductive channel.
  • the shape of the gate electrode may be changed such that a partial region of the gate electrode on the source electrode side or a partial region on the drain current side is narrowed, and the corresponding semiconductor layer is not completely covered, so that the semiconductor not covered by the gate electrode
  • the edge portion of the layer is not applied with a voltage, and the edge portion of the semiconductor layer is equivalent to insulation without applying a voltage, and its resistance is very large, thereby having a function of blocking leakage current.
  • the thin film transistor of the embodiment of the present disclosure includes a gate electrode 11 , a gate insulating layer (not shown), a semiconductor layer 12 , a source electrode 13 , and a drain electrode 14 .
  • the gate electrode 11 includes a first region 111 on the source electrode 13 side, a second region 112 on the drain electrode 14 side, and between the first region 111 and the second region 112.
  • the intermediate portion 113 (the dotted line portion in FIG. 2 indicates the boundary line of each different region), wherein the intermediate portion 113 completely covers the semiconductor layer disposed corresponding to the intermediate portion 113, and the first region 111 covers and a portion of the semiconductor layer corresponding to the first region 111, that is, the first region 111 does not completely cover the semiconductor layer corresponding to the first region 111, and the second region 112 covers and
  • the second region 112 corresponds to a partial region of the semiconductor layer disposed, that is, the second region 112 does not completely cover the semiconductor layer disposed corresponding to the second region 112.
  • the semiconductor layer 12 is located on the side of the drain electrode 14 In the right side region corresponding to the second region 112, the region B1 is covered by the second region 112, and the regions B2 and B3 are not covered by the second region 112.
  • the edge portions (regions A2, A3, B2, and B3) of the semiconductor layer 12 not covered by the gate electrode 11 are not applied with a voltage, and the edge portion of the semiconductor layer 12 is applied without applying a voltage. It is equivalent to insulation, and its resistance is very large, so as to block the leakage current, so that the leakage current in the thin film transistor is very small, thereby improving the characteristics of the thin film transistor, and there is no problem of ion contamination due to ion doping. At the same time, there is no need to add any process in the preparation process, which reduces the production cost.
  • the first region 111 does not completely cover the semiconductor layer disposed corresponding to the first region 111, and the second region 112 does not completely cover the portion corresponding to the second region 112.
  • a portion of the semiconductor layer, that is, the semiconductor layer 12, is not covered by the gate electrode 11.
  • the gate electrode 11 may also be configured such that the first region 111 does not completely cover the semiconductor layer disposed corresponding to the first region 111, The second region 112 completely covers the semiconductor layer disposed corresponding to the second region 112; or the first region 111 completely covers the semiconductor layer disposed corresponding to the first region 111, the second region 112 does not completely cover the semiconductor layer disposed corresponding to the second region 112. That is, the semiconductor layer 12 has a portion that is not covered by the gate electrode 11 on only one side.
  • the width of the intermediate region 113 in the first direction is greater than the width of the correspondingly disposed semiconductor layer in the first direction, the first direction being the source electrode 13 and the The length direction of the conductive channel formed between the drain electrodes 14 is perpendicular.
  • the width of the intermediate region 113 in the first direction may also be equal to the width of the correspondingly disposed semiconductor layer in the first direction.
  • the intermediate portion 113 is rectangular, and the first region 111 and the second region 112 have the same shape and are all triangular.
  • the shape of the gate electrode 11 is not limited thereto. In other embodiments of the present disclosure, the gate electrode may also have other shapes.
  • the first region 111 and the first The shape of the two regions 112 is trapezoidal or arbitrary Polygon or curved shape.
  • the semiconductor layer 12 may be a low temperature polysilicon semiconductor layer, or may be an amorphous silicon semiconductor layer or the like.
  • Embodiments of the present disclosure also provide an array substrate including the above thin film transistor.
  • An embodiment of the present disclosure further provides a display device including the above array substrate.

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  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)

Abstract

一种薄膜晶体管及使用其的阵列基板和显示装置，该薄膜晶体管包括：栅电极（11）、栅绝缘层、半导体层（12）、源电极（13）及漏电极（14），栅电极（11）包括位于源电极（13）侧的第一区域（111），位于漏电极（14）侧的第二区域（112）及位于第一区域（111）和第二区域（112）之间的中间区域（113），其中，所述中间区域（113）完全覆盖与所述中间区域（113）对应设置的所述半导体层（12），所述第一区域（111）和所述第二区域（112）中的至少一个覆盖对应设置的所述半导体层（12）的部分区域。在不使用轻掺杂漏极的情况下，有效抑制薄膜晶体管的漏电流，有利于降低成本。

Description

薄膜晶体管、阵列基板及显示装置
相关申请的交叉引用
本申请主张在2014年7月15日在中国提交的中国专利申请号No.201410337121.5的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及薄膜晶体管领域，尤其涉及一种薄膜晶体管、阵列基板及显示装置。
背景技术
LTPS(Low Temperature Poly-Silicon，低温多晶硅)工艺中，漏电流是导致其良率降低的主要原因之一，目前，在LTPS TFT-LCD(Thin Film Transistor-Liquid Crystal Display，薄膜晶体管液晶显示器)工艺中，通常采用轻掺杂漏极的方式(LDD，Light Doped Drain)来抑制异常增加的漏电流，这种方法需要进行离子掺杂，容易导致离子的污染，发生晶格畸变等问题，另外离子掺杂也增加了工序及原材料(如光刻胶及掺杂离子等)，提高了生产成本。
发明内容
有鉴于此，本公开提供一种薄膜晶体管、阵列基板及显示装置，以解决现有的采用轻掺杂漏极的方式来抑制薄膜晶体管的漏电流容易导致离子的污染，且成本高的问题。
为解决上述技术问题，本公开提供一种薄膜晶体管，包括：栅电极、栅绝缘层、半导体层、源电极及漏电极，其中，所述栅电极包括：位于所述源电极侧的第一区域，位于所述漏电极侧的第二区域，以及位于所述第一区域和所述第二区域之间的中间区域，其中，所述中间区域完全覆盖与所述中间区域对应设置的所述半导体层，所述第一区域和所述第二区域中的至少一个覆盖对应设置的所述半导体层的部分区域。
可选地，所述中间区域在第一方向上的宽度大于或等于对应设置的所述半导体层在所述第一方向上的宽度，所述第一方向为与所述源电极和所述漏电极之间形成的导电沟道的长度方向相垂直的方向。
可选地，所述中间区域为矩形，所述第一区域和所述第二区域均为三角形。
可选地，所述中间区域为矩形，所述第一区域和所述第二区域均为梯形。
可选地，所述半导体层为低温多晶硅半导体层。
可选地，所述半导体层为非晶硅半导体层。
本公开还提供一种阵列基板，包括上述薄膜晶体管。
本公开还提供一种显示装置，包括上述阵列基板。
本公开的上述技术方案的有益效果如下：
由于栅电极两端较窄，不能完全覆盖对应设置的半导体层，因而当薄膜晶体管关断时，未被栅电极覆盖的半导体层的边缘部分没有被施加上电压，在不加电压的情况下，半导体层的边缘部分相当于绝缘，其电阻非常大，从而具有阻断漏电流的作用，使得薄膜晶体管中的漏电流会非常小，从而提高了薄膜晶体管的特性，且不存在因离子掺杂而产生离子污染的问题，同时在制备过程中也不需要增加任何工序，降低了生产成本。
附图说明
图1为本公开实施例的薄膜晶体管的俯视图。
图2为图1中的薄膜晶体管的栅电极及半导体层的俯视图。
图3为本公开另一实施例的薄膜晶体管的俯视图。
具体实施方式
首先对本公开实施例的薄膜晶体管的实现原理进行简单说明。
薄膜晶体管通常包括：栅电极、栅绝缘层、半导体层、源电极和漏电极，当薄膜晶体管打开时，栅电极施以电压，栅电压在栅绝缘层中产生电场，电力线由栅电极指向半导体层表面，并在表面处产生感应电荷。随着栅电压增 加，半导体层表面将由耗尽层转变为电子积累层，形成反型层，当达到强反型时(即达到开启电压时)，源电极和漏电极间加上电压就会有载流子通过导电沟道。
当薄膜晶体管关断时，由于自由电子的存在，使得源电极和漏电极之间存在漏电流，漏电流会导致薄膜晶体管的性能降低。
本公开实施例中，可改变栅电极的形状，使得栅电极位于源电极侧的部分区域或位于漏电流侧的部分区域变窄，不完全覆盖对应的半导体层，使得未被栅电极覆盖的半导体层的边缘部分不会被施加上电压，在不加电压的情况下，半导体层的边缘部分相当于绝缘，其电阻非常大，从而具有阻断漏电流的作用。
为使本公开要解决的技术问题、技术方案和优点更加清楚，下面将结合附图及具体实施例进行详细描述。
请参考图1和图2，本公开实施例的薄膜晶体管包括：栅电极11、栅绝缘层(图未示出)、半导体层12、源电极13及漏电极14。
所述栅电极11包括：位于所述源电极13侧的第一区域111，位于所述漏电极14侧的第二区域112，以及位于所述第一区域111和所述第二区域112之间的中间区域113(图2中虚线部分表示各个不同区域的分界线)，其中，所述中间区域113完全覆盖与所述中间区域113对应设置的所述半导体层，所述第一区域111覆盖与所述第一区域111对应设置的所述半导体层的部分区域，即所述第一区域111不完全覆盖与所述第一区域111对应设置的所述半导体层，所述第二区域112覆盖与所述第二区域112对应设置的所述半导体层的部分区域，即所述第二区域112不完全覆盖与所述第二区域112对应设置的所述半导体层。
从图2中可以看出，所述半导体层12在位于所述源电极13侧的、与所述第一区域111对应的左侧区域中，区域A1被第一区域111覆盖，区域A2和A3未被第一区域111覆盖，所述半导体层12在位于所述漏电极14侧的、 与所述第二区域112对应的右侧区域中，区域B1被第二区域112覆盖，区域B2和B3未被第二区域112覆盖。
当薄膜晶体管关断时，未被栅电极11覆盖的半导体层12的边缘部分(区域A2、A3、B2和B3)没有被施加上电压，在不加电压的情况下，半导体层12的边缘部分相当于绝缘，其电阻非常大，从而具有阻断漏电流的作用，使得薄膜晶体管中的漏电流会非常小，从而提高了薄膜晶体管的特性，且不存在因离子掺杂而产生离子污染的问题，同时在制备过程中也不需要增加任何工序，降低了生产成本。
上述实施例中，所述第一区域111不完全覆盖与所述第一区域111对应设置的所述半导体层，所述第二区域112不完全覆盖与所述第二区域112对应设置的所述半导体层，即半导体层12的两侧均存在未被栅电极11覆盖的部分。当然，在本公开的其他实施例中，所述栅电极11也可以为下述结构：所述第一区域111不完全覆盖与所述第一区域111对应设置的所述半导体层，所述第二区域112完全覆盖与所述第二区域112对应设置的所述半导体层；或者，所述第一区域111完全覆盖与所述第一区域111对应设置的所述半导体层，所述第二区域112不完全覆盖与所述第二区域112对应设置的所述半导体层。即，半导体层12仅一侧存在未被栅电极11覆盖的部分。
上述实施例中，所述中间区域113在第一方向上的宽度大于对应设置的所述半导体层在所述第一方向上的宽度，所述第一方向为与所述源电极13和所述漏电极14之间形成的导电沟道的长度方向相垂直的方向。
当然，在本公开的其他实施例中，所述中间区域113在第一方向上的宽度也可以等于对应设置的所述半导体层在所述第一方向上的宽度。
上述实施例中，所述中间区域113为矩形，所述第一区域111和所述第二区域112的形状相同，均为三角形。当然，所述栅电极11的形状并不限于此，在本公开的其他实施例中，所述栅电极也可以为其他形状，例如，参见附图3，所述第一区域111和所述第二区域112的形状均为梯形，或者任意形 状的多边形或者弧形等。
本公开实施例中，所述半导体层12可以为低温多晶硅半导体层，也可以为非晶硅半导体层等。
本公开实施例还提供一种阵列基板，包括上述薄膜晶体管。
本公开实施例还提供一种显示装置，包括上述阵列基板。
以上所述是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (8)

  1. 一种薄膜晶体管，包括：栅电极、栅绝缘层、半导体层、源电极及漏电极，其中，所述栅电极包括：位于所述源电极侧的第一区域，位于所述漏电极侧的第二区域，以及位于所述第一区域和所述第二区域之间的中间区域，其中，所述中间区域完全覆盖与所述中间区域对应设置的所述半导体层，所述第一区域和所述第二区域中的至少一个覆盖对应设置的所述半导体层的部分区域。
  2. 根据权利要求1所述的薄膜晶体管，其中，所述中间区域在第一方向上的宽度大于或等于对应设置的所述半导体层在所述第一方向上的宽度，所述第一方向为与所述源电极和所述漏电极之间形成的导电沟道的长度方向相垂直的方向。
  3. 根据权利要求1所述的薄膜晶体管，其中，所述中间区域为矩形，所述第一区域和所述第二区域均为三角形。
  4. 根据权利要求1所述的薄膜晶体管，其中，所述中间区域为矩形，所述第一区域和所述第二区域均为梯形。
  5. 根据权利要求1-4任一项所述的薄膜晶体管，其中，所述半导体层为低温多晶硅半导体层。
  6. 根据权利要求1-4任一项所述的薄膜晶体管，其中，所述半导体层为非晶硅半导体层。
  7. 一种阵列基板，包括如权利要求1-6任一项所述的薄膜晶体管。
  8. 一种显示装置，包括如权利要求7所述的阵列基板。
PCT/CN2014/088896 2014-07-15 2014-10-20 薄膜晶体管、阵列基板及显示装置 Ceased WO2016008224A1 (zh)

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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05275698A (ja) * 1992-03-27 1993-10-22 Sony Corp 薄膜トランジスタ
CN1828909A (zh) * 2005-02-11 2006-09-06 三星电子株式会社 显示装置的薄膜晶体管基板及其制造方法
US20100051948A1 (en) * 2008-09-01 2010-03-04 Seiko Epson Corporation Thin film transistor, electro-optic device, and electronic apparatus
US20110024763A1 (en) * 2009-07-30 2011-02-03 Hitachi Display, Ltd. Display device and manufacturing method thereof
CN102194886A (zh) * 2010-03-10 2011-09-21 三星移动显示器株式会社 薄膜晶体管、其制造方法和具有该薄膜晶体管的显示设备
CN102034873B (zh) * 2009-09-30 2014-04-16 索尼公司 薄膜晶体管和制造薄膜晶体管的方法
CN203941905U (zh) * 2014-07-15 2014-11-12 京东方科技集团股份有限公司 一种薄膜晶体管、阵列基板及显示装置

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120032172A1 (en) * 2010-08-06 2012-02-09 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
KR101286526B1 (ko) * 2012-01-20 2013-07-19 동아대학교 산학협력단 박막 트랜지스터 및 그의 제조 방법

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05275698A (ja) * 1992-03-27 1993-10-22 Sony Corp 薄膜トランジスタ
CN1828909A (zh) * 2005-02-11 2006-09-06 三星电子株式会社 显示装置的薄膜晶体管基板及其制造方法
US20100051948A1 (en) * 2008-09-01 2010-03-04 Seiko Epson Corporation Thin film transistor, electro-optic device, and electronic apparatus
US20110024763A1 (en) * 2009-07-30 2011-02-03 Hitachi Display, Ltd. Display device and manufacturing method thereof
CN102034873B (zh) * 2009-09-30 2014-04-16 索尼公司 薄膜晶体管和制造薄膜晶体管的方法
CN102194886A (zh) * 2010-03-10 2011-09-21 三星移动显示器株式会社 薄膜晶体管、其制造方法和具有该薄膜晶体管的显示设备
CN203941905U (zh) * 2014-07-15 2014-11-12 京东方科技集团股份有限公司 一种薄膜晶体管、阵列基板及显示装置

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