WO2016008224A1 - Thin-film transistor, array substrate and display apparatus - Google Patents

Thin-film transistor, array substrate and display apparatus Download PDF

Info

Publication number
WO2016008224A1
WO2016008224A1 PCT/CN2014/088896 CN2014088896W WO2016008224A1 WO 2016008224 A1 WO2016008224 A1 WO 2016008224A1 CN 2014088896 W CN2014088896 W CN 2014088896W WO 2016008224 A1 WO2016008224 A1 WO 2016008224A1
Authority
WO
WIPO (PCT)
Prior art keywords
region
semiconductor layer
film transistor
thin film
area
Prior art date
Application number
PCT/CN2014/088896
Other languages
French (fr)
Chinese (zh)
Inventor
韩帅
张琨鹏
高鹏飞
王凤国
白妮妮
康峰
刘宇
Original Assignee
京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 鄂尔多斯市源盛光电有限责任公司 filed Critical 京东方科技集团股份有限公司
Publication of WO2016008224A1 publication Critical patent/WO2016008224A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor

Definitions

  • the present disclosure relates to the field of thin film transistors, and in particular, to a thin film transistor, an array substrate, and a display device.
  • leakage current is one of the main reasons for the decrease in yield.
  • the LTPS TFT-LCD Thin Film Transistor-Liquid Crystal Display
  • LDD light-doped drain
  • This method requires ion doping, which may cause ion contamination, lattice distortion, etc. Doping also increases the process and raw materials (such as photoresist and doping ions), increasing production costs.
  • the present disclosure provides a thin film transistor, an array substrate, and a display device, which solves the problem of suppressing leakage of ions of a thin film transistor by using a lightly doped drain, which is highly costly.
  • the present disclosure provides a thin film transistor including: a gate electrode, a gate insulating layer, a semiconductor layer, a source electrode, and a drain electrode, wherein the gate electrode includes: a first region on a side of the source electrode a second region on the side of the drain electrode, and an intermediate region between the first region and the second region, wherein the intermediate region completely covers the semiconductor disposed corresponding to the intermediate region a layer, at least one of the first region and the second region covering a corresponding partial region of the semiconductor layer.
  • a width of the intermediate region in the first direction is greater than or equal to a width of the correspondingly disposed semiconductor layer in the first direction, the first direction being the source electrode and the leakage current
  • the length direction of the conductive channel formed between the poles is perpendicular to the direction.
  • the intermediate area is a rectangle, and the first area and the second area are both triangular.
  • the intermediate area is a rectangle, and the first area and the second area are both trapezoidal.
  • the semiconductor layer is a low temperature polysilicon semiconductor layer.
  • the semiconductor layer is an amorphous silicon semiconductor layer.
  • the present disclosure also provides an array substrate including the above thin film transistor.
  • the present disclosure also provides a display device including the above array substrate.
  • the edge portion of the semiconductor layer not covered by the gate electrode is not applied with a voltage, without applying a voltage
  • the edge portion of the semiconductor layer is equivalent to insulation, and its resistance is very large, so as to block the leakage current, so that the leakage current in the thin film transistor is very small, thereby improving the characteristics of the thin film transistor, and there is no ion doping.
  • the problem of ionic contamination is generated, and no process is required in the preparation process, which reduces the production cost.
  • FIG. 1 is a top plan view of a thin film transistor of an embodiment of the present disclosure.
  • FIG. 2 is a plan view of a gate electrode and a semiconductor layer of the thin film transistor of FIG. 1.
  • FIG 3 is a top plan view of a thin film transistor of another embodiment of the present disclosure.
  • the thin film transistor generally includes a gate electrode, a gate insulating layer, a semiconductor layer, a source electrode, and a drain electrode.
  • the gate electrode When the thin film transistor is turned on, the gate electrode is applied with a voltage, the gate voltage generates an electric field in the gate insulating layer, and the power line is directed from the gate electrode to the semiconductor layer. The surface, and generates an induced charge at the surface.
  • the gate voltage increases Add, the surface of the semiconductor layer will be transformed from a depletion layer to an electron accumulation layer to form an inversion layer.
  • a strong inversion type is reached (ie, when the on-voltage is reached), a voltage is applied between the source electrode and the drain electrode, and carriers are passed. Conductive channel.
  • the shape of the gate electrode may be changed such that a partial region of the gate electrode on the source electrode side or a partial region on the drain current side is narrowed, and the corresponding semiconductor layer is not completely covered, so that the semiconductor not covered by the gate electrode
  • the edge portion of the layer is not applied with a voltage, and the edge portion of the semiconductor layer is equivalent to insulation without applying a voltage, and its resistance is very large, thereby having a function of blocking leakage current.
  • the thin film transistor of the embodiment of the present disclosure includes a gate electrode 11 , a gate insulating layer (not shown), a semiconductor layer 12 , a source electrode 13 , and a drain electrode 14 .
  • the gate electrode 11 includes a first region 111 on the source electrode 13 side, a second region 112 on the drain electrode 14 side, and between the first region 111 and the second region 112.
  • the intermediate portion 113 (the dotted line portion in FIG. 2 indicates the boundary line of each different region), wherein the intermediate portion 113 completely covers the semiconductor layer disposed corresponding to the intermediate portion 113, and the first region 111 covers and a portion of the semiconductor layer corresponding to the first region 111, that is, the first region 111 does not completely cover the semiconductor layer corresponding to the first region 111, and the second region 112 covers and
  • the second region 112 corresponds to a partial region of the semiconductor layer disposed, that is, the second region 112 does not completely cover the semiconductor layer disposed corresponding to the second region 112.
  • the semiconductor layer 12 is located on the side of the drain electrode 14 In the right side region corresponding to the second region 112, the region B1 is covered by the second region 112, and the regions B2 and B3 are not covered by the second region 112.
  • the edge portions (regions A2, A3, B2, and B3) of the semiconductor layer 12 not covered by the gate electrode 11 are not applied with a voltage, and the edge portion of the semiconductor layer 12 is applied without applying a voltage. It is equivalent to insulation, and its resistance is very large, so as to block the leakage current, so that the leakage current in the thin film transistor is very small, thereby improving the characteristics of the thin film transistor, and there is no problem of ion contamination due to ion doping. At the same time, there is no need to add any process in the preparation process, which reduces the production cost.
  • the first region 111 does not completely cover the semiconductor layer disposed corresponding to the first region 111, and the second region 112 does not completely cover the portion corresponding to the second region 112.
  • a portion of the semiconductor layer, that is, the semiconductor layer 12, is not covered by the gate electrode 11.
  • the gate electrode 11 may also be configured such that the first region 111 does not completely cover the semiconductor layer disposed corresponding to the first region 111, The second region 112 completely covers the semiconductor layer disposed corresponding to the second region 112; or the first region 111 completely covers the semiconductor layer disposed corresponding to the first region 111, the second region 112 does not completely cover the semiconductor layer disposed corresponding to the second region 112. That is, the semiconductor layer 12 has a portion that is not covered by the gate electrode 11 on only one side.
  • the width of the intermediate region 113 in the first direction is greater than the width of the correspondingly disposed semiconductor layer in the first direction, the first direction being the source electrode 13 and the The length direction of the conductive channel formed between the drain electrodes 14 is perpendicular.
  • the width of the intermediate region 113 in the first direction may also be equal to the width of the correspondingly disposed semiconductor layer in the first direction.
  • the intermediate portion 113 is rectangular, and the first region 111 and the second region 112 have the same shape and are all triangular.
  • the shape of the gate electrode 11 is not limited thereto. In other embodiments of the present disclosure, the gate electrode may also have other shapes.
  • the first region 111 and the first The shape of the two regions 112 is trapezoidal or arbitrary Polygon or curved shape.
  • the semiconductor layer 12 may be a low temperature polysilicon semiconductor layer, or may be an amorphous silicon semiconductor layer or the like.
  • Embodiments of the present disclosure also provide an array substrate including the above thin film transistor.
  • An embodiment of the present disclosure further provides a display device including the above array substrate.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)

Abstract

A thin-film transistor as well as an array substrate utilizing same and a display apparatus. The thin-film transistor comprises: a gate electrode (11), a gate insulating layer, a semiconductor layer (12), a source electrode (13) and a drain electrode (14), the gate electrode (11) comprising a first area (111) located at the side of the source electrode (13), a second area (112) located at the side of the drain electrode (14) and a middle area (113) located between the first area (111) and the second area (112), the middle area (113) completely covering the semiconductor layer (12) arranged corresponding to the middle area (113), and at least one of the first area (111) and the second area (112) covering a partial area of the corresponding semiconductor layer (12). In the case of no use of a lightly-doped drain electrode, the leak current of the thin-film transistor is effectively suppressed, so that the cost can be decreased.

Description

薄膜晶体管、阵列基板及显示装置Thin film transistor, array substrate and display device
相关申请的交叉引用Cross-reference to related applications
本申请主张在2014年7月15日在中国提交的中国专利申请号No.201410337121.5的优先权，其全部内容通过引用包含于此。The present application claims priority to Chinese Patent Application No. 201410337121.5, filed on Jan. 15, 2014, the entire content of
技术领域Technical field
本公开涉及薄膜晶体管领域，尤其涉及一种薄膜晶体管、阵列基板及显示装置。The present disclosure relates to the field of thin film transistors, and in particular, to a thin film transistor, an array substrate, and a display device.
背景技术Background technique
LTPS(Low Temperature Poly-Silicon，低温多晶硅)工艺中，漏电流是导致其良率降低的主要原因之一，目前，在LTPS TFT-LCD(Thin Film Transistor-Liquid Crystal Display，薄膜晶体管液晶显示器)工艺中，通常采用轻掺杂漏极的方式(LDD，Light Doped Drain)来抑制异常增加的漏电流，这种方法需要进行离子掺杂，容易导致离子的污染，发生晶格畸变等问题，另外离子掺杂也增加了工序及原材料(如光刻胶及掺杂离子等)，提高了生产成本。In the LTPS (Low Temperature Poly-Silicon) process, leakage current is one of the main reasons for the decrease in yield. Currently, the LTPS TFT-LCD (Thin Film Transistor-Liquid Crystal Display) process In the light-doped drain (LDD), the abnormally increased leakage current is usually suppressed. This method requires ion doping, which may cause ion contamination, lattice distortion, etc. Doping also increases the process and raw materials (such as photoresist and doping ions), increasing production costs.
发明内容Summary of the invention
有鉴于此，本公开提供一种薄膜晶体管、阵列基板及显示装置，以解决现有的采用轻掺杂漏极的方式来抑制薄膜晶体管的漏电流容易导致离子的污染，且成本高的问题。In view of the above, the present disclosure provides a thin film transistor, an array substrate, and a display device, which solves the problem of suppressing leakage of ions of a thin film transistor by using a lightly doped drain, which is highly costly.
为解决上述技术问题，本公开提供一种薄膜晶体管，包括：栅电极、栅绝缘层、半导体层、源电极及漏电极，其中，所述栅电极包括：位于所述源电极侧的第一区域，位于所述漏电极侧的第二区域，以及位于所述第一区域和所述第二区域之间的中间区域，其中，所述中间区域完全覆盖与所述中间区域对应设置的所述半导体层，所述第一区域和所述第二区域中的至少一个覆盖对应设置的所述半导体层的部分区域。 In order to solve the above technical problem, the present disclosure provides a thin film transistor including: a gate electrode, a gate insulating layer, a semiconductor layer, a source electrode, and a drain electrode, wherein the gate electrode includes: a first region on a side of the source electrode a second region on the side of the drain electrode, and an intermediate region between the first region and the second region, wherein the intermediate region completely covers the semiconductor disposed corresponding to the intermediate region a layer, at least one of the first region and the second region covering a corresponding partial region of the semiconductor layer.
可选地，所述中间区域在第一方向上的宽度大于或等于对应设置的所述半导体层在所述第一方向上的宽度，所述第一方向为与所述源电极和所述漏电极之间形成的导电沟道的长度方向相垂直的方向。Optionally, a width of the intermediate region in the first direction is greater than or equal to a width of the correspondingly disposed semiconductor layer in the first direction, the first direction being the source electrode and the leakage current The length direction of the conductive channel formed between the poles is perpendicular to the direction.
可选地，所述中间区域为矩形，所述第一区域和所述第二区域均为三角形。Optionally, the intermediate area is a rectangle, and the first area and the second area are both triangular.
可选地，所述中间区域为矩形，所述第一区域和所述第二区域均为梯形。Optionally, the intermediate area is a rectangle, and the first area and the second area are both trapezoidal.
可选地，所述半导体层为低温多晶硅半导体层。Optionally, the semiconductor layer is a low temperature polysilicon semiconductor layer.
可选地，所述半导体层为非晶硅半导体层。Optionally, the semiconductor layer is an amorphous silicon semiconductor layer.
本公开还提供一种阵列基板，包括上述薄膜晶体管。The present disclosure also provides an array substrate including the above thin film transistor.
本公开还提供一种显示装置，包括上述阵列基板。The present disclosure also provides a display device including the above array substrate.
本公开的上述技术方案的有益效果如下：The beneficial effects of the above technical solutions of the present disclosure are as follows:
由于栅电极两端较窄，不能完全覆盖对应设置的半导体层，因而当薄膜晶体管关断时，未被栅电极覆盖的半导体层的边缘部分没有被施加上电压，在不加电压的情况下，半导体层的边缘部分相当于绝缘，其电阻非常大，从而具有阻断漏电流的作用，使得薄膜晶体管中的漏电流会非常小，从而提高了薄膜晶体管的特性，且不存在因离子掺杂而产生离子污染的问题，同时在制备过程中也不需要增加任何工序，降低了生产成本。Since the two ends of the gate electrode are narrow, the corresponding semiconductor layer cannot be completely covered, and when the thin film transistor is turned off, the edge portion of the semiconductor layer not covered by the gate electrode is not applied with a voltage, without applying a voltage, The edge portion of the semiconductor layer is equivalent to insulation, and its resistance is very large, so as to block the leakage current, so that the leakage current in the thin film transistor is very small, thereby improving the characteristics of the thin film transistor, and there is no ion doping. The problem of ionic contamination is generated, and no process is required in the preparation process, which reduces the production cost.
附图说明DRAWINGS
图1为本公开实施例的薄膜晶体管的俯视图。1 is a top plan view of a thin film transistor of an embodiment of the present disclosure.
图2为图1中的薄膜晶体管的栅电极及半导体层的俯视图。2 is a plan view of a gate electrode and a semiconductor layer of the thin film transistor of FIG. 1.
图3为本公开另一实施例的薄膜晶体管的俯视图。3 is a top plan view of a thin film transistor of another embodiment of the present disclosure.
具体实施方式detailed description
首先对本公开实施例的薄膜晶体管的实现原理进行简单说明。First, the implementation principle of the thin film transistor of the embodiment of the present disclosure will be briefly described.
薄膜晶体管通常包括：栅电极、栅绝缘层、半导体层、源电极和漏电极，当薄膜晶体管打开时，栅电极施以电压，栅电压在栅绝缘层中产生电场，电力线由栅电极指向半导体层表面，并在表面处产生感应电荷。随着栅电压增 加，半导体层表面将由耗尽层转变为电子积累层，形成反型层，当达到强反型时(即达到开启电压时)，源电极和漏电极间加上电压就会有载流子通过导电沟道。The thin film transistor generally includes a gate electrode, a gate insulating layer, a semiconductor layer, a source electrode, and a drain electrode. When the thin film transistor is turned on, the gate electrode is applied with a voltage, the gate voltage generates an electric field in the gate insulating layer, and the power line is directed from the gate electrode to the semiconductor layer. The surface, and generates an induced charge at the surface. As the gate voltage increases Add, the surface of the semiconductor layer will be transformed from a depletion layer to an electron accumulation layer to form an inversion layer. When a strong inversion type is reached (ie, when the on-voltage is reached), a voltage is applied between the source electrode and the drain electrode, and carriers are passed. Conductive channel.
当薄膜晶体管关断时，由于自由电子的存在，使得源电极和漏电极之间存在漏电流，漏电流会导致薄膜晶体管的性能降低。When the thin film transistor is turned off, leakage current exists between the source electrode and the drain electrode due to the presence of free electrons, and the leakage current causes the performance of the thin film transistor to be lowered.
本公开实施例中，可改变栅电极的形状，使得栅电极位于源电极侧的部分区域或位于漏电流侧的部分区域变窄，不完全覆盖对应的半导体层，使得未被栅电极覆盖的半导体层的边缘部分不会被施加上电压，在不加电压的情况下，半导体层的边缘部分相当于绝缘，其电阻非常大，从而具有阻断漏电流的作用。In the embodiment of the present disclosure, the shape of the gate electrode may be changed such that a partial region of the gate electrode on the source electrode side or a partial region on the drain current side is narrowed, and the corresponding semiconductor layer is not completely covered, so that the semiconductor not covered by the gate electrode The edge portion of the layer is not applied with a voltage, and the edge portion of the semiconductor layer is equivalent to insulation without applying a voltage, and its resistance is very large, thereby having a function of blocking leakage current.
为使本公开要解决的技术问题、技术方案和优点更加清楚，下面将结合附图及具体实施例进行详细描述。The technical problems, the technical solutions, and the advantages of the present invention will be more clearly described in conjunction with the accompanying drawings and specific embodiments.
请参考图1和图2，本公开实施例的薄膜晶体管包括：栅电极11、栅绝缘层(图未示出)、半导体层12、源电极13及漏电极14。Referring to FIGS. 1 and 2 , the thin film transistor of the embodiment of the present disclosure includes a gate electrode 11 , a gate insulating layer (not shown), a semiconductor layer 12 , a source electrode 13 , and a drain electrode 14 .
所述栅电极11包括：位于所述源电极13侧的第一区域111，位于所述漏电极14侧的第二区域112，以及位于所述第一区域111和所述第二区域112之间的中间区域113(图2中虚线部分表示各个不同区域的分界线)，其中，所述中间区域113完全覆盖与所述中间区域113对应设置的所述半导体层，所述第一区域111覆盖与所述第一区域111对应设置的所述半导体层的部分区域，即所述第一区域111不完全覆盖与所述第一区域111对应设置的所述半导体层，所述第二区域112覆盖与所述第二区域112对应设置的所述半导体层的部分区域，即所述第二区域112不完全覆盖与所述第二区域112对应设置的所述半导体层。The gate electrode 11 includes a first region 111 on the source electrode 13 side, a second region 112 on the drain electrode 14 side, and between the first region 111 and the second region 112. The intermediate portion 113 (the dotted line portion in FIG. 2 indicates the boundary line of each different region), wherein the intermediate portion 113 completely covers the semiconductor layer disposed corresponding to the intermediate portion 113, and the first region 111 covers and a portion of the semiconductor layer corresponding to the first region 111, that is, the first region 111 does not completely cover the semiconductor layer corresponding to the first region 111, and the second region 112 covers and The second region 112 corresponds to a partial region of the semiconductor layer disposed, that is, the second region 112 does not completely cover the semiconductor layer disposed corresponding to the second region 112.
从图2中可以看出，所述半导体层12在位于所述源电极13侧的、与所述第一区域111对应的左侧区域中，区域A1被第一区域111覆盖，区域A2和A3未被第一区域111覆盖，所述半导体层12在位于所述漏电极14侧的、 与所述第二区域112对应的右侧区域中，区域B1被第二区域112覆盖，区域B2和B3未被第二区域112覆盖。As can be seen from FIG. 2, in the left region of the semiconductor layer 12 on the side of the source electrode 13 corresponding to the first region 111, the region A1 is covered by the first region 111, and the regions A2 and A3 Not covered by the first region 111, the semiconductor layer 12 is located on the side of the drain electrode 14 In the right side region corresponding to the second region 112, the region B1 is covered by the second region 112, and the regions B2 and B3 are not covered by the second region 112.
当薄膜晶体管关断时，未被栅电极11覆盖的半导体层12的边缘部分(区域A2、A3、B2和B3)没有被施加上电压，在不加电压的情况下，半导体层12的边缘部分相当于绝缘，其电阻非常大，从而具有阻断漏电流的作用，使得薄膜晶体管中的漏电流会非常小，从而提高了薄膜晶体管的特性，且不存在因离子掺杂而产生离子污染的问题，同时在制备过程中也不需要增加任何工序，降低了生产成本。When the thin film transistor is turned off, the edge portions (regions A2, A3, B2, and B3) of the semiconductor layer 12 not covered by the gate electrode 11 are not applied with a voltage, and the edge portion of the semiconductor layer 12 is applied without applying a voltage. It is equivalent to insulation, and its resistance is very large, so as to block the leakage current, so that the leakage current in the thin film transistor is very small, thereby improving the characteristics of the thin film transistor, and there is no problem of ion contamination due to ion doping. At the same time, there is no need to add any process in the preparation process, which reduces the production cost.
上述实施例中，所述第一区域111不完全覆盖与所述第一区域111对应设置的所述半导体层，所述第二区域112不完全覆盖与所述第二区域112对应设置的所述半导体层，即半导体层12的两侧均存在未被栅电极11覆盖的部分。当然，在本公开的其他实施例中，所述栅电极11也可以为下述结构：所述第一区域111不完全覆盖与所述第一区域111对应设置的所述半导体层，所述第二区域112完全覆盖与所述第二区域112对应设置的所述半导体层；或者，所述第一区域111完全覆盖与所述第一区域111对应设置的所述半导体层，所述第二区域112不完全覆盖与所述第二区域112对应设置的所述半导体层。即，半导体层12仅一侧存在未被栅电极11覆盖的部分。In the above embodiment, the first region 111 does not completely cover the semiconductor layer disposed corresponding to the first region 111, and the second region 112 does not completely cover the portion corresponding to the second region 112. A portion of the semiconductor layer, that is, the semiconductor layer 12, is not covered by the gate electrode 11. Of course, in other embodiments of the present disclosure, the gate electrode 11 may also be configured such that the first region 111 does not completely cover the semiconductor layer disposed corresponding to the first region 111, The second region 112 completely covers the semiconductor layer disposed corresponding to the second region 112; or the first region 111 completely covers the semiconductor layer disposed corresponding to the first region 111, the second region 112 does not completely cover the semiconductor layer disposed corresponding to the second region 112. That is, the semiconductor layer 12 has a portion that is not covered by the gate electrode 11 on only one side.
上述实施例中，所述中间区域113在第一方向上的宽度大于对应设置的所述半导体层在所述第一方向上的宽度，所述第一方向为与所述源电极13和所述漏电极14之间形成的导电沟道的长度方向相垂直的方向。In the above embodiment, the width of the intermediate region 113 in the first direction is greater than the width of the correspondingly disposed semiconductor layer in the first direction, the first direction being the source electrode 13 and the The length direction of the conductive channel formed between the drain electrodes 14 is perpendicular.
当然，在本公开的其他实施例中，所述中间区域113在第一方向上的宽度也可以等于对应设置的所述半导体层在所述第一方向上的宽度。Of course, in other embodiments of the present disclosure, the width of the intermediate region 113 in the first direction may also be equal to the width of the correspondingly disposed semiconductor layer in the first direction.
上述实施例中，所述中间区域113为矩形，所述第一区域111和所述第二区域112的形状相同，均为三角形。当然，所述栅电极11的形状并不限于此，在本公开的其他实施例中，所述栅电极也可以为其他形状，例如，参见附图3，所述第一区域111和所述第二区域112的形状均为梯形，或者任意形 状的多边形或者弧形等。In the above embodiment, the intermediate portion 113 is rectangular, and the first region 111 and the second region 112 have the same shape and are all triangular. Of course, the shape of the gate electrode 11 is not limited thereto. In other embodiments of the present disclosure, the gate electrode may also have other shapes. For example, referring to FIG. 3, the first region 111 and the first The shape of the two regions 112 is trapezoidal or arbitrary Polygon or curved shape.
本公开实施例中，所述半导体层12可以为低温多晶硅半导体层，也可以为非晶硅半导体层等。In the embodiment of the present disclosure, the semiconductor layer 12 may be a low temperature polysilicon semiconductor layer, or may be an amorphous silicon semiconductor layer or the like.
本公开实施例还提供一种阵列基板，包括上述薄膜晶体管。Embodiments of the present disclosure also provide an array substrate including the above thin film transistor.
本公开实施例还提供一种显示装置，包括上述阵列基板。An embodiment of the present disclosure further provides a display device including the above array substrate.
以上所述是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。 The above is a preferred embodiment of the present disclosure, and it should be noted that those skilled in the art can also make several improvements and refinements without departing from the principles of the present disclosure. It should be considered as the scope of protection of this disclosure.

Claims (8)

  1. 一种薄膜晶体管，包括：栅电极、栅绝缘层、半导体层、源电极及漏电极，其中，所述栅电极包括：位于所述源电极侧的第一区域，位于所述漏电极侧的第二区域，以及位于所述第一区域和所述第二区域之间的中间区域，其中，所述中间区域完全覆盖与所述中间区域对应设置的所述半导体层，所述第一区域和所述第二区域中的至少一个覆盖对应设置的所述半导体层的部分区域。A thin film transistor includes: a gate electrode, a gate insulating layer, a semiconductor layer, a source electrode, and a drain electrode, wherein the gate electrode includes: a first region on the source electrode side, and a first electrode on the drain electrode side a second region, and an intermediate region between the first region and the second region, wherein the intermediate region completely covers the semiconductor layer disposed corresponding to the intermediate region, the first region and At least one of the second regions covers a portion of the semiconductor layer that is disposed correspondingly.
  2. 根据权利要求1所述的薄膜晶体管，其中，所述中间区域在第一方向上的宽度大于或等于对应设置的所述半导体层在所述第一方向上的宽度，所述第一方向为与所述源电极和所述漏电极之间形成的导电沟道的长度方向相垂直的方向。The thin film transistor according to claim 1, wherein a width of the intermediate portion in the first direction is greater than or equal to a width of the correspondingly disposed semiconductor layer in the first direction, the first direction being A direction in which a length direction of the conductive channel formed between the source electrode and the drain electrode is perpendicular.
  3. 根据权利要求1所述的薄膜晶体管，其中，所述中间区域为矩形，所述第一区域和所述第二区域均为三角形。The thin film transistor according to claim 1, wherein the intermediate portion is a rectangle, and the first region and the second region are both triangular.
  4. 根据权利要求1所述的薄膜晶体管，其中，所述中间区域为矩形，所述第一区域和所述第二区域均为梯形。The thin film transistor according to claim 1, wherein the intermediate portion is a rectangle, and the first region and the second region are both trapezoidal.
  5. 根据权利要求1-4任一项所述的薄膜晶体管，其中，所述半导体层为低温多晶硅半导体层。The thin film transistor according to any one of claims 1 to 4, wherein the semiconductor layer is a low temperature polysilicon semiconductor layer.
  6. 根据权利要求1-4任一项所述的薄膜晶体管，其中，所述半导体层为非晶硅半导体层。The thin film transistor according to any one of claims 1 to 4, wherein the semiconductor layer is an amorphous silicon semiconductor layer.
  7. 一种阵列基板，包括如权利要求1-6任一项所述的薄膜晶体管。An array substrate comprising the thin film transistor according to any one of claims 1-6.
  8. 一种显示装置，包括如权利要求7所述的阵列基板。 A display device comprising the array substrate of claim 7.
PCT/CN2014/088896 2014-07-15 2014-10-20 Thin-film transistor, array substrate and display apparatus WO2016008224A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201410337121.5 2014-07-15
CN201410337121.5A CN104134699A (en) 2014-07-15 2014-07-15 Thin film transistor, array substrate and display device

Publications (1)

Publication Number Publication Date
WO2016008224A1 true WO2016008224A1 (en) 2016-01-21

Family

ID=51807303

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2014/088896 WO2016008224A1 (en) 2014-07-15 2014-10-20 Thin-film transistor, array substrate and display apparatus

Country Status (2)

Country Link
CN (1) CN104134699A (en)
WO (1) WO2016008224A1 (en)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05275698A (en) * 1992-03-27 1993-10-22 Sony Corp Thin film transistor
CN1828909A (en) * 2005-02-11 2006-09-06 三星电子株式会社 TFT substrate for display device and manufacturing method of the same
US20100051948A1 (en) * 2008-09-01 2010-03-04 Seiko Epson Corporation Thin film transistor, electro-optic device, and electronic apparatus
US20110024763A1 (en) * 2009-07-30 2011-02-03 Hitachi Display, Ltd. Display device and manufacturing method thereof
CN102194886A (en) * 2010-03-10 2011-09-21 三星移动显示器株式会社 Thin film transistor, method of manufacturing the same, and display device having thin film transistor
CN102034873B (en) * 2009-09-30 2014-04-16 索尼公司 Thin film transistor and method for manufacturing the same
CN203941905U (en) * 2014-07-15 2014-11-12 京东方科技集团股份有限公司 A kind of thin-film transistor, array base palte and display unit

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120032172A1 (en) * 2010-08-06 2012-02-09 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
KR101286526B1 (en) * 2012-01-20 2013-07-19 동아대학교 산학협력단 Thin film transistor and manufacturing method thereof

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05275698A (en) * 1992-03-27 1993-10-22 Sony Corp Thin film transistor
CN1828909A (en) * 2005-02-11 2006-09-06 三星电子株式会社 TFT substrate for display device and manufacturing method of the same
US20100051948A1 (en) * 2008-09-01 2010-03-04 Seiko Epson Corporation Thin film transistor, electro-optic device, and electronic apparatus
US20110024763A1 (en) * 2009-07-30 2011-02-03 Hitachi Display, Ltd. Display device and manufacturing method thereof
CN102034873B (en) * 2009-09-30 2014-04-16 索尼公司 Thin film transistor and method for manufacturing the same
CN102194886A (en) * 2010-03-10 2011-09-21 三星移动显示器株式会社 Thin film transistor, method of manufacturing the same, and display device having thin film transistor
CN203941905U (en) * 2014-07-15 2014-11-12 京东方科技集团股份有限公司 A kind of thin-film transistor, array base palte and display unit

Also Published As

Publication number Publication date
CN104134699A (en) 2014-11-05

Similar Documents

Publication Publication Date Title
US10395931B2 (en) LDMOS transistor, ESD device, and fabrication method thereof
US7449717B2 (en) Asymmetry thin-film transistor
US8993425B2 (en) Tunneling field effect transistor (TFET) formed by asymmetric ion implantation and method of making same
WO2015096605A1 (en) Split-gate power semiconductor field-effect transistor
WO2017156899A1 (en) Array substrate, liquid crystal display panel and liquid crystal display device
KR102281848B1 (en) Thin film transistor and method of manufacturing the same
US8829576B2 (en) Semiconductor structure and method of manufacturing the same
US10158027B2 (en) Semiconductor device and method for manufacturing same
US20140061792A1 (en) Field effect transistor devices with recessed gates
US9627543B2 (en) Thin film transistor and method for manufacturing the same, array substrate including the thin film transistor and display device including the array substrate
US9620640B2 (en) Body-contact metal-oxide-semiconductor field effect transistor device
US20140217398A1 (en) Thin-film transistor device and thin-film transistor display apparatus
US9614095B2 (en) Semiconductor device
WO2016008224A1 (en) Thin-film transistor, array substrate and display apparatus
CN100481515C (en) Unsymmetrical thin-film transistor structure
CN203941905U (en) A kind of thin-film transistor, array base palte and display unit
US20180197996A1 (en) Array substrate, and display device, and fabrication methods
JP7403225B2 (en) Array substrate and its manufacturing method, display panel and display device
US20190319134A1 (en) Thin film transistor array substrate, low temperature poly-silicon thin film transistor, and method for manufacturing low temperature poly-silicon thin film transistor
US9793302B1 (en) Active device
US9368618B2 (en) Semiconductor structure
JPH11233781A (en) Thin film transistor
TWI676289B (en) Semiconductor device and method for manufacturing the same
Chen et al. High performance four-masks GOLDD TFT structure without additional ion implantation
US20160343873A1 (en) Thin film transistor and manufacturing method thereof

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 14897876

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 18.05.2017)

122 Ep: pct application non-entry in european phase

Ref document number: 14897876

Country of ref document: EP

Kind code of ref document: A1