JPH05275698A - Thin film transistor - Google Patents

Abstract

PURPOSE:To provide a thin film transistor having less parasitic capacitance between a source/drain and a gate and less leakage current. CONSTITUTION:A thin film transistor is formed on an insulating substrate 1. The transistor is of inversely staggered structure, where a gate insulating film 3, a semiconductor active layer 4, a source electrode 7, and a drain electrode 8 are successively laminated on a gate electrode 2. The gate electrode 2 is provided with rugged side faces along the crosswise direction of a channel region. The ends of the source electrode 7 and the drain electrode 8 are matched to the rugged end faces of the gate electrode 2 and and small in overlap area with the gate electrode 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor used for a pixel driving switching element of an active matrix type liquid crystal display device. More specifically, it relates to a gate electrode structure of a thin film transistor.

[0002]

2. Description of the Related Art A thin film transistor is an insulated gate field effect transistor formed on a semiconductor thin film formed on an insulating substrate, and basically has a gate arranged on a channel region via an insulating film. It has an electrode and a source / drain connected to both ends of the channel region. Polycrystalline silicon or amorphous silicon is used as the semiconductor thin film material. There are a top gate type and a bottom gate type depending on the relative position of the gate electrode with respect to the channel region. Further, there are a planar type and a staggered type depending on the positional relationship between the channel region and the source / drain. In any structure, the gate electrode extends in the width direction of the channel region when seen in a plan view. Ideally, the ends of the source / drain connected to the channel region are preferably aligned with the ends of the gate electrode in plan view. However, in the thin film transistor having a laminated structure, the thin film transistors overlap each other in order to absorb an alignment error between the gate electrode and the source / drain. Since the insulating film is interposed in the overlap portion, a parasitic capacitance is generated between the gate electrode and the source / drain. This parasitic capacitance hinders the high speed operation of the thin film transistor. If such a thin film transistor is used for a pixel driving switching element of an active matrix type liquid crystal display device, the image quality is adversely affected. In order to remove the overlap, there is a method of forming source / drain regions by performing ion implantation by self-alignment using the gate electrode as a mask. However, since this self-alignment method cannot be applied depending on the structure of the thin film transistor, it cannot necessarily be a practical measure for removing overlap.

[0003]

Recently, an offset gate structure has been proposed for the purpose of suppressing the leak current of a thin film transistor. For example, it is disclosed in a document “Excimer laser annealing poly-Si TFT with low leak current, Kenji Sera et al., NEC Corporation”. FIG. 7 shows an example of the offset gate structure. This example is a top gate stagger type polycrystalline silicon thin film transistor. A source electrode 102 and a drain electrode 103 are formed on the insulating substrate 101 so as to be spaced apart from each other in the channel longitudinal direction. A polycrystalline silicon film 104 to be a semiconductor active layer is formed on it. The insulating film 10 is formed on the channel region 105.
The gate electrode 107 is formed by patterning via 6. The end portions of the source electrode 102 and the drain electrode 103 and the both end portions of the gate electrode 107 do not overlap with each other in plan view and are provided with a predetermined amount of offset. The leakage current largely depends on the electric field strength at the drain end. By using an offset gate, the electric field applied to the drain end can be reduced and a low leakage current can be achieved. Although the leak current or the off current can be reduced as the offset length is increased, the leakage current or the off current is saturated for a certain length, and conversely the on current is significantly reduced. It is considered that the limit is about 1 μm, and this region is hereinafter referred to as an effective field.

The above-mentioned offset gate structure is intended to reduce the leak current, but since the source / drain and the gate do not overlap each other, the parasitic capacitance can be removed at the same time. However, the effective field is 1μ
Since it is about m, it is difficult to set the offset amount within this range in the actual manufacturing process in consideration of the alignment error. Therefore, it cannot be a reproducible measure for removing the parasitic capacitance.

In view of the above-mentioned problems or problems of the prior art, it is an object of the present invention to provide a thin film transistor having a gate structure capable of absorbing an alignment error, removing a parasitic capacitance and reducing a leak current. To do.

[0006]

In order to achieve the object of the present invention, the following means were taken. That is, the present invention is characterized in that a thin film transistor formed on an insulating substrate is provided with a gate electrode having an uneven end face shape along the width direction of the channel region. A thin film transistor having such a gate structure is applied to, for example, a pixel electrode driving switching element of an active matrix type liquid crystal display device.

[0007]

According to the present invention, the gate electrode has an uneven end face shape along the width direction of the channel region. In other words,
An uneven band is provided along both side edges of the gate electrode. The ends of the source / drain are aligned with this uneven band. In other words, the source / drain end portions overlap the gate electrode in plan view in the convex portion and are separated in the concave portion. Since the offset gate structure is formed at least in the concave portion, the parasitic capacitance can be reduced as compared with the conventional case. Further, since the offset gate structure is partially provided, it is possible to reduce the leak current as compared with the conventional one. Further, the uneven strip has a complicated and complicated shape, and the effective field is uniformly distributed. Since the source / drain ends match this effective field, sufficient on-current can be obtained. In addition, an alignment error can be absorbed by taking a sufficient width of the uneven band.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 shows a first embodiment of the thin film transistor according to the present invention. The upper part of FIG. 1 shows a cross-sectional shape cut along the channel longitudinal direction, and the lower part shows a planar shape. This embodiment is a bottom gate inverted stagger type.
A gate electrode 2 patterned in a predetermined shape is formed on an insulating substrate 1. A semiconductor active layer 4 is provided on the gate electrode 2 with an insulating film 3 interposed therebetween and patterned into a predetermined shape. The active layer 4 is made of, for example, a polycrystalline silicon thin film or an amorphous silicon thin film. The exposed portion of the active layer 4 is covered with a stopper 5, and a channel region is formed thereunder. A source electrode 7 is connected to one end of the channel region via an intervening layer 6. Similarly, the drain electrode 8 is connected to the other end of the channel region through the intervening layer 6. The intervening layer 6 is for making ohmic contact between the electrode and the active layer, and is made of, for example, a polycrystalline silicon thin film doped with a high concentration of impurities.

When viewed in a plan view, the gate electrode 2 has an uneven end face shape along the width direction of the channel region. In this embodiment, the uneven end face has a rectangular shape. The end or edge of the source electrode 7 is aligned with the uneven strip located on one side of the gate electrode 2. Further, the end portion or edge of the drain electrode 8 is aligned with the uneven band located on the other side of the gate electrode 2. In other words, each edge portion overlaps the gate electrode 2 at the convex portion and is separated from the gate electrode at the concave portion.

The function of the present invention will be described in detail with reference to FIG. FIG. 2 is an enlarged view of the matching portion between the gate electrode 2 and the drain electrode 8. The edge 9 of the drain electrode 8 crosses the convex portion 10 of the gate electrode 2 and partially overlaps. However, in the concave portion 11 located between the adjacent convex portions 10, the edge 9 is separated from the gate electrode 2 and has an offset structure. Therefore, in this portion, the parasitic capacitance between the gate electrode 2 and the drain electrode 8 is extremely small. In addition, since the electric field strength at the drain end is weakened in the recess 11, the leak current can be suppressed.

The area indicated by the dotted line represents the effective field 12 of the gate electrode 2 described above. As described above, the width of the effective field 12 is about 1 μm. In the present invention, the effective field 12 is designed to fill the concave portion 11 or the valley by appropriately setting the shape dimensions of the concave and convex end faces. Therefore, the end portion of the drain electrode 8 uniformly overlaps the effective field 12 along the side portion of the gate electrode 2. Therefore, a sufficient on-current of the thin film transistor can be obtained as in the conventional case.

The alternate long and short dash line shows the alignment error of the edge 9 of the drain electrode 8 with respect to the gate electrode 2. The length dimension of the convex portion 10 is set so that this error can be absorbed. Therefore, the present invention can be carried out in an actual manufacturing process with normal alignment accuracy without using a self-alignment technique as in the past.

FIG. 3 shows a second embodiment of the thin film transistor according to the present invention. This embodiment has a top gate positive stagger type structure. To facilitate understanding, the components corresponding to those in the first embodiment shown in FIG. 1 are designated by the corresponding reference numerals. A source electrode 7 and a drain electrode 8 are formed on the insulating substrate 1 so as to be separated from each other. The surfaces of these electrodes are covered with an intervening layer 6. Further, the semiconductor active layer 4 is formed. The active layer 4 is made of, for example, a polycrystalline silicon thin film or an amorphous silicon thin film. A gate electrode 2 patterned in a predetermined shape is provided on the active layer 4 via a gate insulating film 3.
The gate electrode 2 has a predetermined irregular end face shape along the width direction of the channel region.

FIG. 4 shows a plan view of the second embodiment shown in FIG. In this example, the gate electrode 2 has a triangular uneven portion. The source electrode 7 and the drain electrode 8 are formed so as to be aligned with this uneven portion. Figure 1
As is apparent from the comparison between FIG. 4 and FIG. 4, the overlapping area of the source electrode 7 and the drain electrode 8 and the gate electrode 2 is smaller when the triangular concave-convex shape is used as compared with the rectangular concave-convex shape. Therefore, the parasitic capacitance between the gate and the source / drain can be reduced more effectively.

FIG. 5 shows a third embodiment of the thin film transistor according to the present invention. In this example, the thin film transistor has a top gate planar structure and is used as a pixel driving switching element of an active matrix liquid crystal display device. For easier understanding,
Components corresponding to those in the previous embodiment are designated by corresponding reference numbers. On the surface of the insulating substrate 1, an island-shaped patterned semiconductor active layer 4 is formed. The active layer 4 is made of, for example, a polycrystalline silicon thin film or an amorphous silicon thin film. The island-shaped active layer 4 is partially doped with impurities at a high concentration and has a source region 7 and a drain region 8. Source region 7 and drain region 8
A gate electrode 2 patterned in a predetermined shape is formed on the channel region located between the two via a gate insulating film 3. The gate electrode 2 has an uneven end face shape along the width direction of the channel region.

The surface of the planar type thin film transistor having such a structure is covered with a first interlayer insulating film 13. A pixel electrode 14 made of a transparent conductive thin film is patterned on the surface of the interlayer insulating film 13 and is electrically connected to the drain region 8 through a contact hole.
A wiring electrode 15 made of metal aluminum or the like is also formed and electrically connected to the source region 7 through the contact hole. Finally, only the pixel electrode 14 is exposed to cover the second interlayer insulating film 16 or the protective film.

On the other hand, a counter electrode 18 is entirely formed on the surface of the other substrate 17 which is arranged to face the insulating substrate 1 with a predetermined gap. A liquid crystal layer 19 is filled and sealed between the two substrates 1 and 17 to form an active matrix type liquid crystal display device. The pixel electrodes 14 are arranged in a matrix and define the individual pixels together with the counter electrode 18. Each pixel is switching-driven by the corresponding thin film transistor.

FIG. 6 shows a plan view of the third embodiment shown in FIG. In this example, the gate electrode 2 has a corrugated end face shape. Only the corrugated convex portion overlaps the source region 7 and the drain region 8, so that the parasitic capacitance can be reduced as compared with the conventional case. When a thin film transistor having such a structure is used as a pixel driving switching transistor of an active matrix liquid crystal display device as shown in FIG. 5, it is possible to prevent deterioration of display image quality due to parasitic capacitance.

The application of the present invention is not limited to the above embodiment. Top gate type and bottom gate type,
It is widely applicable to various types of structures such as a planar type, a staggered type, a polycrystalline silicon transistor and an amorphous silicon thin film transistor. In particular, the present invention is effective for a structure to which the self-alignment technique cannot be applied.

[0020]

As described above, according to the present invention, in the thin film transistor formed on the insulating substrate, the gate electrode has a concavo-convex end face shape along the width direction of the channel region. The overlap area with the gate is reduced. Therefore, there is an effect that the parasitic capacitance between the source / drain and the gate is reduced and the speed of the thin film transistor can be increased. In particular, when a thin film transistor having such a structure is used for a pixel driving switching element of an active matrix type liquid crystal display device, the absolute value of the parasitic capacitance can be suppressed low and the variation of the capacitance can be suppressed, so that the display image quality is improved The effect is that you can do things. In addition, since it partially has the offset structure, there is an effect that the leak current or the off current of the thin film transistor can be reduced. Further, unlike the conventional self-alignment technique, there is an effect on the manufacturing technique that it can be applied to, for example, a bottom gate type thin film transistor.

[Brief description of drawings]

FIG. 1 is a schematic view showing a cross-sectional shape and a planar shape of a first embodiment of a thin film transistor according to the present invention.

FIG. 2 is a functional explanatory diagram of the present invention.

FIG. 3 is a cross-sectional view showing a second embodiment of the thin film transistor according to the present invention.

FIG. 4 is a plan view showing a second embodiment of the same.

FIG. 5 is a schematic cross-sectional view showing a third embodiment of a thin film transistor according to the present invention, showing a case where it is applied to a pixel driving switching element of an active matrix liquid crystal display device.

FIG. 6 is a plan view of a third embodiment.

FIG. 7 is a schematic sectional view showing a thin film transistor having a conventional offset gate structure.

[Explanation of symbols]

 1 Insulating Substrate 2 Gate Electrode 3 Insulating Film 4 Semiconductor Active Layer 5 Stopper 6 Intervening Layer 7 Source Electrode 8 Drain Electrode 9 Edge 10 Convex 11 Concave 12 Effective Field 14 Pixel Electrode 17 Counter Substrate 18 Counter Electrode 19 Liquid Crystal Layer

Claims (2)

[Claims] 1. A thin film transistor formed on an insulating substrate, comprising a gate electrode having an uneven end face shape along a width direction of a channel region. 2. One substrate having pixel electrodes arranged in a matrix and thin film transistors connected to the pixel electrodes, and the other substrate having a counter electrode and arranged to face the one substrate. A liquid crystal display device comprising a liquid crystal layer held on both substrates, wherein the thin film transistor includes a gate electrode having an uneven end face shape along a width direction of a channel region.