WO2016008194A1 - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
WO2016008194A1
WO2016008194A1 PCT/CN2014/084513 CN2014084513W WO2016008194A1 WO 2016008194 A1 WO2016008194 A1 WO 2016008194A1 CN 2014084513 W CN2014084513 W CN 2014084513W WO 2016008194 A1 WO2016008194 A1 WO 2016008194A1
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semiconductor layer
substrate
semiconductor
layer
isolation structure
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PCT/CN2014/084513
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English (en)
French (fr)
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许静
闫江
陈邦明
王红丽
唐波
唐兆云
徐烨锋
李春龙
杨萌萌
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中国科学院微电子研究所
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Priority to US14/391,889 priority Critical patent/US20160293695A1/en
Publication of WO2016008194A1 publication Critical patent/WO2016008194A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/764—Air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present invention relates to the field of semiconductor devices, and in particular, to a semiconductor device and a method of fabricating the same. Background technique
  • the channel length of MOSFETs is shortening.
  • a series of negligible effects in the long channel model of MOSFETs become more and more obvious, and even become the dominant factor affecting device performance. Short channel effect. Short channel effects can degrade the electrical performance of the device, such as causing gate threshold voltage drops, increased power consumption, and reduced signal-to-noise ratio.
  • the SOI substrate is embedded with a silicon dioxide layer under the silicon.
  • the device formed by the SOI substrate can significantly reduce leakage current and power consumption, improve short channel effect, and has obvious performance advantages.
  • the cost of the SOI substrate is high, and a larger device area is required to avoid the floating body effect, which is difficult to meet the requirements of high integration of the device, and the heat dissipation of the device due to the embedded silicon dioxide layer. Performance is affected. Summary of the invention
  • An object of the present invention is to provide at least one of the above technical drawbacks, and to provide a semiconductor device and a method of fabricating the same.
  • the present invention provides a semiconductor device comprising:
  • a second semiconductor layer overlying the substrate;
  • a third semiconductor layer located above the second semiconductor layer, is a device formation region;
  • an isolation structure is located on both sides of the third semiconductor layer and over the substrate;
  • the substrate is a bulk silicon substrate
  • the second semiconductor layer is Ge ⁇ i ⁇ , 0 ⁇ 1
  • the third semiconductor layer is silicon
  • it also includes:
  • An oxide layer is on the surface of the semiconductor material that makes up the cavity.
  • an oxide layer is also formed between the isolation structure and the substrate and between the third semiconductor layer and the isolation structure.
  • the present invention also provides a method of fabricating a semiconductor device, comprising the steps of: providing a substrate, the substrate having a first semiconductor material;
  • the third semiconductor layer is a device formation region, and the opening is located under the source and drain regions of the third semiconductor layer.
  • the substrate is a bulk silicon substrate
  • the step of forming the second semiconductor layer and the third semiconductor layer is specifically:
  • the second semiconductor layer and the third semiconductor layer are patterned.
  • the step of removing a portion of the second semiconductor layer from the end of the second semiconductor layer to form the opening comprises:
  • the second semiconductor layer is selectively removed by wet etching to form an opening at the end of the second semiconductor layer.
  • the wet etching etchant is a mixture of HF, H 2 O 2 , C 3 ⁇ 4 COOH, and H 2 0.
  • the method further includes the steps of:
  • an oxide layer is formed on the inner wall of the opening.
  • the step of forming an oxide layer on the inner wall of the opening specifically includes:
  • Oxidation is performed to form an oxide layer on the exposed surface of the substrate, the second semiconductor layer, and the third semiconductor layer.
  • a semiconductor device and a method of fabricating the same according to embodiments of the present invention have a structure in which a cavity is formed under a source/drain region of a third semiconductor layer forming a device, and a semiconductor layer under the channel region of the third semiconductor layer is a semiconductor layer.
  • Such a device structure has the advantages of both bulk silicon devices and SOI devices, and has the characteristics of low cost, low leakage current, low power consumption, high speed, relatively simple process and high integration. At the same time, with
  • the present invention is directed to a semiconductor device.
  • the semiconductor device includes: a substrate 10, the substrate being a first semiconductor material;
  • the second semiconductor layer 11 is located on the substrate 10;
  • the third semiconductor layer 12 is located above the second semiconductor layer 11 as a device formation region; the isolation structure 16 is located on both sides of the third semiconductor layer 12 and over the substrate 10;
  • the cavity 22 is located under the source and drain regions 31 of the third semiconductor layer, between the isolation structure 16 and the end of the second semiconductor layer 11.
  • a second semiconductor layer is formed over the substrate, and a second semiconductor layer for forming a device is formed over the second semiconductor layer, the second semiconductor being formed only in the channel region of the third semiconductor layer
  • a structure having a cavity is formed between the second semiconductor layer and the isolation and under the source and drain regions, so that the leakage current and power consumption of the device are significantly reduced due to the presence of the cavity, and the device integration is increased. degree.
  • the channel region is connected to the substrate under the channel region, which has better heat dissipation performance and avoids the floating body effect.
  • the device can use bulk silicon as the substrate, the limitation of the excessive cost of the SOI wafer is avoided.
  • the lower dielectric constant of the cavity allows the device to withstand higher voltages.
  • the device of the present invention can be applied to a strong radiation environment, such as a strategic weapon. Since there is no silicon oxide insulating layer under the channel, the area of the radiation sensitive area is reduced, and the back gate can be adjusted, and the release portion can be released. The electron-hole pair caused by irradiation avoids the floating body effect caused by irradiation.
  • the material of the substrate, the second semiconductor layer, and the third semiconductor layer may be selected according to the requirements of the device in the manufacturing process and the requirements of the device performance, and the same or different semiconductor materials may be used, in the preferred implementation of the present invention.
  • the substrate is a bulk silicon substrate
  • the second semiconductor layer is
  • the third semiconductor layer is silicon.
  • the selection of such a semiconductor material facilitates the formation of the second and third semiconductor layers of the crystal by epitaxial growth, and the device has more excellent performance.
  • an oxide layer 15 is formed on the surface of the semiconductor material of the cavity, that is, the surface of the third semiconductor layer in the cavity, the side surface of the second semiconductor layer, and the oxide layer are formed on the surface of the substrate, further An oxide layer 15 is also formed between the third semiconductor layer 12 and the isolation structure 16 and between the substrate 10 and the isolation structure 16.
  • the formation of the oxide layer can eliminate surface defects formed during etching and the like. , to make the surface flat.
  • the oxide layer 15 may be an ultra-thin oxide layer having a thickness of 10-100 ⁇ .
  • the present invention also provides a method of fabricating the above-described semiconductor device.
  • a specific embodiment will be described in detail below with reference to the flowchart.
  • a substrate 10 is provided, which is a first semiconductor material, as shown in Fig. 1.
  • the substrate is a semiconductor substrate, preferably a two-body substrate having a single semiconductor material, and may be, for example, a Si substrate, a Ge substrate, a SiGe substrate, or may include other elemental semiconductors or compound semiconductors.
  • a substrate such as GaAs, InP or SiC, etc., in this embodiment,
  • the substrate is a bulk silicon substrate.
  • a second semiconductor layer 11 is formed on the substrate, and a third semiconductor layer 12 is formed on the second semiconductor layer 11, as shown in Fig. 2.
  • a second semiconductor material 11 of Ge x — x and a third semiconductor material 12 of silicon are sequentially epitaxially grown on the bulk silicon substrate 10, wherein, 0
  • a hard mask material such as silicon nitride is deposited on the third semiconductor material 12, and then a photoresist is applied and etched to form a patterned hard mask 13 and The photosensitive etchant is removed, and the pattern of the hard mask is to form an active region of the device; then, under the mask of the hard mask 13, etching is continued to form the patterned second semiconductor layer 11 and the third semiconductor Layer 12, as shown in Figure 2.
  • a portion of the second semiconductor layer 11 may be selectively removed by wet etching.
  • the solvent may be 49% HF, 30% H 2 O 2 , 99.8% of a mixed solution of CH 3 COOH and H 2 0 in a ratio of 1:18:27:8.
  • an oxide layer 15 is formed on the inner wall of the opening 20, as shown in Fig. 4.
  • an ultra-thin oxide layer is formed by a dry oxidation method such as rapid thermal oxidation, and may have a thickness of 10 to 100 ⁇ .
  • a dry oxidation method such as rapid thermal oxidation
  • an oxide layer is formed on the surface of the exposed semiconductor material, that is, an oxide layer is formed on the inner wall of the opening, on the substrate, and on the sidewall of the third semiconductor layer, so that the etching process is Defects formed on the surface of the semiconductor layer are repaired, and the surface of the exposed semiconductor material is flatter.
  • the read isolation structure 16 is formed on both sides of the third semiconductor layer 12 and over the substrate, as shown in FIG.
  • the read isolation structure 16 can be formed by a conventional process. First, deposition of a dielectric material, such as silicon oxide, is performed; then, planarization is performed, such as chemical mechanical polishing (CMP), until the hard mask is exposed. The surface of 13, then, further, the hard mask 13 can be removed until the surface of the third semiconductor layer 12 is exposed, thereby forming the isolation structure 16 and the cavity 22.
  • CMP chemical mechanical polishing
  • processing of the device is performed to form the semiconductor device 30 on the third semiconductor layer, as shown in FIG. Shown.
  • the device can be formed in accordance with a conventional process.
  • the CMOS device 30 is formed.
  • the well doping is formed in the second semiconductor layer 11 and the third semiconductor layer 12, and can be further formed to the In a portion of the substrate under the second semiconductor layer, a gate structure 33 is formed over the third semiconductor layer 12; a sidewall spacer 34 is formed on the sidewall of the gate structure 33; and a third semiconductor on both sides of the gate electrode
  • a source/drain region 31 is formed in the layer, and a read source drain region is located above the cavity 22; a metal silicide layer 35 is also formed over the source and drain regions 31.
  • Other components of the device such as source-drain contacts, gate contacts, interconnect structures, and the like, can also be formed.

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Abstract

一种半导体器件，包括：衬底，所述衬底具有第一半导体材料；第二半导体层，位于衬底之上；第三半导体层，位于第二半导体层之上，为器件形成区域；隔离结构，位于第三半导体层两侧、衬底之上；空腔，位于第三半导体层的源漏区域之下、隔离结构与第二半导体层端部之间。上述器件结构，同时具有体硅器件和SOI器件的各自优势，具有低成本、漏电小、功耗低、速度快、工艺较为简单且集成度高的特点。同时，与SOI器件相比，消除了浮体效应和自热效应。此外，空腔处较低的介电常数，使得其可承受较高的电压。

Description

半导体器件及其制造方法
本申请要求了 2014年 7月 16日提交的、 申请号为 201410340090.9、发明 名称为 "半导体器件及其制造方法" 的中国专利申请的优先权， 其全部内容通 过引用结合在本申请中。 技术领域
本发明涉及半导体器件领域， 特别涉及一种半导体器件及其制造方法。 背景技术
随着器件尺寸的不断缩小，单位面积芯片上的器件数目越来越多，这会导 致动态功耗的增加， 同时， 器件尺寸的不断缩小必然引起漏电流的增加， 进而 引起静态功耗的增加， 而随着半导体器件的高度集成， MOSFET 沟道长度不 断缩短， 一系列在 MOSFET长沟道模型中可以忽略的效应变得愈发显著， 甚 至成为影响器件性能的主导因素，这种现象统称为短沟道效应。短沟道效应会 恶化器件的电学性能，如造成栅极阈值电压下降、功耗增加以及信噪比下降等 问题。
SOI衬底是在硅的下方嵌入了二氧化硅层， 相对于体硅器件， SOI衬底形 成的器件可以明显减小漏电流和功耗，改善短沟道效应，具有明显的性能优势。 然而， SOI衬底的造价较高， 并需要更大的器件面积以避免浮体效应（Floating Body Effect ), 难以满足器件高度集成化的要求， 此外， 由于嵌入了二氧化硅 层， 其器件的散热性能受到影响。 发明内容
本发明的目的旨在至少解决上述技术缺陷之一，提供一种半导体器件及其 制造方法。
本发明提供了一种半导体器件， 包括：
衬底， 所述衬底具有第一半导体材料；
第二半导体层， 位于衬底之上； 第三半导体层， 位于第二半导体层之上， 为器件形成区域； 隔离结构， 位于第三半导体层两侧、 衬底之上；
空腔，位于第三半导体层的源漏区域之下、 隔离结构与第二半导体层端部 之间。
可选的， 所述衬底为体硅衬底， 第二半导体层为 Ge^i^, 0<χ<1 , 第三半 导体层为硅。
可选的， 还包括：
氧化物层， 位于构成空腔的半导体材料的表面上。
可选的，在隔离结构与衬底之间以及第三半导体层与隔离结构之间也形成 有氧化物层。
此外， 本发明还提供了一种半导体器件的制造方法， 包括步骤： 提供衬底， 所述衬底具有第一半导体材料；
在衬底上形成第二半导体层， 以及在第二半导体层上形成第三半导体层； 从第二半导体层的端部去除部分的第二半导体层， 以形成开口； 在第三半导体层两侧、 衬底之上形成隔离结构；
其中， 第三半导体层为器件形成区域， 开口位于第三半导体层的源漏区域 之下。
可选的， 所述衬底为体硅衬底，形成第二半导体层和第三半导体层的步骤 具体为：
在衬底上外延生长 GexSi 的第二半导体层， 0<χ<1 ;
在第二半导体层上外延生长硅的第三半导体层；
图案化所述第二半导体层及第三半导体层。
可选的，从第二半导体层的端部去除部分的第二半导体层， 以形成开口的 步骤具体包括：
采用湿法刻蚀，选择性去除第二半导体层， 以在第二半导体层的端部形成 开口。
可选的， 湿法刻蚀的刻蚀剂为 HF、 H202、 C¾COOH和 H20的混合液。 可选的， 在形成开口与形成隔离结构之间， 还包括步骤：
在开口的内壁上形成氧化物层。 可选的， 在开口的内壁上形成氧化物层的步骤具体包括：
进行氧化， 在衬底、 第二半导体层、 第三半导体层的暴露的表面上形成氧 化层。
本发明实施例提供的半导体器件及其制造方法，在形成器件的第三半导体 层的源漏区域之下形成有空腔的结构，且第三半导体层的沟道区域之下为半导 体层。 这样的器件结构， 同时具有体硅器件和 SOI 器件的各自优势， 具有低 成本、 漏电小、 功耗低、 速度快、 工艺较为筒单且集成度高的特点。 同时， 与
SOI器件相比， 消除了浮体效应和自热效应。 此外， 空腔处较低的介电常数， 使得其可承受较高的电压。 附图说明
本发明上述的和 /或附加的方面和优点从下面结合附图对实施例的描述中 将变得明显和容易理解， 其中： 图；
具体实施方式
下面详细描述本发明的实施例， 所述实施例的示例在附图中示出，其中自 件。 下面通过参考附图描述的实施例是示例性的， 仅用于解释本发明， 而不能 解释为对本发明的限制。
本发明旨在提出一种半导体器件， 参考图 6所示， 该半导体器件包括： 衬底 10， 所述衬底为第一半导体材料；
第二半导体层 11， 位于衬底 10之上；
第三半导体层 12, 位于第二半导体层 11之上， 为器件形成区域； 隔离结构 16， 位于第三半导体层 12两侧、 衬底 10之上；
空腔 22， 位于第三半导体层的源漏区域 31之下、 隔离结构 16与第二半 导体层 11端部之间。 在本发明中，在衬底之上形成了第二半导体层，该第二半导体层之上有用 于形成器件的第三半导体层，该第二半导体仅形成在第三半导体层的沟道区域 的下方， 而在第二半导体层与隔离之间、 源漏区域的下方形成有空腔的结构， 这样， 由于空腔的存在， 明显减小了器件的漏电流和功耗， 增加了器件的集成 度。 与 SOI 器件相比， 沟道区域下方与衬底相连， 具有更好的散热性能且避 免了浮体效应的产生。 同时， 由于器件可以采用体硅为衬底， 避免了 SOI 晶 圆成本过高的限制。 此外， 空腔处较低的空气介电常数， 使得器件可承受较高 的电压。
此外， 本发明的器件可适用于强辐射的环境， 如战略武器等， 由于沟道下 并无氧化硅的绝缘层， 减小了辐照敏感区域面积， 并可以通过背栅进行调节， 释放部分辐照引起的电子空穴对， 避免辐照引起的浮体效应。
在本发明中，可以根据器件在制造工艺中需要以及器件性能的需求，选择 衬底、 第二半导体层、 第三半导体层的材料， 可以采用相同或不同的半导体材 料，在本发明的优选实施例中，所述衬底为体硅衬底，第二半导体层为
Figure imgf000006_0001
0<χ<1， 第三半导体层为硅， 这种半导体材料的选择便于通过外延生长形成晶 体的第二、 第三半导体层， 器件具有更优异的性能。
此外， 在空腔的半导体材料的表面上形成有氧化物层 15， 即空腔中第三 半导体层的表面、 第二半导体层的侧面以及衬底的表面上形成有氧化物层， 更 进一步的， 在第三半导体层 12与隔离结构之间 16以及衬底 10与隔离结构之 间 16也形成有氧化物层 15, 该氧化物层的形成， 能够消除刻蚀等工艺过程中 形成的表面缺陷， 使得表面平坦化。 该氧化物层 15可以为超薄的氧化物层， 厚度在 10-100 A。
此外，本发明还提供了上述半导体器件的制造方法， 为了更好的理解本发 明的技术方案以及技术效果，以下将结合流程图 7对具体的实施例进行详细描 述。
首先， 提供衬底 10， 所述衬底为第一半导体材料， 参考图 1所示。
在本发明中所述衬底为半导体衬底，优选可以为具有单一半导体材料二体 衬底， 例如可以为 Si衬底、 Ge衬底、 SiGe衬底， 还可以为包括其他元素半导 体或化合物半导体的衬底， 例如 GaAs、 InP或 SiC等， 在本实施例中， 所述 衬底为体硅衬底。
而后， 在衬底上形成第二半导体层 11， 以及在第二半导体层 11上形成第 三半导体层 12， 参考图 2所示。
在本实施例中， 具体的， 首先， 如图 1所示， 在体硅衬底 10上依次通过 外延生长 Gex _x的第二半导体材料 11 和硅的第三半导体材料 12， 其中， 0<χ<1 ; 而后， 在第三半导体材料 12上淀积硬掩膜材料， 如氮化硅， 而后涂 抹光敏刻蚀剂 （photoresist ) 并进行刻蚀， 形成图案化的硬掩膜 13 , 并将光敏 刻蚀剂去除， 硬掩膜的图案是形成器件的有源区； 而后， 在该硬掩膜 13的掩 盖下， 继续进行刻蚀， 形成图案化的第二半导体层 11和第三半导体层 12， 如 图 2所示。
接着， 从第二半导体层 11的端部去除部分的第二半导体层， 以形成开口 20, 如图 3所示。
在本实施例中， 可以采用湿法刻蚀， 选择性的去除部分的第二半导体层 11，具体的，在一个优选实施例中，溶剂可以采用 49%的 HF、 30%H2O2、 99.8% 的 CH3COOH和 H20的混合溶液， 比例为 1： 18 :27 :8 , 通过控制时间， 去除两 端部分的第二半导体体层， 也即在有源区的源漏区下没有第二半导体层的支 撑， 为空的部分。
而后， 在开口 20的内壁上形成氧化物层 15， 参考图 4所示。
在本实施例中，通过干氧化法，如快速热氧化法，来形成超薄的氧化物层， 厚度可以为 10-100 A。热氧化后，在暴露的半导体材料的表面上都形成了氧化 物层，即开口的内壁上、衬底上以及第三半导体层的侧壁上都形成了氧化物层， 使得刻蚀过程中在半导体层表面形成的缺陷得以修复，暴露的半导体材料的表 面更平坦。
接着，在第三半导体层 12两侧、衬底之上形成隔离结构 16,如图 5所示。 在本实施例中， 可以通过传统工艺来形成读隔离结构 16， 首先， 进行介 质材料的淀积， 例如氧化硅； 而后， 进行平坦化， 例如进行化学机械研磨 ( CMP ), 直到暴露硬掩膜 13的表面， 而后， 进一步的可以将硬掩膜 13去除， 直到暴露第三半导体层 12的表面， 从而形成隔离结构 16以及空腔 22。
而后， 进行器件的加工， 以在第三半导体层上形成半导体器件 30， 如图 6 所示。
可以按照传统的工艺来形成器件， 本实施例中， 形成了 CMOS器件 30， 如图 6所示， 阱掺杂形成在第二半导体层 11和第三半导体层 12中，也可以进 一步形成至第二半导体层下的部分衬底中， 在第三半导体层 12之上形成了栅 极结构 33 ; 所述栅极结构 33的侧壁上形成了侧墙 34; 在栅极两侧的第三半导 体层中形成了源漏区 31， 读源漏区位于空腔 22之上； 在源漏区 31之上还形 成有金属硅化物层 35。 之后， 还可以形成器件的其他部件， 如源漏接触、 栅 极接触和互连结构等等。
以上所述，仅是本发明的较佳实施例而已， 并非对本发明作任何形式上的 限制。
虽然本发明已以较佳实施例披露如上， 然而并非用以限定本发明。任何熟 悉本领域的技术人员，在不脱离本发明技术方案范围情况下，都可利用上述揭 示的方法和技术内容对本发明技术方案做出许多可能的变动和修饰 ,或修改为 等同变化的等效实施例。 因此， 凡是未脱离本发明技术方案的内容， 依据本发 明的技术实质对以上实施例所做的任何筒单修改、等同变化及修饰， 均仍属于 本发明技术方案保护的范围内。

Claims

权利 要 求 书
1、 一种半导体器件， 其特征在于， 包括：
衬底， 所述衬底具有第一半导体材料；
第二半导体层， 位于衬底之上；
第三半导体层， 位于第二半导体层之上， 为器件形成区域；
隔离结构， 位于第三半导体层两侧、 衬底之上；
空腔，位于第三半导体层的源漏区域之下、 隔离结构与第二半导体层端部 之间。
2、 根据权利要求 1所述的半导体器件， 其特征在于， 所述衬底为体硅衬 底， 第二半导体层为
Figure imgf000009_0001
0<χ<1 , 第三半导体层为硅。
3、 根据权利要求 1所述的半导体器件， 其特征在于， 还包括：
氧化物层， 位于构成空腔的半导体材料的表面上。
4、 根据权利要求 3所述的半导体器件， 其特征在于， 在隔离结构与衬底 之间以及第三半导体层与隔离结构之间也形成有氧化物层。
5、 一种半导体器件的制造方法， 其特征在于， 包括步骤：
提供衬底， 所述衬底具有第一半导体材料；
在衬底上形成第二半导体层， 以及在第二半导体层上形成第三半导体层； 从第二半导体层的端部去除部分的第二半导体层， 以形成开口；
在第三半导体层两侧、 衬底之上形成隔离结构；
其中， 第三半导体层为器件形成区域， 开口位于第三半导体层的源漏区域 之下。
6、 根据权利要求 5所述的制造方法， 其特征在于， 所述衬底为体硅衬底， 形成第二半导体层和第三半导体层的步骤具体为：
在衬底上外延生长 GexSi 的第二半导体层， 0<χ<1 ;
在第二半导体层上外延生长硅的第三半导体层；
图案化所述第二半导体层及第三半导体层。
7、 根据权利要求 6所述的制造方法， 其特征在于， 从第二半导体层的端 部去除部分的第二半导体层， 以形成开口的步骤具体包括： 采用湿法刻蚀，选择性去除第二半导体层， 以在第二半导体层的端部形成 开口。
8、 根据权利要求 7所述的制造方法， 其特征在于， 湿法刻蚀的刻蚀剂为 HF、 H202、 C¾COOH和 H20的混合液。
9、 根据权利要求 5所述的制造方法， 其特征在于， 在形成开口与形成隔 离结构之间， 还包括步骤：
在开口的内壁上形成氧化物层。
10、 根据权利要求 9所述的制造方法， 其特征在于， 在开口的内壁上形成 氧化物层的步骤具体包括：
进行氧化， 在衬底、 第二半导体层、 第三半导体层的暴露的表面上形成氧 化层。
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