WO2016004573A1 - Procédé de formation d'interconnexion de métal - Google Patents

Procédé de formation d'interconnexion de métal Download PDF

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Publication number
WO2016004573A1
WO2016004573A1 PCT/CN2014/081790 CN2014081790W WO2016004573A1 WO 2016004573 A1 WO2016004573 A1 WO 2016004573A1 CN 2014081790 W CN2014081790 W CN 2014081790W WO 2016004573 A1 WO2016004573 A1 WO 2016004573A1
Authority
WO
WIPO (PCT)
Prior art keywords
barrier layer
oxide film
layer
recessed area
metal
Prior art date
Application number
PCT/CN2014/081790
Other languages
English (en)
Inventor
Jian Wang
Zhaowei Jia
Yinuo JIN
Dongfeng XIAO
Guipu YANG
Yingwei DAI
Hui Wang
Original Assignee
Acm Research (Shanghai) Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Acm Research (Shanghai) Inc. filed Critical Acm Research (Shanghai) Inc.
Priority to CN201480079797.7A priority Critical patent/CN106463455B/zh
Priority to JP2017501030A priority patent/JP6301003B2/ja
Priority to PCT/CN2014/081790 priority patent/WO2016004573A1/fr
Priority to KR1020177000636A priority patent/KR102247940B1/ko
Publication of WO2016004573A1 publication Critical patent/WO2016004573A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76865—Selective removal of parts of the layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation

Definitions

  • the present invention generally relates to a field of fabricating semiconductor devices, and more particularly relates to a method for forming metal interconnection, which can avoid over etching of a barrier layer deposited on sidewalls of trenches.
  • a method for forming copper interconnection generally includes the following steps: providing a substrate 101, such as a wafer; depositing a dielectric layer 102 on the substrate 101; depositing a hard mask layer 103 on the dielectric layer 102; forming trenches on the hard mask layer 103 and the dielectric layer 102, a trench 106 is shown as an example in FIG. 1(a) to FIG.
  • a traditional method for removing the copper 105, the barrier layer 104 and the hard mask layer 103 is CMP (chemical mechanical polishing).
  • CMP chemical mechanical polishing
  • the substrate 101 is positioned on a CMP pad located on a platen.
  • a force is applied to press the substrate 101 against the CMP pad.
  • the CMP pad and the substrate 101 are moved relatively to each other while applying the force to polish and planarize the copper 105, the barrier layer 104 and the hard mask layer 103.
  • a polishing solution often known as polishing slurry, is dispensed on the CMP pad to facilitate the polishing.
  • the CMP method has several deleterious effects on the semiconductor structure because of the relatively strong mechanical force involved.
  • the mechanical force can cause permanent damage to the low-k dielectric.
  • the polishing slurry can reduce the property of the low-k dielectric.
  • the aforesaid perfect barrier layer removing result means the barrier layer 104 deposited on the non-recessed area is absolutely removed and the barrier layer 104 deposited on the sidewalls of the trenches are not destroyed and etched, as shown in FIG. 1(c).
  • a dry etch method is used for removing the barrier layer 104 and the hard mask layer 103.
  • XeF 2 gas phase etching with a high temperature and low pressure environment is utilized to remove the barrier layer 104 and the hard mask layer 103 after removing copper 105 by CMP, where the material of the barrier layer 104 is Tantalum, Tantalum nitride, Titanium, or Titanium nitride and the material of the hard mask layer 103 is Titanium nitride.
  • the XeF 2 gas phase etching has no damage to the copper 105 and the dielectric layer 102.
  • FIG. 2 shows an under etching of the barrier layer 104. It can be seen from FIG. 2 that the barrier layer 104 on the non- recessed area is not completely removed and a part of barrier layer 104 is remained on the non-recessed area. As shown in FIG. 3, FIG. 3 shows an over etching of the barrier layer 104. It can be seen from FIG. 3 that although the barrier layer 104 on the non- recessed area is completely removed, but a part of the barrier layer 104 deposited on the sidewall of the trench 106 is also removed. The top surface of the barrier layer 104 in the trench 106 is lower than the top surface of the copper 105 in the trench 106. Whatever the under etching or over etching of the barrier layer 104 will reduce the quality of the semiconductor devices.
  • the present invention provides a method for forming metal interconnection, which avoids a barrier layer deposited on sidewalls of recessed areas being over etched.
  • a method for forming metal interconnection includes the following steps: forming a recessed area on a hard mask layer and a dielectric layer; depositing a barrier layer on the hard mask layer, sidewall of the recessed area and bottom of the recessed area; depositing metal on the barrier layer and filling the recessed area with the metal; removing the metal deposited on non-recessed area by electropolishing and the metal filled in the recessed area being over polished to form a dishing, an oxide film being formed on the barrier layer during the electropolishing process, the thickness of the oxide film on the barrier layer deposited on the sidewall of the recessed area being thicker than the oxide film on the barrier layer deposited on the hard mask layer; removing the oxide film on the barrier layer deposited on the hard mask layer, and retaining a certain thickness of oxide film on the barrier layer deposited on the sidewall of the recessed area; removing the barrier layer and the hard mask layer by etching which has a high selectivity to the oxide film, the retained oxide film
  • the exposed barrier layer is passivated by forming the oxide film on the barrier layer.
  • the dielectric layer is under the barrier layer and the hard mask layer, hence, charges are uniformly distributed in the conductive layer (composed of the barrier layer and the hard mask layer), and the charges will accumulate on the surface of the dielectric layer.
  • the charges distribution on the non-conductive material surface is inversely proportional to radius of curvature, therefore, more charges are accumulated on the shoulder of the barrier layer than the flat surface, so this area's oxide film is thicker than the other area's.
  • the thickness of the oxide film on the barrier layer deposited on the sidewall of the recessed area is thicker than the oxide film on the barrier layer deposited on the hard mask layer.
  • the retained oxide film on the barrier layer deposited on the sidewall of the recessed area forms a continue film on the barrier layer for preventing the barrier layer deposited on the sidewall of the recessed area from being over etched during removing the barrier layer and the hard mask layer, which improves the quality of semiconductor devices.
  • FIGS. 1(a) to 1(c) are sectional views illustrating a process of forming metal interconnection;
  • FIG. 2 is a sectional view illustrating under etching of a barrier layer;
  • FIG. 3 is a sectional view illustrating over etching of the barrier layer
  • FIGS. 4(a) to 4(d) are sectional views illustrating a method for forming metal interconnection of the present invention.
  • FIG. 5 is a flow chart illustrating the method for forming metal interconnection of the present invention
  • FIG. 6 illustrates a measuring result of weight percentage content of oxygen element after electropolishing process
  • FIG. 7 illustrates STEM cross section of POST-TFE sample, showing a perfect barrier layer removing result
  • FIG. 8 illustrates FIB/SEM cross section of POST-TFE sample, showing over etching of a barrier layer.
  • FIGS. 4(a) to 4(d) and FIG. 5 a method for forming metal interconnection according to an exemplary embodiment of the present invention is illustrated and the method comprises the following steps which will be described in detail hereinafter.
  • Step 301 forming a recessed area on a hard mask layer and a dielectric layer.
  • a substrate 201 such as a wafer
  • a dielectric layer 202 is deposited on the substrate 201.
  • the dielectric layer 202 may include materials such as SiO 2 , SiOC, SiOF, SiLK, BD, BDII, BDIII, etc.
  • the dielectric layer 202 selects low-k dielectric for reducing capacitance between the interconnection structures in a semiconductor device.
  • the dielectric layer 202 can be composed of two layers or more than two layers.
  • a hard mask layer 203 is deposited on the dielectric layer 202.
  • the material of the hard mask layer 203 may include tantalum nitride or titanium nitride.
  • Recessed areas, for example, trenches, vias, etc., are formed on the hard mask layer 203 and the dielectric layer 202 by using existing methods in prior art.
  • a recessed area 207 is shown in the figures as an example.
  • Step 302 depositing a barrier layer 204 on the hard mask layer 203, sidewall of the recessed area 207 and bottom of the recessed area 207.
  • the barrier layer 204 is deposited on the hard mask layer 203 and on the sidewall and the bottom of the recessed areas by any appropriate deposition method, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and the like.
  • the barrier layer 204 may be formed from a conductive material, for instance, the barrier layer 204 may include materials such as tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, cobalt, etc.
  • Step 303 depositing metal 205 on the barrier layer 204 and filling the recessed area 207 with metal 205.
  • metal 205 is deposited on the barrier layer 204 and filling the recessed area 207 by any appropriate method, such as PVD, CVD, ALD, electroplating and the like.
  • a metal seed layer can be deposited onto the barrier layer 204 before depositing the metal 205.
  • the metal seed layer may include the same material as metal 205 in order to facilitate the deposition and bonding of metal 205 onto the barrier layer 204.
  • Metal 205 fills the recessed area 207 and covers non-recessed areas, as shown in FIG. 4(a).
  • the metal 205 is copper.
  • Step 304 removing the metal 205 deposited on non-recessed area by electropolishing, the metal 205 filled in the recessed area 207 is over polished to form a dishing.
  • an oxide film 206 is formed on the barrier layer 204, and the thickness of the oxide film 206 on the barrier layer 204 deposited on the sidewall of the recessed area is thicker than the oxide film 206 on the barrier layer 204 deposited on the hard mask layer 203.
  • the exposed barrier layer 204 is passivated by forming the oxide film 206 on the barrier layer 204.
  • the dielectric layer 202 is under the barrier layer 204 and the hard mask layer 203, hence, charges are uniformly distributed in the conductive layer (composed of the barrier layer 204 and the hard mask layer 203), and the charges will accumulate on the surface of the dielectric layer 202.
  • the charges distribution on the non-conductive material surface is inversely proportional to radius of curvature, therefore, more charges are accumulated on the shoulder of the barrier layer 204 than the flat surface, so the oxide film 206 on the shoulders of the barrier layer 204 is thicker than the other area's oxide film 206.
  • the thickness of the oxide film 206 on the barrier layer 204 deposited on the sidewall (corresponding to the shoulder) of the recessed area is thicker than the oxide film 206 on the barrier layer 204 deposited on the hard mask layer 203 (corresponding to the flat surface).
  • the thickness of the oxide film 206 on the barrier layer 204 deposited on the sidewall of the recessed area is thicker than the oxide film 206 on the barrier layer 204 deposited on the hard mask layer 203 by experiment.
  • the energy of the electron beam is 3kv.
  • the scan length is about 2 ⁇ and the number of scan points is 400 points.
  • the scan length of the barrier layer 204 is ⁇ and the scan length of the metal structures on either side of the barrier layer 204 is ⁇ .
  • the weight percentage content of oxygen element in the barrier layer 204 close to the metal structure is higher than the other area, which proves that the thickness of the oxide film 206 on the barrier layer 204 deposited on the sidewall of the recessed area is thicker than the oxide film 206 on the barrier layer 204 deposited on the hard mask layer 203.
  • the metal 205 filled in the recessed areas is over polished to form a dishing, as shown in FIG. 4(b).
  • the thickness of the oxide film 206 formed on the barrier layer 204 is proportional to the over polished amount of the metal 205 filled in the recessed area.
  • the over polished amount of the metal 205 is equal to or larger than the thickness of the barrier layer 204 and the hard mask layer 203. In an embodiment, the over polished amount of the metal 205 is 300-500 angstrom.
  • Step 305 removing the oxide film 206 on the barrier layer 204 deposited on the hard mask layer 203, and retaining a certain thickness of oxide film 206 on the barrier layer 204 deposited on the sidewall of the recessed area, as shown in FIG. 4(c).
  • the oxide film 206 on the barrier layer 204 is removed by wet etching, such as BHF solution.
  • the oxide film 206 on the barrier layer 204 is removed by dry etching, such as HF vapor or the mixture of HF vapor and one of the following, ethyl alcohol, methyl alcohol or IPA.
  • the retained oxide film 206 on the barrier layer 204 deposited on the sidewall of the recessed area 207 forms a continuous film on the barrier layer 204 and the thickness of the retained oxide film 206 is larger than 5 angstrom. If the oxide film 206 on the barrier layer 204 deposited on the sidewall of the recessed area 207 is etched and cannot form a continuous film on the barrier layer 204, the barrier layer 204 sandwiched between the metal 205 and the dielectric layer 202 will be over etched, as shown in FIG. 8 which illustrates FIB/SEM cross section of POST-TFE sample, showing over etching of the barrier layer.
  • Step 306 removing the barrier layer 204 and the hard mask layer 203 by etching which has a high selectivity to the oxide film 206, the retained oxide film 206 preventing the barrier layer 204 deposited on the sidewall of the recessed area from being over etched, as shown in FIG. 4(d).
  • the high selectivity means the etch rate of the barrier layer 204 and the hard mask layer 203 is much higher than the etch rate of the oxide film 206.
  • the barrier layer 204 and the hard mask layer 203 are removed by gas phase etching, and the gas selects from the following: XeF 2 , XeF 4 , XeF 6 , KrF 2 , BrF 3 .
  • XeF 2 reacts spontaneously with the barrier layer Ta/TaN at certain temperature and pressure.
  • XeF 2 is an isotropic selective etching of Ta/TaN.
  • the XeF 2 gas has a good selectivity to both copper and dielectric materials.
  • the pressure of XeF 2 gas during the etch process is between O.lTorr and 100 Torr, however 0.5 Torr ⁇ 20 Torr is preferred.
  • the XeF 2 has a high selectivity to the oxide film 206, so during the etching process of the barrier layer 204 and the hard mask layer 203, the oxide film 206 can prevent the barrier layer 204 deposited on the sidewall of the recessed area from being over etched.
  • FIG. 7 illustrates STEM cross section of POST-TFE sample, showing a perfect barrier layer removing result which means the barrier layer 204 deposited on the non-recessed areas is absolutely removed but the barrier layer 204 sandwiched between the metal
  • the dielectric layer 202 are not destroyed and etched.
  • the barrier layer 204 and the hard mask layer 203 on the non-recessed areas are completely removed, the adjacent metal interconnections are separated by the dielectric layer 202.
  • the exposed barrier layer 204 is passivated by forming the oxide film 206 on the barrier layer 204 and the thickness of the oxide film 206 on the barrier layer 204 deposited on the sidewall of the recessed area is thicker than the oxide film
  • the retained oxide film 206 on the barrier layer 204 deposited on the sidewall of the recessed area forms a continuous film on the barrier layer 204 for preventing the barrier layer 204 deposited on the sidewall of the recessed area from being over etched during removing the barrier layer 204 and the hard mask layer 203, which improves the quality of semiconductor devices.

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  • Engineering & Computer Science (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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  • General Chemical & Material Sciences (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

L'invention concerne un procédé de formation d'interconnexion de métal, lequel peut éviter la surgravure d'une couche de barrière (204) déposée sur la paroi latérale d'une zone évidée (207). Les étapes du procédé consistent : à former une zone évidée (207) sur une couche de masque dur (203) et une couche diélectrique (202); à déposer une couche de barrière (204) sur la couche de masque dur (203), la paroi latérale de la zone évidée (207) et le fond de la zone évidée (207); à déposer du métal (205) sur la couche de barrière (204) et à remplir la zone évidée (207) du métal (205); à retirer le métal (205) déposé sur la zone non évidée par polissage électrolytique et le métal (205) remplissant la zone évidée (207) qui est surpoli pour former une concavité, une pellicule d'oxyde (206) étant formée sur la couche de barrière (204) pendant le processus de polissage électrolytique; à retirer la pellicule d'oxyde (206) sur la couche de barrière (204) déposée sur la couche de masque dur (203), et à retenir une certaine épaisseur de pellicule d'oxyde (206) sur la couche de barrière (204) déposée sur la paroi latérale de la zone évidée (207); à retirer la couche de barrière (204) et la couche de masque dur (203) par une gravure présentant une haute sélectivité à la pellicule d'oxyde (206), la pellicule d'oxyde (206) retenue empêchant la surgravure de la couche de barrière (204) déposée sur la paroi latérale de la zone évidée (207).
PCT/CN2014/081790 2014-07-08 2014-07-08 Procédé de formation d'interconnexion de métal WO2016004573A1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN201480079797.7A CN106463455B (zh) 2014-07-08 2014-07-08 一种形成金属互连结构的方法
JP2017501030A JP6301003B2 (ja) 2014-07-08 2014-07-08 金属配線形成方法
PCT/CN2014/081790 WO2016004573A1 (fr) 2014-07-08 2014-07-08 Procédé de formation d'interconnexion de métal
KR1020177000636A KR102247940B1 (ko) 2014-07-08 2014-07-08 금속 상호접속을 형성하는 방법

Applications Claiming Priority (1)

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PCT/CN2014/081790 WO2016004573A1 (fr) 2014-07-08 2014-07-08 Procédé de formation d'interconnexion de métal

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WO2016004573A1 true WO2016004573A1 (fr) 2016-01-14

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KR (1) KR102247940B1 (fr)
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