WO2016000174A1 - Procédé de gestion de la force consommée, dispositif de gestion de la force consommée, et processeur - Google Patents

Procédé de gestion de la force consommée, dispositif de gestion de la force consommée, et processeur Download PDF

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Publication number
WO2016000174A1
WO2016000174A1 PCT/CN2014/081275 CN2014081275W WO2016000174A1 WO 2016000174 A1 WO2016000174 A1 WO 2016000174A1 CN 2014081275 W CN2014081275 W CN 2014081275W WO 2016000174 A1 WO2016000174 A1 WO 2016000174A1
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WO
WIPO (PCT)
Prior art keywords
processor core
processor
operation information
trigger
power supply
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PCT/CN2014/081275
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English (en)
Chinese (zh)
Inventor
宋昆鹏
陈云
崔晓松
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to PCT/CN2014/081275 priority Critical patent/WO2016000174A1/fr
Priority to CN201480003858.1A priority patent/CN105393188B/zh
Publication of WO2016000174A1 publication Critical patent/WO2016000174A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power

Definitions

  • the present invention relates to the field of communications technologies, and in particular, to a power management method, a power management device, and a processor. Background technique
  • processor cores of many-core processors typically share main memory and I/O devices, causing each processor core to access I/O devices or appear due to resource races and local congestion on the on-chip network. Cache Miss will have a long delay when accessing main memory and other operations.
  • the processor core generates unnecessary power consumption while waiting for such long delay operations. Although the long delay can be hidden by the multi-thread rotation technology, the processor is always in working state, but for the hardware thread in the waiting state, its registers and other resources still consume energy. Therefore, reducing the power consumption of the processor in the waiting phase becomes a technical problem to be solved.
  • Memory ferroelectric random access memory
  • the processor chip integrates centralized Flash or FeRAM as non-volatile memory, and writes the state data of the processor core to the centralized non-volatile memory when the system needs to enter the low-power state.
  • the state and data in the centralized non-volatile memory are read and restored to the processor core when the system returns from the low power state to the normal operating state. Since the write and restore of the status data of the processor core is implemented by serial access via the bus, serial access is slower and causes the processor to run slower.
  • the save and restore process also consumes high power. Summary of the invention
  • the embodiment of the invention provides a power consumption management method, a power consumption management device, and a processor, which are used to improve the running speed of the processor and provide conditions for reducing power consumption.
  • An embodiment of the present invention provides a power consumption management method, including:
  • the processor core If it is determined that the processor core needs to be backed up according to the operation information, first sending a backup control signal to the trigger of the processor core, so that the trigger of the processor core is to be the state of the processor core. Backing up to the non-volatile memory corresponding to the trigger; then turning off power to the processor core.
  • the method further includes:
  • the result data of the operation corresponding to the operation information is:
  • the obtaining the operation information from the processor core includes: monitoring the processor The operational behavior of the core obtains operational information of the processor core, or receives operational information sent by the processor core.
  • the determining, according to the operation information, whether the processor core needs to be performed Backups include:
  • the operation information is compared with the pre-configured backup control rule. If the operation information meets the pre-configured backup control rule, it is determined that the backup needs to be performed.
  • the operation information is: an operation to generate a delay exceeding a predetermined threshold Corresponding operation information.
  • a second aspect of the present invention provides a power management apparatus, including: a processor operation detecting module, configured to acquire operation information from the processor core;
  • a signal generating module configured to send a backup control signal to a trigger of the processor core, if it is determined that the processor core needs to be backed up according to the operation information acquired by the processor operation detecting module, so that the A trigger of the processor core backs up a state of the processor core to a non-volatile memory corresponding to the trigger;
  • a power supply control module configured to cut off power supply to the processor core after the signal generation module sends the backup control signal.
  • the processor operation detecting module is further configured to receive the operation information after the power supply control module cuts off power supply to the processor core. Corresponding to the result data of the operation;
  • the power supply control module is further configured to resume power supply to the processor core if the processor operation detecting module receives result data corresponding to the operation information of the operation information;
  • the signal generating module is further configured to: after the power supply control module resumes power supply to the processor core, send a resume control signal to the processor core, so that the trigger is to be stored in the nonvolatile The state of the processor core of the memory is restored to the processor core.
  • the processor operates a detection module, configured to receive after the power supply control module cuts off power supply to the processor core
  • the operation information returned by the on-chip network router corresponds to the result data of the operation.
  • the operation information of the processor core is monitored by the processor operation detection module.
  • the operational behavior of the processor core is obtained, or the operational information of the processor core is received by the processor operation detection module from the processor core.
  • the processor operation detection module includes: a backup control rule storage unit and a processor Operating detection unit;
  • the backup control rule storage unit is configured to store a pre-configured backup control rule; the processor operation detecting unit is configured to compare the operation information with a backup control rule stored in the backup control rule storage unit If the operation information meets the pre-configured backup control rule, it is determined that the backup needs to be performed.
  • the operation information is: an operation that is to generate a delay exceeding a predetermined threshold Corresponding operation information.
  • a third aspect of the present invention provides a processor, including: a processor core, or two or more processor cores; if the processor includes two or more processor cores, The processor cores establish a communicable connection between the processor cores through the on-chip network router;
  • a power management device connected to the processor core, the power consumption management device is a power consumption management device according to any one of the embodiments of the present invention.
  • the device that implements power consumption management determines the need to back up the processor core through the operation information of the processor core, and controls the trigger of the processor core to the processor.
  • the state of the core is backed up to non-volatile memory and then powered off.
  • the processor Since the processor has a flip-flop and data storage through the flip-flop, the problem that the processor core needs to access the centralized memory through the bus to slow the running speed of the processor can be avoided, thereby improving the running speed of the processor;
  • the operation information is used to determine whether power consumption control is performed, and a smaller granularity of power consumption control can be realized, and the state of the processor core is backed up to a nonvolatile memory corresponding to the trigger, and the nonvolatileity corresponding to the trigger Memory can be designed to be much smaller than centralized memory, thus providing the conditions for drastically reducing power consumption.
  • FIG. 1 is a schematic flowchart of a method according to an embodiment of the present invention.
  • FIG. 2A is a schematic structural diagram of a multi-core processor according to the present invention.
  • FIG. 2B is a schematic structural diagram of a processor node in a multi-core processor according to an embodiment of the present invention
  • FIG. 3 is a schematic structural diagram of a non-volatile management unit according to an embodiment of the present invention
  • FIG. 4 is a schematic flowchart of a method according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of a power consumption management apparatus according to an embodiment of the present invention
  • 6 is a schematic structural diagram of a power consumption management apparatus according to an embodiment of the present invention
  • FIG. 7 is a schematic structural diagram of a processor according to an embodiment of the present invention. detailed description
  • the embodiment of the invention provides a power consumption management method, as shown in FIG. 1 , including:
  • the operation information is information used to indicate the operation of the processor core, and the operation information may specifically include: an operation type, an operation name, an operation parameter, an operation result, and the like.
  • the operation information from the processor core may be obtained by active monitoring or may be actively sent by the processor core.
  • the specific implementation may be selected according to the design requirements of the processor-related chip, which is not limited by the embodiment of the present invention.
  • the operation information is used to determine whether the processor core needs to be backed up in the embodiment of the present invention.
  • the rule for determining whether the backup needs to be performed may be preset, and the setting manner may be implemented by fixed hardware logic, or may be adopted.
  • operation information that needs to be backed up is used, and generally corresponds to operation information that generates a long delay, for example, an operation name of an operation for accessing an I/O device, and a Cache (cache) access process.
  • the operation result of the cache hit failure (Cache Miss) may be the operation name of the operation of accessing the external memory after Cache Miss.
  • the trigger may be integrated in the processor core, and the trigger may be located in the same chip as the processor core independently of the processor core; the trigger and the processor core have corresponding Relationship.
  • the non-volatile memory can be used as a processor core-specific non-volatile memory on the same chip as the processor core, or can be a centralized non-volatile memory for use by multiple processor cores.
  • the above implementation manners do not affect the implementation of the embodiment of the present invention.
  • the specific structure may be selected by a technician according to the specific design requirements of the chip, which is not limited by the embodiment of the present invention.
  • the above backup control signal will eventually be sent to the trigger, since the trigger can be integrated in the processor core, or it can be independent of the processor; therefore, the backup control signal can be sent to the interface of the processor core.
  • the trigger can also be sent directly to the trigger.
  • the device implementing the power consumption management determines that the processor core needs to be backed up by using the operation information of the processor core, and controls the trigger of the processor core to back up the state of the processor core to the non-volatile memory, and then Turn off the power supply.
  • the processor Since the processor has a flip-flop and data storage through the flip-flop, the problem that the processor core needs to access the centralized memory through the bus to slow the running speed of the processor can be avoided, thereby improving the running speed of the processor;
  • the operation information is used to determine whether power consumption control is performed, and a smaller granularity of power consumption control can be realized, and the state of the processor core is backed up to a nonvolatile memory corresponding to the trigger, and the nonvolatileity corresponding to the trigger Memory can be designed to be much smaller than centralized memory, thus providing the conditions for drastically reducing power consumption.
  • the above embodiment provides a solution for how to cut off the power supply and reduce the power consumption.
  • the embodiment of the present invention further provides a solution for restoring the power supply and completing the state recovery of the processor core, as follows: Further, the power supply to the processor core is cut off. After that, the above method further includes:
  • the present embodiment since the reception of the result data means that the processor core can continue to operate without continuing to wait, the present embodiment uses the result data to trigger the restoration of the power supply, and then the state recovery is performed.
  • the processor core of the embodiment of the present invention may be a processor core on a single core processor, or may be a processor core in a many-core processor (including two or more processor cores), for multi-core processing.
  • external communication and communication between processor cores can be passed through the on-chip network router.
  • the result data may be derived from an on-chip network router, as follows:
  • the result data of the operation corresponding to receiving the operation information includes: receiving the foregoing returned by the on-chip network router
  • the operation information corresponds to the result data of the operation.
  • the operation information from the processor core may be obtained by active monitoring or may be actively sent by the processor core.
  • the specific implementation scheme may be selected according to the design requirements of the processor-related chip, optionally, the foregoing acquisition.
  • the operational information from the processor core includes:
  • the operation behavior of the processor core is monitored to obtain operation information of the processor core, or the operation information sent by the processor core is received.
  • the processor core can send all of the operational information to the device that implements power management, or can send operational information when it is determined that transmission is needed.
  • a rule for the processor core to determine whether it is necessary to send operation information (which may be referred to as an operation information transmission rule), and may refer to the foregoing rule (whether a backup control rule) that needs to be backed up.
  • determining, according to the foregoing operation information, whether to back up the processor core includes: comparing the operation information with a pre-configured backup control rule, and determining, if the operation information meets a pre-configured backup control rule, determining A backup is required.
  • the backup control rule may be a rule corresponding to the operation information, and the backup control rule is set according to the delay of the operation information may exceed a predetermined threshold; for example: the time of some types of operations exceeds a predetermined threshold, or some If the operation time exceeds the predetermined threshold, or the operation result of some operations may cause the subsequent operation time to exceed the predetermined threshold, the following method may be used to determine that the processor core needs to be backed up: the preset will be generated more than the predetermined width
  • the operation type, the operation name, and/or the operation result information of the value delay operation are backup control rules; if the acquired operation information satisfies the above backup control rule 1 J, it is determined that the processor core needs to be backed up.
  • the operation information transmission rule is configured in the processor core or the backup control rule is configured in the device that implements the power consumption control
  • the operation can be flexibly controlled to perform backup on the processor core, and the implementation is accurate to specific. Power consumption control of the operation, thereby increasing the flexibility of power control and reducing power consumption.
  • the processor in the embodiment of the present invention may include a plurality of processor cores. Since the processor core and the flip-flop have a corresponding relationship, when the processor core has two or more processor cores, The trigger can respond to the backup requirements of the corresponding processor core in time, so the above will be Backing up the state of the processor core to the non-volatile memory corresponding to the above trigger will actually be: backing up the state of the processor core in parallel to the non-volatile memory corresponding to the trigger.
  • the operation information is: operation information corresponding to an operation to generate a delay exceeding a predetermined threshold.
  • the operation information may be operation information corresponding to any operation, but actually the operation information that needs to be backed up is not all operation information, for example, those operations with a short delay may not be performed.
  • Backup which can reduce the number of backup/recovery and power switching times, and improve the running speed of the processor.
  • the predetermined threshold of the delay can be arbitrarily set, and the longer setting can reduce the backup/recovery. The number of times and the number of power-on switches increase the running speed of the processor. If the setting is shorter, the effect of lower power consumption can be achieved.
  • There are many operations with long delays for example: access to I/O devices, cache The operation of accessing external memory caused by Cache Miss.
  • the application scenario is a many-core processor.
  • the technical aim of the embodiment of the present invention is to realize low-power design and fine-grained power management of the processor by using non-volatile technology without affecting the life and performance of the processor.
  • the main idea of the embodiment in the subsequent multi-core processor application scenario is to use a non-volatile management unit (the non-volatile management sheet is a device for implementing power consumption management, and the power consumption management device in the subsequent embodiment)
  • the main functions are the same), monitor and judge the specific operation of the processor core, control the trigger of the processor core to perform backup and recovery based on the judgment result, and control the power supply to the processor core through the trigger to achieve fine-grained processing. Power management.
  • the present embodiment proposes a technical solution for reducing the power consumption of the multi-core processor, and provides fine-grained use of the characteristics of the fast backup/restore of the trigger. Power management capabilities to reduce processor power consumption.
  • the trigger may be a Non-Volatile Flip-Flop (NVFF).
  • processor core When the processor core performs a specific operation (such as accessing the external memory after the Cache Miss occurs during the access to the Cache, accessing the I/O device and other long delay operations), backing up the state to the trigger, turning off the processor core power supply. ;
  • FIG. 2B is a schematic structural diagram of a multi-core processor according to an embodiment of the present invention
  • FIG. 2B is a schematic structural diagram of a processor node (including a processor core and an attached component) in the multi-core processor.
  • one circle represents a processor node, which communicates with external components; external components may include: ETH (EtherNet, Ethernet), MemC (memory controller) MAC (Media Access Control, Media Access Control) SATA (Serial Advanced Technology Attachment).
  • ETH EtherNet, Ethernet
  • MemC memory controller
  • MAC Media Access Control, Media Access Control
  • SATA Serial Advanced Technology Attachment
  • a nonvolatile, multi-core processor includes a number of processor nodes that communicate with peripherals, memory controllers, and an on-chip network.
  • the processor node includes a processor core 100, a non-volatile management unit 101, and an on-chip network router 102.
  • the trigger establishes a connection between the processor core and the non-volatile memory to make non-volatile.
  • the memory acts as a cache for the processor core;
  • a nonvolatile management unit for backup/recovery control and power supply control
  • the non-volatile management unit 101 includes: a backup/restore signal generating module 310, a processor operation detecting module 320, and a power supply control module 330.
  • the processor operation detecting module 320 includes a plurality of backup control rule items 321, the functions of which are: Backup/restore signal generation module 310: generating a control signal required to cause a trigger to perform a backup/restore operation;
  • the processor operation detecting module 320 receives specific operation information of the processor core 100, determines whether a state backup of the processor core is required to be performed based on the operation information, and receives result data corresponding to the operation information returned by the above-mentioned operation information returned by the on-chip network router 102, and controls
  • the backup/restore signal generation module 310 generates a recovery control signal to restore the state of the previous backup to the processor core 100;
  • the backup control rule item 321 the processor operation detecting module 320 searches the operation information of the processor core 100 in the plurality of backup control rule items 321 , and determines whether the processor core 100 needs to perform state backup based on the search result.
  • the backup control rule entry 321 can be fixed hardware logic or dynamically configured by software;
  • Power Control Module 330 Controls power to the processor core 100.
  • the embodiment of the present invention utilizes a trigger to reduce the control flow of the multi-core processor power consumption. Please refer to FIG. 2A, FIG. 2B, FIG. 3 and FIG. 4 together:
  • the I/O device accesses the main storage equal-length delay operation when the Cache Miss is used, and sends the operation type and parameter information to the non-volatile management unit 101 corresponding to the processor core 100;
  • the processor operation detecting module 320 of the non-volatile management unit 101 determines whether a backup is needed according to the received operation type and parameter information, and if yes, enters 404, otherwise enters 401;
  • the backup/restore signal generating module 301 of the non-volatile management unit 101 generates backup control information to the processor core 100, so that the trigger of the processor core 100 backs up the state of the processor core 100 to the non-parallel manner. Volatile memory; then enter 405;
  • the power supply control module 330 turns off the power supply to the processor core 100; enters a wait state until the on-chip network router 102 returns the result data of the specific operation, and proceeds to 406;
  • the power supply control module 330 resumes power supply to the processor core 100, and then enters 407;
  • the backup/restore signal generating module 301 of the non-volatile management unit 101 generates recovery control information to the processor core 100, so that the trigger of the processor core 100 will back up the processor core 100 of the non-volatile memory.
  • the state is restored to the above processor core 100; then, 401 is entered.
  • the processor core 100 receives the return of the on-chip network router 102. Result data.
  • each processor core can be powered off until the end of the operation when performing a specific operation (especially a long delay operation), which can effectively reduce the power consumption of the processor and improve the performance-to-power ratio.
  • the embodiment of the present invention uses a configurable non-volatile management unit to provide fine-grained power management capabilities for different types of specific operations, and to reduce the impact on processor performance, and to reduce backup and recovery operations. Loss of life of the device.
  • the embodiment of the invention further provides a power consumption management device, as shown in FIG. 5, including:
  • a processor operation detecting module 501 configured to acquire operation information from the processor core
  • the signal generating module 502 is configured to: if it is determined that the processor core needs to be backed up according to the operation information acquired by the processor operation detecting module 501, send a backup control signal to the trigger of the processor core to enable the processor core The trigger backs up the state of the processor core to the non-volatile memory corresponding to the trigger;
  • the power supply control module 503 is configured to cut off power supply to the processor core after the signal generation module 502 sends the backup control signal.
  • the operation information is information used to indicate the operation of the processor core, and the operation information may specifically include: an operation type, an operation name, an operation parameter, an operation result, and the like.
  • the operation information from the processor core may be obtained by active monitoring or may be actively sent by the processor core.
  • the specific implementation may be selected according to the design requirements of the processor-related chip, which is not limited by the embodiment of the present invention.
  • the operation information is used to determine whether the processor core needs to be backed up in the embodiment of the present invention.
  • the rule for determining whether the backup needs to be performed may be preset, and the setting manner may be implemented by fixed hardware logic or by software. Dynamic configuration, both solutions are feasible for the embodiments of the present invention, and the embodiments of the present invention are not limited thereto.
  • operation information that needs to be backed up is generated, and generally corresponds to operation information that may generate a long delay, for example, an operation name of an operation of accessing an I/O device, and a Cache (cache) access process.
  • the operation result of the cache hit failure (Cache Miss) may be the operation name of the operation of accessing the external memory after Cache Miss.
  • the backup control rule may be a rule corresponding to the operation information, and the backup control rule is set according to the delay that the operation information may cause to exceed a predetermined threshold; for example: a certain class If the operation time of the type exceeds the predetermined threshold, or the time of some operations exceeds the predetermined threshold, or the operation result of some operations causes the time of the subsequent operation to exceed the predetermined threshold, the following method may be used to determine the need for the above
  • the processor core performs backup: presets the operation type, operation name, and/or operation result information of the operation to generate a delay exceeding a predetermined threshold as a backup control rule; if the acquired operation information satisfies the backup control rule, it is determined that Back up the above processor core.
  • the device implementing the power consumption management determines that the processor core needs to be backed up by using the operation information of the processor core, and controls the trigger of the processor core to back up the state of the processor core to the non-volatile memory, and then Turn off the power supply.
  • the processor Since the processor has a flip-flop and data storage through the flip-flop, the problem that the processor core needs to access the centralized memory through the bus to slow the running speed of the processor can be avoided, thereby improving the running speed of the processor;
  • the operation information is used to determine whether power consumption control is performed, and a smaller granularity of power consumption control can be realized, and the state of the processor core is backed up to a nonvolatile memory corresponding to the trigger, and the nonvolatileity corresponding to the trigger Memory can be designed to be much smaller than centralized memory, thus providing the conditions for drastically reducing power consumption.
  • the above embodiment provides a solution for how to cut off the power supply and reduce the power consumption.
  • the embodiment of the present invention further provides a solution for restoring the power supply and completing the state recovery of the processor core, which is specifically as follows: Further, the processor operates the detection module 501, After receiving the power supply to the processor core by the power supply control module 503, receiving the result data of the operation corresponding to the operation information;
  • the power supply control module 503 is further configured to resume power supply to the processor core if the processor operation detecting module 501 receives the result data of the operation operation corresponding to the operation information;
  • the signal generating module 502 is further configured to: after the power supply control module 503 resumes power supply to the processor core, send a resume control signal to the processor core, so that the trigger is to be stored in the non-volatile memory. The state of the processor core is restored to the above processor core.
  • the present embodiment since the reception of the result data means that the processor core can continue to operate without continuing to wait, the present embodiment uses the result data to trigger the restoration of the power supply, and then the state recovery is performed.
  • the processor core of the embodiment of the present invention may be a processor core on a single core processor, or may be a processor core in a many-core processor (including two or more processor cores), for multi-core processing.
  • the communication between the processor core and the external communication and the processor core can be realized by the on-chip network router. Therefore, for the device that implements power consumption management, the source of the result data can be derived from the tablet network.
  • the router is specifically configured as follows:
  • the processor operation detecting module 501 is configured to: after the power supply control module 503 cuts off power supply to the processor core, receive the result data of the operation operation corresponding to the operation information returned by the on-chip network router. .
  • the operation information from the processor core may be obtained by active monitoring or may be actively sent by the processor core.
  • the specific implementation scheme may be selected according to the design requirements of the processor-related chip, optionally, the foregoing processing.
  • the operation information of the controller core is obtained by the processor operation detection module 501 monitoring the operation behavior of the processor core, or the operation information of the processor core is received by the processor operation detection module 501 from the processor core.
  • the processor core can send all of the operational information to the device that implements power management, or can send operational information when it is determined that transmission is needed.
  • a rule for the processor core to determine whether it is necessary to send operation information (which may be referred to as an operation information transmission rule), and may refer to the foregoing rule (whether a backup control rule) that needs to be backed up.
  • the processor operation detecting module 501 includes: a backup control rule storage unit 601 and a processor operation detecting unit 602;
  • the backup control rule storage unit 601 is configured to store the pre-configured backup control rule.
  • the processor operation detecting unit 602 is configured to compare the operation information with the backup control rule stored in the backup control rule storage unit 601. If the above operation information meets the pre-configured backup control rules, it is determined that a backup is required.
  • the operation information transmission rule is configured in the processor core or the backup control rule is configured in the device that implements the power consumption control
  • the operation can be flexibly controlled to perform backup on the processor core, and the implementation is accurate to specific. Power consumption control of the operation, thereby increasing the flexibility of power control and reducing power consumption.
  • the processor in the embodiment of the present invention may include a plurality of processor cores. Since the processor core and the flip-flop have a corresponding relationship, when the processor core has two or more processor cores, The above-mentioned backup of the state of the processor core to the non-volatile memory corresponding to the trigger is actually: backing up the state of the processor core in parallel to the non-volatile memory corresponding to the trigger.
  • the operation information is: operation information corresponding to an operation to generate a delay exceeding a predetermined threshold.
  • the operation information may be operation information corresponding to any operation, but actually the operation information that needs to be backed up is not all operation information, for example, those operations with a short delay may not be performed.
  • Backup which can reduce the number of backup/recovery and power switching times, and improve the running speed of the processor.
  • the predetermined threshold of the delay can be arbitrarily set, and the longer setting can reduce the backup/recovery. The number of times and the number of power-on switches increase the running speed of the processor. If the setting is shorter, the effect of lower power consumption can be achieved.
  • There are many operations with long delays for example: access to I/O devices, cache The operation of accessing external memory caused by Cache Miss.
  • the embodiment of the present invention further provides a processor, as shown in FIG. 7, comprising: a processor core 701, or two or more processor cores 701; if the processor includes two or two In the above processor core 701, the processor core 701 establishes a communicable connection between the processor cores 702.
  • the processor further includes: a power consumption management device 703 connected to the processor core 701, and the power consumption management.
  • the device 703 is a power consumption management device according to any one of the embodiments of the present invention.
  • the number of the processor core 701, the power consumption management device 703, and the on-chip network router 702 may be any number.
  • the number shown in FIG. 7 is not to be construed as limiting the embodiment of the present invention.
  • the device implementing the power consumption management determines that the processor core needs to be backed up by using the operation information of the processor core, and controls the trigger of the processor core to back up the state of the processor core to the non-volatile memory, and then Turn off the power supply.
  • the processor Since the processor has a flip-flop and data storage through the flip-flop, the problem that the processor core needs to access the centralized memory through the bus to slow the running speed of the processor can be avoided, thereby improving the running speed of the processor;
  • the operation information is used to determine whether power consumption control is performed, and a smaller granularity of power consumption control can be realized, and the state of the processor core is backed up to a nonvolatile memory corresponding to the trigger, and the nonvolatileity corresponding to the trigger Memory can be designed to be much smaller than centralized memory, thus providing the conditions for drastically reducing power consumption.
  • the operation information transmission rule is configured in the processor core or the backup control rule is configured in the device that implements the power consumption control
  • the operation can be flexibly controlled. Backups are performed to achieve power consumption control that is accurate to specific operations, thereby increasing power control flexibility and reducing power consumption.

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Abstract

L'invention concerne un procédé de gestion de la force consommée, un dispositif de gestion de la force consommée, et un processeur. La mise en oeuvre du procédé comprend les étapes suivantes consistant à : acquérir des informations de fonctionnement à partir d'un coeur de processeur; s'il est déterminé, selon ces informations, que le coeur du processeur nécessite une sauvegarde, tout d'abord envoyer un signal de commande de sauvegarde à un déclencheur du coeur du processeur, de façon que ce déclencheur du coeur du processeur sauvegarde l'état du coeur du processeur dans une mémoire non-volatile correspondant au déclencheur ; et couper l'alimentation vers le coeur du processeur. On évite ainsi le problème selon lequel le processeur fonctionne lentement du fait que le cœur du processeur doit visiter une mémoire centralisée par l'intermédiaire d'un bus, et on accélère la vitesse de fonctionnement du processeur.
PCT/CN2014/081275 2014-06-30 2014-06-30 Procédé de gestion de la force consommée, dispositif de gestion de la force consommée, et processeur WO2016000174A1 (fr)

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CN201480003858.1A CN105393188B (zh) 2014-06-30 2014-06-30 一种功耗管理方法、功耗管理装置，及处理器

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CN101697198A (zh) * 2009-10-28 2010-04-21 浪潮电子信息产业股份有限公司 一种动态调整单一计算机系统内活动处理器数量的方法
CN101782791A (zh) * 2010-01-29 2010-07-21 杭州电子科技大学 一种通信处理器芯片中的时钟/复位和配置控制器硬核
US20120166852A1 (en) * 2011-12-22 2012-06-28 Sodhi Inder M Method, apparatus, and system for energy efficiency and energy conservation including improved processor core deep power down exit latency by using register secondary uninterrupted power supply
CN103425232A (zh) * 2012-05-14 2013-12-04 美国博通公司 用于多核处理器的漏变化感知功率管理

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CN1828482A (zh) * 2005-04-13 2006-09-06 威盛电子股份有限公司 控制输出信号切换次数以节省电力消耗
CN101697198A (zh) * 2009-10-28 2010-04-21 浪潮电子信息产业股份有限公司 一种动态调整单一计算机系统内活动处理器数量的方法
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CN103425232A (zh) * 2012-05-14 2013-12-04 美国博通公司 用于多核处理器的漏变化感知功率管理

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