WO2015196603A1 - 像素电路及其驱动方法和显示装置 - Google Patents

像素电路及其驱动方法和显示装置 Download PDF

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Publication number
WO2015196603A1
WO2015196603A1 PCT/CN2014/087316 CN2014087316W WO2015196603A1 WO 2015196603 A1 WO2015196603 A1 WO 2015196603A1 CN 2014087316 W CN2014087316 W CN 2014087316W WO 2015196603 A1 WO2015196603 A1 WO 2015196603A1
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Prior art keywords
transistor
driving
driving transistor
gate
reset
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PCT/CN2014/087316
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English (en)
French (fr)
Inventor
马占洁
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京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to EP14861099.1A priority Critical patent/EP3163560A4/en
Priority to US14/443,951 priority patent/US10255849B2/en
Publication of WO2015196603A1 publication Critical patent/WO2015196603A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a pixel circuit, a driving method thereof, and a display device.
  • the driving level VDD and the threshold voltage Vth of the driving transistor are latched in synchronization.
  • the driving circuit of the pixel circuit is diode-connected in the latching stage, it is equivalent to charging a large resistance and a capacitor through the source of the driving transistor, so the charging of the capacitor is very slow, and it is not fully charged to a predetermined time.
  • the voltage can only be charged to a certain voltage lower than the predetermined voltage, wherein the ratio of the voltage to the predetermined voltage is called the charging rate, so that the latched driving level VDD should be multiplied by the charging rate, so that in the illuminating phase
  • the drive level VDD cannot be fully compensated.
  • a main object of the present disclosure is to provide a pixel circuit, a driving method thereof, and a display device to improve a compensation effect of a driving level.
  • the present disclosure provides a pixel circuit including a driving transistor, a storage capacitor, and a light emitting element; the driving transistor is connected to a first end of the light emitting element, and the second end of the light emitting element is connected to a driving level; a first end of the storage capacitor is connected to a gate of the driving transistor; wherein the pixel circuit further comprises:
  • a reset unit configured to connect a reset voltage to a gate of the driving transistor, so that the driving transistor is reset
  • a writing unit configured to write a data voltage to the second end of the storage capacitor after the driving transistor is reset, and write a reference voltage to the second pole of the driving transistor;
  • a threshold voltage latch unit configured to turn on a connection between a gate of the driving transistor and a first electrode of the driving transistor after the driving transistor is reset, thereby latching a threshold voltage of the driving transistor to the a gate of the driving transistor;
  • Driving a level latch unit for latching a second driving level to a second end of the storage capacitor after latching a threshold voltage of the driving transistor to a gate of the driving transistor;
  • a light emission control unit configured to: after latching a threshold voltage of the driving transistor to a gate of the driving transistor, to connect the second driving level to a second electrode of the driving transistor, thereby controlling the A driving transistor drives the light emitting element to emit light, and a gate-source voltage of the driving transistor compensates a threshold voltage of the driving transistor and the second driving level.
  • the reset voltage is less than a sum of the reference voltage and a threshold voltage of the drive transistor.
  • the reset unit is controlled by a reset control signal
  • the write unit and the threshold voltage latch unit are controlled by a scan signal
  • the drive level latch unit and the illumination control unit are controlled by an illumination control signal .
  • the reset unit includes:
  • a reset transistor wherein a gate of the reset transistor is coupled to the reset control signal, wherein a first pole of the reset transistor is coupled to the reset voltage, wherein a second pole of the reset transistor is coupled to the drive transistor Gate connection.
  • the writing unit includes:
  • a data write transistor wherein a gate of the data write transistor is coupled to the scan signal, wherein a first pole of the data write transistor is coupled to a second end of the storage capacitor, wherein the data is written a second pole of the transistor is coupled to the data voltage;
  • a reference voltage write transistor wherein a gate of the reference voltage write transistor is coupled to the scan signal, wherein a first pole of the reference voltage write transistor is coupled to a second pole of the drive transistor, wherein a second pole of the reference voltage writing transistor is connected to the reference voltage;
  • the threshold voltage latch unit includes: a threshold voltage latch transistor, wherein a gate of the threshold voltage latch transistor is coupled to the scan signal, wherein the threshold voltage latches a first transistor A pole is coupled to the first pole of the drive transistor, wherein a second pole of the threshold voltage latch transistor is coupled to a gate of the drive transistor.
  • the driving level latch unit includes: a driving level latching transistor, wherein a gate of the driving level latching transistor is coupled to the lighting control signal, wherein the driving level latches a transistor a first pole is coupled to the second end of the storage capacitor, wherein a second pole of the drive level latch transistor is coupled to the second drive level;
  • the illumination control unit includes: an illumination control transistor, wherein a gate of the illumination control transistor is coupled to the illumination control signal, wherein a first pole of the illumination control transistor is coupled to a second pole of the drive transistor, wherein The second pole of the light emission control transistor is coupled to the second driving level.
  • the present disclosure also provides a driving method of a pixel circuit, which is applied to the pixel circuit described above, and the driving method of the pixel circuit includes:
  • the reset unit connects the reset voltage to the gate of the driving transistor
  • the writing unit writes the data voltage to the second end of the storage capacitor, and writes the reference voltage to the second pole of the driving transistor;
  • a threshold voltage latch unit turns on a connection of a gate of the driving transistor and a first pole of the driving transistor, thereby latching a threshold voltage of the driving transistor to a gate of the driving transistor;
  • the illumination control unit connects the second driving level to the second pole of the driving transistor, thereby controlling the driving transistor to drive the light emitting element to emit light, and the gate-source voltage of the driving transistor compensates for the driving transistor a threshold voltage and the second driving level.
  • the present disclosure also provides a display device including the above-described pixel circuit.
  • the display device is an active matrix organic light emitting diode display device.
  • the pixel circuit and the driving method thereof and the display device of the present disclosure step-by-step latching the driving level and the threshold voltage of the driving transistor, thereby maximally compensating for the driving level and improving the compensation effect.
  • FIG. 1 is a block diagram showing the structure of a pixel circuit according to an embodiment of the present disclosure
  • FIG. 2 is a circuit diagram of a pixel circuit according to an embodiment of the present disclosure
  • 3 is a timing chart showing the operation of the pixel circuit of the embodiment of the present disclosure.
  • the pixel circuit of the embodiment of the present disclosure includes a driving transistor, a storage capacitor, and a light emitting element; the driving transistor is connected to the first end of the light emitting element, and the second end of the light emitting element is connected to the first driving level The first end of the storage capacitor is connected to the gate of the driving transistor; the pixel circuit further includes:
  • a reset unit configured to connect a reset voltage to a gate of the driving transistor, so that the driving transistor is reset
  • a writing unit configured to write a data voltage to the second end of the storage capacitor after the driving transistor is reset, and write a reference voltage to the second pole of the driving transistor;
  • a threshold voltage latch unit configured to turn on a connection between a gate of the driving transistor and a first electrode of the driving transistor after the driving transistor is reset, thereby latching a threshold voltage of the driving transistor to the a gate of the driving transistor;
  • Driving a level latch unit for latching a second driving level to a second end of the storage capacitor after latching the threshold voltage to a gate of the driving transistor
  • an illumination control unit configured to: after the threshold voltage is latched to a gate of the driving transistor, connect the second driving level to a second pole of the driving transistor, thereby controlling the driving transistor
  • the light emitting element is driven to emit light, and a gate-source voltage of the driving transistor compensates a threshold voltage of the driving transistor and the second driving level.
  • the pixel circuit according to the embodiment of the present disclosure steps the driving level and the threshold voltage of the driving transistor step by step, thereby maximally compensating for the driving level and improving the compensation effect.
  • a pixel circuit includes a driving transistor DTFT, a storage capacitor CST, and a light emitting element D1; and the driving transistor DTFT and the light emitting element D1.
  • the first end is connected, the second end of the light emitting element D1 is connected to the first driving level V1; the first end of the storage capacitor CST is connected to the gate of the driving transistor DTFT; the pixel circuit further includes:
  • the reset unit 11 is controlled by the reset control signal RST for connecting the reset voltage Initial to the gate of the driving transistor DTFT, so that the driving transistor DTFT is reset;
  • the writing unit 12 is controlled by the scan signal Scan for writing the data voltage Vdata to the second end of the storage capacitor CST after the reset of the driving transistor DTFT, and writing the reference voltage Vref to the driving transistor DTFT Second pole
  • the threshold voltage latch unit 13 is controlled by the scan signal Scan for turning on the connection between the gate of the driving transistor DTFT and the first pole of the driving transistor DTFT after the driving transistor DTFT is reset, thereby Locking a threshold voltage Vth of the driving transistor DTFT to a gate of the driving transistor DTFT;
  • the driving level latch unit 14 is controlled by the light emission control signal Emission for latching the second driving level V2 to the storage capacitor after latching the threshold voltage Vth to the gate of the driving transistor DTFT The second end of the CST;
  • the illumination control unit 15 is controlled by the illumination control signal Emission for accessing the second driving level V2 after the threshold voltage Vth is latched to the gate of the driving transistor DTFT.
  • Driving a second pole of the transistor DTFT thereby controlling the driving transistor DTFT to drive the light emitting element D1 to emit light, and a gate-source voltage of the driving transistor DTFT compensating for a threshold voltage Vth and a second driving power of the driving transistor DTFT Flat V2.
  • the light emitting element D1 may be an OLED (Organic Light-Emitting Diode).
  • the driving transistor DTFT used in the pixel circuit of the embodiment of the present disclosure is a p-type transistor
  • the first driving level V1 is a low level VSS
  • the second driving level V2 is a high level VDD
  • the driving transistor DTFT used in the pixel circuit of the embodiment of the present disclosure is an n-type transistor
  • the first driving level V1 is a high level VDD
  • the second driving level V2 is a low level VSS.
  • the reset voltage is smaller than a sum of the reference voltage Vref and a threshold voltage Vth of the driving transistor DTFT to facilitate latching of a threshold voltage Vth of the driving transistor.
  • the transistors employed in all embodiments of the present disclosure may each be a thin film transistor or a field effect transistor or other device having the same characteristics.
  • One of the poles is referred to as a source and the other pole is referred to as a drain.
  • the transistor can be classified into an n-type transistor or a p-type transistor according to the characteristics of the transistor.
  • all transistors are described by taking a p-type transistor as an example, but the disclosure is not limited thereto.
  • n-type transistor for an n-type transistor, a first extreme source, a second extreme drain, a first extreme drain, and a second extreme source for a p-type transistor.
  • the light emitting element D1 is an OLED, and its cathode is connected to a low level VSS;
  • the reset transistor MR has its gate connected to the reset control signal RST, its first pole is connected to the reset voltage Initial, and its second pole is connected to the gate of the driving transistor DTFT.
  • the writing unit 12 includes:
  • the data is written into the transistor MD, the gate thereof is connected to the scan signal Scan, the first pole is connected to the second end of the storage capacitor CST, and the second pole is connected to the data voltage Vdata;
  • a reference voltage writing transistor MRef having a gate connected to the scan signal Scan, a first pole connected to the second pole of the driving transistor DTFT, and a second pole connected to the reference voltage Vref;
  • all of the transistors are p-type transistors, and when the transistor is a p-type transistor, the first very drain, the second source, and the p-type transistor
  • the threshold voltage Vth is less than zero.
  • phase a ie, reset phase: the reset control signal RST is at a low level, the light emission control signal Emission and the scan signal Scan are at a high level, and the data voltage Vdata is at a low level, and the transistor is reset
  • the reset voltage Initial discharges the charge remaining in the first end of the storage capacitor CST in the previous frame, and is stored at the same time.
  • the potential of the first end of the capacitor CST is pulled low to complete the writing of the threshold voltage Vth of the driving transistor DTFT, wherein the reset voltage Initial is a low level;
  • phase b ie, voltage writing and threshold voltage latching phase: the scan signal Scan is at a low level, the light emission control signal Emission, the reference voltage Vref, and the data voltage Vdata are at a high level, The transistor MRef, the transistor MD and the transistor ML1 are turned on, the transistor MD is turned on, the data signal Vdata is written to the second end of the storage capacitor CST, and the opening of the transistor MRef writes the reference voltage Vref to the source of the DTFT, and the ML1 is turned on.
  • the DTFT is formed in a diode connection manner, and a potential difference between a source of the driving transistor DTFT and a drain of the driving transistor DTFT is changed to Vth (Vth is a threshold voltage of the DTFT), and thus written to the storage capacitor CST
  • Vth is a threshold voltage of the DTFT
  • the potential of the first terminal becomes Ref1+Vth, Initial ⁇ Vref+Vth, and the potential of the reference voltage Vref is relatively low, which is favorable for the writing of Ref1+Vth.
  • the Vth signal is latched to the gate of the driving transistor DTFT.
  • the potential of the second end of the storage capacitor CST and the potential of the first end of the storage capacitor CST are: Vdata and Ref1+Vth, respectively; wherein the reference The voltage Vref is at a high level;
  • phase c ie, driving level latching and lighting control phase: the lighting control signal Emission is at a low level, the reference voltage Vref and the scan signal Scan are at a high level, and the data voltage Vdata is low Level, the transistor ME and the transistor ML2 are turned on, and the opening of the transistor ML2 latches VDD at the second end of the storage capacitor CST, while latching VDD to the gate of the driving transistor DTFT according to the principle of conservation of capacitance of the storage capacitor CST Therefore, the potential of the second end of the storage capacitor CST and the potential of the first end of the storage capacitor CST are: VDD and VDD-(Vdata-Vref-Vth); the opening of the transistor ME inputs VDD to the driving transistor The source of the DTFT, such that the gate potential of the driving transistor DTFT is VDD-(Vdata-Vref-Vth), the source potential of the DTFT is VDD, the driving transistor DTFT is in a saturated state, and the driving transistor DTFT
  • the voltage value of the reference voltage Vref needs to be set according to the magnitude of the threshold voltage Vth, such as when the threshold voltage of the driving transistor Vth is at -2.5V.
  • the voltage value of the reference voltage Vref can be set at about 1V, and the voltage value of the reference voltage Vref needs to be matched with the voltage value of the reset voltage Initial to achieve a good threshold voltage compensation effect.
  • the reset voltage Initial that achieves the reset effect should be smaller than the sum of the reference voltage Vref and the threshold voltage Vth of the driving transistor so that the threshold voltage Vth of the driving transistor DTFT can be quickly written to the storage capacitor CST.
  • the embodiment of the present disclosure is exemplified by a bottom emission type structure, but the disclosure is not limited thereto. It is conceivable that the implementation of the top emission type structure can be easily conceived by those skilled in the art without creative efforts, and therefore falls within the scope of the embodiments of the present disclosure.
  • the driving method of the pixel circuit according to the embodiment of the present disclosure is applied to the pixel circuit described above, and includes:
  • the reset unit connects the reset voltage to the gate of the driving transistor
  • the write unit writes a data voltage to the second end of the storage capacitor and writes a reference voltage to the second pole of the drive transistor;
  • the threshold voltage latch unit turns on the gate of the drive transistor and the drive transistor a first pole connection to latch a threshold voltage of the drive transistor to a gate of the drive transistor;
  • a driving level latch unit latches a second driving level to a second end of the storage capacitor; the lighting control unit connects the second driving level to a second pole of the driving transistor, thereby controlling the A driving transistor drives the light emitting element to emit light, and a gate-source voltage of the driving transistor compensates a threshold voltage of the driving transistor and the second driving level.
  • the display device includes the pixel circuit described above.
  • the display device For the structure and working principle of the pixel circuit included in the above, refer to the above embodiment, and details are not described herein again.
  • the structure of other parts of the display device can refer to the prior art, and will not be described in detail herein.
  • the display device may be any product or component having a display function such as a home appliance, a communication device, an engineering device, an electronic entertainment product, or the like.
  • the display device is an AMOLED display device.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of El Displays (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

本公开提供一种像素电路及其驱动方法和显示装置。所述像素电路包括：复位单元，将复位电压接入驱动晶体管的栅极，使得驱动晶体管复位；写入单元，将数据电压写入存储电容的第二端，将参考电压写入驱动晶体管的第二极；阈值电压锁存单元，导通驱动晶体管的栅极和驱动晶体管的第一极的连接，将驱动晶体管的阈值电压锁存到驱动晶体管的栅极；驱动电平锁存单元，将第二驱动电平锁存到存储电容的第二端；以及发光控制单元，在将所述驱动晶体管的阈值电压锁存到驱动晶体管的栅极之后，将第二驱动电平接入驱动晶体管的第二极，控制驱动晶体管驱动发光元件发光，驱动晶体管的栅源电压补偿驱动晶体管的阈值电压和第二驱动电平。

Description

像素电路及其驱动方法和显示装置
相关申请的交叉参考
本申请主张在2014年06月25日在中国提交的中国专利申请号201410293096.5的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，尤其涉及一种像素电路及其驱动方法和显示装置。
背景技术
在现有的应用于AMOLED(Active Matrix/Organic Light Emitting Diode，有源矩阵有机发光二极管)显示装置的像素电路中，驱动电平VDD和驱动晶体管的阈值电压Vth同步进行锁存。然而，由于像素电路中在锁存阶段驱动晶体管采用二极管连接方式，相当于通过驱动晶体管的源极给一个超大电阻和电容充电，因此向电容充电非常缓慢，在一定时间内并不能完全充电到预定电压，而只能充电至低于预定电压的某一电压，其中该电压与预定电压的比例被称作充电率，这样锁存的驱动电平VDD应该乘以该充电率，这样在发光阶段并不能完全补偿驱动电平VDD。
发明内容
本公开的主要目的在于提供一种像素电路及其驱动方法和显示装置，以改善驱动电平的补偿效果。
为达到上述目的，本公开提供了一种像素电路，包括驱动晶体管、存储电容和发光元件；所述驱动晶体管与所述发光元件的第一端连接，所述发光元件的第二端接入第一驱动电平；所述存储电容的第一端与所述驱动晶体管的栅极连接；其中，所述像素电路还包括：
复位单元，用于将复位电压接入所述驱动晶体管的栅极，使得所述驱动晶体管复位；
写入单元，用于在所述驱动晶体管复位之后，将数据电压写入所述存储电容的第二端，并将参考电压写入所述驱动晶体管的第二极；
阈值电压锁存单元，用于在所述驱动晶体管复位之后，导通所述驱动晶体管的栅极和所述驱动晶体管的第一极的连接，从而将所述驱动晶体管的阈值电压锁存到所述驱动晶体管的栅极；
驱动电平锁存单元，用于在将所述驱动晶体管的阈值电压锁存到所述驱动晶体管的栅极之后，将第二驱动电平锁存到所述存储电容的第二端；以及，
发光控制单元，用于在将所述驱动晶体管的阈值电压锁存到所述驱动晶体管的栅极之后，将所述第二驱动电平接入所述驱动晶体管的第二极，从而控制所述驱动晶体管驱动所述发光元件发光，并且所述驱动晶体管的栅源电压补偿所述驱动晶体管的阈值电压和所述第二驱动电平。
实施时，所述复位电压小于所述参考电压与所述驱动晶体管的阈值电压之和。
实施时，所述复位单元受复位控制信号控制，所述写入单元和所述阈值电压锁存单元受扫描信号控制，所述驱动电平锁存单元和所述发光控制单元受发光控制信号控制。
实施时，所述复位单元包括：
复位晶体管，其中所述复位晶体管的栅极接入所述复位控制信号，其中所述复位晶体管的第一极接入所述复位电压，其中所述复位晶体管的第二极与所述驱动晶体管的栅极连接。
实施时，所述写入单元包括：
数据写入晶体管，其中所述数据写入晶体管的栅极接入所述扫描信号，其中所述数据写入晶体管的第一极与所述存储电容的第二端连接，其中所述数据写入晶体管的第二极接入所述数据电压；以及，
参考电压写入晶体管，其中所述参考电压写入晶体管的栅极接入所述扫描信号，其中所述参考电压写入晶体管的第一极与所述驱动晶体管的第二极连接，其中所述参考电压写入晶体管的第二极接入所述参考电压；
所述阈值电压锁存单元包括：阈值电压锁存晶体管，其中所述阈值电压锁存晶体管的栅极接入所述扫描信号，其中所述阈值电压锁存晶体管的第一 极与所述驱动晶体管的第一极连接，其中所述阈值电压锁存晶体管的第二极与所述驱动晶体管的栅极连接。
实施时，所述驱动电平锁存单元包括：驱动电平锁存晶体管，其中所述驱动电平锁存晶体管的栅极接入所述发光控制信号，其中所述驱动电平锁存晶体管的第一极与所述存储电容的第二端连接，其中所述驱动电平锁存晶体管的第二极接入所述第二驱动电平；
所述发光控制单元包括：发光控制晶体管，其中所述发光控制晶体管的栅极接入所述发光控制信号，其中所述发光控制晶体管的第一极与所述驱动晶体管的第二极连接，其中所述发光控制晶体管的第二极接入所述第二驱动电平。
本公开还提供了一种像素电路的驱动方法，应用于上述的像素电路，所述像素电路的驱动方法包括：
复位单元将复位电压接入驱动晶体管的栅极；
写入单元将数据电压写入存储电容的第二端，并将参考电压写入所述驱动晶体管的第二极；
阈值电压锁存单元导通所述驱动晶体管的栅极和所述驱动晶体管的第一极的连接，从而将所述驱动晶体管的阈值电压锁存到所述驱动晶体管的栅极；
驱动电平锁存单元将第二驱动电平锁存到所述存储电容的第二端；以及
发光控制单元将所述第二驱动电平接入所述驱动晶体管的第二极，从而控制所述驱动晶体管驱动所述发光元件发光，并且所述驱动晶体管的栅源电压补偿所述驱动晶体管的阈值电压和所述第二驱动电平。
本公开还提供了一种显示装置，包括上述的像素电路。
可选的，所述显示装置为有源矩阵有机发光二极管显示装置。
与现有技术相比，本公开所述的像素电路及其驱动方法和显示装置，将驱动电平和驱动晶体管的阈值电压分步锁存，可以最大程度补偿驱动电平并且改善补偿效果。
附图说明
图1是本公开实施例所述的像素电路的结构框图；
图2是本公开一具体实施例所述的像素电路的电路图；
图3是本公开该具体实施例所述的像素电路的工作时序图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开实施例所述的像素电路，包括驱动晶体管、存储电容和发光元件；所述驱动晶体管与所述发光元件的第一端连接，所述发光元件的第二端接入第一驱动电平；所述存储电容的第一端与所述驱动晶体管的栅极连接；所述像素电路还包括：
复位单元，用于将复位电压接入所述驱动晶体管的栅极，使得所述驱动晶体管复位；
写入单元，用于在所述驱动晶体管复位之后，将数据电压写入所述存储电容的第二端，并将参考电压写入所述驱动晶体管的第二极；
阈值电压锁存单元，用于在所述驱动晶体管复位之后，导通所述驱动晶体管的栅极和所述驱动晶体管的第一极的连接，从而将所述驱动晶体管的阈值电压锁存到所述驱动晶体管的栅极；
驱动电平锁存单元，用于在将该阈值电压锁存到所述驱动晶体管的栅极之后，将第二驱动电平锁存到所述存储电容的第二端；
以及，发光控制单元，用于在将该阈值电压锁存到所述驱动晶体管的栅极之后，将所述第二驱动电平接入所述驱动晶体管的第二极，从而控制所述驱动晶体管驱动所述发光元件发光，并所述驱动晶体管的栅源电压补偿所述驱动晶体管的阈值电压和所述第二驱动电平。
本公开实施例所述的像素电路，将驱动电平和驱动晶体管的阈值电压分步锁存，可以最大程度补偿驱动电平，改善补偿效果。
如图1所示，本公开实施例所述的像素电路，包括驱动晶体管DTFT、存储电容CST和发光元件D1；所述驱动晶体管DTFT与所述发光元件D1的 第一端连接，所述发光元件D1的第二端接入第一驱动电平V1；所述存储电容CST的第一端与所述驱动晶体管DTFT的栅极连接；所述像素电路还包括：
复位单元11，受复位控制信号RST控制，用于将复位电压Initial接入所述驱动晶体管DTFT的栅极，使得所述驱动晶体管DTFT复位；
写入单元12，受扫描信号Scan控制，用于在所述驱动晶体管DTFT复位之后，将数据电压Vdata写入所述存储电容CST的第二端，并将参考电压Vref写入所述驱动晶体管DTFT的第二极；
阈值电压锁存单元13，受所述扫描信号Scan控制，用于在所述驱动晶体管DTFT复位之后，导通所述驱动晶体管DTFT的栅极和所述驱动晶体管DTFT的第一极的连接，从而将所述驱动晶体管DTFT的阈值电压Vth锁存到所述驱动晶体管DTFT的栅极；
驱动电平锁存单元14，受发光控制信号Emission控制，用于在将该阈值电压Vth锁存到所述驱动晶体管DTFT的栅极之后，将第二驱动电平V2锁存到所述存储电容CST的第二端；
以及，发光控制单元15，受所述发光控制信号Emission控制，用于在将该阈值电压Vth锁存到所述驱动晶体管DTFT的栅极之后，将所述第二驱动电平V2接入所述驱动晶体管DTFT的第二极，从而控制所述驱动晶体管DTFT驱动所述发光元件D1发光，并所述驱动晶体管DTFT的栅源电压补偿所述驱动晶体管DTFT的阈值电压Vth和所述第二驱动电平V2。
实施时，所述发光元件D1可以为OLED(Organic Light-Emitting Diode，有机发光二极管)。
在实际操作时，当本公开实施例所述的像素电路采用的驱动晶体管DTFT为p型晶体管时，第一驱动电平V1为低电平VSS，第二驱动电平V2为高电平VDD；当本公开实施例所述的像素电路采用的驱动晶体管DTFT为n型晶体管时，第一驱动电平V1为高电平VDD，第二驱动电平V2为低电平VSS。可选的，所述复位电压小于所述参考电压Vref与所述驱动晶体管DTFT的阈值电压Vth之和，以利于驱动晶体管的阈值电压Vth的锁存。
本公开所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。在本公开实施例中，为区分晶体管除栅极之外的两极， 将其中一极称为源极，另一极称为漏极。此外，按照晶体管的特性区分可以将晶体管分为n型晶体管或p型晶体管。在本公开实施例提供的驱动电路中，所有晶体管均是以p型晶体管为例进行的说明，但本公开并不以此为限。可以想到的是，在采用n型晶体管实现时是本领域技术人员可在没有做出创造性劳动前提下轻易想到的，因此也是在落入在本公开的实施例保护范围内的。在本公开实施例中，对于n型晶体管，第一极为源极，第二极为漏极，对于p型晶体管，第一极为漏极，第二极为源极。
如图2所示，在本公开一具体实施例所述的像素电路中：
所述发光元件D1为OLED，其阴极接入低电平VSS；
所述复位单元11包括：
复位晶体管MR，其栅极接入所述复位控制信号RST，其第一极接入所述复位电压Initial，其第二极与所述驱动晶体管DTFT的栅极连接。
所述写入单元12包括：
数据写入晶体管MD，其栅极接入所述扫描信号Scan，其第一极与所述存储电容CST的第二端连接，其第二极接入所述数据电压Vdata；
以及，参考电压写入晶体管MRef，其栅极接入所述扫描信号Scan，其第一极与所述驱动晶体管DTFT的第二极连接，其第二极接入所述参考电压Vref；
所述阈值电压锁存单元13包括：阈值电压锁存晶体管ML1，其栅极接入所述扫描信号Scan，其第一极与所述驱动晶体管DTFT的第一极连接，其第二极与所述驱动晶体管DTFT的栅极连接；
所述驱动电平锁存单元14包括：驱动电平锁存晶体管ML2，其栅极接入所述发光控制信号Emission，其第一极与所述存储电容CST的第二端连接，其第二极接入高电平VDD；
所述发光控制单元包括15：发光控制晶体管ME，其栅极接入所述发光控制信号Emission，其第一极与所述驱动晶体管DTFT的第二极连接，其第二极接入所述高电平VDD。
在如图2所示的像素电路的实施例中，所有的晶体管都为p型晶体管，当晶体管为p型晶体管时，第一极为漏极，第二极为源极，并且p型晶体管 的阈值电压Vth小于0。如图2所示的像素电路的实施例的具体工作过程如下：
在阶段a(即复位阶段)：所述复位控制信号RST为低电平，所述发光控制信号Emission和所述扫描信号Scan为高电平，所述数据电压Vdata为低电平，将复位晶体管MR打开，所述扫描信号Scan和所述发光控制信号Emission为高电平，其他的晶体管都关断，复位电压Initial将上一帧残留在存储电容CST第一端的电荷放掉，同时将存储电容CST的第一端的电位拉低，以便所述驱动晶体管DTFT的阈值电压Vth的完整写入，其中复位电压Initial为低电平；
在阶段b(即电压写入和阈值电压锁存阶段)：所述扫描信号Scan为低电平，所述发光控制信号Emission、所述参考电压Vref和所述数据电压Vdata为高电平，将晶体管MRef，晶体管MD和晶体管ML1开启，晶体管MD的开启，将数据信号Vdata写入到存储电容CST的第二端，晶体管MRef的开启将参考电压Vref写入到DTFT的源极，ML1的开启，使得DTFT形成二极管连接方式，将所述驱动晶体管DTFT的源极和所述驱动晶体管DTFT的漏极之间的电位差变为Vth(Vth为DTFT的阈值电压)，这样写入到存储电容CST的第一端的电位变成Ref1+Vth，Initial＜Vref+Vth，同时所述参考电压Vref的电位又相对比较低，很利于Ref1+Vth的写入。这样Vth信号便锁存到了所述驱动晶体管DTFT的栅极，此时存储电容CST的第二端的电位和存储电容CST的第一端的电位分别为：Vdata和Ref1+Vth；其中，所述参考电压Vref为高电平；
在阶段c(即驱动电平锁存和发光控制阶段)：所述发光控制信号Emission为低电平，所述参考电压Vref和所述扫描信号Scan为高电平，所述数据电压Vdata为低电平，将晶体管ME和晶体管ML2打开，晶体管ML2的开启将VDD锁存在存储电容CST的第二端，同时根据存储电容CST的电容电荷守恒原理，将VDD锁存到所述驱动晶体管DTFT的栅极，这样存储电容CST的第二端的电位和存储电容CST的第一端的电位便分别为：VDD和VDD-(Vdata-Vref-Vth)；晶体管ME的开启，将VDD输入到所述驱动晶体管DTFT的源极，这样所述驱动晶体管DTFT的栅极电位是VDD-(Vdata-Vref-Vth)， DTFT的源极电位是VDD，所述驱动晶体管DTFT处于饱和状态，所述驱动晶体管DTFT在饱和状态的工作电流Ids如下：Ids＝1/2×K×(Vgs-Vth)2＝1/2×K×(VDD-(Vdata-Vref-Vth)-VDD-Vth)2＝1/2×K×(Vdata-Vref)2，其中Vgs为所述驱动晶体管DTFT的栅源电压，K＝W/L×C×u，其中，W/L为所述驱动晶体管DTFT的宽长比，C为所述驱动晶体管DTFT的极间电容，u为所述驱动晶体管DTFT的迁移率，在相同结构中K的数值相对稳定，可以算为常量；因此流经与驱动晶体管DTFT的漏极相连接的有机发光二极管的电流就只与Vref和Vdata相关，而与Vth和VDD无关。
在实际操作时，为了实现驱动晶体管的阈值电压Vth的快速锁存，需根据阈值电压Vth的大小来设定参考电压Vref的电压值，如当驱动晶体管的阈值电压Vth的电压值在-2.5V-3V之间时，参考电压Vref的电压值可设定在1V左右，同时参考电压Vref的电压值还需与复位电压Initial的电压值进行匹配，才能实现好的阈值电压的补偿效果。实现复位效果的复位电压Initial应小于参考电压Vref与驱动晶体管的阈值电压Vth之和，以便能快速将所述驱动晶体管DTFT的阈值电压Vth写入存储电容CST上。
本公开实施例是以底发射型结构为例的，但是本公开并不以此为限。可以想到的是，在采用顶发射型结构实现时是本领域技术人员可在没有做出创造性劳动前提下轻易想到的，因此也是落入在本公开的实施例保护范围内的。本公开实施例所述的像素电路的驱动方法，应用于上述的像素电路，包括：
复位单元将复位电压接入驱动晶体管的栅极；
写入单元将数据电压写入存储电容的第二端，并将参考电压写入所述驱动晶体管的第二极；阈值电压锁存单元导通所述驱动晶体管的栅极和所述驱动晶体管的第一极的连接，从而将所述驱动晶体管的阈值电压锁存到所述驱动晶体管的栅极；
驱动电平锁存单元将第二驱动电平锁存到所述存储电容的第二端；发光控制单元将所述第二驱动电平接入所述驱动晶体管的第二极，从而控制所述驱动晶体管驱动所述发光元件发光，并所述驱动晶体管的栅源电压补偿所述驱动晶体管的阈值电压和所述第二驱动电平。
本公开实施例所述的显示装置包括上述的像素电路。其中，所述显示装 置所包括的像素电路的结构以及工作原理请参见上述实施例，在此不再赘述。另外，显示装置的其他部分的结构可以参考现有技术，对此本文不再详细描述。该显示装置可以为：家用电器、通信设备、工程设备、电子娱乐产品等任何具有显示功能的产品或部件。
可选的，所述显示装置为AMOLED显示装置。
以上所述是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

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  1. 一种像素电路，包括驱动晶体管、存储电容和发光元件；所述驱动晶体管与所述发光元件的第一端连接，所述发光元件的第二端接入第一驱动电平；所述存储电容的第一端与所述驱动晶体管的栅极连接；其中，所述像素电路还包括：
    复位单元，用于将复位电压接入所述驱动晶体管的栅极，使得所述驱动晶体管复位；
    写入单元，用于在所述驱动晶体管复位之后，将数据电压写入所述存储电容的第二端，并将参考电压写入所述驱动晶体管的第二极；
    阈值电压锁存单元，用于在所述驱动晶体管复位之后，导通所述驱动晶体管的栅极和所述驱动晶体管的第一极的连接，从而将所述驱动晶体管的阈值电压锁存到所述驱动晶体管的栅极；
    驱动电平锁存单元，用于在将所述驱动晶体管的阈值电压锁存到所述驱动晶体管的栅极之后，将第二驱动电平锁存到所述存储电容的第二端；以及，
    发光控制单元，用于在将所述驱动晶体管的阈值电压锁存到所述驱动晶体管的栅极之后，将所述第二驱动电平接入所述驱动晶体管的第二极，从而控制所述驱动晶体管驱动所述发光元件发光，并且所述驱动晶体管的栅源电压补偿所述驱动晶体管的阈值电压和所述第二驱动电平。
  2. 如权利要求1所述的像素电路，其中，所述复位电压小于所述参考电压与所述驱动晶体管的阈值电压之和。
  3. 如权利要求2所述的像素电路，其中，所述复位单元受复位控制信号控制，所述写入单元和所述阈值电压锁存单元受扫描信号控制，所述驱动电平锁存单元和所述发光控制单元受发光控制信号控制。
  4. 如权利要求3所述的像素电路，其中，所述复位单元包括：
    复位晶体管，其中所述复位晶体管的栅极接入所述复位控制信号，所述复位晶体管的第一极接入所述复位电压，所述复位晶体管的第二极与所述驱动晶体管的栅极连接。
  5. 如权利要求3或4所述的像素电路，其中，
    所述写入单元包括：
    数据写入晶体管，其中所述数据写入晶体管的栅极接入所述扫描信号，所述数据写入晶体管的第一极与所述存储电容的第二端连接，所述数据写入晶体管的第二极接入所述数据电压；以及，
    参考电压写入晶体管，其中所述参考电压写入晶体管的栅极接入所述扫描信号，所述参考电压写入晶体管的第一极与所述驱动晶体管的第二极连接，所述参考电压写入晶体管的第二极接入所述参考电压；
    所述阈值电压锁存单元包括：阈值电压锁存晶体管，其中所述阈值电压锁存晶体管的栅极接入所述扫描信号，所述阈值电压锁存晶体管的第一极与所述驱动晶体管的第一极连接，所述阈值电压锁存晶体管的第二极与所述驱动晶体管的栅极连接。
  6. 如权利要求5所述的像素电路，其中，
    所述驱动电平锁存单元包括：驱动电平锁存晶体管，其中所述驱动电平锁存晶体管的栅极接入所述发光控制信号，所述驱动电平锁存晶体管的第一极与所述存储电容的第二端连接，所述驱动电平锁存晶体管的第二极接入所述第二驱动电平；
    所述发光控制单元包括：发光控制晶体管，其中所述发光控制晶体管的栅极接入所述发光控制信号，所述发光控制晶体管的第一极与所述驱动晶体管的第二极连接，所述发光控制晶体管的第二极接入所述第二驱动电平。
  7. 一种像素电路的驱动方法，应用于如权利要求1至6中任一权利要求所述的像素电路，其中，所述像素电路的驱动方法包括：
    复位单元将复位电压接入驱动晶体管的栅极；
    写入单元将数据电压写入存储电容的第二端，并将参考电压写入所述驱动晶体管的第二极；
    阈值电压锁存单元导通所述驱动晶体管的栅极和所述驱动晶体管的第一极的连接，从而将所述驱动晶体管的阈值电压锁存到所述驱动晶体管的栅极；
    驱动电平锁存单元将第二驱动电平锁存到所述存储电容的第二端；以及
    发光控制单元将所述第二驱动电平接入所述驱动晶体管的第二极，从而控制所述驱动晶体管驱动所述发光元件发光，并且所述驱动晶体管的栅源电 压补偿所述驱动晶体管的阈值电压和所述第二驱动电平。
  8. 一种显示装置，其中，包括如权利要求1至6中任一权利要求所述的像素电路。
  9. 如权利要求8所述的显示装置，其中，所述显示装置为有源矩阵有机发光二极管显示装置。
PCT/CN2014/087316 2014-06-25 2014-09-24 像素电路及其驱动方法和显示装置 WO2015196603A1 (zh)

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