WO2015188594A1 - Procédé de préparation de couche de silicium polycristallin et de substrat d'affichage, et substrat d'affichage - Google Patents

Procédé de préparation de couche de silicium polycristallin et de substrat d'affichage, et substrat d'affichage Download PDF

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WO2015188594A1
WO2015188594A1 PCT/CN2014/092061 CN2014092061W WO2015188594A1 WO 2015188594 A1 WO2015188594 A1 WO 2015188594A1 CN 2014092061 W CN2014092061 W CN 2014092061W WO 2015188594 A1 WO2015188594 A1 WO 2015188594A1
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region
thin film
film transistor
amorphous silicon
layer
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PCT/CN2014/092061
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English (en)
Chinese (zh)
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张慧娟
亢澎涛
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京东方科技集团股份有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
    • H01L27/1285—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor using control of the annealing or irradiation parameters, e.g. using different scanning direction or intensity for different transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1229—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with different crystal properties within a device or between different devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L2021/775—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate comprising a plurality of TFTs on a non-semiconducting substrate, e.g. driving circuits for AMLCDs

Definitions

  • Amorphous silicon crystallization technology mainly includes Solid Phase Crystallization (SPC), Metal-Induced Lateral Crystallization (MILC), and Excimer Laser Crystallization (ELC). And other technologies. ELC technology is commonly used for the crystallization of amorphous silicon with its high mobility and yield.
  • the first region corresponds to a region in which a first thin film transistor is formed
  • the second region corresponds to a region in which a second thin film transistor is formed.
  • the first thin film transistor includes a switching thin film transistor
  • the second thin film transistor includes a driving thin film transistor
  • the plurality of first bump structures located in the first thin film transistor region are equally spaced, and the plurality of second bump structures located in the second thin film transistor region are equally spaced.
  • a polysilicon layer including a first region and a second region, the first region having a grain size smaller than a grain size of the second region.
  • an array substrate includes a polysilicon layer, the polysilicon layer includes a first region and a second region, and the first region has a grain size smaller than that of the second region Grain size.
  • a method of preparing a display substrate includes forming an active layer on a region of a base substrate where a first thin film transistor is to be formed and a region where a second thin film transistor is to be formed, a gate insulating layer, a gate electrode, and a source electrode over the active layer And a drain electrode, and forming an electrode structure;
  • the active layer includes a source region, a drain region, a channel region between the source region and the drain region; wherein, the first thin film transistor region is located
  • the active layer of the domain and the second thin film transistor region is obtained by doping a region of the polysilicon layer according to any one of the above, corresponding to the source region and the drain region.
  • the electrode structure includes an anode and a cathode.
  • the first thin film transistor includes a switching thin film transistor
  • the second thin film transistor includes a driving thin film transistor
  • the method further includes forming a buffer layer on a surface of the base substrate.
  • a display substrate prepared by the method of any of the above.
  • a display device including the display substrate.
  • FIG. 1 is a schematic structural diagram of an amorphous silicon layer according to an embodiment of the present invention.
  • FIG. 2 is a schematic view showing a grain size of a polysilicon layer according to an embodiment of the present invention
  • FIG. 4a and FIG. 5 are schematic diagrams showing a process for preparing an amorphous silicon layer according to an embodiment of the present invention
  • FIG. 7 is a schematic structural diagram 1 of a backplane of an OLED according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram 2 of a backplane of an OLED according to an embodiment of the present disclosure.
  • FIG. 9 is a circuit diagram showing a connection relationship between a switching thin film transistor and a driving thin film transistor in a sub-pixel unit of an OLED according to an embodiment of the present invention.
  • Embodiments of the present invention provide a method for preparing a polysilicon layer, and the method for preparing the polysilicon layer includes the following steps:
  • amorphous silicon layer 10 as shown in FIG. 1 by a patterning process on a substrate, the amorphous silicon layer 10 including an amorphous silicon bottom portion 101 and a plurality of portions on the amorphous silicon bottom portion 101 A raised structure 102 and a plurality of second raised structures 103.
  • the plurality of first protruding structures 102 are located in the first area A.
  • the first region is, for example, a region where a first thin film transistor is to be formed.
  • the plurality of second protruding structures 103 are located in the second region B.
  • the second area is, for example, to form a second thin The area of the film transistor.
  • a spacing between the plurality of first raised structures 102 is less than a spacing between the plurality of second raised structures 103.
  • the polysilicon layer may be applied to a display substrate including at least two thin film transistors each of the sub-pixel units, and the at least two thin film transistors include at least one first thin film transistor and at least one second thin film transistor.
  • the substrate may be a substrate that does not form any film layer, such as a transparent glass substrate or other substrate, or may be a substrate on which a film layer is formed.
  • the critical full melting energy density of the amorphous silicon layers having different thicknesses is inevitably different.
  • the convex structure of the portion of the amorphous silicon layer 10 is in an incompletely molten state, so that the convex structures can be uniformly nucleated during the crystallization process, ensuring uniform distribution of polycrystalline silicon crystal grains in each thin film transistor region, and increasing The size of the grain is large.
  • the embodiment of the present invention does not specifically define the shapes of the first protruding structure 102 and the second protruding structure 103.
  • the protruding structure may have a square, rectangular or circular cross section to facilitate the shape.
  • Nuclear but the invention is not limited thereto.
  • the spacing between the plurality of first protruding structures 102 and the spacing between the plurality of second protruding structures 103 can be set according to actual conditions, so that the mobility requirements of different thin film transistors can be simultaneously integrated, thereby Product performance is guaranteed.
  • the amorphous silicon layer 10 includes an amorphous silicon bottom portion 101 and a plurality of first protruding structures 102 and a plurality of second protruding structures 103 on the amorphous silicon bottom portion 101. That is, in the region A where the first thin film transistor is to be formed, including the amorphous silicon bottom portion 101 and the amorphous silicon substrate a plurality of first bump structures 102 on the portion 101; a region B where the second thin film transistor is to be formed, including an amorphous silicon bottom portion 101 and a plurality of second bumps on the amorphous silicon bottom portion 101 Structure 103.
  • the thicknesses of the amorphous silicon bottom portions 101 of all of the thin film transistor regions are equal, and all of the first raised structures 102 and the second raised structures 103 are equal in thickness.
  • the thickness of the amorphous silicon bottom portion 101, the first raised structure 102, and the second raised structure 103 may vary as needed.
  • Embodiments of the present invention provide a method of fabricating a polysilicon layer, the method comprising: forming an amorphous silicon layer 10 on a substrate by a patterning process, the amorphous silicon layer 10 including an amorphous silicon bottom portion 101 and located at the A plurality of first raised structures 102 and a plurality of second raised structures 103 on the amorphous silicon bottom portion 101.
  • the first raised structure 102 is located at a first area A of the substrate, such as a region where a first thin film transistor is to be formed.
  • the second raised structure 103 is located in a second region B of the substrate, such as a region where a second thin film transistor is to be formed.
  • the spacing between the first raised structures 102 is less than the spacing between the second raised structures 103.
  • the method further includes performing excimer laser crystallization on the amorphous silicon layer 10 to obtain a polysilicon layer.
  • the polysilicon layer may be applied to a display substrate including at least two thin film transistors each of the sub-pixel units, and the at least two thin film transistors include at least one first thin film transistor and at least one second thin film transistor.
  • the grain size of the polysilicon layer is proportional to the mobility
  • the grain size of the polysilicon layer formed in the first region A can be relatively small, so that the first The grain size of the polysilicon layer of the second region B is relatively large. This allows simultaneous integration of different devices, such as thin-film transistors, with mobility requirements to ensure product performance.
  • the first thin film transistor formed in the first region includes a switching thin film transistor
  • the second thin film transistor formed in the second region includes a driving thin film transistor
  • the amorphous silicon bottom portion 101 and the first bump structure 102 located in the switching thin film transistor region will be used as a switching thin film transistor after being crystallized.
  • the active layer while the amorphous silicon bottom portion 101 and the second bump structure 103 located in the driving thin film transistor region are crystallized, will serve as an active layer for driving the thin film transistor.
  • a corresponding ion implantation process is performed on the formed polysilicon layer to form an active layer as a thin film transistor.
  • the spacing between the plurality of first protruding structures 102 is 1000-2000 nm
  • the spacing between the plurality of second protruding structures 103 is 1500-2500 nm.
  • the mobility of the appropriate switching thin film transistor can be ensured, and the off-state leakage current of the switching thin film transistor can be limited to a reasonable range, and the mobility of other thin film transistors can be relatively high.
  • the plurality of first protruding structures 102 located in the first thin film transistor region are equally spaced, and the plurality of second protruding structures 103 located in the second thin film transistor region are equally spaced.
  • the uniform distribution of the polycrystalline silicon crystal grains located in the respective thin film transistor regions can be further ensured, so that the polysilicon layer formed in each of the thin film transistor regions is more uniform.
  • Forming the amorphous silicon layer 10 on the substrate by a patterning process can be achieved by the following steps:
  • an amorphous silicon film 10a is formed on a substrate, and a photoresist 20 is applied on the amorphous silicon film 10a.
  • a Plasma Enhanced Chemical Vapor Deposition (PECVD) method can be used to form a non-deposit on the substrate.
  • Crystalline silicon film 10a For example, under a pressure of 2000 mtor, a chamber temperature of 390 ° C, and a radio frequency power of 100 W, SiH 4 reacts with H 2 to deposit an amorphous silicon film 10 a on a substrate.
  • the thickness of the amorphous silicon film 10a can be, for example, However, the present invention is not limited thereto, and the thickness of the amorphous silicon film 10a may be set according to actual needs.
  • the working principle of the half-order mask 30 is explained as follows: by controlling the thickness of the light-shielding metal layer at different regions on the half-step mask 30, the intensity of transmitted light in different regions is different.
  • a photoresist completely remaining portion 201 corresponding to the completely opaque portion 301 and the translucent portion 302 of the half-order mask 30 is formed, and lithography is formed.
  • the glue half retains portion 202.
  • the principle of the gray scale mask is similar to that of the half mask 90.
  • the photoresists 20 referred to in all embodiments of the present invention are positive gels.
  • the thickness of the amorphous silicon film 10a is When the thickness of the amorphous silicon substrate 101 formed after the etching can be made
  • the shape of the first protruding structure 102 and the second protruding structure 103 may be a shape of a cube, a cylinder or the like.
  • the polysilicon layer obtained by crystallizing the amorphous silicon layer 10 when applied to the active layer, the polysilicon layer of the non-thin film transistor region can be removed by a patterning process, and then passed through corresponding The ion implantation process results in an active layer as a thin film transistor.
  • the patterned amorphous silicon layer only in the thin film transistor region can be directly formed by the following steps, so that the crystallization and corresponding ion implantation processes can be directly obtained on the basis of the above steps.
  • an active layer of a thin film transistor for example,
  • the half-order mask 30 may include a fully opaque portion 301, a translucent portion 302, and a fully transparent portion 303. That is, the half-order mask 30 means that a light-shielding metal layer which is opaque is formed in some areas on the transparent substrate material, a light-shielding metal layer which is semi-transparent is formed in other areas, and no light-shielding metal layer is formed in other areas. .
  • the semi-transmissive light-shielding metal layer has a thickness smaller than a thickness of the completely opaque light-shielding metal layer. Further, the transmittance of the semi-transmissive light-shielding metal layer to ultraviolet light can be changed by adjusting the thickness of the semi-transmissive light-shielding metal layer.
  • the working principle of the half-order mask 30 is explained as follows: by controlling the thickness of the light-shielding metal layer at different regions on the half-step mask 30, the intensity of transmitted light in different regions is different.
  • the photoresist corresponding to the completely opaque portion 301, the translucent portion 302, and the completely transparent portion 303 of the half-order mask 30 is completely retained.
  • the present invention may select, for example, a buffer layer formed on the substrate.
  • the buffer layer may be a single layer of silicon oxide, silicon nitride or a laminate of the two.
  • the embodiment of the present invention further provides a method for preparing a display substrate.
  • the method includes: a first thin film transistor region A and a second surface of the base substrate 40.
  • the thin film transistor regions B each form an active layer 50, a gate insulating layer 60 over the active layer 50, a gate electrode 70, a source electrode 801, and a drain electrode 802, and form an electrode structure.
  • the active layer 50 includes a source region 501, a drain region 502, and a channel region 503 between the source region 501 and the drain region 502.
  • the active layer 50 located in the first thin film transistor region A and the second thin film transistor region B is doped by the region corresponding to the source region 501 and the drain region 502 of the above polysilicon layer. Miscellaneous crafts are obtained.
  • FIG. 7 only two thin film transistors and corresponding electrode structures are schematically illustrated, and the connection between the two thin film transistors is not illustrated, but those skilled in the art should clearly The difference in the type of the display substrate, in either of the sub-pixel units, whether there are two thin film transistors or two or more thin film transistors, there is a corresponding connection relationship, which may be determined according to actual conditions.
  • the amorphous silicon layer 10 is etched into an amorphous silicon bottom portion 101 and the plurality of first raised structures 102 and the plurality of second raised structures 103 on the amorphous silicon bottom portion 101.
  • the nucleation can be uniformly performed during the crystallization of the amorphous silicon layer 10, thereby ensuring uniform distribution of polycrystalline silicon crystal grains in each thin film transistor region, thereby preparing a polycrystalline silicon layer having good uniformity.
  • the grain size of the polysilicon layer is proportional to the mobility, the pitch between the plurality of first bump structures 102 located in the first switching thin film transistor region is smaller than the plurality of second portions located in the second thin film transistor region
  • the pitch between the bump structures 103 is increased, the crystal grain size of the polysilicon layer formed in the first thin film transistor region may be relatively small to be formed in the second thin film transistor region.
  • the grain size of the polysilicon layer is relatively large, so that the mobility requirements of different thin film transistors can be integrated at the same time, thereby ensuring product performance.
  • the buffer layer 200 is formed, for example, on the base substrate 40.
  • the buffer layer 200 may be a single layer of silicon oxide, silicon nitride, or a laminate of the two.
  • the display substrate may be a back plate of an Organic Light-Emitting Diode (OLED).
  • OLED Organic Light-Emitting Diode
  • the electrode structure includes an anode 901 and a cathode 902.
  • the method further includes forming an organic material functional layer 903 between the anode 901 and the cathode 902.
  • the organic material functional layer 903 may include an electron transport layer, a light emitting layer, and a hole transport layer. In order to increase the efficiency of the electrons and the hole injection into the light-emitting layer, the organic material functional layer 903 may further include an electron injection layer disposed between the cathode and the electron transport layer, and at the anode a hole injection layer with the hole transport layer.
  • an encapsulation layer for encapsulating the organic material is formed to block water and oxygen, thereby forming an organic electroluminescent diode display device.
  • the single-sided light-emitting display device can be further classified into an upper light-emitting type and a lower light-emitting type depending on the materials of the anode 901 and the cathode 902.
  • the cathode 902 is disposed away from the base substrate 40, and the material of the anode 901 is a transparent conductive material, and the material of the cathode 902 is an opaque conductive material. Since the light is emitted from the anode 901 and the side of the base substrate 40, such a single-sided light-emitting display device can be referred to as a lower light-emitting type.
  • Such a single-sided light-emitting type display device can be referred to as an upper light-emitting type.
  • the cathode 902 is disposed away from the base substrate 40, or when the anode 901 is disposed away from the base substrate 40, The cathode 902 is disposed adjacent to the base substrate 40, and when the material of the anode 904 and the cathode 902 is a transparent or translucent conductive material, since light is from the anode 901 and the substrate substrate 40 side
  • the emission device is emitted from the cathode 902 and the encapsulation layer disposed opposite to the substrate 40, and thus the display device can be referred to as a double-sided illumination type.
  • the first thin film transistor includes a switching thin film transistor
  • the second thin film transistor includes a driving thin film transistor.
  • forming the active layer 50 on the first thin film transistor region and the second thin film transistor region of the base substrate 40 includes forming in the switching thin film transistor region and the driving thin film transistor region of each sub-pixel unit. The active layer 50.
  • FIG. 9 it is an equivalent circuit diagram of a connection relationship between a switching thin film transistor and a driving thin film transistor.
  • the gate electrode 70 of the switching thin film transistor is electrically connected to the gate line
  • the source electrode 801 of the switching thin film transistor is electrically connected to the data line
  • the drain electrode 802 of the switching thin film transistor is electrically connected to the gate electrode 70 of the driving thin film transistor
  • the source electrode of the thin film transistor is driven.
  • the 801 is electrically connected to the power line of the OLED
  • the drain electrode 802 of the driving thin film transistor is electrically connected to the anode 901 of the OLED.
  • the buffer layer 200 can be formed by depositing a single layer of silicon oxide, silicon nitride, or a combination of both on a substrate.
  • the thickness of the buffer layer 200 can be
  • an amorphous silicon layer 10 is formed on the buffer layer 200 by a patterning process.
  • the amorphous silicon layer 10 includes an amorphous silicon substrate 101 and a plurality of first protruding structures 102 and a plurality of second protruding structures 103 on the amorphous silicon substrate 101.
  • the first raised structure 102 is located in a switching thin film transistor region of each sub-pixel unit
  • the second raised structure 103 is located in a driving thin film transistor region of each sub-pixel unit.
  • the spacing between the plurality of first protruding structures 102 is 1000-2000 nm
  • the spacing between the plurality of second protruding structures 103 is 1500-2500 nm.
  • the thickness of the amorphous silicon substrate 101 may be The thickness of the first protrusion structure 102 and the second protrusion structure 103 may be
  • hydrogen in the amorphous silicon layer can be removed by heating at 450 ° C for 1.5 hours in a conventional annealing furnace.
  • the gate insulating layer 40 may be a single layer of silicon oxide, silicon nitride, or a laminate of the two.
  • the thickness of the gate insulating layer 40 may be
  • the gate electrode 50 may be made of a conductive material such as a metal or a metal alloy such as molybdenum or molybdenum alloy. Thickness can be
  • the active layer 50 includes a source region 501, a drain region 502, and a channel region 503 between the source region 501 and the drain region 502.
  • S207 On the basis of completing S206, an interlayer insulating layer is formed, and a source electrode 801 and a drain electrode 802 are formed on the interlayer insulating layer.
  • the source electrode 801 and the drain electrode 802 are in contact with the source region 501 and the drain region 502 through via holes formed on the interlayer insulating layer and the gate insulating layer 60, respectively.
  • the interlayer insulating layer may be a single layer of silicon oxide or a stack of silicon oxide and silicon nitride.
  • the thickness of the interlayer insulating layer can be
  • the source electrode 801 and the drain electrode 802 may be made of a conductive material such as a metal or a metal alloy such as molybdenum, molybdenum alloy, aluminum, aluminum alloy, or titanium. Thickness can be
  • a switching thin film transistor and a driving thin film transistor have been formed in which the drain electrode 802 of the switching thin film transistor is electrically connected to the gate electrode 70 of the driving thin film transistor.
  • a planarization layer is formed, and an anode 901 electrically connected to the drain electrode 802 of the driving thin film transistor, and an organic material functional layer 903 and a cathode 902 are formed on the planarization layer.
  • the back sheet of the OLED has been prepared.
  • an encapsulation layer for encapsulating an organic material is formed to block water and oxygen, thereby forming an organic electroluminescent diode display device.
  • the embodiment of the invention further provides a display substrate, which is passed through the display base described above.
  • the preparation method of the board is obtained.
  • Embodiments of the present invention also provide a display device including the display substrate.
  • Embodiments of the present invention provide a method for fabricating a polysilicon layer and a display substrate, and a display substrate, the polysilicon layer being applied to a display substrate each including at least two thin film transistors, wherein the at least two thin film transistors include There are at least one first thin film transistor and at least one second thin film transistor.
  • the amorphous silicon layer can be formed by etching the amorphous silicon layer into an amorphous silicon bottom portion and the first protruding structure and the second protruding structure on the amorphous silicon bottom portion. Uniform nucleation during crystallization ensures uniform distribution of polycrystalline silicon grains in each thin film transistor region, thereby preparing polycrystalline silicon with better uniformity.

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Abstract

Cette invention concerne un procédé de préparation d'une couche de silicium polycristallin et d'un substrat d'affichage, et un substrat d'affichage. Ledit procédé de préparation d'une couche de silicium polycristallin comprend les étapes consistant à : former une couche de silicium amorphe (10) sur un substrat au moyen d'un procédé de formation de motifs, ladite couche de silicium amorphe (10) comprenant une partie inférieure de silicium amorphe (101) et une pluralité de premières structures de renflement (102) et une pluralité de secondes structures de renflement (103) disposées sur la partie inférieure de silicium amorphe (101), la pluralité de premières structures de renflement (102) étant située dans une première région (A), la pluralité de secondes structures de renflement (103) étant située dans une seconde région (B), et l'espacement entre la pluralité de premières structures de renflement (102) étant inférieur à l'espacement entre la pluralité de secondes structures de renflement (103) ; et réaliser une cristallisation par laser à excimère sur la couche de silicium amorphe (10) afin de former une couche de silicium polycristallin. Le procédé selon l'invention permet d'intégrer simultanément les exigences de différents dispositifs concernant la vitesse de migration.
PCT/CN2014/092061 2014-06-11 2014-11-24 Procédé de préparation de couche de silicium polycristallin et de substrat d'affichage, et substrat d'affichage WO2015188594A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201410258999.X 2014-06-11
CN201410258999.XA CN104037127A (zh) 2014-06-11 2014-06-11 一种多晶硅层及显示基板的制备方法、显示基板

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WO2015188594A1 true WO2015188594A1 (fr) 2015-12-17

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