WO2015172484A1 - 阵列基板及其制造方法、显示装置 - Google Patents

阵列基板及其制造方法、显示装置 Download PDF

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Publication number
WO2015172484A1
WO2015172484A1 PCT/CN2014/086801 CN2014086801W WO2015172484A1 WO 2015172484 A1 WO2015172484 A1 WO 2015172484A1 CN 2014086801 W CN2014086801 W CN 2014086801W WO 2015172484 A1 WO2015172484 A1 WO 2015172484A1
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array substrate
signal line
substrate
protrusions
protrusion
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PCT/CN2014/086801
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English (en)
French (fr)
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张锋
曹占锋
姚琪
齐永莲
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京东方科技集团股份有限公司
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Publication of WO2015172484A1 publication Critical patent/WO2015172484A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements

Definitions

  • Embodiments of the present invention relate to an array substrate, a method of manufacturing the same, and a display device.
  • liquid crystal display devices have replaced cathode ray tube display devices as mainstream display devices in the field of daily display.
  • the resolution thereof is constantly increasing.
  • the resolution is defined as the number of pixels per inch of area in the liquid crystal display device.
  • the higher the resolution the smaller the size of the pixel unit in the liquid crystal display device, and correspondingly, as shown in FIG.
  • the spacing between the pixel electrodes 4 in the two pixel units is also getting smaller and smaller.
  • a first aspect of the present invention provides an array substrate, comprising: a substrate substrate; a signal line disposed above the substrate substrate, wherein the signal line is provided with pixel electrodes on both sides thereof, and the substrate substrate is provided with All or part of the signal line position corresponding to the protrusion.
  • a second aspect of the invention provides a display device comprising the above array substrate.
  • a third aspect of the invention provides a method of fabricating an array substrate, comprising: providing a formed a raised base substrate, wherein the protrusions correspond to all or a portion of signal line positions; and the signal lines and pixel electrodes on both sides of the signal lines are formed over the base substrate.
  • 1 is a schematic structural view of a known array substrate
  • FIG. 2 is a schematic view showing deflection of a liquid crystal molecule driven by a known array substrate
  • FIG. 3 is a schematic diagram showing the results of light leakage test of a known array substrate
  • FIG. 4 is a schematic structural view 1 of an array substrate according to an embodiment of the present invention.
  • FIG. 5 is a schematic view showing deflection of liquid crystal molecules driven by an array substrate according to an embodiment of the present invention
  • FIG. 6 is a schematic diagram of a light leakage test result of an array substrate according to an embodiment of the present invention.
  • FIG. 7 is a plan view 1 of an array substrate according to an embodiment of the present invention.
  • FIG. 8 is a schematic plan view 2 of an array substrate according to an embodiment of the present invention.
  • FIG. 9 is a schematic plan view 3 of an array substrate according to an embodiment of the present invention.
  • FIG. 10 is a plan view 4 of an array substrate according to an embodiment of the present invention.
  • FIG. 11 is a schematic plan view 5 of an array substrate according to an embodiment of the present invention.
  • FIG. 12 is a plan view 6 of an array substrate according to an embodiment of the present invention.
  • FIG. 13 is a schematic plan view 7 of an array substrate according to an embodiment of the present invention.
  • FIG. 14 is a second schematic structural diagram of an array substrate according to an embodiment of the present invention.
  • 15 is a schematic structural view 3 of an array substrate according to an embodiment of the present invention.
  • FIG. 16 is a schematic structural diagram 4 of an array substrate according to an embodiment of the present invention.
  • 1 substrate substrate
  • 2 signal line
  • 3 protrusion
  • 4 pixel electrode
  • 5 first insulating layer
  • 6 second insulating layer
  • 7 third insulating layer
  • 8 common electrode
  • 9 fourth insulating layer
  • 10 black matrix
  • 11 color film
  • 12 liquid crystal molecules
  • 13 preset region.
  • an array substrate As shown in FIG. 4, the array substrate includes:
  • the base substrate is provided with protrusions corresponding to all or part of the position of the signal line, and pixel electrodes are disposed on both sides of the signal line, it is obvious that the protrusion causes two pixel electrodes
  • the height of the substrate between the substrates is larger than the height of the pixel electrode, so that the pixel electrode is less likely to form an electric field, and the protrusion can reduce the interference of the electric field between the adjacent two pixel electrodes, and reduce the relationship between the adjacent two pixel units.
  • the color mixing and light leakage phenomenon improve the display effect of the display device.
  • the isolation of the protrusions 3 can be reduced.
  • the pixel electrode 4 interferes with the electric field of the other pixel electrode 4 in the pixel unit b adjacent thereto, thereby avoiding the liquid crystal molecules 12 and the pixel unit b between the adjacent two pixel electrodes 4 being close to the edge of the pixel unit a.
  • the liquid crystal molecules 12 at the deflection are deflected.
  • FIG. 6 when the array substrate is applied to a display device, macroscopically, the light leakage phenomenon between two adjacent pixel units in the display device is reduced, and the display effect is improved.
  • the predetermined region 13 on the base substrate 1 may be etched by an etching solution such as hydrogen fluoride (HF) to form all or part of the signal line 2 Protrusion 3.
  • HF hydrogen fluoride
  • the preset area 13 is exactly the corresponding area of the pixel unit on the array substrate.
  • the object of the present invention can be achieved by separately forming the protrusions 3 on the existing base substrate 1.
  • the presence of the protrusion 3 causes the surface of the corresponding area of the protrusion 3 to be higher than the surface of the other area after the array substrate is formed, as shown in FIG. 4, the presence of the protrusion 3 makes The surface of the array substrate corresponding to the protrusions 3 is higher than the surface of other regions, such as the surface of the pixel electrode 4, the surface of the array substrate corresponding to the protrusions 3, and the surface of the pixel electrode 4.
  • the height difference d between the surface of the array substrate corresponding to the protrusions 3 and the pixel electrode 4 is at least about 1 micrometer.
  • each pixel unit is rectangular, that is, the pixel unit includes a long side and a short side, and since the potential of the pixel electrode 4 of each pixel unit is not equal due to the operation of the display device, the pixel units are mutually not in contact.
  • FIG. 6 when the pixel unit is arranged on the array substrate, the long side and the long side of the pixel unit are adjacent, the short side and the short side are adjacent, and the long side and the short side are perpendicular.
  • the pixel electrode 4 is usually filled with the pixel unit, that is, the long side and the long side of the pixel electrode 4 are adjacent, the short side and the short side are adjacent, the long side and the short side are perpendicular, and there is a gap between the pixel electrodes 4, and the protrusion 3 can be located. At the gap between the pixel electrodes 4.
  • the protrusions 3 may be arranged in the following three types: as shown in FIG. 7, the protrusions 3 are disposed only between the long sides of the adjacent pixel electrodes 4, that is, two columns of pixel units. Correspondingly, a protrusion 3 is disposed correspondingly; or, as shown in FIG. 8, the protrusion 3 is disposed only between the short sides of the adjacent pixel electrodes 4, that is, a protrusion 3 is correspondingly arranged between the two rows of pixel units; or, for example, As shown in FIG. 7, the protrusions 3 are disposed only between the long sides of the adjacent pixel electrodes 4, that is, two columns of pixel units. Correspondingly, a protrusion 3 is disposed correspondingly; or, as shown in FIG. 8, the protrusion 3 is disposed only between the short sides of the adjacent pixel electrodes 4, that is, a protrusion 3 is correspondingly arranged between the two rows of pixel units; or, for example, As shown in FIG. 7, the protrusion
  • the protrusions 3 are disposed between the long sides of the adjacent pixel electrodes 4, and are also disposed between the short sides of the adjacent pixel electrodes 4, that is, adjacent two rows and two columns of pixel units. There is a protrusion 3 corresponding to each other.
  • a gap may be formed between the adjacent protrusions 3, or as shown in Fig. 10, a plurality of protrusions 3 located between the long sides of the adjacent columns of the pixel electrodes 4 may be integrally formed. Accordingly, the protrusions provided along the long sides in FIG. 9 may be connected to the protrusions provided along the short sides, as shown in FIG. 11, forming a plurality of small lattices surrounding each of the pixel electrodes 4. It should be set according to the actual situation, which is not limited by the embodiment of the present invention.
  • the protrusions 3 may be disposed in a plurality of rows of pixel electrodes 4.
  • the protrusions 3 are disposed apart from the two columns of pixel electrodes 4, that is, protrusions 3 are formed between each of the two columns of pixel electrodes 4.
  • the protrusions 3 may be disposed at intervals of the plurality of rows of pixel electrodes 4.
  • the protrusions 3 may be disposed by two rows of pixel electrodes 4, that is, protrusions 3 are formed between the two rows of pixel electrodes 4.
  • the signal line 2 in the embodiment of the present invention may include a data line and/or a gate line, that is, the protrusion 3 may be corresponding to the data line, may be corresponding to the gate line, or may correspond to the gate line and the data line.
  • the protrusion 3 may be corresponding to the data line, may be corresponding to the gate line, or may correspond to the gate line and the data line.
  • Settings Specifically, it should be set according to the actual situation, and the embodiment of the present invention does not specifically limit this.
  • the protrusions between the long sides of the two columns of pixel electrodes are set for the corresponding data lines.
  • the protrusion is considered to be more effective in achieving the above-described isolation effect of the electric field interference when the distance between the protrusion 3 and the adjacent two pixel electrodes 4 which are close to each other is small, and therefore, referring to FIG. 4 It is shown that the width of the protrusion 3 is greater than or equal to the width of the data line, for example, 3 to 6 micrometers.
  • the protrusions 3 located between the short sides of the two rows of pixel electrodes 4 are protrusions provided corresponding to the gate lines.
  • the width of the protrusion 3 is greater than or equal to the width of the gate line, for example, 3 to 6 ⁇ m.
  • the array substrate is an array substrate of a twisted nematic (TN) mode. At this time, at least a substrate is formed on the substrate substrate 1 of the array substrate.
  • the first insulating layer 5 under the signal line 2, the second insulating layer 6 over the signal line 2, and the third insulating layer 7, the pixel electrode 4 is located above the third insulating layer 7.
  • the array substrate is an array substrate of an Advanced Super Dimension Switch (ADS) mode, that is, formed on the pixel electrode 4 on the basis of FIG. 3 .
  • the fourth insulating layer 9 insulates the common electrode 8 and the pixel electrode 4 to ensure normal operation of the array substrate.
  • ADV Advanced Super Dimension Switch
  • ADS Advanced Super Dimension Switch
  • Its core technical characteristics are described as: the electric field generated by the edge of the slit electrode in the same plane and the electric field generated between the slit electrode layer and the plate electrode layer.
  • the multi-dimensional electric field is formed, so that all the aligned liquid crystal molecules between the slit electrodes in the liquid crystal cell and directly above the electrode can be rotated, thereby improving the working efficiency of the liquid crystal and increasing the light transmission efficiency.
  • Advanced super-dimensional field conversion technology can improve the picture quality of TFT-LCD products, with high resolution, high transmittance, low power consumption, wide viewing angle, high aperture ratio, low chromatic aberration, push mura, etc. advantage.
  • the improved technology of ADS technology is divided into high transmittance I-ADS technology, high aperture ratio H-ADS and high resolution S-ADS technology.
  • the common electrode 8 of the above embodiment may be in the shape of a plate or a slit, as is the pixel electrode 4; of course, the upper and lower order of the pixel electrode 4 and the common electrode 8 may be reversed, as shown in FIG. And both the pixel electrode 4 and the common electrode 8 may be slit electrodes.
  • the second insulating layer 6 in FIGS. 4, 14, and 15 may be omitted.
  • the array substrate is a COA array substrate.
  • a black matrix 10 and a color film 11 are formed on the second insulating layer 6 in FIG. 16, and then a third insulating layer 7, a common electrode 8, and a fourth insulating layer are sequentially formed over the color film 11.
  • the pixel electrode 4 here is in the shape of a slit.
  • the black matrix 10 is the boundary of the color film 11 of two colors
  • the color film corresponding to the black matrix 10 A solid line is drawn at 11 to indicate that the color of the color film 11 on the left and right sides of the line is different.
  • the common electrode 8 may be in the shape of a plate or a slit, and the pixel electrode 4 is also the same; of course, the upper and lower order of the pixel electrode 4 and the common electrode 8 may be reversed, and both the pixel electrode 4 and the common electrode 8 may be slit electrodes. This will not be repeated here.
  • the height of the protrusions 3 of the base substrate 1 may be 1 to 2 ⁇ m, and at the same time, in order to facilitate the fabrication of the signal lines 2, the width of the protrusions 3 Greater than or equal to the width of the signal line 2, for example, the protrusion 3 may have a width of 3 to 6 ⁇ m.
  • the embodiment of the invention further provides a display device comprising the above array substrate.
  • the display device may be a product or a component having any display function such as a liquid crystal panel, a liquid crystal television, a liquid crystal display, a digital photo frame, a mobile phone, or a tablet computer.
  • Embodiments of the present invention provide a method for fabricating an array substrate, including:
  • Step S101 providing a substrate substrate formed with protrusions corresponding to all or part of signal line positions.
  • Step S102 forming the signal line and the pixel electrodes on both sides of the signal line above the base substrate.
  • the step S101 may include:
  • the base substrate 1 is etched such that a portion of the base substrate 1 is formed as a protrusion 3 corresponding to the position of all or part of the signal lines 2.
  • a predetermined region on the base substrate 1 may be etched by a glass etching solution such as hydrogen fluoride (HF) to form protrusions 3 corresponding to all or part of the signal lines 2.
  • HF hydrogen fluoride
  • the protrusions 3 may be disposed corresponding to all of the signal lines 2, or may be disposed only corresponding to the part of the signal lines 2 on the premise that the pixel electrodes 4 do not interfere with each other, for example, the protrusions 3 and all odd-numbered lines or all even-numbered lines of signal lines 2 The location corresponds.
  • the signal line 2 in the embodiment of the present invention may include a data line and/or a gate line, that is, the protrusion 3 may be Corresponding to the data line setting, the corresponding gate line setting, and the corresponding grid line and the data line setting, wherein the position of the protrusion 3 should be set according to the actual situation, which is not specifically limited in the embodiment of the present invention.
  • the height of the protrusions 3 of the base substrate 1 may be 1 to 2 ⁇ m, and at the same time, in order to facilitate the fabrication of the signal lines 2, the width of the protrusions 3 Greater than or equal to the width of the signal line 2, for example, the protrusion 3 may have a width of 3 to 6 microns.

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Abstract

一种阵列基板及其制造方法、显示装置。该阵列基板包括：衬底基板（1）和设置于所述衬底基板上方的信号线（2），所述信号线（2）两侧设置有像素电极（4），所述衬底基板（1）提供有全部或部分所述信号线（2）位置对应的突起（3），上述阵列基板能够防止LCD中相邻像素电极形成相互干扰的电场，保证LCD的显示效果。

Description

阵列基板及其制造方法、显示装置 技术领域
本发明实施例涉及一种阵列基板及其制造方法、显示装置。
背景技术
随着薄膜晶体管液晶显示(TFT-LCD Display)技术的发展和进步，液晶显示装置已经取代了阴极射线管显示装置成为了日常显示领域的主流显示装置。
为了不断提高液晶显示装置显示图像的质量，其分辨率在不断地提高。分辨率定义为液晶显示装置中每英寸面积内的像素的数量，这样一来，分辨率越高则液晶显示装置中像素单元的尺寸就越小，相应地，如图1所示，相邻的两个像素单元中的像素电极4之间的间距也越来越小，当给像素电极4通入一定的工作电压时，将导致相邻的两个像素电极4之间的电场发生干扰(如图中箭头所示)，从而影响显示画面的质量。
例如，如图2所示，当仅要求像素单元a内的液晶分子12偏转而与该像素单元a相邻的另一个像素单元b内的液晶分子12不发生偏转时，由于像素单元a与像素单元b之间的间隔很小，使得相邻的两个像素电极4之间的电场发生干扰，导致相邻的像素单元a与像素单元b之间的液晶分子12、以及像素单元b靠近像素单元a的边缘处的液晶分子12发生偏转，从而如图3所示，使液晶显示装置中相邻的像素单元产生混色、漏光等现象，影响了液晶显示装置的显示效果。
发明内容
本发明的第一方面提供了一种阵列基板，包括：衬底基板、设置于所述衬底基板上方的信号线，所述信号线两侧设置有像素电极，所述衬底基板提供有与全部或部分所述信号线位置对应的突起。
本发明的第二方面提供了一种显示装置，包括上述的阵列基板。
本发明的第三方面提供了一种阵列基板的制造方法，包括：提供形成有 突起的衬底基板，其中所述突起与全部或部分信号线位置对应；和在所述衬底基板上方形成所述信号线和位于所述信号线两侧的像素电极。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1为已知阵列基板的结构示意图；
图2为已知阵列基板驱动液晶分子的偏转示意图；
图3为已知阵列基板漏光性测试结果示意图；
图4为本发明实施例中的阵列基板的结构示意图一；
图5为本发明实施例中的阵列基板驱动液晶分子的偏转示意图；
图6为本发明实施例中的阵列基板漏光性测试结果示意图；
图7为本发明实施例中的阵列基板的平面示意图一；
图8为本发明实施例中的阵列基板的平面示意图二；
图9为本发明实施例中的阵列基板的平面示意图三；
图10为本发明实施例中的阵列基板的平面示意图四；
图11为本发明实施例中的阵列基板的平面示意图五；
图12为本发明实施例中的阵列基板的平面示意图六；
图13为本发明实施例中的阵列基板的平面示意图七；
图14为本发明实施例中的阵列基板的结构示意图二；
图15为本发明实施例中的阵列基板的结构示意图三；
图16为本发明实施例中的阵列基板的结构示意图四。
附图标记说明：
1—衬底基板；2—信号线；3—突起；4—像素电极；5—第一绝缘层；
6—第二绝缘层；7—第三绝缘层；8—公共电极；9—第四绝缘层；10—黑矩阵；11—彩膜；12—液晶分子；13—预设区域。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
实施例一
本发明实施例提供一种阵列基板，如图4所示，该阵列基板包括：
衬底基板1和设置于所述衬底基板1上方的信号线2，所述信号线2两侧设置有像素电极4，所述衬底基板1提供有与全部或部分所述信号线2位置对应的突起3。
在本发明实施例的技术方案中，由于所述衬底基板提供有与全部或部分所述信号线位置对应的突起，并且所述信号线两侧设置有像素电极，显然，突起导致两像素电极之间的衬底基板高度较大，大于像素电极的高度，使得像素电极不易形成电场，该突起可以减少相邻的两个像素电极之间电场的干扰，降低相邻的两个像素单元之间的混色、漏光现象，提高显示装置的显示效果。
如图5所示，在所述阵列基板应用于显示装置并工作时，当像素单元a内的像素电极4对应的液晶分子12发生偏转时，由于上述的所述突起3的隔离作用，可以减小该像素电极4对与其相邻的像素单元b内的另一个像素电极4的电场干扰，从而避免了相邻两个像素电极4之间的液晶分子12以及像素单元b靠近像素单元a的边缘处的液晶分子12发生偏转。如图6所示，当所述阵列基板应用于显示装置时，宏观上表现为减少了显示装置中的相邻的两个像素单元之间的漏光现象，提高了显示效果。
如图4所示，若衬底基板1为玻璃制成，可利用氟化氢(HF)等腐蚀液对衬底基板1上的预设区域13进行腐蚀处理，形成对应全部或部分所述信号线2的突起3。该预设区域13恰好是阵列基板上的像素单元的对应区域。可选地，可以在现有衬底基板1上单独制作突起3同样能实现本发明目的。
显然，由于衬底基板1提供有突起3，该突起3的存在导致阵列基板制成后，突起3的对应区域的表面会高于其他区域的表面，如图4所示，突起3的存在使得突起3所对应的阵列基板的表面高于其他区域的表面，例如像素电极4的表面，所述突起3所对应的阵列基板的表面和像素电极4的表面 之间的高度差较大时，突起3所起到的隔离相邻两个像素电极4之间的电场干扰作用更为明显。在一个示例中，所述突起3所对应的阵列基板的表面和像素电极4之间的高度差d至少约为1微米。
如图5所示，每一像素单元都为矩形，即像素单元包括长边和短边，并且由于显示装置在工作时，每一像素单元的像素电极4的电势不相等，因此，像素单元相互不接触。如图6所示，在像素单元排布于阵列基板上时，像素单元的长边和长边相邻，短边和短边相邻，长边和短边相垂直。由于像素电极4通常充满像素单元，即像素电极4的长边和长边相邻，短边和短边相邻，长边和短边相垂直，像素电极4之间有间隙，突起3可位于像素电极4之间的间隙处。
因此，在本发明实施例中，突起3的设置可有如下三种：如图7所示，所述突起3仅设置在相邻的像素电极4的长边之间，即两列像素单元之间对应设置一个突起3；或者，如图8所示，所述突起3仅设置在相邻的像素电极4的短边之间，即两行像素单元之间对应设置一个突起3；或者，如图9所示，所述突起3既设置在相邻的像素电极4的长边之间，也设置在相邻的像素电极4的短边之间，即相邻两行和两列像素单元之间都对应设置有一个突起3。
如图7所示，相邻突起3之间可以形成有空隙，也可以如图10所示，位于两列相邻的像素电极4的长边之间的多个突起3相连形成一整体。相应的，图9中的沿长边设置的突起可以与沿短边设置的突起相连，如图11所示，形成包围每一像素电极4的多个小格子。具体应根据实际情况进行设置，本发明实施例对此不进行限制。
类似的，突起3还可以间隔数列像素电极4设置，例如，如图12所示，突起3间隔两列像素电极4设置，即每两列像素电极4之间形成有突起3。相应的，突起3也可以间隔数行像素电极4设置，例如，如图13所示，突起3可间隔两行像素电极4设置，即每两行像素电极4之间形成有突起3。
综上所述，本发明实施例中的信号线2可包括数据线和/或栅线，即，所述突起3可对应数据线设置、可对应栅线设置、也可对应栅线和数据线设置。具体应根据实际情况进行设置，本发明实施例对此不进行具体限制。
在一个示例中，位于两列像素电极的长边之间的突起为对应数据线设置 的突起，考虑到当所述突起3与相互靠近的所述相邻的两个像素电极4之间的距离较小时，对实现上述的电场干扰的隔离效果更为有效，因此，参考图4所示，所述突起3的宽度大于等于所述数据线的宽度，例如为3～6微米。
在一个示例中，位于两行像素电极4的短边之间的突起3为对应栅线设置的突起。所述突起3的宽度大于等于所述栅线的宽度，例如为3～6微米。
在一个示例中，如图4所示，该阵列基板为扭曲向列型(Twisted Nematic，简称TN)模式的阵列基板，此时，该阵列基板的衬底基板1之上至少还形成有位于所述信号线2之下的第一绝缘层5、信号线2之上的第二绝缘层6和第三绝缘层7，像素电极4位于第三绝缘层7之上。
在另一个示例中，如图14所示，该阵列基板为高级超维场转换(Advanced Super Dimension Switch，简称ADS)模式的阵列基板，即在图3的基础上，在像素电极4之上形成狭缝状的公共电极8和位于像素电极4和公共电极8之间的第四绝缘层9。第四绝缘层9将公共电极8和像素电极4绝缘，保证阵列基板的正常工作。
所谓高级超维场转换技术(ADvanced Super Dimension Switch)，简称ADS,其核心技术特性描述为：通过同一平面内狭缝电极边缘所产生的电场以及狭缝电极层与板状电极层间产生的电场形成多维电场，使液晶盒内狭缝电极间、电极正上方所有取向液晶分子都能够产生旋转，从而提高了液晶工作效率并增大了透光效率。高级超维场转换技术可以提高TFT-LCD产品的画面品质，具有高分辨率、高透过率、低功耗、宽视角、高开口率、低色差、无挤压水波纹(push Mura)等优点。针对不同应用，ADS技术的改进技术分为高透过率I-ADS技术、高开口率H-ADS和高分辨率S-ADS技术等。
本领域技术人员应该可以理解，上述实施例的公共电极8可以为板状或者狭缝状，像素电极4也是如此；当然，像素电极4和公共电极8的上下顺序可颠倒，如图15所示，而且像素电极4和公共电极8均可以为狭缝状电极。
另外，为了减少制作成本、简化工艺流程，图4、图14和图15中的第二绝缘层6可以略去。
在又一个示例中，如图16所示，该阵列基板为COA阵列基板。相对于图3而言，图16中第二绝缘层6之上形成有黑矩阵10和彩膜11，之后，依次在彩膜11之上形成第三绝缘层7、公共电极8、第四绝缘层9和像素电极 4，此处的像素电极4为狭缝状。
需要说明的是，由于一般黑矩阵10两侧的彩膜11的颜色不同，即黑矩阵10为两种颜色的彩膜11的交界处，因此，在图16中，黑矩阵10对应的彩膜11处画上一条实线来表示线左右的彩膜11的颜色不同。
公共电极8可以为板状或者狭缝状，像素电极4也是如此；当然，像素电极4和公共电极8的上下顺序可颠倒，而且像素电极4和公共电极8均可以为狭缝状电极，在此不再赘述。
在上述示例中，为了保证像素电极4之间互不干扰，所述衬底基板1的突起3的高度可为1～2微米，同时，为了便于信号线2的制作，所述突起3的宽度大于或等于所述信号线2的宽度，例如，所述突起3的宽度可为3～6微米。
本发明实施例还提供了一种显示装置，包括上述的阵列基板。该显示装置可以为：液晶面板、液晶电视、液晶显示器、数码相框、手机、平板电脑等具有任何显示功能的产品或部件。
实施例二
本发明实施例提供了一种阵列基板的制造方法，包括：
步骤S101、提供形成有突起的衬底基板，所述凸起对应于全部或部分信号线位置。
步骤S102、在所述衬底基板上方形成所述信号线和位于所述信号线两侧的像素电极。
若衬底基板1为玻璃制成，所述步骤S101可包括：
对所述衬底基板1进行刻蚀，使得所述衬底基板1的一部分形成为与全部或部分信号线2位置对应的突起3。
例如若衬底基板1为玻璃制成，可利用氟化氢(HF)等玻璃腐蚀液对衬底基板1上的预设区域进行腐蚀处理，形成对应全部或部分所述信号线2设置的突起3。
突起3可对应全部信号线2设置，也可在保证像素电极4互不干扰的前提下，仅对应部分信号线2设置，例如，所述突起3与所有奇数行或所有偶数行的信号线2位置对应。
本发明实施例中的信号线2可包括数据线和/或栅线，即，所述突起3可 对应数据线设置、可对应栅线设置、也可对应栅线和数据线设置，其中，突起3的位置应根据实际情况进行设置，本发明实施例对此不进行具体限制。
在一个示例中，为了保证像素电极4之间互不干扰，所述衬底基板1的突起3的高度可为1～2微米，同时，为了便于信号线2的制作，所述突起3的宽度大于或等于所述信号线2的宽度，例如所述突起3的宽度可为3～6微米。
以上所述仅是本发明的示范性实施方式，而非用于限制本发明的保护范围，本发明的保护范围由所附的权利要求确定。
本申请基于并且要求于2014年5月13日递交的中国专利申请第201410200272.6号的优先权，在此全文引用上述中国专利申请公开的内容。

Claims (16)

  1. 一种阵列基板，包括：衬底基板和设置于所述衬底基板上方的信号线，所述信号线两侧设置有像素电极，所述衬底基板提供有与全部或部分所述信号线位置对应的突起。
  2. 根据权利要求1所述的阵列基板，其中所述突起与所有奇数行或所有偶数行的信号线位置对应。
  3. 根据权利要求1或2所述的阵列基板，其中所述信号线包括数据线和栅线中的至少一种。
  4. 根据权利要求1-3任一项所述的阵列基板，其中所述突起的高度为1～2微米，所述突起的宽度大于或等于所述信号线的宽度。
  5. 根据权利要求4所述的阵列基板，其中所述突起的宽度为3～6微米。
  6. 根据权利要求1-5任一项所述的阵列基板，其中所述突起为格子形状。
  7. 根据权利要求1-5任一项所述的阵列基板，其中所述衬底基板提供有相互间隔的多个突起。
  8. 一种显示装置，包括权利要求1-7任一项所述的阵列基板。
  9. 一种阵列基板的制造方法，包括：
    提供形成有突起的衬底基板，其中所述突起与全部或部分信号线位置对应；和
    在所述衬底基板上方形成所述信号线和位于所述信号线两侧的像素电极。
  10. 根据权利要求9所述的制造方法，其中所述提供形成有突起的衬底基板包括：对所述衬底基板进行刻蚀，使得所述衬底基板的一部分形成为与全部或部分信号线位置对应的突起。
  11. 根据权利要求9或10所述的制造方法，其中所述突起与所有奇数行或所有偶数行的信号线位置对应。
  12. 根据权利要求9-11任一项所述的制造方法，其中所述信号线包括数据线和栅线中的至少一种。
  13. 根据权利要求9-12任一项所述的制造方法，其中所述突起的高度为1～2微米，所述突起的宽度大于或等于所述信号线的宽度。
  14. 根据权利要求13所述的制造方法，其中所述突起的宽度为3～6微米。
  15. 根据权利要求9-14任一项所述的制造方法，其中所述突起为格子形状。
  16. 根据权利要求9-15任一项所述的制造方法，其中所述衬底基板提供有相互间隔的多个突起。
PCT/CN2014/086801 2014-05-13 2014-09-18 阵列基板及其制造方法、显示装置 WO2015172484A1 (zh)

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