WO2015146247A1 - Variable gain transimpedance amplifier - Google Patents

Variable gain transimpedance amplifier Download PDF

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Publication number
WO2015146247A1
WO2015146247A1 PCT/JP2015/051459 JP2015051459W WO2015146247A1 WO 2015146247 A1 WO2015146247 A1 WO 2015146247A1 JP 2015051459 W JP2015051459 W JP 2015051459W WO 2015146247 A1 WO2015146247 A1 WO 2015146247A1
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Prior art keywords
transistor
variable
current source
variable gain
emitter
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PCT/JP2015/051459
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French (fr)
Japanese (ja)
Inventor
慎介 中野
正史 野河
秀之 野坂
裕之 福山
十林　正俊
茂弘 栗田
雅広 遠藤
Original Assignee
日本電信電話株式会社
Ｎｔｔエレクトロニクス株式会社
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Publication of WO2015146247A1 publication Critical patent/WO2015146247A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/04—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only
    • H03F3/08—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only controlled by light
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/32—Modifications of amplifiers to reduce non-linear distortion
    • H03F1/3211—Modifications of amplifiers to reduce non-linear distortion in differential amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/4508—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using bipolar transistors as the active amplifying circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G1/00—Details of arrangements for controlling amplification
    • H03G1/0005—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal
    • H03G1/0017—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal the device being at least one of the amplifying solid state elements of the amplifier
    • H03G1/0023—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal the device being at least one of the amplifying solid state elements of the amplifier in emitter-coupled or cascode amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45306—Indexing scheme relating to differential amplifiers the common gate stage implemented as dif amp eventually for cascode dif amp
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45318—Indexing scheme relating to differential amplifiers the AAC comprising a cross coupling circuit, e.g. two extra transistors cross coupled

Definitions

  • the present invention relates to a transimpedance amplifier for converting a current signal converted from an optical signal by a light receiving element into a voltage signal in an optical receiver for receiving an optical signal, and particularly to a variable gain transimpedance amplifier having a variable gain. It is.
  • a transimpedance amplifier is used in an optical receiver and plays a role of converting a current signal converted from an optical signal by a light receiving element into a voltage signal.
  • the variable gain TIA having a variable gain is used for an application that requires a wide dynamic range of an optical signal.
  • the optical receiver is desired to be capable of receiving optical signals of various modulation formats and high symbol rate transmission. For this reason, it is desired that a wide bandwidth characteristic and a wide linear operation characteristic are compatible as the TIA characteristic.
  • FIG. 12 shows a configuration example of a general base-grounded variable gain TIA.
  • the variable gain TIA of FIG. 12 includes a transistor Q10, a load resistor RL, and a variable current source IS.
  • Vcc is a positive power supply voltage
  • Vcs1 is a fixed bias voltage
  • Vcs2 is a gain control bias voltage for controlling gain
  • Iin is an input signal
  • Vout is an output signal.
  • the grounded base transistor Q10 is used, the amount of current of the variable current source IS is changed by the gain control bias voltage Vcs2, and the amount of current flowing through the transistor Q10 is controlled, thereby changing the amplification factor of the transistor Q10. I try to let them.
  • FIG. 13 shows a conventional configuration example of the differential variable gain TIA.
  • the differential variable gain TIA of FIG. 13 includes transistors Q10 to Q13, load resistors RL10 and RL11, and constant current sources IS10 and IS11.
  • Vctl is a variable gain control voltage
  • IinP is a positive phase input signal
  • IinN is a negative phase input signal
  • VoutP is a positive phase output signal
  • VoutN is a negative phase output signal.
  • FIG. 14 shows a configuration example of another differential variable gain TIA.
  • the variable gain TIA is realized by controlling the amount of current flowing through the transistors Q10 and Q13 by the transistors Q11 and Q12 and the variable gain control voltage Vctl.
  • variable gain TIA In the variable gain TIA shown in FIG. 12, since the load at the signal output terminal (the collector of the transistor Q10) can be realized only by the load resistor RL and the transistor Q10, the bandwidth can be increased. However, in the configuration shown in FIG. 12, since the gain is controlled by controlling the amount of current of the variable current source IS, the DC operating point of the signal output terminal changes depending on the amount of current flowing through the transistor Q10, and a wide linear operating region is obtained. There is a problem that the output cannot be removed (the output waveform is greatly distorted).
  • transistors Q11 and Q12 for newly controlling current are added between the signal output terminal (collectors of the transistors Q10 and Q13) and the constant current sources IS10 and IS11. By doing so, a linear operation region can be secured.
  • the transistors Q11 and Q12 increase as loads at the signal output terminal, which causes a problem that the bandwidth of the amplifier deteriorates and it is difficult to increase the bandwidth.
  • the load at the signal output terminal (the collectors of the transistors Q10 and Q13) can be realized only by the load resistors RL10 and RL11 and the transistors Q10 and Q13 as in the configuration of FIG.
  • the load at the signal output terminal can be realized only by the load resistors RL10 and RL11 and the transistors Q10 and Q13 as in the configuration of FIG.
  • the DC of the signal output terminal is the same as in the configuration of FIG. Since the operating point changes, there is a problem that a wide linear operating region cannot be obtained.
  • the present invention has been made to solve the above-described problems, and an object thereof is to provide a variable gain TIA having a wide bandwidth and a wide linear operation region.
  • the variable gain transimpedance amplifier of the present invention has a first transistor having an emitter connected to a signal input terminal, a collector connected to a signal output terminal, grounded at the base, and an emitter of the first transistor.
  • a current source having one end connected to the first power source and the other end connected to the negative power supply voltage, and a first and a second connected in series between the positive power supply voltage and the collector of the first transistor.
  • a variable resistance control voltage one end connected to a connection point between the first load resistance and the second load resistance, and the other end connected to the emitter of the first transistor.
  • a first variable current source capable of controlling the amount of current according to the above.
  • the variable gain transimpedance amplifier of the present invention has an emitter connected to the positive phase signal input terminal, a collector connected to the negative phase signal output terminal, and a first transistor grounded at the base, A second transistor having an emitter connected to the phase signal input terminal, a collector connected to the positive phase signal output terminal, grounded at the base, and one end connected to the emitter of the first transistor; A second current source having a first current source having a second end connected to the negative power supply voltage, a first end connected to the emitter of the second transistor, and a second end connected to the negative power supply voltage. Between the current source, the first and second load resistors connected in series between the positive power supply voltage and the collector of the first transistor, and between the positive power supply voltage and the collector of the second transistor.
  • the third and fourth load resistors connected to each other, one end connected to the connection point between the first load resistor and the second load resistor, and the other end connected to the emitter of the first transistor.
  • a first variable current source capable of controlling the amount of current according to the gain variable control voltage, and one end connected to a connection point between the third load resistor and the fourth load resistor
  • a second variable current source having a second end connected to the emitter of the second transistor and capable of controlling the amount of current according to the variable gain control voltage.
  • the load resistor connected to the signal output terminal is divided into a series connection of the first and second load resistors, and the first variable current is connected between the connection point of these two load resistors and the signal input terminal. Connect sources.
  • the present invention it is possible to suppress an increase in load at the signal output terminal and to control the current of the first transistor for gain control.
  • the voltage change of the signal output terminal caused by the current of the first transistor can be reduced.
  • a variable gain transimpedance amplifier having a wide bandwidth and a wide linear operation region can be realized.
  • the load resistance connected to the negative-phase signal output terminal is divided into a series connection of the first and second load resistances, and the second resistance is connected between the connection point of these two load resistances and the signal input terminal.
  • the load resistance connected to the positive phase signal output terminal is divided into a series connection of third and fourth load resistances, and the connection point between these two load resistances and the signal input terminal A second variable current source is connected between them.
  • FIG. 1 is a circuit diagram showing a configuration example of a variable gain transimpedance amplifier according to a first embodiment of the present invention.
  • FIG. 2 is a circuit diagram showing a configuration example of a variable gain transimpedance amplifier according to the second embodiment of the present invention.
  • FIG. 3 is a circuit diagram showing a configuration example of a variable gain transimpedance amplifier according to the third embodiment of the present invention.
  • FIG. 4 is a diagram showing gain-frequency characteristics of a conventional variable gain transimpedance amplifier and a variable gain transimpedance amplifier according to the third embodiment of the present invention.
  • FIG. 5A is a diagram showing input current-output voltage characteristics of a conventional variable gain transimpedance amplifier.
  • FIG. 5A is a diagram showing input current-output voltage characteristics of a conventional variable gain transimpedance amplifier.
  • FIG. 5B is a diagram showing input current-output voltage characteristics of a conventional variable gain transimpedance amplifier.
  • FIG. 5C is a graph showing input current-output voltage characteristics of the variable gain transimpedance amplifier according to the third example of the present invention.
  • FIG. 6 is a circuit diagram showing a configuration example of a variable gain transimpedance amplifier according to the fourth embodiment of the present invention.
  • FIG. 7 is a circuit diagram showing another configuration example of the variable gain transimpedance amplifier according to the fourth exemplary embodiment of the present invention.
  • FIG. 8 is a circuit diagram showing a configuration example of a variable gain transimpedance amplifier according to the fifth embodiment of the present invention.
  • FIG. 9 is a circuit diagram showing another configuration example of the variable gain transimpedance amplifier according to the fifth exemplary embodiment of the present invention.
  • FIG. 10 is a circuit diagram showing a configuration example of a variable gain transimpedance amplifier according to the sixth embodiment of the present invention.
  • FIG. 11 is a circuit diagram showing another configuration example of the variable gain transimpedance amplifier according to the sixth exemplary embodiment of the present invention.
  • FIG. 12 is a circuit diagram showing a configuration example of a conventional base-grounded variable gain transimpedance amplifier.
  • FIG. 13 is a circuit diagram showing a configuration example of a conventional differential variable gain transimpedance amplifier.
  • FIG. 14 is a circuit diagram showing another configuration example of a conventional differential variable gain transimpedance amplifier.
  • FIG. 1 is a circuit diagram showing a configuration example of a variable gain TIA according to the first embodiment of the present invention.
  • the variable gain TIA of this embodiment has a bias voltage Vcs applied to the base, a transistor Q1 whose emitter is connected to the signal input terminal of the variable gain TIA, and a collector connected to the signal output terminal of the variable gain TIA.
  • the load resistors RL1 and RL2 connected in series between the power supply voltage Vcc and the collector of the transistor Q1, one end connected to the emitter of the transistor Q1, and the other end connected to the negative power supply voltage (GND ground).
  • the current source IS1 and a variable current source IS2 having one end connected to the connection point of the load resistors RL1 and RL2 and the other end connected to the emitter of the transistor Q1.
  • An input signal Iin is input to the signal input terminal (emitter of the transistor Q1), and an output signal Vout is output from the signal output terminal (collector of the transistor Q1).
  • the bias voltage Vcs (Vcc> Vcs) may be set to a value that does not saturate the transistor Q1, for example.
  • a variable current source IS2 is connected between a connection node of these two load resistors RL1 and RL2 and a node (emitter of the transistor Q1) to which the signal input terminal is connected.
  • variable gain TIA is controlled by controlling the amount of current of the variable current source IS2 by the variable gain control voltage Vctl and changing the amount of current flowing through the common base transistor Q1 to change the amplification factor of the transistor Q1.
  • the gain is changed.
  • the current flowing through the variable current source IS2 may be increased and the current flowing through the transistor Q1 may be decreased.
  • the current flowing through the variable current source IS2 may be reduced and the current flowing through the transistor Q1 may be increased.
  • the impedance Z of the load connected to the signal output terminal is expressed by Equation (3). Since RL> RL1, in the variable gain TIA of this embodiment, signal attenuation does not occur until the frequency band in which Expression (4) is established.
  • variable gain TIA of this embodiment it is possible to make the bandwidth wider than the conventional variable gain TIA shown in FIG.
  • the conventional variable gain TIA shown in FIG. 14 since one end of the variable current source formed by the transistors Q11 and Q12 is connected to the positive power supply voltage Vcc, the signal output terminal (collector of the transistors Q10 and Q13).
  • the impedance of the load connected to is configured so as not to be affected by the parasitic capacitance associated with the variable current source, so that the bandwidth can be increased.
  • variable gain TIA of this embodiment when the current flowing through the variable current source IS2 is increased and the current flowing through the transistor Q1 is decreased in order to reduce the gain of the TIA, the current flowing through the load resistor RL1 is reduced. Decrease. However, even in this case, in the variable gain TIA of this embodiment, the current flowing through the load resistor RL2 does not fluctuate, so that the DC operation of the signal output terminal (collector of the transistor Q1) is more than that of the conventional variable gain TIA shown in FIG. The rise of the points can be suppressed, and the linear operation region can be kept wide. Thus, in this embodiment, a variable gain TIA with a wide bandwidth and a wide linear operation region can be realized.
  • FIG. 2 is a circuit diagram showing a configuration example of the variable gain TIA according to the second embodiment of the present invention, and the same components as those in FIG. 1 are denoted by the same reference numerals.
  • the variable current source IS2 of the first embodiment is constituted by a transistor Q2.
  • the variable gain control voltage Vctl is input to the base of the transistor Q2, the collector is connected to the connection point of the load resistors RL1 and RL2, and the emitter is connected to the emitter of the transistor Q1.
  • the current flowing through the transistor Q2 may be increased by the variable gain control voltage Vctl, and the current flowing through the transistor Q1 may be decreased.
  • the current flowing through the transistor Q2 may be reduced and the current flowing through the transistor Q1 may be increased.
  • variable current source In order to form a variable current source, there is a technique that uses a MOSFET element as a commonly used technique.
  • the parasitic capacitance associated with the variable current source greatly affects the TIA band
  • the bipolar transistor Q2 having a relatively small parasitic capacitance is used as the variable current source in this embodiment. This makes it possible to broaden the TIA bandwidth compared to the case of using a MOSFET. Further, the present invention can be applied to a semiconductor process in which an FET cannot be formed.
  • FIG. 3 is a circuit diagram showing a configuration example of the variable gain TIA according to the third embodiment of the present invention.
  • the same reference numerals are given to the same configurations as those in FIGS.
  • the variable gain TIA of this embodiment has transistors Q1 and Q2, load resistors RL1 and RL2, a constant current source IS1, a bias voltage Vcs applied to the base, and an emitter connected to the negative phase signal input terminal of the variable gain TIA.
  • Transistor Q4 whose collector is connected to the positive phase signal output terminal of variable gain TIA, load resistors RL3 and RL4 connected in series between the positive power supply voltage Vcc and the collector of transistor Q4, and one end of which is a transistor
  • a constant current source IS3 connected to the emitter of Q4 and the other end connected to the negative power supply voltage (GND ground)
  • a variable gain control voltage Vctl is applied to the base
  • the collector is connected to the connection point of the load resistors RL3 and RL4.
  • the transistor Q3 is a variable current source which is connected and whose emitter is connected to the emitter of the transistor Q4.
  • the bias voltage Vcs may be set to a value that does not saturate the transistors Q1 and Q4, for example.
  • the present embodiment is an example in which the input / output of the configuration example shown in the second embodiment is converted to a differential signal, and the positive phase input signal IinP is input to the positive phase signal input terminal (emitter of the transistor Q1), and the reverse A negative phase input signal IinN is input to the phase signal input terminal (emitter of the transistor Q4), a positive phase output signal VoutP is output from the positive phase signal output terminal (collector of the transistor Q4), and a negative phase signal output terminal (transistor) A negative phase output signal VoutN is output from the collector of Q1.
  • the current flowing through the transistors Q2 and Q3 may be increased by the variable gain control voltage Vctl, and the current flowing through the transistors Q1 and Q4 may be decreased.
  • the current flowing through the transistors Q2 and Q3 may be reduced and the current flowing through the transistors Q1 and Q4 may be increased.
  • the same effects as those of the first embodiment and the second embodiment are realized, and the common-mode noise included in the differential input signal can be reduced by differentially operating the circuit.
  • FIG. 4 shows simulation results of gain-frequency characteristics of the conventional variable gain TIA of FIG. 13, simulation results of gain-frequency characteristics of the conventional variable gain TIA of FIG. 14, and gain-frequency of the variable gain TIA of this embodiment. The simulation result of characteristics is shown. 4, 40 is the gain-frequency characteristic of the conventional variable gain TIA of FIG. 13, 41 is the gain-frequency characteristic of the conventional variable gain TIA of FIG. 14, and 42 is the gain-frequency characteristic of the variable gain TIA of this embodiment. Show.
  • the conventional variable gain TIA of FIG. 13 has a gain of 1 / ⁇ 2, the ⁇ 3 dB band is 15.675 GHz, the conventional variable gain TIA of FIG. 14 has a ⁇ 3 dB band of 26.988 GHz, and the variable gain TIA of this embodiment
  • the ⁇ 3 dB band is 24.613 GHz.
  • the -3 dB band is inferior by about 10% compared to the conventional variable gain TIA of FIG. 14, but the performance of the variable gain TIA of FIG. It can be confirmed that improvement is possible.
  • FIG. 5A shows the simulation results of the input current-output voltage characteristics under various gain conditions of the conventional variable gain TIA of FIG. 13, and FIG. 5B shows the simulation results of the conventional variable gain TIA of FIG. 14 under various gain conditions. The simulation result of the input current-output voltage characteristic is shown, and FIG. 5C shows the simulation result of the input current-output voltage characteristic under various gain conditions of the variable gain TIA of this embodiment.
  • the conventional variable gain TIA of FIG. 13 and the variable gain TIA of the present embodiment have about ⁇ 0.2 to +0.
  • the output voltage is linear in a wide input current range up to about 2
  • the conventional variable gain TIA in FIG. 14 has a linear output voltage only in a narrow range of about +0.1 to +0.2. . From the simulation results shown in FIGS. 4 and 5A to 5C, it can be understood that a variable gain TIA having a wide bandwidth and a wide linear operation region can be realized by using this embodiment.
  • FIG. 6 is a circuit diagram showing a configuration example of the variable gain TIA according to the fourth embodiment of the present invention.
  • the same reference numerals are given to the same configurations as those in FIGS.
  • the variable gain TIA of this embodiment includes a variable current source having transistors Q1 and Q2, load resistors RL1 and RL2, one end connected to the emitter of the transistor Q1, and the other end connected to a negative power supply voltage (GND ground).
  • the IS1a, the average voltage detection circuit 1 for detecting the average voltage of the output signal Vout of the variable gain TIA, the average voltage of the output signal Vout and the reference voltage Vref are compared, and the variable current source IS1a is compared according to the comparison result.
  • a comparison circuit 2 for controlling the amount of current for controlling the amount of current.
  • the gain control method of the variable gain TIA is as described in the first and second embodiments.
  • a comparison circuit 2 for comparing the average voltage of the output signal Vout and the reference voltage Vref is provided, and the amount of current of the variable current source IS1a, that is, the signal input terminal (emitter of the transistor Q1) is determined by the output of the comparison circuit 2.
  • the amount of current flowing between the negative power sources is controlled.
  • the current flowing between the load input RL2 can be increased by increasing the current flowing between the signal input terminal and the negative power source, and the DC operating point of the signal output terminal (collector of the transistor Q1) is lowered. be able to.
  • the comparison circuit 2 increases the current amount of the variable current source IS1a when the average voltage of the output signal Vout is higher than the reference voltage Vref, and the current amount of the variable current source IS1a when the average voltage of the output signal Vout is lower than the reference voltage Vref. Should be reduced. As a result, it is possible to suppress a change in the DC operating point of the signal output terminal that occurs when controlling the gain of the TIA.
  • the reference voltage Vref may be determined in advance so that, for example, a linear operation region having a desired width of TIA can be obtained.
  • FIG. 6 shows a configuration example in which only the variable current source IS1a is provided between the emitter of the transistor Q1 and the negative power supply voltage and the current amount of the variable current source IS1a is controlled, this is not restrictive.
  • a constant current source IS1 may be provided, and a variable current source IS1a may be provided in parallel with the constant current source IS1 to control the current amount of the variable current source IS1a.
  • the configuration in this case is shown in FIG.
  • FIG. 8 is a circuit diagram showing a configuration example of a variable gain TIA according to the fifth embodiment of the present invention.
  • the same reference numerals are given to the same configurations as those in FIGS.
  • the variable gain TIA of this embodiment includes transistors Q1 and Q2, load resistors RL1 and RL2, a variable current source IS1a, an amplitude detection circuit 3 that detects the amplitude of the output signal Vout of the variable gain TIA, and the output signal Vout.
  • a comparison circuit 4 that compares the amplitude with the reference amplitude and controls the current amount of the variable current source IS1a according to the comparison result is constituted.
  • an amplitude detection circuit 3 for detecting the amplitude of the output signal Vout of the variable gain TIA is provided, the amplitude of the output signal Vout and the reference amplitude are compared by the comparison circuit 4, and the variable current source IS1a is output by the output of the comparison circuit 4. , That is, the amount of current flowing between the signal input terminal (emitter of the transistor Q1) and the negative power source is controlled.
  • the current flowing through the transistor Q1 increases, and the gain as an amplifier increases.
  • the comparison circuit 4 increases the current amount of the variable current source IS1a when the amplitude of the output signal Vout is smaller than the desired reference amplitude, and the current amount of the variable current source IS1a when the amplitude of the output signal Vout is larger than the reference amplitude. Should be reduced. As a result, it is possible to suppress a change in the amplitude of the output signal Vout that occurs when the amplitude of the input signal Iin fluctuates or when the gain of the TIA is changed, and a signal having a constant amplitude can always be output.
  • FIG. 8 shows a configuration example in which only the variable current source IS1a is provided between the emitter of the transistor Q1 and the negative power supply voltage and the current amount of the variable current source IS1a is controlled
  • the present invention is not limited to this.
  • a constant current source IS1 may be provided, and a variable current source IS1a may be provided in parallel with the constant current source IS1 to control the current amount of the variable current source IS1a.
  • the configuration in this case is shown in FIG.
  • FIG. 10 is a circuit diagram showing a configuration example of the variable gain TIA according to the sixth embodiment of the present invention.
  • the same reference numerals are given to the same configurations as those in FIGS. 1 to 3 and FIG.
  • the variable gain TIA of this embodiment is a variable current source in which transistors Q1 to Q4, load resistors RL1 to RL4, one end is connected to the emitter of the transistor Q1, and the other end is connected to the negative power supply voltage (GND ground).
  • variable current source IS3a having one end connected to the emitter of the transistor Q4 and the other end connected to the negative power supply voltage, and average voltages of the positive phase output signal VoutP and the negative phase output signal VoutN of the variable gain TIA Is compared with the average voltage of the positive phase output signal VoutP and the average voltage of the negative phase output signal VoutN, and the current amounts of the variable current sources IS1a and IS3a are controlled according to the comparison result.
  • a comparison circuit 2a a comparison circuit 2a.
  • the gain control method of the variable gain TIA is as described in the third embodiment.
  • a comparison circuit 2a that compares the average voltage of the positive phase output signal VoutP and the average voltage of the negative phase output signal VoutN is provided. It controls the amount of current flowing between the phase signal input terminal (emitter of transistor Q1) and the negative power source and the amount of current flowing between the negative phase signal input terminal (emitter of transistor Q4) and the negative power source.
  • the DC operating point of the negative-phase signal output terminal (the collector of the transistor Q1) is lowered due to an increase in the amount of current between the positive-phase signal input terminal and the negative-side power supply, and between the negative-phase signal input terminal and the negative-side power supply.
  • the DC operating point of the positive phase signal output terminal decreases. Therefore, by relatively changing these two current amounts, the circuit on the positive phase input side (transistors Q1 and Q2, load resistors RL1 and RL2, variable current source IS1a) and the circuit on the negative phase input side (transistors Q3 and Q3).
  • the offset of the DC operating point of the positive / negative phase signal output terminal caused by the mismatch of Q4, load resistors RL3, RL4, and variable current source IS3a) can be suppressed.
  • the comparison circuit 2a increases the current amount of the variable current source IS1a when the average voltage of the negative phase output signal VoutN is higher than the average voltage of the positive phase output signal VoutP, and the current amount of the variable current source IS3a is increased. cut back. Further, when the average voltage of the negative phase output signal VoutN is lower than the average voltage of the positive phase output signal VoutP, the comparison circuit 2a decreases the current amount of the variable current source IS1a and increases the current amount of the variable current source IS3a. Thus, the average voltage of the positive phase output signal VoutP and the average voltage of the negative phase output signal VoutN can be matched.
  • the comparison circuit 2a fixes the current amount of the variable current source IS3a, and increases the current amount of the variable current source IS1a when the average voltage of the negative phase output signal VoutN is higher than the average voltage of the positive phase output signal VoutP. When the average voltage of the phase output signal VoutN is lower than the average voltage of the positive phase output signal VoutP, the current amount of the variable current source IS1a may be reduced.
  • the current amount of the variable current source IS1a when the current amount of the variable current source IS1a is fixed and the average voltage of the negative phase output signal VoutN is higher than the average voltage of the positive phase output signal VoutP, the current amount of the variable current source IS3a is reduced and the negative phase output signal VoutN When the average voltage is lower than the average voltage of the positive phase output signal VoutP, the amount of current of the variable current source IS3a may be increased.
  • FIG. 10 shows a configuration example in which variable current sources IS1a and IS3a are provided between the emitters of the transistors Q1 and Q4 and the negative power supply voltage to control the current amounts of the variable current sources IS1a and IS3a. It is not limited to. As in the third embodiment, constant current sources IS1 and IS3 are provided, and variable current sources IS1a and IS3a are provided in parallel with the constant current sources IS1 and IS3 to control the current amounts of the variable current sources IS1a and IS3a. May be. The configuration in this case is shown in FIG.
  • the present invention can be applied to a transimpedance amplifier.
  • Q1 to Q4 ... transistor, RL1 to RL4 ... load resistance, IS1, IS3 ... constant current source, IS1a, IS2, IS3a ... variable current source, 1,1a ... average voltage detection circuit, 2,2a, 4 ... comparison circuit, 3 ... Amplitude detection circuit.

Abstract

This transimpedance amplifier is provided with: a transistor (Q1) that has an emitter connected to a signal input terminal, a collector connected to a signal output terminal, and a grounded base; a constant current source (IS1) that has one end connected to the emitter of the transistor (Q1) and the other end connected to a negative-side power supply voltage; load resistances (RL1, RL2) that are connected in series between a positive-side power supply voltage and the collector of the transistor (Q1); and a variable current source (IS2) that has one end connected to a connection point of the load resistances (RL1, RL2) and the other end connected to the emitter of the transistor (Q1), and can control amperage in accordance with a variable gain control voltage (Vctl).

Description

可変利得トランスインピーダンスアンプVariable gain transimpedance amplifier
　本発明は、光信号を受信する光受信器において、受光素子によって光信号から変換された電流信号を電圧信号に変換するためのトランスインピーダンスアンプに関し、特に利得が可変な可変利得トランスインピーダンスアンプに関するものである。 The present invention relates to a transimpedance amplifier for converting a current signal converted from an optical signal by a light receiving element into a voltage signal in an optical receiver for receiving an optical signal, and particularly to a variable gain transimpedance amplifier having a variable gain. It is.
　トランスインピーダンスアンプ（Transimpedance Amplifier：ＴＩＡ）は、光受信器に用いられ、受光素子によって光信号から変換された電流信号を電圧信号に変換する役割を果たす。特に利得が可変な可変利得ＴＩＡは、光信号の広いダイナミックレンジが求められるアプリケーションに用いられる。光受信器は、様々な変調形式の光信号受信や高シンボルレート伝送に対応出来ることが望まれる。このため、ＴＩＡの特性として、広い帯域特性および広い線形動作特性の両立が望まれる。 A transimpedance amplifier (TIA) is used in an optical receiver and plays a role of converting a current signal converted from an optical signal by a light receiving element into a voltage signal. In particular, the variable gain TIA having a variable gain is used for an application that requires a wide dynamic range of an optical signal. The optical receiver is desired to be capable of receiving optical signals of various modulation formats and high symbol rate transmission. For this reason, it is desired that a wide bandwidth characteristic and a wide linear operation characteristic are compatible as the TIA characteristic.
　図１２に一般的なベース接地型の可変利得ＴＩＡの構成例を示す。図１２の可変利得ＴＩＡは、トランジスタＱ１０と、負荷抵抗ＲＬと、可変電流源ＩＳとから構成される。図１２におけるＶｃｃは正側電源電圧、Ｖｃｓ１は固定のバイアス電圧、Ｖｃｓ２は利得を制御するための利得制御バイアス電圧、Ｉｉｎは入力信号、Ｖｏｕｔは出力信号である。図１２の構成では、ベース接地型トランジスタＱ１０を用い、利得制御バイアス電圧Ｖｃｓ２によって可変電流源ＩＳの電流量を変化させ、トランジスタＱ１０に流れる電流量を制御することで、トランジスタＱ１０の増幅率を変化させるようにしている。 FIG. 12 shows a configuration example of a general base-grounded variable gain TIA. The variable gain TIA of FIG. 12 includes a transistor Q10, a load resistor RL, and a variable current source IS. In FIG. 12, Vcc is a positive power supply voltage, Vcs1 is a fixed bias voltage, Vcs2 is a gain control bias voltage for controlling gain, Iin is an input signal, and Vout is an output signal. In the configuration of FIG. 12, the grounded base transistor Q10 is used, the amount of current of the variable current source IS is changed by the gain control bias voltage Vcs2, and the amount of current flowing through the transistor Q10 is controlled, thereby changing the amplification factor of the transistor Q10. I try to let them.
　図１３に差動可変利得ＴＩＡの従来構成例を示す。図１３の差動可変利得ＴＩＡは、トランジスタＱ１０～Ｑ１３と、負荷抵抗ＲＬ１０，ＲＬ１１と、定電流源ＩＳ１０，ＩＳ１１とから構成される。図１３におけるＶｃｔｌは利得可変制御電圧、ＩｉｎＰは正相入力信号、ＩｉｎＮは逆相入力信号、ＶｏｕｔＰは正相出力信号、ＶｏｕｔＮは逆相出力信号である。図１３の差動可変利得ＴＩＡは、文献「N.N.Prokopenko，P.S.Budyakov，and A.I.Serebryakov，“Analog Controlled Amplifiers and Voltage Multipliers Based on Modified Gilbert Cells”，5th European Conference on Circuits and Systems for Communications（ECCSC2010），p.140-144，2010」に開示されたギルバートセル型の可変利得ＴＩＡにおいて、増幅作用の役割を成すトランジスタＱ１０，Ｑ１３を、ベース接地型トランジスタで構成した例である。 FIG. 13 shows a conventional configuration example of the differential variable gain TIA. The differential variable gain TIA of FIG. 13 includes transistors Q10 to Q13, load resistors RL10 and RL11, and constant current sources IS10 and IS11. In FIG. 13, Vctl is a variable gain control voltage, IinP is a positive phase input signal, IinN is a negative phase input signal, VoutP is a positive phase output signal, and VoutN is a negative phase output signal. The differential variable gain TIA of FIG. 13 is described in the documents “NNProkopenko, PSBudyakov, and AISerebryakov,“ Analog Controlled Amplifiers and Voltage Multipliers Based on Modified Gilbert Cells ”, 5th European Conference on Circuits andicSystems In the Gilbert cell type variable gain TIA disclosed in “.140-144, 2010”, the transistors Q10 and Q13 which play a role of amplification function are configured as grounded base type transistors.
　また、図１４に別の差動可変利得ＴＩＡの構成例を示す。図１４の例では、トランジスタＱ１０，Ｑ１３に流れる電流量をトランジスタＱ１１，Ｑ１２および利得可変制御電圧Ｖｃｔｌによって制御することで、可変利得ＴＩＡを実現している。 FIG. 14 shows a configuration example of another differential variable gain TIA. In the example of FIG. 14, the variable gain TIA is realized by controlling the amount of current flowing through the transistors Q10 and Q13 by the transistors Q11 and Q12 and the variable gain control voltage Vctl.
　図１２に示した可変利得ＴＩＡでは、信号出力端子（トランジスタＱ１０のコレクタ）における負荷を負荷抵抗ＲＬおよびトランジスタＱ１０のみで実現できるため、広帯域化が可能となる。しかしながら、図１２に示した構成では、可変電流源ＩＳの電流量を制御することで利得を制御するため、トランジスタＱ１０に流れる電流量によって信号出力端子のＤＣ動作点が変化し、広い線形動作領域が取れない（出力波形が大きく歪む）という問題点があった。 In the variable gain TIA shown in FIG. 12, since the load at the signal output terminal (the collector of the transistor Q10) can be realized only by the load resistor RL and the transistor Q10, the bandwidth can be increased. However, in the configuration shown in FIG. 12, since the gain is controlled by controlling the amount of current of the variable current source IS, the DC operating point of the signal output terminal changes depending on the amount of current flowing through the transistor Q10, and a wide linear operating region is obtained. There is a problem that the output cannot be removed (the output waveform is greatly distorted).
　一方、図１３に示した差動可変利得ＴＩＡでは、信号出力端子（トランジスタＱ１０，Ｑ１３のコレクタ）と定電流源ＩＳ１０，ＩＳ１１との間に新たに電流を制御するためのトランジスタＱ１１，Ｑ１２を追加することにより、線形動作領域を確保することができる。しかし、図１３に示した構成では、信号出力端子における負荷としてトランジスタＱ１１，Ｑ１２が増えるため、アンプの帯域が劣化し、広帯域化が困難になるという問題点があった。 On the other hand, in the differential variable gain TIA shown in FIG. 13, transistors Q11 and Q12 for newly controlling current are added between the signal output terminal (collectors of the transistors Q10 and Q13) and the constant current sources IS10 and IS11. By doing so, a linear operation region can be secured. However, in the configuration shown in FIG. 13, the transistors Q11 and Q12 increase as loads at the signal output terminal, which causes a problem that the bandwidth of the amplifier deteriorates and it is difficult to increase the bandwidth.
　また、図１４に示した差動可変利得ＴＩＡでは、信号出力端子（トランジスタＱ１０，Ｑ１３のコレクタ）における負荷は図１２の構成と同様に負荷抵抗ＲＬ１０，ＲＬ１１およびトランジスタＱ１０，Ｑ１３のみで実現できるため、広帯域化が可能な構成となる。しかし、図１４に示した構成では、低い増幅率で差動可変利得ＴＩＡを動作させた場合、すなわちトランジスタＱ１１，Ｑ１２に大きな電流を流した場合、図１２の構成と同様に信号出力端子のＤＣ動作点が変化するため、広い線形動作領域が取れないという問題点があった。 Further, in the differential variable gain TIA shown in FIG. 14, the load at the signal output terminal (the collectors of the transistors Q10 and Q13) can be realized only by the load resistors RL10 and RL11 and the transistors Q10 and Q13 as in the configuration of FIG. Thus, it is possible to increase the bandwidth. However, in the configuration shown in FIG. 14, when the differential variable gain TIA is operated with a low gain, that is, when a large current is passed through the transistors Q11 and Q12, the DC of the signal output terminal is the same as in the configuration of FIG. Since the operating point changes, there is a problem that a wide linear operating region cannot be obtained.
　本発明は、上記課題を解決するためになされたもので、広帯域かつ線形動作領域が広い可変利得ＴＩＡを提供することを目的とする。 The present invention has been made to solve the above-described problems, and an object thereof is to provide a variable gain TIA having a wide bandwidth and a wide linear operation region.
　本発明の可変利得トランスインピーダンスアンプは、信号入力端子に接続されたエミッタと、信号出力端子に接続されたコレクタとを有し、ベース接地された第１のトランジスタと、前記第１のトランジスタのエミッタに接続された一端と、負側電源電圧に接続された他端とを有する電流源と、正側電源電圧と前記第１のトランジスタのコレクタとの間に直列に接続された第１、第２の負荷抵抗と、前記第１の負荷抵抗と第２の負荷抵抗との接続点に接続された一端と、前記第１のトランジスタのエミッタに接続された他端とを有し、利得可変制御電圧に応じて電流量を制御することが可能な第１の可変電流源とを備えることを特徴とするものである。 The variable gain transimpedance amplifier of the present invention has a first transistor having an emitter connected to a signal input terminal, a collector connected to a signal output terminal, grounded at the base, and an emitter of the first transistor. A current source having one end connected to the first power source and the other end connected to the negative power supply voltage, and a first and a second connected in series between the positive power supply voltage and the collector of the first transistor. A variable resistance control voltage, one end connected to a connection point between the first load resistance and the second load resistance, and the other end connected to the emitter of the first transistor. And a first variable current source capable of controlling the amount of current according to the above.
　また、本発明の可変利得トランスインピーダンスアンプは、正相信号入力端子に接続されたエミッタと、逆相信号出力端子に接続されたコレクタとを有し、ベース接地された第１のトランジスタと、逆相信号入力端子に接続されたエミッタと、正相信号出力端子に接続されたコレクタとを有し、ベース接地された第２のトランジスタと、前記第１のトランジスタのエミッタに接続された一端と、負側電源電圧に接続された他端とを有する第１の電流源と、前記第２のトランジスタのエミッタに接続された一端と、負側電源電圧に接続された他端とを有する第２の電流源と、正側電源電圧と前記第１のトランジスタのコレクタとの間に直列に接続された第１、第２の負荷抵抗と、正側電源電圧と前記第２のトランジスタのコレクタとの間に直列に接続された第３、第４の負荷抵抗と、前記第１の負荷抵抗と第２の負荷抵抗との接続点に接続された一端と、前記第１のトランジスタのエミッタに接続された他端とを有し、利得可変制御電圧に応じて電流量を制御することが可能な第１の可変電流源と、前記第３の負荷抵抗と第４の負荷抵抗との接続点に接続された一端と、前記第２のトランジスタのエミッタに接続された他端とを有し、前記利得可変制御電圧に応じて電流量を制御することが可能な第２の可変電流源とを備えることを特徴とするものである。 The variable gain transimpedance amplifier of the present invention has an emitter connected to the positive phase signal input terminal, a collector connected to the negative phase signal output terminal, and a first transistor grounded at the base, A second transistor having an emitter connected to the phase signal input terminal, a collector connected to the positive phase signal output terminal, grounded at the base, and one end connected to the emitter of the first transistor; A second current source having a first current source having a second end connected to the negative power supply voltage, a first end connected to the emitter of the second transistor, and a second end connected to the negative power supply voltage. Between the current source, the first and second load resistors connected in series between the positive power supply voltage and the collector of the first transistor, and between the positive power supply voltage and the collector of the second transistor. Directly The third and fourth load resistors connected to each other, one end connected to the connection point between the first load resistor and the second load resistor, and the other end connected to the emitter of the first transistor. And a first variable current source capable of controlling the amount of current according to the gain variable control voltage, and one end connected to a connection point between the third load resistor and the fourth load resistor And a second variable current source having a second end connected to the emitter of the second transistor and capable of controlling the amount of current according to the variable gain control voltage. To do.
　本発明では、信号出力端子に接続された負荷抵抗を第１、第２の負荷抵抗の直列接続に分割し、これら２つの負荷抵抗の接続点と信号入力端子との間に第１の可変電流源を繋げる。これにより、本発明では、信号出力端子の負荷増加を小さく抑え、かつ利得制御のために第１のトランジスタの電流を制御することができる。また、本発明では、第１のトランジスタの電流によって生じる信号出力端子の電圧変化を小さくすることができる。その結果、本発明では、広帯域かつ線形動作領域が広い可変利得トランスインピーダンスアンプを実現することができる。 In the present invention, the load resistor connected to the signal output terminal is divided into a series connection of the first and second load resistors, and the first variable current is connected between the connection point of these two load resistors and the signal input terminal. Connect sources. Thereby, in the present invention, it is possible to suppress an increase in load at the signal output terminal and to control the current of the first transistor for gain control. In the present invention, the voltage change of the signal output terminal caused by the current of the first transistor can be reduced. As a result, in the present invention, a variable gain transimpedance amplifier having a wide bandwidth and a wide linear operation region can be realized.
　また、本発明では、逆相信号出力端子に接続された負荷抵抗を第１、第２の負荷抵抗の直列接続に分割し、これら２つの負荷抵抗の接続点と信号入力端子との間に第１の可変電流源を繋げると共に、正相信号出力端子に接続された負荷抵抗を第３、第４の負荷抵抗の直列接続に分割し、これら２つの負荷抵抗の接続点と信号入力端子との間に第２の可変電流源を繋げる。その結果、本発明では、広帯域かつ線形動作領域が広い差動可変利得トランスインピーダンスアンプを実現することができる。 Further, in the present invention, the load resistance connected to the negative-phase signal output terminal is divided into a series connection of the first and second load resistances, and the second resistance is connected between the connection point of these two load resistances and the signal input terminal. 1, the load resistance connected to the positive phase signal output terminal is divided into a series connection of third and fourth load resistances, and the connection point between these two load resistances and the signal input terminal A second variable current source is connected between them. As a result, in the present invention, a differential variable gain transimpedance amplifier having a wide bandwidth and a wide linear operation region can be realized.
図１は、本発明の第１実施例に係る可変利得トランスインピーダンスアンプの構成例を示す回路図である。FIG. 1 is a circuit diagram showing a configuration example of a variable gain transimpedance amplifier according to a first embodiment of the present invention. 図２は、本発明の第２実施例に係る可変利得トランスインピーダンスアンプの構成例を示す回路図である。FIG. 2 is a circuit diagram showing a configuration example of a variable gain transimpedance amplifier according to the second embodiment of the present invention. 図３は、本発明の第３実施例に係る可変利得トランスインピーダンスアンプの構成例を示す回路図である。FIG. 3 is a circuit diagram showing a configuration example of a variable gain transimpedance amplifier according to the third embodiment of the present invention. 図４は、従来の可変利得トランスインピーダンスアンプおよび本発明の第３実施例に係る可変利得トランスインピーダンスアンプの利得－周波数特性を示す図である。FIG. 4 is a diagram showing gain-frequency characteristics of a conventional variable gain transimpedance amplifier and a variable gain transimpedance amplifier according to the third embodiment of the present invention. 図５Ａは、従来の可変利得トランスインピーダンスアンプの入力電流－出力電圧特性を示す図である。FIG. 5A is a diagram showing input current-output voltage characteristics of a conventional variable gain transimpedance amplifier. 図５Ｂは、従来の可変利得トランスインピーダンスアンプの入力電流－出力電圧特性を示す図である。FIG. 5B is a diagram showing input current-output voltage characteristics of a conventional variable gain transimpedance amplifier. 図５Ｃは、本発明の第３実施例に係る可変利得トランスインピーダンスアンプの入力電流－出力電圧特性を示す図である。FIG. 5C is a graph showing input current-output voltage characteristics of the variable gain transimpedance amplifier according to the third example of the present invention. 図６は、本発明の第４実施例に係る可変利得トランスインピーダンスアンプの構成例を示す回路図である。FIG. 6 is a circuit diagram showing a configuration example of a variable gain transimpedance amplifier according to the fourth embodiment of the present invention. 図７は、本発明の第４実施例に係る可変利得トランスインピーダンスアンプの別の構成例を示す回路図である。FIG. 7 is a circuit diagram showing another configuration example of the variable gain transimpedance amplifier according to the fourth exemplary embodiment of the present invention. 図８は、本発明の第５実施例に係る可変利得トランスインピーダンスアンプの構成例を示す回路図である。FIG. 8 is a circuit diagram showing a configuration example of a variable gain transimpedance amplifier according to the fifth embodiment of the present invention. 図９は、本発明の第５実施例に係る可変利得トランスインピーダンスアンプの別の構成例を示す回路図である。FIG. 9 is a circuit diagram showing another configuration example of the variable gain transimpedance amplifier according to the fifth exemplary embodiment of the present invention. 図１０は、本発明の第６実施例に係る可変利得トランスインピーダンスアンプの構成例を示す回路図である。FIG. 10 is a circuit diagram showing a configuration example of a variable gain transimpedance amplifier according to the sixth embodiment of the present invention. 図１１は、本発明の第６実施例に係る可変利得トランスインピーダンスアンプの別の構成例を示す回路図である。FIG. 11 is a circuit diagram showing another configuration example of the variable gain transimpedance amplifier according to the sixth exemplary embodiment of the present invention. 図１２は、従来のベース接地型の可変利得トランスインピーダンスアンプの構成例を示す回路図である。FIG. 12 is a circuit diagram showing a configuration example of a conventional base-grounded variable gain transimpedance amplifier. 図１３は、従来の差動可変利得トランスインピーダンスアンプの構成例を示す回路図である。FIG. 13 is a circuit diagram showing a configuration example of a conventional differential variable gain transimpedance amplifier. 図１４は、従来の差動可変利得トランスインピーダンスアンプの別の構成例を示す回路図である。FIG. 14 is a circuit diagram showing another configuration example of a conventional differential variable gain transimpedance amplifier.
［第１実施例］
　以下、本発明の実施例について図面を参照して説明する。図１は本発明の第１実施例に係る可変利得ＴＩＡの構成例を示す回路図である。本実施例の可変利得ＴＩＡは、ベースにバイアス電圧Ｖｃｓが与えられ、エミッタが可変利得ＴＩＡの信号入力端子に接続され、コレクタが可変利得ＴＩＡの信号出力端子に接続されたトランジスタＱ１と、正側電源電圧ＶｃｃとトランジスタＱ１のコレクタとの間に直列に接続された負荷抵抗ＲＬ１，ＲＬ２と、一端がトランジスタＱ１のエミッタに接続され、他端が負側電源電圧（ＧＮＤ接地）に接続された定電流源ＩＳ１と、一端が負荷抵抗ＲＬ１，ＲＬ２の接続点に接続され、他端がトランジスタＱ１のエミッタに接続された可変電流源ＩＳ２とから構成される。信号入力端子（トランジスタＱ１のエミッタ）には入力信号Ｉｉｎが入力され、信号出力端子（トランジスタＱ１のコレクタ）からは出力信号Ｖｏｕｔが出力される。バイアス電圧Ｖｃｓ（Ｖｃｃ＞Ｖｃｓ）は、例えばトランジスタＱ１が飽和しない程度の値に設定すればよい。 [First embodiment]
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing a configuration example of a variable gain TIA according to the first embodiment of the present invention. The variable gain TIA of this embodiment has a bias voltage Vcs applied to the base, a transistor Q1 whose emitter is connected to the signal input terminal of the variable gain TIA, and a collector connected to the signal output terminal of the variable gain TIA. The load resistors RL1 and RL2 connected in series between the power supply voltage Vcc and the collector of the transistor Q1, one end connected to the emitter of the transistor Q1, and the other end connected to the negative power supply voltage (GND ground). The current source IS1 and a variable current source IS2 having one end connected to the connection point of the load resistors RL1 and RL2 and the other end connected to the emitter of the transistor Q1. An input signal Iin is input to the signal input terminal (emitter of the transistor Q1), and an output signal Vout is output from the signal output terminal (collector of the transistor Q1). The bias voltage Vcs (Vcc> Vcs) may be set to a value that does not saturate the transistor Q1, for example.
　図１に示すように、本実施例では、信号出力端子に接続された負荷抵抗ＲＬをＲＬ１，ＲＬ２の２つの抵抗の直列接続に分割（ＲＬ＝ＲＬ１＋ＲＬ２）する。そして、これら２つの負荷抵抗ＲＬ１，ＲＬ２の接続ノードと信号入力端子が接続されているノード（トランジスタＱ１のエミッタ）との間に、可変電流源ＩＳ２を繋げた構成を取る。 As shown in FIG. 1, in this embodiment, the load resistor RL connected to the signal output terminal is divided into two resistors RL1 and RL2 connected in series (RL = RL1 + RL2). A variable current source IS2 is connected between a connection node of these two load resistors RL1 and RL2 and a node (emitter of the transistor Q1) to which the signal input terminal is connected.
　本実施例では、利得可変制御電圧Ｖｃｔｌによって可変電流源ＩＳ２の電流量を制御し、ベース接地型のトランジスタＱ１に流れる電流量を変化させてトランジスタＱ１の増幅率を変化させることにより、可変利得ＴＩＡの利得を変化させるようにしている。ＴＩＡの利得を小さくするためには、可変電流源ＩＳ２に流れる電流を増やし、トランジスタＱ１に流れる電流を減らせばよい。反対にＴＩＡの利得を大きくするためには、可変電流源ＩＳ２に流れる電流を減らし、トランジスタＱ１に流れる電流を増やせばよい。 In this embodiment, the variable gain TIA is controlled by controlling the amount of current of the variable current source IS2 by the variable gain control voltage Vctl and changing the amount of current flowing through the common base transistor Q1 to change the amplification factor of the transistor Q1. The gain is changed. In order to reduce the gain of the TIA, the current flowing through the variable current source IS2 may be increased and the current flowing through the transistor Q1 may be decreased. On the other hand, in order to increase the gain of TIA, the current flowing through the variable current source IS2 may be reduced and the current flowing through the transistor Q1 may be increased.
　図１３に示した従来例では、仮にトランジスタＱ１１，Ｑ１２のコレクタに付随する寄生容量をＣparaとすると、出力負荷のインピーダンスＺは式（１）のようになる。したがって、図１３に示した従来例では、式（２）が成立する周波数帯では信号が減衰する。 In the conventional example shown in FIG. 13, assuming that the parasitic capacitance associated with the collectors of the transistors Q11 and Q12 is C para , the impedance Z of the output load is expressed by equation (1). Therefore, in the conventional example shown in FIG. 13, the signal is attenuated in the frequency band in which Expression (2) is established.
Figure JPOXMLDOC01-appb-M000001
Figure JPOXMLDOC01-appb-M000001
Figure JPOXMLDOC01-appb-M000002
Figure JPOXMLDOC01-appb-M000002
　一方、本実施例の可変利得ＴＩＡでは、可変電流源ＩＳ２に付随する寄生容量を先ほどと同じＣparaとすると、信号出力端子に接続される負荷のインピーダンスＺは式（３）となる。ＲＬ＞ＲＬ１であるため、本実施例の可変利得ＴＩＡでは、式（４）が成立する周波数帯まで信号減衰が生じない。 On the other hand, in the variable gain TIA of the present embodiment, assuming that the parasitic capacitance associated with the variable current source IS2 is the same as C para as described above, the impedance Z of the load connected to the signal output terminal is expressed by Equation (3). Since RL> RL1, in the variable gain TIA of this embodiment, signal attenuation does not occur until the frequency band in which Expression (4) is established.
Figure JPOXMLDOC01-appb-M000003
Figure JPOXMLDOC01-appb-M000003
Figure JPOXMLDOC01-appb-M000004
Figure JPOXMLDOC01-appb-M000004
　よって、本実施例の可変利得ＴＩＡを用いることで、図１３に示した従来の可変利得ＴＩＡよりも広帯域化が可能となる。一方、図１４に示した従来の可変利得ＴＩＡでは、トランジスタＱ１１，Ｑ１２によって形成される可変電流源の一端が正側電源電圧Ｖｃｃに接続されるため、信号出力端子（トランジスタＱ１０，Ｑ１３のコレクタ）に接続される負荷のインピーダンスは可変電流源に付随する寄生容量の影響を受けない構成となっており、広帯域化が可能である。ただし、図１４に示した従来の可変利得ＴＩＡでは、ＴＩＡの利得を小さくするためにトランジスタＱ１１，Ｑ１２に流れる電流を増やした場合、トランジスタＱ１０，Ｑ１３に流れる電流が減って、負荷抵抗ＲＬ１０，ＲＬ１１に流れる電流も減るため、信号出力端子のＤＣ動作点が上昇し、線形動作領域が狭くなってしまうという問題点があった。 Therefore, by using the variable gain TIA of this embodiment, it is possible to make the bandwidth wider than the conventional variable gain TIA shown in FIG. On the other hand, in the conventional variable gain TIA shown in FIG. 14, since one end of the variable current source formed by the transistors Q11 and Q12 is connected to the positive power supply voltage Vcc, the signal output terminal (collector of the transistors Q10 and Q13). The impedance of the load connected to is configured so as not to be affected by the parasitic capacitance associated with the variable current source, so that the bandwidth can be increased. However, in the conventional variable gain TIA shown in FIG. 14, when the currents flowing through the transistors Q11 and Q12 are increased in order to reduce the gain of the TIA, the currents flowing through the transistors Q10 and Q13 are reduced and the load resistors RL10 and RL11. As a result, the DC operating point of the signal output terminal rises and the linear operating region becomes narrow.
　これに対して、本実施例の可変利得ＴＩＡでは、同様にＴＩＡの利得を小さくするために可変電流源ＩＳ２に流れる電流を増やし、トランジスタＱ１に流れる電流を減らした場合、負荷抵抗ＲＬ１に流れる電流が減る。しかし、この場合でも、本実施例の可変利得ＴＩＡでは、負荷抵抗ＲＬ２に流れる電流は変動しないため、図１４に示した従来の可変利得ＴＩＡよりも信号出力端子（トランジスタＱ１のコレクタ）のＤＣ動作点の上昇を抑えることができ、線形動作領域を広く保つことが可能となる。こうして、本実施例では、広帯域かつ線形動作領域が広い可変利得ＴＩＡを実現することができる。 On the other hand, in the variable gain TIA of this embodiment, when the current flowing through the variable current source IS2 is increased and the current flowing through the transistor Q1 is decreased in order to reduce the gain of the TIA, the current flowing through the load resistor RL1 is reduced. Decrease. However, even in this case, in the variable gain TIA of this embodiment, the current flowing through the load resistor RL2 does not fluctuate, so that the DC operation of the signal output terminal (collector of the transistor Q1) is more than that of the conventional variable gain TIA shown in FIG. The rise of the points can be suppressed, and the linear operation region can be kept wide. Thus, in this embodiment, a variable gain TIA with a wide bandwidth and a wide linear operation region can be realized.
［第２実施例］
　次に、本発明の第２実施例について説明する。図２は本発明の第２実施例に係る可変利得ＴＩＡの構成例を示す回路図であり、図１と同様の構成には同一の符号を付してある。本実施例は、第１実施例の可変電流源ＩＳ２をトランジスタＱ２で構成したものである。トランジスタＱ２のベースには利得可変制御電圧Ｖｃｔｌが入力され、コレクタは負荷抵抗ＲＬ１，ＲＬ２の接続点に接続され、エミッタはトランジスタＱ１のエミッタに接続される。 [Second Embodiment]
Next, a second embodiment of the present invention will be described. FIG. 2 is a circuit diagram showing a configuration example of the variable gain TIA according to the second embodiment of the present invention, and the same components as those in FIG. 1 are denoted by the same reference numerals. In this embodiment, the variable current source IS2 of the first embodiment is constituted by a transistor Q2. The variable gain control voltage Vctl is input to the base of the transistor Q2, the collector is connected to the connection point of the load resistors RL1 and RL2, and the emitter is connected to the emitter of the transistor Q1.
　第１実施例と同様に、ＴＩＡの利得を小さくするためには、利得可変制御電圧ＶｃｔｌによってトランジスタＱ２に流れる電流を増やし、トランジスタＱ１に流れる電流を減らせばよい。反対にＴＩＡの利得を大きくするためには、トランジスタＱ２に流れる電流を減らし、トランジスタＱ１に流れる電流を増やせばよい。 As in the first embodiment, in order to reduce the gain of the TIA, the current flowing through the transistor Q2 may be increased by the variable gain control voltage Vctl, and the current flowing through the transistor Q1 may be decreased. On the other hand, in order to increase the TIA gain, the current flowing through the transistor Q2 may be reduced and the current flowing through the transistor Q1 may be increased.
　可変電流源を形成するために、一般的によく用いられる手法としてＭＯＳＦＥＴ素子を用いる手法がある。しかしながら、可変電流源に付随する寄生容量がＴＩＡの帯域に大きく影響を与えるため、本実施例では、可変電流源として寄生容量が比較的小さいバイポーラトランジスタＱ２を用いている。これにより、ＭＯＳＦＥＴを用いる場合よりもＴＩＡの広帯域化が可能となる。また、ＦＥＴが形成不可能な半導体プロセスに本発明を適応することができる。 In order to form a variable current source, there is a technique that uses a MOSFET element as a commonly used technique. However, since the parasitic capacitance associated with the variable current source greatly affects the TIA band, the bipolar transistor Q2 having a relatively small parasitic capacitance is used as the variable current source in this embodiment. This makes it possible to broaden the TIA bandwidth compared to the case of using a MOSFET. Further, the present invention can be applied to a semiconductor process in which an FET cannot be formed.
［第３実施例］
　次に、本発明の第３実施例について説明する。図３は本発明の第３実施例に係る可変利得ＴＩＡの構成例を示す回路図であり、図１、図２と同様の構成には同一の符号を付してある。本実施例の可変利得ＴＩＡは、トランジスタＱ１，Ｑ２と、負荷抵抗ＲＬ１，ＲＬ２と、定電流源ＩＳ１と、ベースにバイアス電圧Ｖｃｓが与えられ、エミッタが可変利得ＴＩＡの逆相信号入力端子に接続され、コレクタが可変利得ＴＩＡの正相信号出力端子に接続されたトランジスタＱ４と、正側電源電圧ＶｃｃとトランジスタＱ４のコレクタとの間に直列に接続された負荷抵抗ＲＬ３，ＲＬ４と、一端がトランジスタＱ４のエミッタに接続され、他端が負側電源電圧（ＧＮＤ接地）に接続された定電流源ＩＳ３と、ベースに利得可変制御電圧Ｖｃｔｌが与えられ、コレクタが負荷抵抗ＲＬ３，ＲＬ４の接続点に接続され、エミッタがトランジスタＱ４のエミッタに接続された可変電流源となるトランジスタＱ３とから構成される。第１実施例、第２実施例と同様に、バイアス電圧Ｖｃｓは、例えばトランジスタＱ１，Ｑ４が飽和しない程度の値に設定すればよい。 [Third embodiment]
Next, a third embodiment of the present invention will be described. FIG. 3 is a circuit diagram showing a configuration example of the variable gain TIA according to the third embodiment of the present invention. The same reference numerals are given to the same configurations as those in FIGS. The variable gain TIA of this embodiment has transistors Q1 and Q2, load resistors RL1 and RL2, a constant current source IS1, a bias voltage Vcs applied to the base, and an emitter connected to the negative phase signal input terminal of the variable gain TIA. Transistor Q4 whose collector is connected to the positive phase signal output terminal of variable gain TIA, load resistors RL3 and RL4 connected in series between the positive power supply voltage Vcc and the collector of transistor Q4, and one end of which is a transistor A constant current source IS3 connected to the emitter of Q4 and the other end connected to the negative power supply voltage (GND ground), a variable gain control voltage Vctl is applied to the base, and the collector is connected to the connection point of the load resistors RL3 and RL4. The transistor Q3 is a variable current source which is connected and whose emitter is connected to the emitter of the transistor Q4. As in the first and second embodiments, the bias voltage Vcs may be set to a value that does not saturate the transistors Q1 and Q4, for example.
　本実施例は、第２実施例に示した構成例の入出力を差動信号化した例であり、正相信号入力端子（トランジスタＱ１のエミッタ）には正相入力信号ＩｉｎＰが入力され、逆相信号入力端子（トランジスタＱ４のエミッタ）には逆相入力信号ＩｉｎＮが入力され、正相信号出力端子（トランジスタＱ４のコレクタ）からは正相出力信号ＶｏｕｔＰが出力され、逆相信号出力端子（トランジスタＱ１のコレクタ）からは逆相出力信号ＶｏｕｔＮが出力される。 The present embodiment is an example in which the input / output of the configuration example shown in the second embodiment is converted to a differential signal, and the positive phase input signal IinP is input to the positive phase signal input terminal (emitter of the transistor Q1), and the reverse A negative phase input signal IinN is input to the phase signal input terminal (emitter of the transistor Q4), a positive phase output signal VoutP is output from the positive phase signal output terminal (collector of the transistor Q4), and a negative phase signal output terminal (transistor) A negative phase output signal VoutN is output from the collector of Q1.
　ＴＩＡの利得を小さくするためには、利得可変制御電圧ＶｃｔｌによってトランジスタＱ２，Ｑ３に流れる電流を増やし、トランジスタＱ１，Ｑ４に流れる電流を減らせばよい。反対にＴＩＡの利得を大きくするためには、トランジスタＱ２，Ｑ３に流れる電流を減らし、トランジスタＱ１，Ｑ４に流れる電流を増やせばよい。
　本実施例では、第１実施例、第２実施例と同様の効果を実現すると共に、回路を差動動作させることで、差動入力信号中に含まれる同相のノイズ低減が可能となる。 In order to reduce the gain of the TIA, the current flowing through the transistors Q2 and Q3 may be increased by the variable gain control voltage Vctl, and the current flowing through the transistors Q1 and Q4 may be decreased. On the other hand, in order to increase the gain of TIA, the current flowing through the transistors Q2 and Q3 may be reduced and the current flowing through the transistors Q1 and Q4 may be increased.
In the present embodiment, the same effects as those of the first embodiment and the second embodiment are realized, and the common-mode noise included in the differential input signal can be reduced by differentially operating the circuit.
　本実施例の可変利得ＴＩＡと図１３、図１４に示した従来の可変利得ＴＩＡにおいて、ゲイン－周波数特性および出力電圧－入力電流特性の性能比較のためにＳｉ－Ｇｅ　Ｂｉ－ＣＭＯＳプロセスパラメタを用いたシミュレーションを行った。図４に、図１３の従来の可変利得ＴＩＡの利得－周波数特性のシミュレーション結果、図１４の従来の可変利得ＴＩＡの利得－周波数特性のシミュレーション結果、および本実施例の可変利得ＴＩＡの利得－周波数特性のシミュレーション結果を示す。図４における４０は図１３の従来の可変利得ＴＩＡの利得－周波数特性、４１は図１４の従来の可変利得ＴＩＡの利得－周波数特性、４２は本実施例の可変利得ＴＩＡの利得－周波数特性を示している。 In the variable gain TIA of the present embodiment and the conventional variable gain TIA shown in FIGS. 13 and 14, Si-Ge Bi-CMOS process parameters are used for performance comparison of gain-frequency characteristics and output voltage-input current characteristics. I had a simulation. FIG. 4 shows simulation results of gain-frequency characteristics of the conventional variable gain TIA of FIG. 13, simulation results of gain-frequency characteristics of the conventional variable gain TIA of FIG. 14, and gain-frequency of the variable gain TIA of this embodiment. The simulation result of characteristics is shown. 4, 40 is the gain-frequency characteristic of the conventional variable gain TIA of FIG. 13, 41 is the gain-frequency characteristic of the conventional variable gain TIA of FIG. 14, and 42 is the gain-frequency characteristic of the variable gain TIA of this embodiment. Show.
　図１３の従来の可変利得ＴＩＡでは利得が１／√２になる－３ｄＢ帯域が１５．６７５ＧＨｚ、図１４の従来の可変利得ＴＩＡでは－３ｄＢ帯域が２６．９８８ＧＨｚ、本実施例の可変利得ＴＩＡでは－３ｄＢ帯域が２４．６１３ＧＨｚである。本実施例の可変利得ＴＩＡでは、－３ｄＢ帯域が図１４の従来の可変利得ＴＩＡと比較して１割程度劣るものの、図１３の従来の可変利得ＴＩＡに対しては６割程度と大幅な性能向上が可能であることが確認できる。 The conventional variable gain TIA of FIG. 13 has a gain of 1 / √2, the −3 dB band is 15.675 GHz, the conventional variable gain TIA of FIG. 14 has a −3 dB band of 26.988 GHz, and the variable gain TIA of this embodiment The −3 dB band is 24.613 GHz. In the variable gain TIA of the present embodiment, the -3 dB band is inferior by about 10% compared to the conventional variable gain TIA of FIG. 14, but the performance of the variable gain TIA of FIG. It can be confirmed that improvement is possible.
　また、図５Ａに図１３の従来の可変利得ＴＩＡの様々な利得状況下における入力電流－出力電圧特性のシミュレーション結果を示し、図５Ｂに図１４の従来の可変利得ＴＩＡの様々な利得状況下における入力電流－出力電圧特性のシミュレーション結果を示し、図５Ｃに本実施例の可変利得ＴＩＡの様々な利得状況下における入力電流－出力電圧特性のシミュレーション結果を示す。 FIG. 5A shows the simulation results of the input current-output voltage characteristics under various gain conditions of the conventional variable gain TIA of FIG. 13, and FIG. 5B shows the simulation results of the conventional variable gain TIA of FIG. 14 under various gain conditions. The simulation result of the input current-output voltage characteristic is shown, and FIG. 5C shows the simulation result of the input current-output voltage characteristic under various gain conditions of the variable gain TIA of this embodiment.
　図５Ａ～図５Ｃの利得が小さい時（グラフの傾き＝－１．２の時）の特性において、図１３の従来の可変利得ＴＩＡおよび本実施例の可変利得ＴＩＡではおよそ－０．２～＋０．２程度まで広い入力電流範囲において出力電圧が線形であるのに対し、図１４の従来の可変利得ＴＩＡでは＋０．１～＋０．２程度までの狭い範囲でしか出力電圧が線形になっていない。図４、図５Ａ～図５Ｃのシミュレーション結果より、本実施例を用いることで広帯域かつ線形動作領域が広い可変利得ＴＩＡを実現できることが解る。 5A to 5C, when the gain is small (when the slope of the graph is −1.2), the conventional variable gain TIA of FIG. 13 and the variable gain TIA of the present embodiment have about −0.2 to +0. The output voltage is linear in a wide input current range up to about 2, whereas the conventional variable gain TIA in FIG. 14 has a linear output voltage only in a narrow range of about +0.1 to +0.2. . From the simulation results shown in FIGS. 4 and 5A to 5C, it can be understood that a variable gain TIA having a wide bandwidth and a wide linear operation region can be realized by using this embodiment.
［第４実施例］
　次に、本発明の第４実施例について説明する。図６は本発明の第４実施例に係る可変利得ＴＩＡの構成例を示す回路図であり、図１、図２と同様の構成には同一の符号を付してある。本実施例の可変利得ＴＩＡは、トランジスタＱ１，Ｑ２と、負荷抵抗ＲＬ１，ＲＬ２と、一端がトランジスタＱ１のエミッタに接続され、他端が負側電源電圧（ＧＮＤ接地）に接続された可変電流源ＩＳ１ａと、可変利得ＴＩＡの出力信号Ｖｏｕｔの平均電圧を検出する平均電圧検出回路１と、出力信号Ｖｏｕｔの平均電圧と基準電圧Ｖｒｅｆとを比較して、この比較結果に応じて可変電流源ＩＳ１ａの電流量を制御する比較回路２とから構成される。 [Fourth embodiment]
Next, a fourth embodiment of the present invention will be described. FIG. 6 is a circuit diagram showing a configuration example of the variable gain TIA according to the fourth embodiment of the present invention. The same reference numerals are given to the same configurations as those in FIGS. The variable gain TIA of this embodiment includes a variable current source having transistors Q1 and Q2, load resistors RL1 and RL2, one end connected to the emitter of the transistor Q1, and the other end connected to a negative power supply voltage (GND ground). The IS1a, the average voltage detection circuit 1 for detecting the average voltage of the output signal Vout of the variable gain TIA, the average voltage of the output signal Vout and the reference voltage Vref are compared, and the variable current source IS1a is compared according to the comparison result. And a comparison circuit 2 for controlling the amount of current.
　可変利得ＴＩＡの利得制御方法は第１実施例、第２実施例で説明したとおりである。本実施例では、出力信号Ｖｏｕｔの平均電圧と基準電圧Ｖｒｅｆとを比較する比較回路２を設け、比較回路２の出力によって可変電流源ＩＳ１ａの電流量、すなわち信号入力端子（トランジスタＱ１のエミッタ）と負側電源間に流れる電流量を制御している。本実施例では、信号入力端子と負側電源間に流れる電流を増加させることで負荷抵抗ＲＬ２を流れる電流を増加させることができ、信号出力端子（トランジスタＱ１のコレクタ）のＤＣ動作点を低くすることができる。 The gain control method of the variable gain TIA is as described in the first and second embodiments. In this embodiment, a comparison circuit 2 for comparing the average voltage of the output signal Vout and the reference voltage Vref is provided, and the amount of current of the variable current source IS1a, that is, the signal input terminal (emitter of the transistor Q1) is determined by the output of the comparison circuit 2. The amount of current flowing between the negative power sources is controlled. In this embodiment, the current flowing between the load input RL2 can be increased by increasing the current flowing between the signal input terminal and the negative power source, and the DC operating point of the signal output terminal (collector of the transistor Q1) is lowered. be able to.
　比較回路２は、出力信号Ｖｏｕｔの平均電圧が基準電圧Ｖｒｅｆより高い場合は可変電流源ＩＳ１ａの電流量を増やし、出力信号Ｖｏｕｔの平均電圧が基準電圧Ｖｒｅｆより低い場合は可変電流源ＩＳ１ａの電流量を減らすようにすればよい。これにより、ＴＩＡの利得を制御する際に生じる信号出力端子のＤＣ動作点の変化を抑えることが可能となる。基準電圧Ｖｒｅｆは、例えばＴＩＡの所望の広さの線形動作領域が得られるように予め定めておけばよい。 The comparison circuit 2 increases the current amount of the variable current source IS1a when the average voltage of the output signal Vout is higher than the reference voltage Vref, and the current amount of the variable current source IS1a when the average voltage of the output signal Vout is lower than the reference voltage Vref. Should be reduced. As a result, it is possible to suppress a change in the DC operating point of the signal output terminal that occurs when controlling the gain of the TIA. The reference voltage Vref may be determined in advance so that, for example, a linear operation region having a desired width of TIA can be obtained.
　なお、図６ではトランジスタＱ１のエミッタと負側電源電圧との間に可変電流源ＩＳ１ａのみを設け、可変電流源ＩＳ１ａの電流量を制御する構成例を示しているが、これに限るものではない。第１実施例、第２実施例と同様に定電流源ＩＳ１を設け、この定電流源ＩＳ１と並列に可変電流源ＩＳ１ａを設けて、可変電流源ＩＳ１ａの電流量を制御するようにしてもよい。この場合の構成を図７に示す。 Although FIG. 6 shows a configuration example in which only the variable current source IS1a is provided between the emitter of the transistor Q1 and the negative power supply voltage and the current amount of the variable current source IS1a is controlled, this is not restrictive. . As in the first and second embodiments, a constant current source IS1 may be provided, and a variable current source IS1a may be provided in parallel with the constant current source IS1 to control the current amount of the variable current source IS1a. . The configuration in this case is shown in FIG.
［第５実施例］
　次に、本発明の第５実施例について説明する。図８は本発明の第５実施例に係る可変利得ＴＩＡの構成例を示す回路図であり、図１、図２、図６と同様の構成には同一の符号を付してある。本実施例の可変利得ＴＩＡは、トランジスタＱ１，Ｑ２と、負荷抵抗ＲＬ１，ＲＬ２と、可変電流源ＩＳ１ａと、可変利得ＴＩＡの出力信号Ｖｏｕｔの振幅を検出する振幅検出回路３と、出力信号Ｖｏｕｔの振幅と基準振幅とを比較して、この比較結果に応じて可変電流源ＩＳ１ａの電流量を制御する比較回路４とから構成される。 [Fifth embodiment]
Next, a fifth embodiment of the present invention will be described. FIG. 8 is a circuit diagram showing a configuration example of a variable gain TIA according to the fifth embodiment of the present invention. The same reference numerals are given to the same configurations as those in FIGS. The variable gain TIA of this embodiment includes transistors Q1 and Q2, load resistors RL1 and RL2, a variable current source IS1a, an amplitude detection circuit 3 that detects the amplitude of the output signal Vout of the variable gain TIA, and the output signal Vout. A comparison circuit 4 that compares the amplitude with the reference amplitude and controls the current amount of the variable current source IS1a according to the comparison result is constituted.
　本実施例では、可変利得ＴＩＡの出力信号Ｖｏｕｔの振幅を検出する振幅検出回路３を設け、出力信号Ｖｏｕｔの振幅と基準振幅を比較回路４で比較し、比較回路４の出力によって可変電流源ＩＳ１ａの電流量、すなわち信号入力端子（トランジスタＱ１のエミッタ）と負側電源間に流れる電流量を制御している。本実施例では、信号入力端子と負側電源間に流れる電流を増加させることでトランジスタＱ１を流れる電流が増加し、アンプとしての利得が大きくなる。 In this embodiment, an amplitude detection circuit 3 for detecting the amplitude of the output signal Vout of the variable gain TIA is provided, the amplitude of the output signal Vout and the reference amplitude are compared by the comparison circuit 4, and the variable current source IS1a is output by the output of the comparison circuit 4. , That is, the amount of current flowing between the signal input terminal (emitter of the transistor Q1) and the negative power source is controlled. In this embodiment, by increasing the current flowing between the signal input terminal and the negative power source, the current flowing through the transistor Q1 increases, and the gain as an amplifier increases.
　比較回路４は、出力信号Ｖｏｕｔの振幅が所望の基準振幅よりも小さい場合は可変電流源ＩＳ１ａの電流量を増やし、出力信号Ｖｏｕｔの振幅が基準振幅よりも大きい場合は可変電流源ＩＳ１ａの電流量を減らすようにすればよい。これにより、入力信号Ｉｉｎの振幅が変動した時やＴＩＡの利得を変化させた時に生じる出力信号Ｖｏｕｔの振幅の変化を抑えることができ、常に一定振幅の信号を出力させることが可能となる。 The comparison circuit 4 increases the current amount of the variable current source IS1a when the amplitude of the output signal Vout is smaller than the desired reference amplitude, and the current amount of the variable current source IS1a when the amplitude of the output signal Vout is larger than the reference amplitude. Should be reduced. As a result, it is possible to suppress a change in the amplitude of the output signal Vout that occurs when the amplitude of the input signal Iin fluctuates or when the gain of the TIA is changed, and a signal having a constant amplitude can always be output.
　なお、図８ではトランジスタＱ１のエミッタと負側電源電圧との間に可変電流源ＩＳ１ａのみを設け、可変電流源ＩＳ１ａの電流量を制御する構成例を示しているが、これに限るものではない。第１実施例、第２実施例と同様に定電流源ＩＳ１を設け、この定電流源ＩＳ１と並列に可変電流源ＩＳ１ａを設けて、可変電流源ＩＳ１ａの電流量を制御するようにしてもよい。この場合の構成を図９に示す。 Although FIG. 8 shows a configuration example in which only the variable current source IS1a is provided between the emitter of the transistor Q1 and the negative power supply voltage and the current amount of the variable current source IS1a is controlled, the present invention is not limited to this. . As in the first and second embodiments, a constant current source IS1 may be provided, and a variable current source IS1a may be provided in parallel with the constant current source IS1 to control the current amount of the variable current source IS1a. . The configuration in this case is shown in FIG.
［第６実施例］
　次に、本発明の第６実施例について説明する。図１０は本発明の第６実施例に係る可変利得ＴＩＡの構成例を示す回路図であり、図１～図３、図６と同様の構成には同一の符号を付してある。本実施例の可変利得ＴＩＡは、トランジスタＱ１～Ｑ４と、負荷抵抗ＲＬ１～ＲＬ４と、一端がトランジスタＱ１のエミッタに接続され、他端が負側電源電圧（ＧＮＤ接地）に接続された可変電流源ＩＳ１ａと、一端がトランジスタＱ４のエミッタに接続され、他端が負側電源電圧に接続された可変電流源ＩＳ３ａと、可変利得ＴＩＡの正相出力信号ＶｏｕｔＰ、逆相出力信号ＶｏｕｔＮのそれぞれの平均電圧を検出する平均電圧検出回路１ａと、正相出力信号ＶｏｕｔＰの平均電圧と逆相出力信号ＶｏｕｔＮの平均電圧とを比較して、この比較結果に応じて可変電流源ＩＳ１ａ，ＩＳ３ａの電流量を制御する比較回路２ａとから構成される。 [Sixth embodiment]
Next, a sixth embodiment of the present invention will be described. FIG. 10 is a circuit diagram showing a configuration example of the variable gain TIA according to the sixth embodiment of the present invention. The same reference numerals are given to the same configurations as those in FIGS. 1 to 3 and FIG. The variable gain TIA of this embodiment is a variable current source in which transistors Q1 to Q4, load resistors RL1 to RL4, one end is connected to the emitter of the transistor Q1, and the other end is connected to the negative power supply voltage (GND ground). IS1a, a variable current source IS3a having one end connected to the emitter of the transistor Q4 and the other end connected to the negative power supply voltage, and average voltages of the positive phase output signal VoutP and the negative phase output signal VoutN of the variable gain TIA Is compared with the average voltage of the positive phase output signal VoutP and the average voltage of the negative phase output signal VoutN, and the current amounts of the variable current sources IS1a and IS3a are controlled according to the comparison result. And a comparison circuit 2a.
　可変利得ＴＩＡの利得制御方法は第３実施例で説明したとおりである。本実施例では、正相出力信号ＶｏｕｔＰの平均電圧と逆相出力信号ＶｏｕｔＮの平均電圧とを比較する比較回路２ａを設け、比較回路２ａの出力によって可変電流源ＩＳ１ａ，ＩＳ３ａの電流量、すなわち正相信号入力端子（トランジスタＱ１のエミッタ）と負側電源間に流れる電流量および逆相信号入力端子（トランジスタＱ４のエミッタ）と負側電源間に流れる電流量を制御している。 The gain control method of the variable gain TIA is as described in the third embodiment. In this embodiment, a comparison circuit 2a that compares the average voltage of the positive phase output signal VoutP and the average voltage of the negative phase output signal VoutN is provided. It controls the amount of current flowing between the phase signal input terminal (emitter of transistor Q1) and the negative power source and the amount of current flowing between the negative phase signal input terminal (emitter of transistor Q4) and the negative power source.
　本実施例では、正相信号入力端子と負側電源間の電流量の増加によって逆相信号出力端子（トランジスタＱ１のコレクタ）のＤＣ動作点が下がり、逆相信号入力端子と負側電源間の電流量の増加によって正相信号出力端子（トランジスタＱ４のコレクタ）のＤＣ動作点が下がる。よって、これら２つの電流量を相対的に変化させることで、正相入力側の回路（トランジスタＱ１，Ｑ２、負荷抵抗ＲＬ１，ＲＬ２、可変電流源ＩＳ１ａ）と逆相入力側の回路（トランジスタＱ３，Ｑ４、負荷抵抗ＲＬ３，ＲＬ４、可変電流源ＩＳ３ａ）のミスマッチによって生じる正相／逆相信号出力端子のＤＣ動作点のオフセットを抑えることができる。 In this embodiment, the DC operating point of the negative-phase signal output terminal (the collector of the transistor Q1) is lowered due to an increase in the amount of current between the positive-phase signal input terminal and the negative-side power supply, and between the negative-phase signal input terminal and the negative-side power supply. As the amount of current increases, the DC operating point of the positive phase signal output terminal (the collector of the transistor Q4) decreases. Therefore, by relatively changing these two current amounts, the circuit on the positive phase input side (transistors Q1 and Q2, load resistors RL1 and RL2, variable current source IS1a) and the circuit on the negative phase input side (transistors Q3 and Q3). The offset of the DC operating point of the positive / negative phase signal output terminal caused by the mismatch of Q4, load resistors RL3, RL4, and variable current source IS3a) can be suppressed.
　具体的には、比較回路２ａは、逆相出力信号ＶｏｕｔＮの平均電圧が正相出力信号ＶｏｕｔＰの平均電圧より高い場合は可変電流源ＩＳ１ａの電流量を増やして、可変電流源ＩＳ３ａの電流量を減らす。また、比較回路２ａは、逆相出力信号ＶｏｕｔＮの平均電圧が正相出力信号ＶｏｕｔＰの平均電圧より低い場合は可変電流源ＩＳ１ａの電流量を減らし、可変電流源ＩＳ３ａの電流量を増やす。こうして、正相出力信号ＶｏｕｔＰの平均電圧と逆相出力信号ＶｏｕｔＮの平均電圧とを一致させることができる。 Specifically, the comparison circuit 2a increases the current amount of the variable current source IS1a when the average voltage of the negative phase output signal VoutN is higher than the average voltage of the positive phase output signal VoutP, and the current amount of the variable current source IS3a is increased. cut back. Further, when the average voltage of the negative phase output signal VoutN is lower than the average voltage of the positive phase output signal VoutP, the comparison circuit 2a decreases the current amount of the variable current source IS1a and increases the current amount of the variable current source IS3a. Thus, the average voltage of the positive phase output signal VoutP and the average voltage of the negative phase output signal VoutN can be matched.
　なお、比較回路２ａは、可変電流源ＩＳ３ａの電流量を固定とし、逆相出力信号ＶｏｕｔＮの平均電圧が正相出力信号ＶｏｕｔＰの平均電圧より高い場合は可変電流源ＩＳ１ａの電流量を増やし、逆相出力信号ＶｏｕｔＮの平均電圧が正相出力信号ＶｏｕｔＰの平均電圧より低い場合は可変電流源ＩＳ１ａの電流量を減らすようにしてもよい。反対に、可変電流源ＩＳ１ａの電流量を固定とし、逆相出力信号ＶｏｕｔＮの平均電圧が正相出力信号ＶｏｕｔＰの平均電圧より高い場合は可変電流源ＩＳ３ａの電流量を減らし、逆相出力信号ＶｏｕｔＮの平均電圧が正相出力信号ＶｏｕｔＰの平均電圧より低い場合は可変電流源ＩＳ３ａの電流量を増やすようにしてもよい。 The comparison circuit 2a fixes the current amount of the variable current source IS3a, and increases the current amount of the variable current source IS1a when the average voltage of the negative phase output signal VoutN is higher than the average voltage of the positive phase output signal VoutP. When the average voltage of the phase output signal VoutN is lower than the average voltage of the positive phase output signal VoutP, the current amount of the variable current source IS1a may be reduced. On the other hand, when the current amount of the variable current source IS1a is fixed and the average voltage of the negative phase output signal VoutN is higher than the average voltage of the positive phase output signal VoutP, the current amount of the variable current source IS3a is reduced and the negative phase output signal VoutN When the average voltage is lower than the average voltage of the positive phase output signal VoutP, the amount of current of the variable current source IS3a may be increased.
　なお、図１０ではトランジスタＱ１，Ｑ４のエミッタと負側電源電圧との間に可変電流源ＩＳ１ａ，ＩＳ３ａを設け、可変電流源ＩＳ１ａ，ＩＳ３ａの電流量を制御する構成例を示しているが、これに限るものではない。第３実施例と同様に定電流源ＩＳ１，ＩＳ３を設け、この定電流源ＩＳ１，ＩＳ３と並列に可変電流源ＩＳ１ａ，ＩＳ３ａを設けて、可変電流源ＩＳ１ａ，ＩＳ３ａの電流量を制御するようにしてもよい。この場合の構成を図１１に示す。 FIG. 10 shows a configuration example in which variable current sources IS1a and IS3a are provided between the emitters of the transistors Q1 and Q4 and the negative power supply voltage to control the current amounts of the variable current sources IS1a and IS3a. It is not limited to. As in the third embodiment, constant current sources IS1 and IS3 are provided, and variable current sources IS1a and IS3a are provided in parallel with the constant current sources IS1 and IS3 to control the current amounts of the variable current sources IS1a and IS3a. May be. The configuration in this case is shown in FIG.
　本発明は、トランスインピーダンスアンプに適用することができる。 The present invention can be applied to a transimpedance amplifier.
　Ｑ１～Ｑ４…トランジスタ、ＲＬ１～ＲＬ４…負荷抵抗、ＩＳ１，ＩＳ３…定電流源、ＩＳ１ａ，ＩＳ２，ＩＳ３ａ…可変電流源、１，１ａ…平均電圧検出回路、２，２ａ，４…比較回路、３…振幅検出回路。 Q1 to Q4 ... transistor, RL1 to RL4 ... load resistance, IS1, IS3 ... constant current source, IS1a, IS2, IS3a ... variable current source, 1,1a ... average voltage detection circuit, 2,2a, 4 ... comparison circuit, 3 ... Amplitude detection circuit.

Claims (7)

  1. 　信号入力端子に接続されたエミッタと、信号出力端子に接続されたコレクタとを有し、ベース接地された第１のトランジスタと、
    　前記第１のトランジスタのエミッタに接続された一端と、負側電源電圧に接続された他端とを有する電流源と、
    　正側電源電圧と前記第１のトランジスタのコレクタとの間に直列に接続された第１、第２の負荷抵抗と、
    　前記第１の負荷抵抗と第２の負荷抵抗との接続点に接続された一端と、前記第１のトランジスタのエミッタに接続された他端とを有し、利得可変制御電圧に応じて電流量を制御することが可能な第１の可変電流源とを備えることを特徴とする可変利得トランスインピーダンスアンプ。     A first transistor having an emitter connected to the signal input terminal, a collector connected to the signal output terminal, and being grounded to the base;
    A current source having one end connected to the emitter of the first transistor and the other end connected to the negative supply voltage;
    First and second load resistors connected in series between a positive power supply voltage and the collector of the first transistor;
    One end connected to a connection point between the first load resistor and the second load resistor, and the other end connected to the emitter of the first transistor, and a current amount according to the gain variable control voltage And a first variable current source capable of controlling the variable gain transimpedance amplifier.
  2. 　請求項１に記載の可変利得トランスインピーダンスアンプにおいて、
    　前記第１の可変電流源は、前記利得可変制御電圧が入力されるベースと、前記第１の負荷抵抗と第２の負荷抵抗との接続点に接続されたコレクタと、前記第１のトランジスタのエミッタに接続されたエミッタとを有する第２のトランジスタから構成されることを特徴とする可変利得トランスインピーダンスアンプ。     The variable gain transimpedance amplifier according to claim 1,
    The first variable current source includes a base to which the variable gain control voltage is input, a collector connected to a connection point between the first load resistor and the second load resistor, and a first transistor A variable gain transimpedance amplifier comprising a second transistor having an emitter connected to the emitter.
  3. 　請求項１に記載の可変利得トランスインピーダンスアンプにおいて、
    　さらに、前記信号出力端子の平均電圧を検出する平均電圧検出回路と、
    　前記信号出力端子の平均電圧と基準電圧とを比較する比較回路とを備え、
    　前記電流源は、第２の可変電流源であり、
    　前記比較回路は、前記信号出力端子の平均電圧と基準電圧との比較結果に応じて前記第２の可変電流源の電流量を制御することを特徴とする可変利得トランスインピーダンスアンプ。     The variable gain transimpedance amplifier according to claim 1,
    Furthermore, an average voltage detection circuit for detecting an average voltage of the signal output terminal,
    A comparison circuit for comparing an average voltage of the signal output terminal and a reference voltage;
    The current source is a second variable current source;
    The variable gain transimpedance amplifier, wherein the comparison circuit controls a current amount of the second variable current source according to a comparison result between an average voltage of the signal output terminal and a reference voltage.
  4. 　請求項１に記載の可変利得トランスインピーダンスアンプにおいて、
    　さらに、前記信号出力端子の信号振幅を検出する振幅検出回路と、
    　前記信号出力端子の信号振幅と基準振幅とを比較する比較回路とを備え、
    　前記電流源は、第２の可変電流源であり、
    　前記比較回路は、前記信号出力端子の信号振幅と基準振幅との比較結果に応じて前記第２の可変電流源の電流量を制御することを特徴とする可変利得トランスインピーダンスアンプ。     The variable gain transimpedance amplifier according to claim 1,
    Furthermore, an amplitude detection circuit that detects the signal amplitude of the signal output terminal;
    A comparison circuit for comparing the signal amplitude of the signal output terminal and a reference amplitude,
    The current source is a second variable current source;
    The variable gain transimpedance amplifier, wherein the comparison circuit controls a current amount of the second variable current source in accordance with a comparison result between a signal amplitude of the signal output terminal and a reference amplitude.
  5. 　正相信号入力端子に接続されたエミッタと、逆相信号出力端子に接続されたコレクタとを有し、ベース接地された第１のトランジスタと、
    　逆相信号入力端子に接続されたエミッタと、正相信号出力端子に接続されたコレクタとを有し、ベース接地された第２のトランジスタと、
    　前記第１のトランジスタのエミッタに接続された一端と、負側電源電圧に接続された他端とを有する第１の電流源と、
    　前記第２のトランジスタのエミッタに接続された一端と、負側電源電圧に接続された他端とを有する第２の電流源と、
    　正側電源電圧と前記第１のトランジスタのコレクタとの間に直列に接続された第１、第２の負荷抵抗と、
    　正側電源電圧と前記第２のトランジスタのコレクタとの間に直列に接続された第３、第４の負荷抵抗と、
    　前記第１の負荷抵抗と第２の負荷抵抗との接続点に接続された一端と、前記第１のトランジスタのエミッタに接続された他端とを有し、利得可変制御電圧に応じて電流量を制御することが可能な第１の可変電流源と、
    　前記第３の負荷抵抗と第４の負荷抵抗との接続点に接続された一端と、前記第２のトランジスタのエミッタに接続された他端とを有し、前記利得可変制御電圧に応じて電流量を制御することが可能な第２の可変電流源とを備えることを特徴とする可変利得トランスインピーダンスアンプ。     A first transistor having an emitter connected to the positive-phase signal input terminal and a collector connected to the negative-phase signal output terminal, the base of which is grounded;
    A second transistor having an emitter connected to the negative-phase signal input terminal and a collector connected to the positive-phase signal output terminal and grounded at the base;
    A first current source having one end connected to the emitter of the first transistor and the other end connected to a negative supply voltage;
    A second current source having one end connected to the emitter of the second transistor and the other end connected to the negative supply voltage;
    First and second load resistors connected in series between a positive power supply voltage and the collector of the first transistor;
    Third and fourth load resistors connected in series between a positive power supply voltage and the collector of the second transistor;
    One end connected to a connection point between the first load resistor and the second load resistor, and the other end connected to the emitter of the first transistor, and a current amount according to the gain variable control voltage A first variable current source capable of controlling
    One end connected to a connection point between the third load resistor and the fourth load resistor, and the other end connected to the emitter of the second transistor, and a current corresponding to the variable gain control voltage A variable gain transimpedance amplifier comprising a second variable current source capable of controlling the amount.
  6. 　請求項５に記載の可変利得トランスインピーダンスアンプにおいて、
    　前記第１の可変電流源は、前記利得可変制御電圧が入力されるベースと、前記第１の負荷抵抗と第２の負荷抵抗との接続点に接続されたコレクタと、前記第１のトランジスタのエミッタに接続されたエミッタとを有する第３のトランジスタから構成され、
    　前記第２の可変電流源は、前記利得可変制御電圧が入力されるベースと、前記第３の負荷抵抗と第４の負荷抵抗との接続点に接続されたコレクタと、前記第２のトランジスタのエミッタに接続されたエミッタとを有する第４のトランジスタから構成されることを特徴とする可変利得トランスインピーダンスアンプ。     The variable gain transimpedance amplifier according to claim 5,
    The first variable current source includes a base to which the variable gain control voltage is input, a collector connected to a connection point between the first load resistor and the second load resistor, and a first transistor A third transistor having an emitter connected to the emitter;
    The second variable current source includes a base to which the variable gain control voltage is input, a collector connected to a connection point between the third load resistor and the fourth load resistor, and a second transistor A variable gain transimpedance amplifier comprising a fourth transistor having an emitter connected to the emitter.
  7. 　請求項５に記載の可変利得トランスインピーダンスアンプにおいて、
    　さらに、前記正相信号出力端子と前記逆相信号出力端子のそれぞれの平均電圧を検出する平均電圧検出回路と、
    　前記正相信号出力端子の平均電圧と前記逆相信号出力端子の平均電圧とを比較する比較回路とを備え、
    　前記第１の電流源は、第３の可変電流源であり、
    　前記第２の電流源は、第４の可変電流源であり、
    　前記比較回路は、前記正相信号出力端子の平均電圧と前記逆相信号出力端子の平均電圧との比較結果に応じて前記第３、第４の可変電流源の電流量を制御することを特徴とする可変利得トランスインピーダンスアンプ。     The variable gain transimpedance amplifier according to claim 5,
    Furthermore, an average voltage detection circuit for detecting an average voltage of each of the positive phase signal output terminal and the negative phase signal output terminal;
    A comparison circuit that compares the average voltage of the positive phase signal output terminal and the average voltage of the negative phase signal output terminal,
    The first current source is a third variable current source;
    The second current source is a fourth variable current source;
    The comparison circuit controls the current amounts of the third and fourth variable current sources in accordance with a comparison result between an average voltage of the positive phase signal output terminal and an average voltage of the negative phase signal output terminal. Variable gain transimpedance amplifier.
PCT/JP2015/051459 2014-03-28 2015-01-21 Variable gain transimpedance amplifier WO2015146247A1 (en)

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