JP6706105B2 - Transimpedance amplifier and optical signal receiver - Google Patents

Transimpedance amplifier and optical signal receiver Download PDF

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JP6706105B2
JP6706105B2 JP2016054737A JP2016054737A JP6706105B2 JP 6706105 B2 JP6706105 B2 JP 6706105B2 JP 2016054737 A JP2016054737 A JP 2016054737A JP 2016054737 A JP2016054737 A JP 2016054737A JP 6706105 B2 JP6706105 B2 JP 6706105B2
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平林 文人
文人 平林
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本発明は、光電変換素子から出力される電流信号を受け、単相の電圧信号に変換し、これを互いに位相が反転した差動信号に変換して出力するトランスインピーダンスアンプおよび光信号受信装置の性能向上のための技術に関する。 The present invention relates to a transimpedance amplifier and an optical signal receiving device that receive a current signal output from a photoelectric conversion element, convert it into a single-phase voltage signal, and convert it into a differential signal whose phase is mutually inverted and output the differential signal. Related to technology for improving performance.

光通信装置の受信部を構成する光信号受信装置は、強度変調された光信号をフォトダイオード等の光電変換素子で受け、その光電変換素子から入力光の強度に応じて電流値が変化する信号(電流信号)を単相の電圧信号に変換し、その単相の電圧信号を、後続の差動型の処理回路や伝送路との接続が容易となるように、互いに位相が反転した2相の電圧信号に変換して出力している。 An optical signal receiving device that constitutes a receiving unit of an optical communication device receives an intensity-modulated optical signal by a photoelectric conversion element such as a photodiode, and a signal whose current value changes from the photoelectric conversion element according to the intensity of input light. (Current signal) is converted into a single-phase voltage signal, and the single-phase voltage signal is inverted into two phases to facilitate connection with the subsequent differential type processing circuit or transmission line. The voltage signal is converted and output.

この電流電圧変換機能と2相の電圧信号への変換出力機能を有する回路を、一般的にトランスインピーダンスアンプ(以下、TIAと記す)と呼んでいる。 A circuit having the current-voltage conversion function and the conversion output function of converting into two-phase voltage signals is generally called a transimpedance amplifier (hereinafter referred to as TIA).

TIAの従来の構成例を図8に示す。
このTIAは、フォトダイオード等の光電変換素子から出力される電流信号Iinを、電流電圧変換回路(以下、I−V回路と記す)11で受け、その電流信号Iinの大きさに比例して電圧が変化する単相の電圧信号Vinに変換する。
FIG. 8 shows a conventional configuration example of the TIA.
This TIA receives a current signal Iin output from a photoelectric conversion element such as a photodiode by a current-voltage conversion circuit (hereinafter referred to as an IV circuit) 11, and a voltage proportional to the magnitude of the current signal Iin. Is converted into a single-phase voltage signal Vin.

ここで、I−V回路11は、反転型の増幅器11aの出力信号を、帰還抵抗Rを介して入力端子に帰還させる構成となっており、帰還抵抗Rの抵抗値が増幅器11aの入力インピーダンスより十分高い場合、電圧信号Vinは、近似的に次のように表される。
Vin=−Iin・R
Here, the IV circuit 11 is configured to feed back the output signal of the inverting amplifier 11a to the input terminal via the feedback resistor R, and the resistance value of the feedback resistor R is greater than the input impedance of the amplifier 11a. If high enough, the voltage signal Vin is approximately represented as:
Vin=-Iin・R

この単相の電圧信号Vinを差動増幅回路12の一方の入力端子に入力し、他方の入力端子に直流のリファレンス電圧Vref を入力することにより、差動増幅回路12の2つの出力端子から、差動入力(Vin−Vref )にほぼ比例した大きさをもち、互いに位相が反転した電圧信号Vout(+)、Vout(-)を出力させることができる。 By inputting this single-phase voltage signal Vin to one input terminal of the differential amplifier circuit 12 and inputting a DC reference voltage Vref to the other input terminal, the two output terminals of the differential amplifier circuit 12 are It is possible to output voltage signals Vout(+) and Vout(-) having a magnitude substantially proportional to the differential input (Vin-Vref) and having mutually inverted phases.

ここで、電圧信号Vinの平均電位とリファレンス電圧Vref に差があると、その直流成分の差分を増幅するので、差動増幅回路12を構成する一対の差動トランジスタの動作点が正常な領域からずれてしまい、出力信号に振幅の低下や歪みが生じてしまう。 Here, if there is a difference between the average potential of the voltage signal Vin and the reference voltage Vref, the difference in the direct current component is amplified, so that the operating points of the pair of differential transistors forming the differential amplifier circuit 12 are from normal regions. As a result, the output signal is deviated and the output signal is reduced in amplitude or distorted.

そのため、この回路例では、ローパスフィルタ(LPF)13によって、電圧信号Vinの直流成分である平均電位Vave を抽出し、これを上記リファレンス電圧Vref として差動増幅回路12に入力している。 Therefore, in this circuit example, the low-pass filter (LPF) 13 extracts the average potential Vave, which is the DC component of the voltage signal Vin, and inputs this to the differential amplifier circuit 12 as the reference voltage Vref.

上記構成のTIAは、例えば特許文献1に開示されている。なお、この特許文献1では、電流電圧変換回路を「トランスインピーダンスアンプ」と呼び、差動増幅回路を含めた回路全体を光信号受信回路としているが、本発明では、電流電圧変換回路および差動増幅回路を含めた回路全体をTIAと呼ぶことにする。 The TIA having the above configuration is disclosed in Patent Document 1, for example. In Patent Document 1, the current-voltage conversion circuit is called a "transimpedance amplifier" and the entire circuit including the differential amplifier circuit is an optical signal receiving circuit. However, in the present invention, the current-voltage conversion circuit and the differential circuit are used. The entire circuit including the amplifier circuit will be called TIA.

特開2007−243510号公報JP, 2007-243510, A

上記した従来のTIAでは、差動増幅回路12の一方の入力端子に単相の電圧信号Vinを入力し、他方の入力端子に電圧信号Vinの平均電位に等しい直流電圧Vref を入力して信号増幅する構成であるから、差動増幅回路12を構成する一対の差動トランジスタの動作が完全に対称とならず、回路構成によっては、出力される電圧信号Vout(+)、Vout(-)の振幅が等しくならない。 In the above-described conventional TIA, a single-phase voltage signal Vin is input to one input terminal of the differential amplifier circuit 12, and a DC voltage Vref equal to the average potential of the voltage signal Vin is input to the other input terminal to amplify the signal. Therefore, the operation of the pair of differential transistors forming the differential amplifier circuit 12 is not completely symmetrical, and depending on the circuit configuration, the amplitude of the output voltage signals Vout(+) and Vout(-) may vary. Are not equal.

つまり、差動増幅回路12は、一般的に図9に示すように、1対の差動トランジスタTr1、Tr2のコレクタと高電位側の電源Vccの間に同一抵抗値の負荷抵抗R1、R2を接続し、エミッタ同士を同一抵抗値の抵抗R3、R4を介して接続し、その接続点を共通の抵抗R5(あるいは定電流源)を介して低電位側の電源に接続した構成を有しており、トランジスタTr1、Tr2のベースに信号IN(+)、IN(-)を与えることで、その差分信号[IN(+)−IN(-)]に比例した、逆相、同相の二つの信号Vout(+)、Vout(-)を出力させる。 That is, the differential amplifier circuit 12 generally includes load resistors R1 and R2 having the same resistance value between the collectors of the pair of differential transistors Tr1 and Tr2 and the power supply Vcc on the high potential side, as shown in FIG. It has a configuration in which the emitters are connected to each other via resistors R3 and R4 having the same resistance value, and the connection point is connected to a power source on the low potential side via a common resistor R5 (or a constant current source). By applying the signals IN(+) and IN(-) to the bases of the transistors Tr1 and Tr2, two signals, an in-phase signal and an in-phase signal, which are proportional to the difference signal [IN(+)-IN(-)] Vout(+) and Vout(-) are output.

ここで、差動増幅回路の一方の入力端子に単相の電圧信号Vinを入力し、他方の入力端子にVinの平均電位と等しい直流電圧Vref を入力した場合、差動増幅回路の電流源が理想的な定電流源であれば、二つのトランジスタTr1、Tr2はほぼ対称的に増幅動作し、出力信号Vout(+)、Vout(-)の振幅もほぼ等しくなる。 When a single-phase voltage signal Vin is input to one input terminal of the differential amplifier circuit and a DC voltage Vref equal to the average potential of Vin is input to the other input terminal, the current source of the differential amplifier circuit is With an ideal constant current source, the two transistors Tr1 and Tr2 perform amplifying operations in a substantially symmetrical manner, and the output signals Vout(+) and Vout(-) have substantially the same amplitude.

一方、特許文献1に示されているように、低い電源電圧で高いダイナミックレンジを得るためには図9のように差動増幅回路の電流源として抵抗を用いる構成が有効であるが、このような回路構成の差動増幅回路の、一方の入力端子に単相の電圧信号Vinを入力し、他方の入力端子にVinの平均電位と等しい直流電圧Vref を入力した場合、出力信号Vout(+)、Vout(-)の振幅が異なってしまう。 On the other hand, as shown in Patent Document 1, in order to obtain a high dynamic range with a low power supply voltage, it is effective to use a resistor as a current source of the differential amplifier circuit as shown in FIG. When a single-phase voltage signal Vin is input to one input terminal and a DC voltage Vref equal to the average potential of Vin is input to the other input terminal of the differential amplifier circuit having various circuit configurations, the output signal Vout(+) , Vout(-) have different amplitudes.

即ち、電流源を抵抗で構成した差動増幅回路では、十分な定電流動作がなされないため、差動増幅回路の同相利得が抑制されず、電圧信号Vinの状態により電流源抵抗に流れる電流が変化するので、Vinがハイレベルの時は電流源抵抗の電流が増加し、ローレベルの時は電流源抵抗の電流が減少する。これが出力信号Vout(+)の振幅変化を強調するように作用し、Vout(+)の振幅がVout(-)の振幅よりも大きくなる非対称性を生じ、信号歪みの原因となる。 That is, in the differential amplifier circuit in which the current source is configured by the resistor, the constant current operation is not sufficiently performed, the common mode gain of the differential amplifier circuit is not suppressed, and the current flowing in the current source resistor depends on the state of the voltage signal Vin. Because of the change, the current of the current source resistance increases when Vin is high level, and the current of the current source resistance decreases when Vin is low level. This acts so as to emphasize the amplitude change of the output signal Vout(+), and causes asymmetry in which the amplitude of Vout(+) becomes larger than the amplitude of Vout(-), which causes signal distortion.

上記特許文献1では、3ボルト程度の単一電源を用いて電流電圧変換回路から出力させる電圧信号の振幅を最大にするために、差動増幅回路の定電流源を抵抗で置換したことによって生じる上記出力波形の非対称性を改善する手段として、この差動増幅回路の出力をさらに別の差動増幅回路でリミッティングして波形整形しているが、パルス振幅変調等の多値変調を用いた光通信においては、TIAは信号をリニアに増幅する機能が求められるので、上記用途のTIAには上記手段を適用することはできなかった。 In Patent Document 1, a constant power source of the differential amplifier circuit is replaced with a resistor in order to maximize the amplitude of the voltage signal output from the current-voltage conversion circuit using a single power supply of about 3 volts. As a means for improving the asymmetry of the output waveform, the output of this differential amplifier circuit is limited by another differential amplifier circuit to shape the waveform, but multi-level modulation such as pulse amplitude modulation is used. In optical communication, the TIA is required to have a function of linearly amplifying a signal, so that the above means cannot be applied to the TIA for the above applications.

また、上記差動増幅回路の電流源を理想的な定電流源で構成した場合でも、差動増幅回路の一方の入力端子に単相の電圧信号Vinを入力し、他方の入力端子にVinの平均電位と等しい直流電圧Vref を入力して信号増幅する構成では、差動増幅回路を構成する一対の差動トランジスタの動作が完全に対称にはならないため、高い周波数領域で2つの出力信号に位相ずれが生じ、信号品質劣化の原因となっていた。 Even when the current source of the differential amplifier circuit is an ideal constant current source, the single-phase voltage signal Vin is input to one input terminal of the differential amplifier circuit and Vin of the other input terminal is input. In the configuration in which the DC voltage Vref equal to the average potential is input and the signal is amplified, the operation of the pair of differential transistors forming the differential amplifier circuit is not completely symmetrical, so that the two output signals are phased in the high frequency region. A shift occurs, which is a cause of signal quality deterioration.

さらに、上記した従来のTIAは、差動増幅回路12の一方の入力端子に単相の電圧信号Vinを入力し、他方の入力端子には、その電圧信号Vinの平均電位と等しい直流電圧Vref を入力して信号増幅する構成であるから、差動増幅回路12の二つの入力端子に互いに位相が反転した差動信号を入力する構成のTIAに比べ、高い利得を得られず、受信部のS/N比を高くできなかった。 Further, in the conventional TIA described above, a single-phase voltage signal Vin is input to one input terminal of the differential amplifier circuit 12, and a DC voltage Vref equal to the average potential of the voltage signal Vin is input to the other input terminal. Since the configuration is such that the input signal is amplified, the TIA having a configuration in which the differential signals whose phases are inverted to each other are input to the two input terminals of the differential amplifier circuit 12 cannot obtain a high gain, and the S of the receiving section is not obtained. The /N ratio could not be increased.

本発明は、上記問題を解決し、等しい振幅で位相ずれのない対称性の良い差動信号を出力でき、リニア動作可能で、高い利得を備えたTIAおよびそれを用いた光信号受信装置を提供することを目的としている。 The present invention solves the above problems and provides a TIA capable of outputting differential signals with equal amplitude and good symmetry without phase shift, capable of linear operation, and having high gain, and an optical signal receiving apparatus using the same. The purpose is to do.

前記目的を達成するために、本発明の請求項1のトランスインピーダンスアンプは、
入力する電流信号を単相の電圧信号に変換する電流電圧変換回路(21)と、
前記電流電圧変換回路から出力される単相の電圧信号をトランジスタの第1端子で受け、該トランジスタの第2端子側と第3端子側から互いに位相が反転した2相の電圧信号を出力する位相分割回路(22)と、
前記位相分割回路から出力される2相の電圧信号を受け、該2相の電圧信号の平均電位を合わせて出力するレベル合わせ回路(23)と、
前記レベル合わせ回路によって平均電位が合わされた2相の電圧信号の一方を反転入力端子、他方を非反転入力端子で受け、該二つの入力端子に入力された2相の電圧信号の差分成分を増幅して、該増幅した信号を反転出力端子および非反転出力端子から互いに位相が反転した信号として出力する差動増幅回路(24)とを備え
前記電流電圧変換回路は、反転型増幅器(21a)と帰還抵抗(R)を備え、前記入力する電流信号が前記反転型増幅器の入力端子に入力され、当該反転型増幅器から出力される前記単相の電圧信号が前記帰還抵抗を介して前記反転型増幅器の入力端子に帰還されるようになっている
In order to achieve the above object, the transimpedance amplifier according to claim 1 of the present invention comprises:
A current-voltage conversion circuit (21) for converting an input current signal into a single-phase voltage signal,
A phase for receiving a single-phase voltage signal output from the current-voltage conversion circuit at the first terminal of the transistor and outputting two-phase voltage signals whose phases are inverted from each other from the second terminal side and the third terminal side of the transistor. A dividing circuit (22),
A level matching circuit (23) for receiving the two-phase voltage signals output from the phase division circuit and outputting the combined average potentials of the two-phase voltage signals;
The inverting input terminal receives one of the two-phase voltage signals whose average potentials have been adjusted by the level adjusting circuit and the other non-inverting input terminal, and amplifies the difference component of the two-phase voltage signals input to the two input terminals. And a differential amplifier circuit (24) for outputting the amplified signal from the inverting output terminal and the non-inverting output terminal as signals whose phases are mutually inverted ,
The current-voltage conversion circuit includes an inverting amplifier (21a) and a feedback resistor (R), and the input current signal is input to an input terminal of the inverting amplifier and output from the inverting amplifier. Is fed back to the input terminal of the inverting amplifier via the feedback resistor .

また、本発明の請求項のトランスインピーダンスアンプにおいて、
前記位相分割回路を構成するトランジスタは、前記第1端子がベース、前記第2端子がコレクタ、前記第3端子がエミッタのバイポーラ型トランジスタ、または、前記第1端子がゲート、前記第2端子がドレイン、前記第3端子がソースの電界効果型トランジスタのいずれかであることを特徴とする。
Further, in the transimpedance amplifier according to claim 1 of the present invention,
A transistor forming the phase dividing circuit is a bipolar transistor in which the first terminal is a base, the second terminal is a collector, and the third terminal is an emitter, or the first terminal is a gate and the second terminal is a drain. The third terminal is any one of a field effect transistor of a source.

また、本発明の請求項のトランスインピーダンスアンプにおいて、
前記レベル合わせ回路は、
前記位相分割回路の前記トランジスタの前記第2端子側から出力される電圧信号の平均電位を、トランジスタあるいはダイオードの順方向電圧降下を利用して所定電圧分低下させるレベルシフト回路(23a)を含んでいることを特徴とする。
Further, in the transimpedance amplifier according to claim 1 of the present invention,
The level matching circuit,
A level shift circuit (23a) for reducing the average potential of the voltage signal output from the second terminal side of the transistor of the phase division circuit by a predetermined voltage by utilizing the forward voltage drop of the transistor or diode. It is characterized by being

また、本発明の請求項のトランスインピーダンスアンプにおいて、
前記レベル合わせ回路は、
前記位相分割回路の前記トランジスタの前記第3端子側から出力される電圧信号の平均電位を、トランジスタあるいはダイオードの順方向電圧降下を利用して所定電圧分上昇させるレベルシフト回路(23b)を含んでいることを特徴とする。
Further, in the transimpedance amplifier according to claim 1 of the present invention,
The level matching circuit,
A level shift circuit (23b) for increasing the average potential of the voltage signal output from the third terminal side of the transistor of the phase division circuit by a predetermined voltage by utilizing the forward voltage drop of the transistor or diode. It is characterized by being

また、本発明の請求項のトランスインピーダンスアンプは、請求項1に記載のトランスインピーダンスアンプにおいて、
前記レベル合わせ回路は、
手動操作による電圧可変が可能な誤差補償電圧を発生させる誤差補償電圧発生器(23c)を有し、該誤差補償電圧を、前記位相分割回路から出力される2相の電圧信号の少なくとも一方、あるいは前記差動増幅回路に入力される2相の電圧信号の少なくとも一方に重畳して、前記2相の電圧信号の平均電位の誤差を縮小させることを特徴とする。
The transimpedance amplifier according to claim 2 of the present invention is the transimpedance amplifier according to claim 1 ,
The level matching circuit,
An error compensating voltage generator (23c) for generating an error compensating voltage capable of voltage variation by manual operation is provided, and the error compensating voltage is at least one of two phase voltage signals output from the phase dividing circuit, or It is characterized in that it is superimposed on at least one of the two-phase voltage signals input to the differential amplifier circuit to reduce the error of the average potential of the two-phase voltage signals.

また、本発明の請求項のトランスインピーダンスアンプは、請求項1または2に記載のトランスインピーダンスアンプにおいて、
前記レベル合わせ回路は、
前記差動増幅回路に入力される2相の電圧信号の平均電位の差、または、前記差動増幅回路から出力される2相の電圧信号の平均電位の差を検出し、該差を縮小するために必要な誤差補償電圧を求める誤差電圧検出回路(23e)を有し、該誤差補償電圧を前記位相分割回路から出力される2相の電圧信号の少なくとも一方、あるいは前記差動増幅回路に入力される2相の電圧信号の少なくとも一方に重畳させて、前記平均電位の差を縮小させることを特徴とする。
The transimpedance amplifier according to claim 3 of the present invention is the transimpedance amplifier according to claim 1 or 2 .
The level matching circuit,
The difference between the average potentials of the two-phase voltage signals input to the differential amplifier circuit or the difference between the average potentials of the two-phase voltage signals output from the differential amplifier circuit is detected and the difference is reduced. Has an error voltage detection circuit (23e) for obtaining an error compensation voltage necessary for that, and inputs the error compensation voltage to at least one of the two-phase voltage signals output from the phase division circuit or to the differential amplifier circuit. The difference between the average potentials is reduced by superimposing it on at least one of the two-phase voltage signals.

また、本発明の請求項の光信号受信装置は、
光信号を受けて電流信号を出力する光電変換素子(1)と、
前記光電変換素子から出力された電流信号を受けるトランスインピーダンスアンプ(20)とを有する光信号受信装置において、
前記トランスインピーダンスアンプが、請求項1〜のいずれかに記載のトランスインピーダンスアンプであることを特徴とする。
The optical signal receiving device according to claim 4 of the present invention is
A photoelectric conversion element (1) that receives an optical signal and outputs a current signal;
An optical signal receiving device having a transimpedance amplifier (20) for receiving a current signal output from the photoelectric conversion element,
The transimpedance amplifier, characterized in that it is a transimpedance amplifier according to any one of claims 1-3.

このように、本発明のTIAでは、電流電圧変換回路から出力される単相の電圧信号を位相分割回路のトランジスタの第1端子に与え、第2端子側と第3端子側から互いに位相が反転した2相の電圧信号を出力させ、その2相の電圧信号の平均電位をレベル合わせ回路によって合わせてから差動増幅回路に与えるようにしている。 As described above, in the TIA of the present invention, the single-phase voltage signal output from the current-voltage conversion circuit is applied to the first terminal of the transistor of the phase division circuit, and the phases are inverted from each other from the second terminal side and the third terminal side. The two-phase voltage signals are output, the average potentials of the two-phase voltage signals are adjusted by the level adjustment circuit, and then applied to the differential amplifier circuit.

このため、差動増幅回路には、平均電位が等しく合わされた互いに位相が反転した電圧信号が入力されるから、差動増幅回路からは、振幅が等しい対称性のある2相の電圧信号を高い利得で得ることができ、従来のように波形整形のために信号をリミッティングする必要がないので、リニア動作可能なTIAを実現できる。 Therefore, the differential amplifier circuit receives the voltage signals whose average potentials are equalized and whose phases are inverted to each other. Therefore, a symmetrical two-phase voltage signal having the same amplitude is output from the differential amplifier circuit. Since the gain can be obtained and there is no need to limit the signal for waveform shaping as in the conventional case, a TIA capable of linear operation can be realized.

また、光信号受信装置のTIAに本発明を適用することで、光電変換素子に入力される光信号の伝送経路での減衰が大きくなっていても高いS/N比で受信可能となり、長距離光通信が可能となる。 Further, by applying the present invention to the TIA of the optical signal receiving device, it becomes possible to receive with a high S/N ratio even if the attenuation of the optical signal input to the photoelectric conversion element in the transmission path is large, and the long distance can be achieved. Optical communication becomes possible.

本発明の実施形態の構成図Configuration diagram of an embodiment of the present invention 本発明の実施形態の要部の回路例を示す図The figure which shows the example of a circuit of the principal part of embodiment of this invention. 本発明の実施形態の要部の回路例を示す図The figure which shows the example of a circuit of the principal part of embodiment of this invention. 本発明の実施形態の要部の別の回路例を示す図The figure which shows another circuit example of the principal part of embodiment of this invention. 本発明の実施形態の要部の別の回路例を示す図The figure which shows another circuit example of the principal part of embodiment of this invention. 本発明の実施形態と従来回路の特性を示す図The figure which shows the characteristic of embodiment of this invention and a conventional circuit. 本発明の実施形態と従来回路の特性を示す図The figure which shows the characteristic of embodiment of this invention and a conventional circuit. 従来回路を示す図Diagram showing conventional circuit 差動増幅回路の回路例を示す図Diagram showing a circuit example of a differential amplifier circuit

以下、図面に基づいて本発明の実施の形態を説明する。
図1は、本発明を適用したTIA20と光電変換素子1からなる光信号受信装置の構成を示している。
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 shows the configuration of an optical signal receiving device including a TIA 20 and a photoelectric conversion element 1 to which the present invention is applied.

図1において、電流電圧変換回路21は、入力する電流信号Iinを単相の電圧信号Vinに変換するものであり、基本的には、反転型増幅器21aの入力端子と出力端子との間に帰還抵抗Rを接続した構成となっており、入力する電流信号Iinと等しい電流が出力端子から入力端子に流れ込むように動作し、−Iin・Rに等しい単相の電圧信号Vinを出力端子から出力する。 In FIG. 1, a current-voltage conversion circuit 21 converts an input current signal Iin into a single-phase voltage signal Vin, and basically, it feeds back between the input terminal and the output terminal of the inverting amplifier 21a. The resistor R is connected so that a current equal to the input current signal Iin flows from the output terminal to the input terminal, and a single-phase voltage signal Vin equal to -Iin·R is output from the output terminal. ..

この単相の電圧信号Vinは、位相分割回路22に入力される。位相分割回路22は、入力される単相の電圧信号Vinを、位相が互いに反転した2相の電圧信号Va(-)、Vb(+)に変換する。 The single-phase voltage signal Vin is input to the phase division circuit 22. The phase dividing circuit 22 converts the input single-phase voltage signal Vin into two-phase voltage signals Va(-) and Vb(+) whose phases are mutually inverted.

この位相分割回路22は、バイポーラ型トランジスタあるいは電界効果型トランジスタ(FET)を用いて構成することができるが、図2にバイポーラ型トランジスタを用いた回路例を示す。 The phase division circuit 22 can be configured by using a bipolar transistor or a field effect transistor (FET), and FIG. 2 shows a circuit example using a bipolar transistor.

図2の(a)の回路は、電圧信号VinをトランジスタTr11のベース(第1端子)に与え、コレクタ(第2端子)とエミッタ(第3端子)に抵抗R11、R12を接続した構成とし、電圧信号Vinに対して位相が反転した電圧信号Va(-)をコレクタ側から出力させ、電圧信号Vinと同相の電圧信号Vb(+)をエミッタ側から出力させる。 The circuit of FIG. 2A has a configuration in which the voltage signal Vin is applied to the base (first terminal) of the transistor Tr11, and resistors R11 and R12 are connected to the collector (second terminal) and the emitter (third terminal), A voltage signal Va(-) whose phase is inverted with respect to the voltage signal Vin is output from the collector side, and a voltage signal Vb(+) in phase with the voltage signal Vin is output from the emitter side.

また、図2の(a)のトランジスタTr1の代わりに、図2の(b)のように、2つのトランジスタTr12、Tr13からなるカスコード回路を用いた構成も可能である。この構成の場合、電圧信号Vinをベース(第1端子)で受けるトランジスタTr12のコレクタ(第2端子)と負荷抵抗R11との間にベース接地型の増幅回路を形成するトランジスタTr13が接続されており、そのトランジスタTr13のベースにはバイアス電圧Vbbが与えられる。この回路の場合は、トランジスタTr12のベース(第1端子)で電圧信号Vinを受け、トランジスタTr12に接続されたトランジスタTr13のコレクタ側と、トランジスタTr12のエミッタ(第3端子)側から、電圧信号Vinに対して逆相と同相の信号を出力する。 Further, instead of the transistor Tr1 shown in FIG. 2A, a cascode circuit including two transistors Tr12 and Tr13 may be used as shown in FIG. 2B. In the case of this configuration, the transistor Tr13 forming a base-grounded amplifier circuit is connected between the collector (second terminal) of the transistor Tr12 that receives the voltage signal Vin at the base (first terminal) and the load resistor R11. The bias voltage Vbb is applied to the base of the transistor Tr13. In the case of this circuit, the voltage signal Vin is received at the base (first terminal) of the transistor Tr12, and the voltage signal Vin is received from the collector side of the transistor Tr13 connected to the transistor Tr12 and the emitter side (third terminal) of the transistor Tr12. The signals of the opposite phase and the same phase are output with respect to.

このようにトランジスタを用いた位相分割回路22で互いに位相が反転した電圧信号を生成させると、出力される2相の電圧信号Va(-)、Vb(+)の平均電位に差が生じる。例えば、上記図2の(a)の構成では、正常な動作範囲にあるトランジスタTr11のコレクタ電圧とエミッタ電圧との間に通常1〜2ボルト程度の電位差ΔVがあるので、この電位差ΔVが2相の電圧信号Va(-)、Vb(+)の平均電位の差として現れる。このように電位差ΔVがある電圧信号Va(-)、Vb(+)をそのまま後述の差動増幅回路24に与えてしまうと、この電位差ΔVの分も増幅されて拡大されて出力されることになるから、光通信装置で一般的に用いられる3V程度の電源では、差動増幅回路24を構成する一対の差動トランジスタの動作点がアンバランスになり、正常な領域からずれてしまい、出力信号に振幅の低下や歪みが生じてしまう。 In this way, when the voltage signals whose phases are inverted to each other are generated by the phase dividing circuit 22 using transistors, a difference occurs in the average potentials of the output two-phase voltage signals Va(-) and Vb(+). For example, in the configuration shown in FIG. 2A, since there is usually a potential difference ΔV of about 1 to 2 V between the collector voltage and the emitter voltage of the transistor Tr11 in the normal operating range, this potential difference ΔV is two phases. Appears as the difference between the average potentials of the voltage signals Va(-) and Vb(+). If the voltage signals Va(-) and Vb(+) having the potential difference ΔV are applied as they are to the differential amplifier circuit 24, which will be described later, the potential difference ΔV is also amplified and expanded and output. Therefore, in a power supply of about 3V generally used in optical communication devices, the operating points of the pair of differential transistors forming the differential amplifier circuit 24 become unbalanced and deviate from the normal range, resulting in an output signal. Amplitude will be reduced and distortion will occur.

このため、この実施形態では、位相分割回路22から出力される2相の電圧信号Va(-)、Vb(+)を受け、その電圧信号Va(-)、Vb(+)の平均電位を合わせて出力するレベル合わせ回路23を設けている。 Therefore, in this embodiment, the two-phase voltage signals Va(-) and Vb(+) output from the phase division circuit 22 are received, and the average potentials of the voltage signals Va(-) and Vb(+) are adjusted. A level matching circuit 23 for outputting the output is provided.

このレベル合わせ回路23としては種々の方式が考えられる。その一つの方式として、2相の電圧信号Va(-)、Vb(+)のうち、平均電位が高い方の電圧信号(上記回路例ではVa(-))を第1のレベルシフト回路23aによって例えばΔV/2だけ低い方にシフトさせ、反対に平均電位が低い方の電圧信号(上記回路例ではVb(+))を第2のレベルシフト回路23bによってΔV/2だけ高い方にシフトさせ、2つの電圧信号Va(-)、Vb(+)の平均電位の差ΔVをほぼ零にして出力する。 Various methods can be considered as the level matching circuit 23. As one of the methods, of the two-phase voltage signals Va(-) and Vb(+), the one having the higher average potential (Va(-) in the above circuit example) is supplied by the first level shift circuit 23a. For example, it shifts to the lower side by ΔV/2, and conversely, the voltage signal of the lower average potential (Vb(+) in the above circuit example) is shifted to the higher side by ΔV/2 by the second level shift circuit 23b. The difference ΔV between the average potentials of the two voltage signals Va(−) and Vb(+) is set to almost zero and the result is output.

より具体的に言えば、図3のように、第1のシフト回路23aをトランジスタTr21とエミッタ抵抗R21を用いたエミッタフォロア回路で形成し、電圧信号Va(-)をトランジスタTr21のベースに与え、トランジスタTr21のベース・エミッタ間の電圧降下分(≒ΔV/2)だけ低い方にシフトした電圧信号Va(-)′をエミッタから出力させる。このエミッタフォロア回路のトランジスタTr21の代わりにダイオードを接続し、電圧信号Va(-)をアノード側に与え、ダイオードの順方向電圧降下分だけ、低い方にシフトして出力させることもできる。 More specifically, as shown in FIG. 3, the first shift circuit 23a is formed by an emitter follower circuit using a transistor Tr21 and an emitter resistor R21, and a voltage signal Va(-) is applied to the base of the transistor Tr21. The voltage signal Va(-)' shifted to the lower side by the voltage drop between the base and the emitter of the transistor Tr21 (≈ΔV/2) is output from the emitter. It is also possible to connect a diode instead of the transistor Tr21 of this emitter follower circuit, apply the voltage signal Va(-) to the anode side, and shift to the lower side by the forward voltage drop of the diode to output.

また、第2のシフト回路23bを、ダイオードD21と、そのダイオードD21のアノード側と高電位側の電源Vccとの間に接続された抵抗R22とで構成し、ダイオードD21のカソード側に電圧信号Vb(+)を与え、ダイオードD21の順方向電圧降下分(≒ΔV/2)だけ高い方にシフトした電圧信号Vb(+)′をアノード側から出力させる。 The second shift circuit 23b is composed of a diode D21 and a resistor R22 connected between the anode side of the diode D21 and the power source Vcc on the high potential side, and the voltage signal Vb is applied to the cathode side of the diode D21. (+) is applied, and the voltage signal Vb(+)' shifted to the higher side by the amount of the forward voltage drop of the diode D21 (≈ΔV/2) is output from the anode side.

上記のように、2相の電圧信号のうち、平均電位が高い方を低くシフトし、平均電位が低い方を高くシフトし2つの電圧信号の平均電位を合わせて差動増幅回路24の反転入力端子、非反転入力端子に入力することで、差動増幅回路24を構成する一対の差動トランジスタの動作点をバランスさせることができる。 As described above, of the two-phase voltage signals, the one with the higher average potential is shifted lower, the one with the lower average potential is shifted higher, and the average potentials of the two voltage signals are combined to obtain the inverting input of differential amplifier circuit 24. By inputting to the terminals and the non-inverting input terminals, the operating points of the pair of differential transistors forming the differential amplifier circuit 24 can be balanced.

なお、平均電位が高い方の電圧信号(上記回路例ではVa(-))のみをほぼΔVだけ低い方にシフトさせて、平均電位が低い方の電圧信号に合わせる方式や、逆に平均電位が低い方の電圧信号(上記回路例ではVb(+))のみをほぼΔVだけ高い方にシフトさせ、平均電位が高い方の電圧信号Va(-)に合わせる方式も採用できる。これらの方式を採用する場合には、上記第1のシフト回路23aや第2のシフト回路23bのトランジスタやダイオードによる電圧シフトを2段構成とすればよい。 It should be noted that only the voltage signal with the higher average potential (Va(-) in the above circuit example) is shifted to the lower side by approximately ΔV to match the voltage signal with the lower average potential, or vice versa. It is also possible to adopt a method in which only the lower voltage signal (Vb(+) in the above circuit example) is shifted to the higher side by approximately ΔV and matched with the higher average voltage signal Va(-). When these methods are adopted, the voltage shift by the transistors and diodes of the first shift circuit 23a and the second shift circuit 23b may be a two-stage configuration.

上記実施形態では、レベル合わせ回路として、シフトさせる電圧が固定の場合について説明したが、2相の電圧信号の平均電位をより厳密に合わせたい場合には、例えば図4に示すように、手動操作によって電圧可変が可能な誤差補償電圧発生器23cを設け、その誤差補償電圧Eを、抵抗結合回路等からなる誤差電圧印加回路23dを介して、電圧信号Va(-)、Vb(+)の少なくとも一方、あるいは電圧信号Va(-)′、Vb(+)′の少なくとも一方に重畳(加算、減算のいずれでもよい)させる。これによって、差動増幅回路24に入力される2相の電圧信号、あるいは、差動増幅回路24から出力される2相の電圧信号の平均電位を精度よく合わせることができる。 In the above-described embodiment, the case where the voltage to be shifted is fixed has been described as the level matching circuit. However, when it is desired to more accurately match the average potentials of the two-phase voltage signals, for example, as shown in FIG. An error compensation voltage generator 23c capable of varying the voltage is provided, and the error compensation voltage E is supplied to at least the voltage signals Va(-) and Vb(+) via the error voltage application circuit 23d including a resistance coupling circuit. On the other hand, it is superposed (either addition or subtraction is possible) on at least one of the voltage signals Va(-)' and Vb(+)'. Thereby, the average potentials of the two-phase voltage signals input to the differential amplifier circuit 24 or the two-phase voltage signals output from the differential amplifier circuit 24 can be accurately matched.

また、図5に示すように、平均電位の誤差電圧を自動的に検出する誤差電圧検出回路23eを設け、その検出した誤差電圧を縮小するように誤差補償電圧Eを、誤差補償電圧印加回路23dを介して電圧信号Va(-)、Vb(+)の少なくとも一方、あるいは電圧信号Va(-)′、Vb(+)′の少なくとも一方に重畳させることで、差動増幅回路24に入力される電圧信号の平均電位あるいは差動増幅回路24から出力される電圧信号の平均電位を自動的に精度よく合わせることもできる。 Further, as shown in FIG. 5, an error voltage detection circuit 23e for automatically detecting the error voltage of the average potential is provided, and the error compensation voltage E is applied so as to reduce the detected error voltage. It is input to the differential amplifier circuit 24 by being superposed on at least one of the voltage signals Va(-) and Vb(+) or at least one of the voltage signals Va(-)' and Vb(+)' via It is also possible to automatically and accurately match the average potential of the voltage signal or the average potential of the voltage signal output from the differential amplifier circuit 24.

図5の(a)は、差動増幅回路24に入力される電圧信号の平均電位を自動的に合わせる回路例であり、この回路例の誤差電圧検出回路23eは、電圧信号Va(-)′、Vb(+)′の平均電位の差を検出し、この差が縮小するために必要な誤差補償電圧Eを求めて、第1のシフト回路23aの入力側に設けられた誤差補償電圧印加回路23dを介して電圧信号Va(-)に重畳させている。 FIG. 5A is an example of a circuit that automatically adjusts the average potential of the voltage signal input to the differential amplifier circuit 24. The error voltage detection circuit 23e of this circuit example has a voltage signal Va(-)'. , Vb(+)′ average potential difference is detected, an error compensation voltage E required for reducing the difference is determined, and an error compensation voltage application circuit provided on the input side of the first shift circuit 23a is detected. It is superimposed on the voltage signal Va(-) via 23d.

また、図5の(b)は、差動増幅回路24から出力される電圧信号の平均電位を自動的に合わせる回路例であり、この回路例の誤差電圧検出回路23eは、差動増幅回路24から出力される電圧信号の平均電位の差E′を検出し、その差が縮小するために必要な誤差補償電圧Eを、差動増幅回路24の差動利得Aを用いてE′/Aの演算で求めて、第1のシフト回路23aの入力側に設けられた誤差補償電圧印加回路23dを介して電圧信号Va(-)に重畳させている。 Further, FIG. 5B is a circuit example in which the average potential of the voltage signal output from the differential amplifier circuit 24 is automatically adjusted, and the error voltage detection circuit 23e in this circuit example is the differential amplifier circuit 24. The difference E′ between the average potentials of the voltage signals output from the detector is detected, and the error compensation voltage E necessary for reducing the difference is calculated by using the differential gain A of the differential amplifier circuit 24 as E′/A. Calculated, it is superimposed on the voltage signal Va(-) via the error compensation voltage applying circuit 23d provided on the input side of the first shift circuit 23a.

上記回路例では、2相の電圧信号の平均電位の差を検出して、その差が縮小するのに必要な誤差補償電圧Eを求め、その平均電位の差の検出位置より前段側回路に入力される2相の信号の一方に重畳していたが、検出位置の信号ラインに挿入された誤差補償電圧印加回路23dを介して重畳してもよい。また、2相の信号の一方だけでなく、双方に誤差補償電圧を重畳して、平均電位の差を縮小させるようにしてもよい。また、図5の(b)のように差動増幅回路24から出力される2相の電圧信号の誤差電圧を検出する場合の変形例として、差動増幅回路24が多段構成の場合、そのいずれの段の出力からも誤差電圧を検出することができる。 In the above circuit example, the difference between the average potentials of the two-phase voltage signals is detected, the error compensation voltage E required to reduce the difference is obtained, and the error compensation voltage E is input to the circuit on the preceding stage from the detection position of the difference between the average potentials. Although it is superposed on one of the two-phase signals, it may be superposed via the error compensation voltage applying circuit 23d inserted in the signal line at the detection position. Further, not only one of the two-phase signals but also the error-compensating voltage may be superimposed on both of them to reduce the difference in average potential. Further, as a modified example of detecting the error voltage of the two-phase voltage signals output from the differential amplifier circuit 24 as shown in FIG. 5B, when the differential amplifier circuit 24 has a multi-stage configuration, whichever The error voltage can also be detected from the output of the stage.

上記の構成を用いれば、差動増幅回路24には、位相が互いに反転し、平均電位が自動制御で常に一致した電圧信号Va(-)′、Vb(+)′を入力することができる。 With the above configuration, the voltage signals Va(-)' and Vb(+)' whose phases are mutually inverted and whose average potentials are always matched by automatic control can be input to the differential amplifier circuit 24.

さらに、図2の位相分割回路のR11とR12を同一の抵抗値に設定すれば、Va(-)、Vb(+)の振幅はほぼ等しくでき、差動増幅回路24には位相が互いに反転し、振幅と平均電位が揃った電圧信号を入力できるので、差動増幅回路の動作は最も対称性が良くなり、電流源が抵抗で構成された場合であっても、振幅が揃った出力信号Vout(+)、Vout(-)を得ることができる。 Further, if R11 and R12 of the phase division circuit of FIG. 2 are set to the same resistance value, the amplitudes of Va(-) and Vb(+) can be made almost equal, and the phases of the differential amplifier circuit 24 are inverted from each other. Since a voltage signal whose amplitude and average potential are uniform can be input, the operation of the differential amplifier circuit has the best symmetry, and even when the current source is composed of a resistor, the output signal Vout whose amplitude is uniform is obtained. (+) and Vout(-) can be obtained.

また、差動増幅回路24は位相が互いに反転した入力信号Va(-)′、Vb(+)′の差分を差動利得Aで増幅するので、単相の電圧信号Vinを差動増幅回路で増幅する従来の構成よりも大きな振幅の出力信号を得ることができる。それによりTIA全体の利得を高くすることができる。 Since the differential amplifier circuit 24 amplifies the difference between the input signals Va(-)' and Vb(+)' whose phases are mutually inverted by the differential gain A, the single-phase voltage signal Vin is output by the differential amplifier circuit. It is possible to obtain an output signal having a larger amplitude than that of the conventional configuration for amplification. As a result, the gain of the entire TIA can be increased.

図6は従来回路と本発明の実施形態の回路の、2つの出力端子(Vout(+)、Vout(-))におけるトランスインピーダンスゲイン(dBohm)の周波数特性のシミュレーション結果を示している。なお、どちらの回路も電源電圧3.3Vで、差動増幅回路の電流源は抵抗で構成している。また、本発明の実施形態の回路には、図5の(a)の自動制御回路を用いており、位相分割回路のR11とR12の抵抗値はどちらも50Ωとしている。また、回路を形成するトランジスタとして、ft:230GHz、fmax:400GHz程度のInP HBTを用いている。また、解析する周波数は、光通信で一般的に用いられる周波数領域の100kHz〜50GHzとした。 FIG. 6 shows simulation results of frequency characteristics of transimpedance gain (dBohm) at two output terminals (Vout(+) and Vout(-)) of the conventional circuit and the circuit of the embodiment of the present invention. Both circuits have a power supply voltage of 3.3 V, and the current source of the differential amplifier circuit is a resistor. Further, the circuit of the embodiment of the present invention uses the automatic control circuit of FIG. 5A, and the resistance values of R11 and R12 of the phase division circuit are both 50Ω. Further, as a transistor forming a circuit, InP HBT having ft: 230 GHz and fmax: 400 GHz is used. The frequency to be analyzed was 100 kHz to 50 GHz in the frequency range generally used in optical communication.

図6の(b)に示すように、従来回路では、2つの出力信号のゲインに約3dBの差が、低い周波数領域から生じている。これは前記したように、電流源が抵抗で構成された差動増幅回路の、一方の入力端子に単相の電圧信号を入力して信号増幅しているので、電圧信号Vinの状態により差動増幅回路の電流が変化し、回路の動作が非対称になるためである。 As shown in FIG. 6B, in the conventional circuit, a difference of about 3 dB occurs in the gains of the two output signals from the low frequency region. As described above, this is because the single-phase voltage signal is input to one of the input terminals of the differential amplifier circuit in which the current source is composed of a resistor to amplify the signal, so that the differential signal is generated depending on the state of the voltage signal Vin. This is because the current of the amplifier circuit changes and the operation of the circuit becomes asymmetric.

一方、図6の(a)の本発明の実施形態の回路では、差動増幅回路の2つの入力端子に位相が互いに反転した振幅の等しい電圧信号が入力されるので、電流源が抵抗で構成された差動増幅回路であっても、回路が対称性良く動作し、2つの出力信号のゲインはほぼ一致した特性となっている。 On the other hand, in the circuit according to the embodiment of the present invention shown in FIG. 6A, voltage signals having the same amplitude and inverted phases are input to the two input terminals of the differential amplifier circuit. Even in the differential amplifier circuit, the circuit operates with good symmetry, and the gains of the two output signals have almost the same characteristics.

図7は、図6の従来回路と本発明の実施形態の回路において、差動増幅回路の電流源を理想的な定電流源に置き換えた場合の、トランスインピーダンスゲイン(dBohm)とその位相特性のシミュレーション結果を示している。なお、Vout(-)の位相は180度シフトした位相を示している。 FIG. 7 shows the transimpedance gain (dBohm) and its phase characteristics when the current source of the differential amplifier circuit is replaced with an ideal constant current source in the conventional circuit of FIG. 6 and the circuit of the embodiment of the present invention. The simulation result is shown. The phase of Vout(-) shows a phase shifted by 180 degrees.

図7の(b)の従来回路のゲインを見ると、差動増幅回路の電流源を理想的な定電流源にしたことにより、低い周波数領域での2つの出力信号のゲインは等しくなっているが、30GHz以上からゲイン差が現れ、50GHzでの差は1.5dBとなっている。また、2つの出力信号の位相特性は、50GHzにおいて17度の位相ずれが生じている。この位相ずれは、後段回路のジッタ劣化等の要因となる。一方、本発明の実施形態の回路では、図7の(a)のように、2つの出力信号のゲイン、位相は全周波数領域において一致した特性となっている。また、本発明の実施形態の回路と従来回路のゲインを比較すると、カットオフ周波数Fc はほぼ同等にもかかわらず、本発明の実施形態の回路は従来回路に比べ4dBほど高いゲインが得られている。 Looking at the gain of the conventional circuit of FIG. 7B, the gains of the two output signals in the low frequency region are equal because the current source of the differential amplifier circuit is an ideal constant current source. However, the gain difference appears from 30 GHz or more, and the difference at 50 GHz is 1.5 dB. In addition, the phase characteristics of the two output signals have a phase shift of 17 degrees at 50 GHz. This phase shift causes deterioration of jitter in the subsequent circuit. On the other hand, in the circuit according to the embodiment of the present invention, as shown in FIG. 7A, the gain and phase of the two output signals have the same characteristics in the entire frequency range. Further, comparing the gains of the circuit of the present invention and the conventional circuit, although the cutoff frequency Fc is almost the same, the circuit of the embodiment of the present invention has a gain of about 4 dB higher than that of the conventional circuit. There is.

以上より、本発明の実施形態の回路は、等しい振幅で位相ずれのない対称性の良い差動信号を出力でき、高い利得を得られることがわかる。 From the above, it can be seen that the circuit of the embodiment of the present invention can output a differential signal having equal amplitude and good phase symmetry and good symmetry, and high gain.

なお、上記実施形態では、位相分割回路22を構成するトランジスタとして、バイポーラ型トランジスタを用いる例を示したが、図2に示した回路のトランジスタTr11〜Tr13を、電界効果型トランジスタ(FET)に置き換えることも可能である。この場合、トランジスタTr11〜Tr13のベース、コレクタ、エミッタをそれぞれFETのゲート、ドレイン、ソースに置き換えた回路とすればよく、トランジスタTr11、Tr12のベース、コレクタ、エミッタに対応するゲート、ドレイン、ソースをそれぞれ第1端子、第2端子、第3端子とすればよい。また、電流電圧変換回路21や差動増幅回路24についても、バイポーラ型トランジスタで構成されるものだけでなく、電界効果型トランジスタ(FET)で構成されるものであってもよい。 In the above embodiment, an example in which a bipolar transistor is used as the transistor forming the phase division circuit 22 is shown, but the transistors Tr11 to Tr13 in the circuit shown in FIG. 2 are replaced with field effect transistors (FETs). It is also possible. In this case, the bases, collectors, and emitters of the transistors Tr11 to Tr13 may be replaced by the gates, drains, and sources of the FETs, and the gates, drains, and sources corresponding to the bases, collectors, and emitters of the transistors Tr11, Tr12 may be replaced by the circuits. It may be a first terminal, a second terminal, and a third terminal, respectively. Further, the current-voltage conversion circuit 21 and the differential amplifier circuit 24 are not limited to the bipolar transistors, but may be field-effect transistors (FETs).

1……光電変換素子、20……TIA(トランスインピーダンスアンプ)、21……電流電圧変換回路、22……位相分割回路、23……レベル合わせ回路、23a……第1のシフト回路、23b……第2のシフト回路、23c……誤差補償電圧発生器、23d……誤差補償電圧印加回路、23e……誤差電圧検出回路、24……差動増幅回路 1... Photoelectric conversion element, 20... TIA (transimpedance amplifier), 21... Current-voltage conversion circuit, 22... Phase division circuit, 23... Level matching circuit, 23a... First shift circuit, 23b... Second shift circuit 23c Error compensation voltage generator 23d Error compensation voltage application circuit 23e Error voltage detection circuit 24 Differential amplifier circuit

Claims (4)

入力する電流信号を単相の電圧信号に変換する電流電圧変換回路(21)と、
前記電流電圧変換回路から出力される単相の電圧信号をトランジスタの第1端子で受け、該トランジスタの第2端子側と第3端子側から互いに位相が反転した2相の電圧信号を出力する位相分割回路(22)と、
前記位相分割回路から出力される2相の電圧信号を受け、該2相の電圧信号の平均電位を合わせて出力するレベル合わせ回路(23)と、
前記レベル合わせ回路によって平均電位が合わされた2相の電圧信号の一方を反転入力端子、他方を非反転入力端子で受け、該二つの入力端子に入力された2相の電圧信号の差分成分を増幅して、該増幅した信号を反転出力端子および非反転出力端子から互いに位相が反転した信号として出力する差動増幅回路(24)とを備えたトランスインピーダンスアンプであって、
前記電流電圧変換回路は、反転型増幅器(21a)と帰還抵抗(R)を備え、前記入力する電流信号が前記反転型増幅器の入力端子に入力され、当該反転型増幅器から出力される前記単相の電圧信号が前記帰還抵抗を介して前記反転型増幅器の入力端子に帰還されるようになっており、
前記位相分割回路を構成するトランジスタは、前記第1端子がベース、前記第2端子がコレクタ、前記第3端子がエミッタのバイポーラ型トランジスタ、または、前記第1端子がゲート、前記第2端子がドレイン、前記第3端子がソースの電界効果型トランジスタのいずれかであり、
前記レベル合わせ回路は、前記位相分割回路の前記トランジスタの前記第2端子側から出力される電圧信号の平均電位を、トランジスタあるいはダイオードの順方向電圧降下を利用して所定電圧分低下させるレベルシフト回路(23a)を含んでおり、
前記レベル合わせ回路は、前記位相分割回路の前記トランジスタの前記第3端子側から出力される電圧信号の平均電位を、トランジスタあるいはダイオードの順方向電圧降下を利用して所定電圧分上昇させるレベルシフト回路(23b)を含んでいる、トランスインピーダンスアンプ
A current-voltage conversion circuit (21) for converting an input current signal into a single-phase voltage signal,
A phase for receiving a single-phase voltage signal output from the current-voltage conversion circuit at the first terminal of the transistor and outputting two-phase voltage signals whose phases are inverted from each other from the second terminal side and the third terminal side of the transistor. A dividing circuit (22),
A level matching circuit (23) for receiving the two-phase voltage signals output from the phase division circuit and outputting the combined average potentials of the two-phase voltage signals;
The inverting input terminal receives one of the two-phase voltage signals whose average potentials have been adjusted by the level adjusting circuit and the other non-inverting input terminal, and amplifies the difference component of the two-phase voltage signals input to the two input terminals. And a differential amplifier circuit (24) for outputting the amplified signal from the inverting output terminal and the non-inverting output terminal as signals whose phases are mutually inverted ,
The current-voltage conversion circuit includes an inverting amplifier (21a) and a feedback resistor (R), and the input current signal is input to an input terminal of the inverting amplifier and output from the inverting amplifier. The voltage signal of is fed back to the input terminal of the inverting amplifier via the feedback resistor,
A transistor forming the phase dividing circuit is a bipolar transistor in which the first terminal is a base, the second terminal is a collector, and the third terminal is an emitter, or the first terminal is a gate and the second terminal is a drain. , The third terminal is any one of a source field effect transistor,
The level matching circuit lowers the average potential of the voltage signal output from the second terminal side of the transistor of the phase division circuit by a predetermined voltage by utilizing the forward voltage drop of the transistor or the diode. (23a) is included,
The level matching circuit raises the average potential of the voltage signal output from the third terminal side of the transistor of the phase division circuit by a predetermined voltage by utilizing the forward voltage drop of the transistor or the diode. A transimpedance amplifier including (23b) .
前記レベル合わせ回路は、
手動操作による電圧可変が可能な誤差補償電圧を発生させる誤差補償電圧発生器(23c)を有し、該誤差補償電圧を、前記位相分割回路から出力される2相の電圧信号の少なくとも一方、あるいは前記差動増幅回路に入力される2相の電圧信号の少なくとも一方に重畳して、前記2相の電圧信号の平均電位の誤差を縮小させることを特徴とする請求項1に記載のトランスインピーダンスアンプ。
The level matching circuit,
An error compensating voltage generator (23c) for generating an error compensating voltage capable of voltage variation by manual operation is provided, and the error compensating voltage is at least one of two phase voltage signals output from the phase dividing circuit, or The transimpedance amplifier according to claim 1, wherein the differential impedance circuit is superposed on at least one of the two-phase voltage signals to reduce an error in average potential of the two-phase voltage signals. ..
前記レベル合わせ回路は、
前記差動増幅回路に入力される2相の電圧信号の平均電位の差、または、前記差動増幅回路から出力される2相の電圧信号の平均電位の差を検出し、該差を縮小するために必要な誤差補償電圧を求める誤差電圧検出回路(23e)を有し、該誤差補償電圧を前記位相分割回路から出力される2相の電圧信号の少なくとも一方、あるいは前記差動増幅回路に入力される2相の電圧信号の少なくとも一方に重畳させて、前記平均電位の差を縮小させることを特徴とする請求項1に記載のトランスインピーダンスアンプ。
The level matching circuit,
The difference between the average potentials of the two-phase voltage signals input to the differential amplifier circuit or the difference between the average potentials of the two-phase voltage signals output from the differential amplifier circuit is detected and the difference is reduced. Has an error voltage detection circuit (23e) for obtaining an error compensation voltage necessary for that, and inputs the error compensation voltage to at least one of the two-phase voltage signals output from the phase division circuit or to the differential amplifier circuit. The transimpedance amplifier according to claim 1, wherein the transimpedance amplifier is superimposed on at least one of the two-phase voltage signals to reduce the difference between the average potentials.
光信号を受けて電流信号を出力する光電変換素子(1)と、
前記光電変換素子から出力された電流信号を受けるトランスインピーダンスアンプ(20)とを有する光信号受信装置において、
前記トランスインピーダンスアンプが、請求項1〜のいずれかに記載のトランスインピーダンスアンプであることを特徴とする光信号受信装置。
A photoelectric conversion element (1) that receives an optical signal and outputs a current signal;
An optical signal receiving device having a transimpedance amplifier (20) for receiving a current signal output from the photoelectric conversion element,
The transimpedance amplifier, an optical signal receiving apparatus, characterized in that the transimpedance amplifier according to any one of claims 1-3.
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