JP6192179B2 - Transimpedance amplifier circuit and semiconductor device thereof - Google Patents

Description

  The present invention relates to a transimpedance amplifier circuit and a semiconductor device thereof, and more particularly to a transimpedance amplifier circuit that converts an output current of a photodiode into a current-voltage and a semiconductor device thereof.

  As a communication system for transmitting and receiving optical signals, a PON (Passive Optical Network) system is exemplified. The PON system connects a plurality of subscriber home terminals (ONU: Optical Network Unit) and a station (OLT: Optical Line Terminal) with an optical fiber, and the distance between each subscriber home and the station is large. Is different. For this reason, the optical receiver of the OLT needs to convert optical signals having different amplitudes into electrical signals, a photodiode that receives the optical signal, and a transimpedance amplifier circuit that performs current-voltage conversion on the output current of the photodiode. It has.

  Patent Documents 1 to 4 disclose a single-end-to-differential (SD) conversion technique in which an output current signal of a photodiode is converted into a voltage by a transimpedance amplifier circuit and the single-ended signal is input to an input terminal of a differential amplifier circuit. Is disclosed. For example, in Patent Documents 1 and 2, a single-ended output terminal is connected to one input terminal of a differential amplifier circuit, a DC voltage obtained by smoothing a single-ended output with a low-pass filter is applied to the other input terminal, and the other The DC level is determined. In Patent Document 3, a single-ended output terminal is connected to one input terminal of a differential amplifier circuit, and a DC voltage generated by DC feedback is applied to the other input terminal to generate a differential output of a differential amplifier. The DC level is determined. For this DC feedback, a low-pass filter and a differential amplifier circuit are used. In Patent Document 4, a single-ended output terminal and one input terminal of a differential amplifier are connected via a capacitor.

JP 2012-28879 A (FIG. 1) JP2011-217237A (FIG. 1) JP2010-136169A (FIG. 1, paragraph 0033) Japanese Patent Laying-Open No. 2008-306614 (FIG. 6)

In the techniques described in Patent Documents 1 to 4, a capacitor is disposed at the input terminal of the differential amplifier circuit. A capacitor that can be formed by a semiconductor process has a capacitance per unit area of about 2 [fF / μm ² ], and a practical upper limit of capacitance is about 10 pF from the viewpoint of miniaturization and cost reduction. Further, the core circuit portion in which a large number of transistor elements are arranged has no region where a capacitor can be formed, and the limit is about 100 fF.

  In particular, the technique of Patent Document 3 requires a capacitor of about 100 nF at a cutoff frequency of 100 kHz. It is not realistic to form such a capacitor on a chip. In the technique of Patent Document 3, if the capacitance of the capacitor is insufficient, the DC level is not stabilized, correct signal amplification is not performed, and the output signal waveform is distorted. In the technique of Patent Document 4, the low frequency component of the signal is cut off unless there is a capacitance of the order of several hundreds nF. By blocking the signal, the technique of Patent Document 4 cannot correctly transmit the signal when the logic level is 0 level or 1 level continues.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a transimpedance amplifier circuit that can obtain a differential output without providing a capacitor, and a semiconductor device thereof.

In order to solve the above-mentioned problem, the first invention is a transimpedance amplifier circuit that converts an input current flowing through an input terminal (Iin) into a voltage and differentially outputs the converted voltage, one end of which is connected to the input terminal. A resistor (10) to be connected; an inverter for inverting the voltage of the input terminal; a first load to which a predetermined voltage is applied ; a first transistor having an output voltage of the inverter as a gate voltage; and a second load And the other end of the resistor is connected to a first connection point that connects the first transistor and the second load (T3), and connects the first load and the first transistor. A voltage is output from both the second connection point and the first connection point. However, symbols and characters in parentheses are examples.

  The present invention can obtain a differential output without disposing a capacitor. Therefore, a semiconductor device with a small occupation area can be formed.

It is a block diagram of the optical receiver using the transimpedance amplifier circuit which is 1st Embodiment of this invention. 1 is a circuit diagram of a transimpedance amplifier circuit according to a first embodiment of the present invention. It is a wave form diagram (1) of the transimpedance amplifier circuit which is 1st Embodiment of this invention. It is a wave form diagram (2) of the transimpedance amplifier circuit which is 1st Embodiment of this invention. It is an eye pattern (1) of the transimpedance amplifier circuit which is 1st Embodiment of this invention. It is an eye pattern (2) of the transimpedance amplifier circuit which is 1st Embodiment of this invention. It is a frequency characteristic figure of the transimpedance amplifier circuit which is 1st Embodiment of this invention. 1 is an overall configuration diagram of a PON system in which a transimpedance amplifier circuit according to a first embodiment of the present invention is used. It is a circuit diagram of the transimpedance amplifier circuit which is 2nd Embodiment of this invention. It is a circuit diagram of the transimpedance amplifier circuit which is 3rd Embodiment of this invention. It is a circuit diagram of the optical receiver which is a 1st comparative example of this invention. It is a circuit diagram of the optical receiver which is the 2nd comparative example of this invention. It is a circuit diagram of the optical receiver which is the 3rd comparative example of the present invention.

  Hereinafter, an embodiment of the present invention (hereinafter referred to as “the present embodiment”) will be described in detail with reference to the drawings. Each figure is only schematically shown so that the present invention can be fully understood. Therefore, the present invention is not limited to the illustrated example. Moreover, in each figure, the same code | symbol is attached | subjected about the common component and the same component, and those overlapping description is abbreviate | omitted.

(First embodiment)
FIG. 1 is a configuration diagram of an optical receiver using a transimpedance amplifier circuit according to a first embodiment of the present invention.
The optical receiver 500 includes a transimpedance amplifier circuit 200, a differential amplifier circuit 110, and a photodiode 300. The transimpedance amplifier circuit 200 includes the transimpedance amplifier circuit 100 and the differential amplifier circuit 110. The transimpedance amplifier circuit 200 is configured as a semiconductor device formed by a semiconductor manufacturing process.

The transimpedance amplifier circuit 100 includes one current input terminal I _in and two output voltage terminals V _out and V _outB , and the output voltage terminals V _out and V _outB function as differential output terminals. The differential amplifier circuit 110 includes a differential input terminal and a differential output terminal connected to the output voltage terminals V _out and V _outB of the transimpedance amplifier circuit 100, and a difference between the differential input terminal and the differential output terminal. This is an amplifier circuit that amplifies the voltage with a gain G. In each figure, the inverting input terminal and the inverting output terminal of the differential amplifier circuit 110 are marked with “◯”, and the non-inverting input terminal and the non-inverting output terminal are marked with “◯”. By not doing so, both are distinguished.

The photodiode 300 is an element that converts light intensity into a current, and has a cathode end connected to the power supply terminal V _DD and an anode end connected to the current input terminal I _in . Note that a voltage higher than the ground potential is applied to the power supply terminal V _DD .

With these configurations, in the optical receiver 500, the photodiode 300 converts an optical signal into a current signal, the transimpedance amplifier circuit 100 converts the converted current signal into a voltage signal, and the converted voltage signal is differentially converted. The amplifier circuit 110 is configured to amplify to a logic level, and the differential amplifier circuit 110 is configured to transmit a signal to a signal processing circuit at the next stage. Here, the transimpedance amplifier circuit 100 receives a single-ended current signal from the photodiode 300 and outputs a differential voltage signal from the output voltage terminals V _out and V _outB .

  The reason why the transimpedance amplifier circuit 100 outputs the differential voltage signal is to enhance the noise resistance of the signal or to use the differential amplifier circuit 110 to suppress the characteristic variation between elements in the semiconductor process. .

FIG. 2 is a circuit diagram of the transimpedance amplifier circuit according to the first embodiment of the present invention.
The transimpedance amplifier circuit 100 includes P-channel transistors T2, T7, and T8, N-channel transistors T1, T3, T4, T5, and T6, and resistors 10 and 11. The transimpedance amplifier circuit 100 is also a circuit formed as a semiconductor device. Here, in the claims, the transistor T1 is a third transistor, the transistor T2 is a fourth transistor, the transistor T3 is a second transistor, and the transistor T4 is a first transistor.

The transimpedance amplifier circuit 100 includes power supply terminals V _DD and V _SS , a current input terminal I _in , output voltage terminals V _out and V _outB , and control voltage terminals V _C1 and V _C2 . A positive power supply voltage is applied to the power supply terminal V _DD with respect to the ground potential, and the power supply terminal _VSS is connected to the ground potential or a virtual ground point.

The current input terminal I _in is connected to the gates of the two transistors T1 and T2, and the source of the transistor T2 and the drain of the transistor T1 are connected. The source of the transistor T1 is connected to a power supply terminal V _SS, drain and substrate terminal of the transistor T2 is connected to the power supply terminal V _DD. The substrate terminal of the transistor T1 is connected to the power supply terminal V _SS.

With these connections, the transistors T1 and T2 function as inverters, and the transistors T1 and T2 have a gate voltage v ₁ (t) and a potential at a connection point P between the source of the transistor T2 and the drain of the transistor T1. Invert.

The gate of the transistor T4 is connected to the connection point P between the source of the transistor T2 and the drain of the transistor T1, and the drain is connected to one end of the resistor 11. The other end of the resistor 11 is connected to the power supply terminal V _DD . On the other hand, the transistor T3 has its gate connected to the control voltage terminal V _C1, a drain connected to one end of the source, and the resistor 10 of the transistor T4, and a source connected to a power supply terminal V _SS. The other end of the resistor 10 is connected to the current input terminal I _in. The substrate terminals of the transistors T3, T4 are connected to a power supply terminal _{V SS.}

With these connections, the resistor 10 functions as a feedback resistor, and the product of the input current i _in (t) flowing into the current input terminal I _in and the resistance value R _F of the resistor 10 is the transistor T1, T2. The gate voltage v ₁ (t) is equal to a value obtained by subtracting a voltage v ₂ (t) at a connection point (point X) between the drain of the transistor T3, the source of the transistor T4, and one end of the resistor 10. That is, the input current i _in (t) flowing into the current input terminal I _in and the gate voltage v ₁ (t) of the transistors T1 and T2 are in phase.

The transistor T4 causes the resistor 11 to pass a negative-phase current having a phase opposite to that of the change in the voltage v ₁ (t). The transistor T4 takes out the positive-phase drain voltage v ₃ (t) using the resistor 11 as a resistive load, and takes out the source voltage v ₂ (t) at the point X in reverse phase using the transistor T3 as a current source. It is.

The transistor T4 functions as a source follower circuit using the transistor T3 as a current source, and the source voltage v ₂ (t) is extracted with low impedance. That is, the resistor 10 and the source follower circuit function as a transimpedance amplifier that converts the input current i _in (t) flowing into the current input terminal I _in into the voltage v ₂ (t). The transistor T4 also functions as a source grounding circuit using the resistor 11 as a resistance load. For this reason, the source voltage v ₂ (t) and the drain voltage v ₃ (t) have a reversed phase relationship with different amplitudes.

Further, the gate voltage and the drain voltage v ₃ (t) of the transistor T4 are inverted from each other. Since the transistors T1 and T2 function as inverters, the gate voltage v ₁ (t) and the drain voltage v ₃ (t) of the transistor T4 are in phase. That is, the input current i _in flowing into the current input terminal I _in and the drain voltage v ₃ (t) of the transistor T4 are in phase.

The transistor T6 has a gate connected to a connection point (second connection point) between the drain of the transistor T4 and the other end of the resistor 11, a source connected to the drain of the transistor T5, and the output voltage terminal _Vout , It is connected to the power supply terminal V _DD . Transistor T5 has a gate connected to the control voltage terminal V _C1, and a source connected to a power supply terminal V _SS. Thereby, the transistor T6 forms a source follower circuit using the transistor T5 as a current source, and the drain voltage v ₃ (t) of the transistor T4 is extracted from the output voltage terminal V _{out in the} same phase. The voltage of the output voltage terminal _{V out} and the voltage _v 4 (t).

Transistor T7 has its gate connected point between one end of the source and the resistor 10 of the drain of the transistor T4 of the transistor T3 (X point, the first connection point) is connected to a drain connected to the power supply terminal V _SS The source is connected to the drain of the transistor T8 and the output voltage terminal _VoutB . The transistor T8 has a gate connected to the control voltage terminal V _C2 and a source connected to the power supply terminal V _DD . Note that the substrate terminal of the transistor T7 and the substrate terminal of the transistor T8 are connected to the power supply terminal _VDD .

Thereby, the transistor T7 forms a source follower circuit using the transistor T8 as a current source, and the drain voltage v ₂ (t) of the transistor T3 is extracted from the output voltage terminal V _{outB in the} same phase. The voltage at the output voltage terminal V _outB is _defined as a voltage v ₅ (t). Since the drain voltage v ₂ (t) of the transistor T3 and the drain voltage v ₃ (t) of the transistor T4 are opposite in phase, the voltage v ₅ (t) at the output voltage terminal V _outB and the voltage v ₄ (at the output voltage terminal V _out ( t) is in opposite phase.

Further, the control voltage terminals V _C1 and V _C2 have a differential voltage of 0 V between the DC level of the voltage v ₅ (t) of the output voltage terminal V _outB and the DC level of the voltage v ₄ (t) of the output voltage terminal V _out. Set as follows.

(simulation result)
3 and 4 are waveform diagrams of the transimpedance amplifier circuit according to the first embodiment of the present invention.
3A shows the waveform of the voltage v ₁ (t), FIG. 3B shows the waveform of the voltage v ₂ (t), and FIG. 3C shows the voltage v ₃ (t). It is a waveform. FIG. 4A shows the waveform of voltage v ₄ (t), and FIG. 4B shows the waveform of voltage v ₅ (t). The horizontal axis represents time [nsec], and the vertical axis represents logical values “1” and “0” by V _nmax and V _nmin (n is 1 to 5).

When the voltage v ₁ (t) in FIG. 3A increases, the voltage v ₂ (t) in FIG. 3B decreases, and when the voltage v ₁ (t) decreases, the voltage v ₂ (t) increases. Yes. That is, the voltage v ₁ (t) and the voltage v ₂ (t) are inverted. Here, the voltage drop of the resistor 11 as the feedback resistor is {v ₁ (t) −v ₂ (t)}, and the phase of the input current i _in (t) and the phase of the voltage v ₁ (t). Is in phase.

Since the voltage v ₃ (t) in FIG. 3C is in phase with v ₁ (t) in FIG. 3A, it is _in phase with the phase of the input current i _in (t). Since the voltage v ₄ (t) in FIG. 4A is in phase with the voltage v ₃ (t), it is in phase with the phase of the input current i _in (t). Since the voltage v ₅ (t) in FIG. 4B is opposite in phase to the voltage v ₁ (t), it is opposite in phase from the input current i _in (t). In other words, the output voltage terminal V _out outputs a voltage _in phase with the phase of the input current i _in (t), and the output voltage terminal V _outB outputs a voltage _in phase opposite to the phase of the input current i _in (t). .

5 and 6 are eye patterns of the transimpedance amplifier circuit according to the first embodiment of the present invention. The horizontal axis represents time “psec”, and the vertical axis represents the logical value “1” or “0” as V _nmax or V _nmin .
5A is an eye pattern of the voltage v ₁ (t), FIG. 5B is an eye pattern of the voltage v ₂ (t), and FIG. 5C is a voltage v ₃ (t ) Eye pattern. 6A shows an eye pattern of voltage v ₄ (t), and FIG. 6B shows an eye pattern of voltage v ₅ (t).

  The eye pattern is obtained by sampling a large number of signal waveform transitions and overlaying them to display graphically. If multiple waveforms overlap at the same position (timing / voltage), the waveform is good quality. On the other hand, when the waveform position (timing / voltage) is shifted, the waveform is poor in quality and jitter is deteriorated. 5 and 6 show that the waveform is good because the eyes are open.

FIG. 7 is a frequency characteristic diagram of the transimpedance amplifier circuit according to the first embodiment of the present invention. The solid line indicates the frequency characteristic of the gain of the voltage v ₄ (t) of the output voltage terminal V _out , and the broken line indicates the frequency characteristic of the gain of the voltage v ₅ (t) of the output voltage terminal V _outB . The vertical axis is transimpedance [dBohm], and the horizontal axis is frequency [100 MHz to 20 GHz].
The transimpedance amplifier circuit 100 has predetermined transimpedances in both the voltage v ₄ (t) and the voltage v ₅ (t) over the entire frequency range. The voltage v ₅ (t) at the output voltage terminal V _outB has a higher gain than the voltage v ₄ (t) at the output voltage terminal V _out . This mismatch in gain is not a problem if the differential amplifier circuit 110 is provided with a gain limiting function.

Also, as the frequency increases, both transimpedances become substantially equal (Δv ₄ (t) ≈−Δv ₅ (t)), but the gain of the transistor T4 decreases as the frequency increases. Here, Δv ₄ (t) and Δv ₅ (t) indicate AC components of v ₄ (t) and v ₅ (t). Incidentally, the transimpedance when the frequency is high, the resistance value R _F of the resistor 10 is dominant.

  The output voltage vo (t) is determined by the gain of the differential amplifier circuit 110 (FIG. 1) connected to the next stage of the transimpedance amplifier circuit 100 and the gain limiting function.

(PON system)
FIG. 8 is an overall configuration diagram of a PON system in which the transimpedance amplifier circuit 200 according to the first embodiment of the present invention is used.
The PON system 800 includes a plurality of subscriber home terminals 700, 701, 702, a station 600, and a splitter 750. The station 600 and the plurality of subscriber home terminals 700, 701, 702 are connected via the splitter 750. Are connected to communicate. Here, a receiver installed in the station 600 (OLT) includes a photodiode (PD) 300 that converts an optical signal into a current, and a transformer that converts an output current output from the photodiode 300 into a differential voltage. And an impedance amplifier circuit 200.

  The downlink data transmitted from the station (OLT) to the subscriber's home terminal (ONU) is a continuous signal, but the uplink data transmitted from the subscriber's home terminal (ONU) to the station (OLT) is data There is no signal between the data and the burst signal. In addition, the amplitude of the signal transmitted from the terminal 700, 701, 702 at the subscriber's home is constant, but the distance between the terminal 700, 701, 702 at the subscriber's home and the station 600 varies. , The burst signal from the terminal 700 of a specific subscriber's home may become strong, and the burst signal from a different subscriber's home 701 may become weak. For this reason, the station (OLT) needs an optical receiver 500 (FIG. 1) that converts these optical burst signals having different intensities and timings into electrical signals having a constant intensity.

(Second Embodiment)
The transimpedance amplifier circuit 100 of the first embodiment uses the resistor 11 as a resistive load, but can be changed to an active load.
FIG. 9 is a circuit diagram of a transimpedance amplifier circuit according to the second embodiment of the present invention.
The transimpedance amplifier circuit 101 is obtained by changing the resistor 11 (FIG. 2) to a transistor T9 as a fourth transistor with respect to the transimpedance amplifier circuit 100 shown in FIG.
That is, the source of the transistor T9 is connected to the connection point between the drain of the transistor T4 and the gate of the transistor T6, the drain is connected to the power supply terminal V _DD , and the gate is connected to V _C2 . The substrate terminal of the transistor T9 is connected to the power supply terminal V _DD .

With this connection, the transistor T9 functions as an active load of the transistor T4.
The active load performs an operation close to that of a constant current source, and the voltage change becomes larger than that of the resistive load. Therefore, the amplification factor of the transistor T4 is high. In addition, since the transimpedance amplifier circuit 101 does not use the resistor 11 (FIG. 2), circuit characteristics are determined by the gate width size of all the transistors and the size ratio between the elements, so that variation in characteristics between elements is suppressed. The

(Third embodiment)
In the transimpedance amplifier circuit 100 of the first embodiment, the gates of the transistors T1 and T2 are connected to each other to form an inverter circuit. However, the transistor T2 can be an active load.

FIG. 10 is a circuit diagram of a transimpedance amplifier circuit according to the third embodiment of the present invention.
Compared with the transimpedance amplifier circuit 101 (FIG. 9), the transimpedance amplifier circuit 102 changes the connection of the transistor T2 to be a transistor T10. That is, the transistor T10 as the fourth transistor has a drain connected to the power supply terminal V _DD , a gate connected to the control voltage terminal V _C2 , a source connected to the drain of the transistor T1 and the gate of the transistor T4, and a substrate terminal It is connected to the power supply terminal V _DD .

Transimpedance amplifier circuit 102, a gate connected to the current input terminal I _in is only the transistor T1.

(First comparative example)
FIG. 11 is a circuit diagram of an optical receiver which is a first comparative example of the present invention.
The optical receiver 501 includes a photodiode 300 and a transimpedance amplifier circuit 201. The transimpedance amplifier circuit 201 includes a transimpedance amplifier circuit 103, a differential amplifier circuit 110, a resistor 12, and a capacitor 20. Have.

The photodiode 300 is the same as that in FIG. 1 of the first embodiment in that the cathode is connected to the power supply terminal V _DD and the anode is connected to the input terminal of the transimpedance amplifier circuit 103. The transimpedance amplifier circuit 103 is different from the transimpedance amplifier circuit 100 (FIGS. 1 and 2) in that it is a single-ended output amplifier circuit. The transimpedance amplifier circuit 103 can be configured by externally connecting a feedback resistor to a general-purpose operational amplifier. The general-purpose operational amplifier is provided with a phase compensation capacitor.

  The single-ended output terminal of the transimpedance amplifier circuit 103 is connected to the non-inverting input terminal of the differential amplifier circuit 110. In the differential amplifier circuit 110, a resistor 12 is connected between a non-inverting input terminal and an inverting input terminal, and one end of a capacitor 20 is connected to a connection point between the inverting input terminal and the resistor 12. Yes. The other end of the capacitor 20 is grounded. That is, the resistor 12 and the capacitor 20 constitute a low-pass filter, which removes an AC component (high-frequency component) of the output voltage of the transimpedance amplifier circuit 103 and uses only the DC component as an inverting input of the differential amplifier circuit 110. It has a function to be applied to the terminal.

  The differential amplifier circuit 110 is a circuit that amplifies a differential voltage between a voltage applied to the non-inverting input terminal and a voltage applied to the inverting input terminal. For this reason, the differential amplifier circuit 110 cancels the DC component of the output voltage of the single-ended output terminal of the transimpedance amplifier circuit 103, amplifies only the AC component, and outputs it.

Incidentally, since the capacitor 20 requires a relatively large capacity, it is difficult to integrate the transimpedance amplifier circuit 201. On the other hand, since the transimpedance amplifier circuit 200 of the first embodiment does not include a capacitor, it can be integrated with a small occupied area. Further, since the transimpedance amplifier circuit 100 (FIG. 2) can align the DC potentials of the output voltage terminals V _out and V _outB when there is no signal, the differential amplifier circuit 110 cancels the aligned DC potentials, Only the AC component can be amplified.

(Second comparative example)
FIG. 12 is a circuit diagram of an optical receiver which is a second comparative example of the present invention.
The optical receiver 502 includes a photodiode 300 and a transimpedance amplifier circuit 202. The transimpedance amplifier circuit 202 includes a transimpedance amplifier circuit 103, two differential amplifier circuits 110 and 111, a resistor 13, And a capacitor 21. The differential amplifier circuit 110 has a differential output terminal, whereas the differential amplifier circuit 111 has a single-ended output terminal.

  The photodiode 300 and the transimpedance amplifier circuit 103 are connected in the same manner as in the first comparative example, and the single-ended output terminal of the transimpedance amplifier circuit 103 is connected to the non-inverting input terminal of the differential amplifier circuit 110.

  The differential amplifier circuit 110 has its differential output terminal connected to the differential input terminal of the differential amplifier circuit 111. A single-ended output terminal of the differential amplifier circuit 111 is connected to one end of the resistor 13. The other end of the resistor 13 is connected to one end of the capacitor 21 and the inverting input terminal of the differential amplifier circuit. The other end of the capacitor 21 is grounded. The resistor 13 and the capacitor 21 constitute a low-pass filter, and apply the DC component of the single-ended output terminal of the differential amplifier circuit 111 to the inverting input terminal of the differential amplifier circuit 110. Thereby, the closed circuit of the differential amplifier circuits 110 and 111, the resistor 13, and the capacitor 21 has a DC component of the potential of the non-inverting input terminal of the differential amplifier circuit 111 and a potential (DC potential) of the inverting input terminal. They function to match and constitute a DC feedback circuit.

  Therefore, the transimpedance amplifier circuit 202 cancels the DC component of the output voltage of the transimpedance amplifier circuit 103, and the differential amplifier circuit 110 amplifies only the AC component (high frequency component). By the way, since the capacitor 21 needs a relatively large capacity, it is difficult to integrate the transimpedance amplifier circuit 202. On the other hand, since the transimpedance amplifier circuit 200 of the first embodiment does not include a capacitor, it can be integrated with a small occupied area.

(Third comparative example)
FIG. 13 is a circuit diagram of an optical receiver which is a third comparative example of the present invention.
The optical receiver 503 includes a photodiode 300 and a transimpedance amplifier circuit 203. The transimpedance amplifier circuit 203 includes a transimpedance amplifier circuit 103, a differential amplifier circuit 110, and four resistors 14, 15, and 16. , 17 and capacitor 22.

  The photodiode 300 has the same connection as in the first comparative example, but the transimpedance amplifier circuit 103 has a single-ended output terminal connected to the non-inverting input terminal of the differential amplifier circuit 110 via the capacitor 22. Is different. Further, the differential amplifier circuit 110 uses two resistors 14 and 15 to apply a DC bias to the non-inverting input terminal. That is, the transimpedance amplifier circuit 103 and the differential amplifier circuit 110 are AC coupled. Further, the differential amplifier circuit 110 uses two resistors 16 and 17 to apply a DC bias to the inverting input terminal.

That is, the capacitor 22 is connected to the single-ended output terminal of the transimpedance amplifier circuit 103 and the non-inverting input terminal of the differential amplifier circuit 110. Also, the series circuit, and a series circuit of resistors 16 and 17 of the resistor 14 and 15 is connected a power supply terminal _{V DD,} and the power supply terminal _{V SS.} The connection point of the series circuit of the resistors 14 and 15 is connected to one end of the capacitor 22 and the non-inverting input terminal of the differential amplifier circuit 110. The connection point of the series circuit of the resistors 16 and 17 is connected to the inverting input terminal of the differential amplifier circuit 110.

  With these connections, the differential amplifier circuit 110 applies the AC component of the output voltage of the transimpedance amplifier circuit 103 and the divided voltage (DC voltage) of the resistors 14 and 15 to the non-inverting input terminal. , 17 is applied to the inverting input terminal. Here, if the resistance values of the resistors 14 and 16 are made uniform and the resistance values of the resistors 15 and 17 are made uniform, the divided voltage of the resistors 16 and 17 and the divided voltage of the resistors 16 and 17 become equal. As a result, the differential amplifier circuit 110 cancels the divided voltage of the resistors 16 and 17 and the divided voltage of the resistors 16 and 17 and amplifies only the AC component of the output voltage of the transimpedance amplifier circuit 103.

  By the way, since the capacitor 22 needs a relatively large capacity, it is difficult to integrate the transimpedance amplifier circuit 203. On the other hand, since the transimpedance amplifier circuit 200 of the first embodiment does not include a capacitor, it can be integrated with a small occupied area.

(Modification)
(1) The transimpedance amplifier circuit 100 according to the first embodiment uses the transistors T1, T2, and T4 to flow the drain current of the transistor T4 having a phase opposite to the change in the gate voltage v ₁ (t) of the transistor T1. Yes. However, the transistors T1, T2, and T4 can be regarded as a single amplifier circuit. That is, the transistor T4 can be considered to have passed the drain current changes and reverse-phase voltage of the current input terminal I _in the resistor 11.

(2) The impedance amplifying circuits 100, 101, and 102 of each of the above embodiments _{obtain a} differential output voltage from the output voltage terminals V _out and V _outB via the source follower circuits T5 and T6 and the source follower circuits T7 and T8. I was getting. However, since the input impedance of the differential amplifier circuit 110 at the next stage is usually high, the source follower circuits T5 and T6 and the source follower circuits T7 and T8 are often unnecessary. That is, the drain of the transistor T4 of the transimpedance amplifier circuit 100 is connected to the non-inverting input terminal of the differential amplifier circuit, and the drain of the transistor T3 of the transimpedance amplifier circuit 100 is connected to the inverting input terminal of the differential amplifier circuit. The

(3) Although the impedance amplifying circuit 102 (FIG. 10) of the third embodiment uses the transistor T9 as an active load, a resistive load can be used instead of the transistor T9. In addition, the transistor T3 in each of the above embodiments is used as a current source for extracting the voltage at the voltage V2 (t) at the point X as a source follower, but may be a resistive load.

10 Resistor 11 Resistor (resistance load)
12, 13, 14, 15, 16, 17 Resistor 20, 21, 22 Capacitor 100, 101, 102, 103, 200, 201, 202, 203 Transimpedance amplifier circuit (semiconductor device)
110, 111 Differential amplifier circuit 300 Photodiode (PD)
500, 501, 502, 503 Optical receiver 600 Station 700, 701, 702 Subscriber's house 750 Splitter 800 PON system T1 transistor (third transistor, N-channel transistor)
T2 transistor (4th transistor, P-channel transistor)
T3 transistor (second load, second transistor, N-channel transistor)
T4 transistor (first transistor, N-channel transistor)
T5, T6 transistor (second source follower circuit, N-channel transistor)
T7, T8 transistor (first source follower circuit, P-channel transistor)
T9 (4th transistor, P-channel transistor, active load)
T10 transistor (4th transistor, P-channel transistor, active load)
V _DD power source terminal _{V SS} power supply terminal _{V C1, V C2} control voltage terminal _{I in} the current input terminal _{V out, V outB} output voltage terminal _{v 1 (t), v 2} (t), v 3 (t), v 4 ( t), v ₅ (t) Voltage i _in input current

Claims (9)

A transimpedance amplifier circuit that converts an input current flowing into an input terminal into a voltage and differentially outputs the converted voltage,
A resistor having one end connected to the input terminal;
An inverter for inverting the voltage of the input terminal;
A first load to which a predetermined voltage is applied, and a series circuit of a first transistor and a second load having the output voltage of the inverter as a gate voltage ,
The other end of the resistor is connected to a first connection point that connects the first transistor and the second load;
A transimpedance amplifier circuit, wherein a voltage is output from both a second connection point connecting the first load and the first transistor and the first connection point. The transimpedance amplifier circuit according to claim 1 ,
Before Stories second load transimpedance amplifier circuit, which is a second transistor which applies a predetermined voltage to the gate. The transimpedance amplifier circuit according to claim 1 or 2,
The voltage at the first connection point is output through a first source follower circuit,
The voltage at the second connection point is output through a second source follower circuit. The transimpedance amplifier circuit according to claim 3,
Transimpedance amplification characterized in that the output voltage of the first source follower circuit and the output voltage of the second source follower circuit have the same DC voltage level when the input current is in a no-signal state. circuit. The transimpedance amplifier circuit according to claim 4,
The transimpedance amplifier circuit further comprising a differential amplifier circuit to which an output voltage of the first source follower circuit and an output voltage of the second source follower circuit are differentially input. The transimpedance amplifier circuit according to claim 1 or 2,
The transimpedance amplifier circuit further comprising a differential amplifier circuit to which a voltage at the first connection point and a voltage at the second connection point are differentially input. The transimpedance amplifier circuit according to claim 1,
The transimpedance amplifier circuit, wherein the first load is a resistor or an active load. The transimpedance amplifier circuit according to claim 2,
The inverter, the gate is connected to a connection point of the input terminal and the resistor, and a third transistor whose source is connected to a source of the second transistor, before Symbol drain of the third transistor, and the first A fourth transistor having a source connected to the gate of the transistor,
The gate of the fourth transistor is connected to the gate of the third transistor or the drain of the fourth transistor. A semiconductor device in which a transimpedance amplifier circuit that converts an input current flowing into an input terminal into a voltage and differentially outputs the converted voltage is formed,
A resistor having one end connected to the input terminal;
An inverter for inverting the voltage of the input terminal;
A first load to which a predetermined voltage is applied, and a series circuit of a first transistor and a second load having the output voltage of the inverter as a gate voltage ,
The other end of the resistor is connected to a first connection point that connects the first transistor and the second load;
A voltage is output from both a second connection point connecting the first load and the first transistor and the first connection point.

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