JPH06310961A - Signal gain control circuit - Google Patents

Signal gain control circuit

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Publication number
JPH06310961A
JPH06310961A JP12195293A JP12195293A JPH06310961A JP H06310961 A JPH06310961 A JP H06310961A JP 12195293 A JP12195293 A JP 12195293A JP 12195293 A JP12195293 A JP 12195293A JP H06310961 A JPH06310961 A JP H06310961A
Authority
JP
Japan
Prior art keywords
circuit
signal
transistors
voltage
current
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12195293A
Other languages
Japanese (ja)
Inventor
Masanori Honbo
正典 本坊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Denshi KK
Original Assignee
Hitachi Denshi KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Denshi KK filed Critical Hitachi Denshi KK
Priority to JP12195293A priority Critical patent/JPH06310961A/en
Publication of JPH06310961A publication Critical patent/JPH06310961A/en
Pending legal-status Critical Current

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  • Tone Control, Compression And Expansion, Limiting Amplitude (AREA)
  • Control Of Amplification And Gain Control (AREA)
  • Amplifiers (AREA)

Abstract

PURPOSE:To adopt lower drive voltage for the signal gain control circuit by applying an input signal to a voltage-current conversion circuit, applying a control signal between bases of transistors(TRs), and obtaining an output signal from collectors of the TR. CONSTITUTION:A differential amplifier 4 is made up of 1st and 2nd transistors(TRs) 1, 2 whose emitters are connected in common. A constant current circuit 5 connecting to a common emitter of the amplifier 4 and supplying a bias current to the TRs 1, 2, and a load circuit 3 connecting to collectors of the TRs 1, 2 and forming a load of the amplifier 4 are provided. Furthermore, a control means applying a control signal Vc between bases of the TRs 1, 2 and a voltage-current conversion circuit 6 whose output terminal connects to a common emitter of the amplifier 4 and changing the current of the output terminal in response to an input signal ej applied to the input terminal are provided. Then the input signal ej is obtained and an output signal eo whose voltage gain is changed in response to the control signal Vc by the load circuit 3. Thus, the signal gain control circuit is obtained, which is operated at a lower power supply voltage.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は所要電源電圧の低圧化を
図った信号利得制御回路の改良に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement of a signal gain control circuit for reducing the required power supply voltage.

【0002】[0002]

【従来の技術】図2に示す回路は、従来より信号利得制
御回路として広く用いられているアナログ乗算器の基本
回路である。この回路はトランジスタ1,2とその負荷
抵抗3(抵抗値RL)からなる差動増幅器4と、この差動
増幅器4に直流バイアス電流を供給する定電流回路5
と、この定電流回路5と上記差動増幅器4の共通エミッ
タ間にカスケード接続されたトランジスタ17と、この
トランジスタ17のエミッタとアース間に接続された抵
抗18(抵抗値RE)より構成されており、トランジスタ
17のベースに入力信号ei を印加し、トランジスタ
1,2のベース間に制御信号Vcを印加し、トランジス
タ2のコレクタより出力信号eo を得るようになってい
る。この回路において、トランジスタ17のベースに入
力信号ei が印加されると、トランジスタ17のコレク
タに、ほぼ、信号電流i=ei/REが流れる。この信号
電流iはトランジスタ1,2に分流され、これら各々の
トランジスタのコレクタには信号電流iL1,iL2(iL1
+iL2=i)が流れる。これにより、トランジスタ2の
コレクタより、出力信号eo=−iL2・RLが得られる。
一方、トランジスタ1,2の各々を流れる信号電流の比
(iL1:iL2)は、トランジスタ1,2のベース間の電
位差、すなわち、制御信号Vcの値によって変化する。
つまり、制御信号Vcの値を変えることにより信号電流
L2の値を変え、これにより、出力信号eoの利得を制
御できる。この出力信号eoは、
2. Description of the Related Art The circuit shown in FIG. 2 is a basic circuit of an analog multiplier which has been widely used as a signal gain control circuit. This circuit is composed of transistors 1 and 2 and a load resistance 3 (resistance value R L ) of the differential amplifier 4, and a constant current circuit 5 for supplying a DC bias current to the differential amplifier 4.
And a transistor 17 cascade-connected between the constant current circuit 5 and the common emitter of the differential amplifier 4, and a resistor 18 (resistance value R E ) connected between the emitter of the transistor 17 and ground. Therefore, the input signal e i is applied to the base of the transistor 17, the control signal Vc is applied between the bases of the transistors 1 and 2, and the output signal e o is obtained from the collector of the transistor 2. In this circuit, when the input signal e i is applied to the base of the transistor 17, a signal current i = e i / R E almost flows through the collector of the transistor 17. This signal current i is shunted to the transistors 1 and 2, and the signal currents i L1 and i L2 (i L1
+ I L2 = i) flows. As a result, the output signal e o = −i L2 · R L is obtained from the collector of the transistor 2.
On the other hand, the ratio (i L1 : i L2 ) of the signal currents flowing through the transistors 1 and 2 changes depending on the potential difference between the bases of the transistors 1 and 2, that is, the value of the control signal Vc.
That is, the value of the signal current i L2 is changed by changing the value of the control signal Vc, and thus the gain of the output signal e o can be controlled. This output signal e o is

【0003】[0003]

【数1】 K:ボルツマン定数 T:絶対温度 q:単位電荷量 なる式により求められる。ここで、図2に示す回路を動
作させるために必要な各部の電圧を求め、電源電圧(V
cc)の所要値を求める。なお、定電流回路5には通常、
同図に示したカレント・ミラー回路12が用いられるの
で、ここではこれに置き換えて考えることにする。図2
の回路中のトランジスタはすべてA級動作となるが、こ
れに必要なバイアス電圧VCE(コレクタ・エミッタ間電
圧)を、VCE≧VBE(ベース・エミッタ間電圧)と仮定
すると、図2のトランジスタ1,2,17,10は3段
のカスケード回路を構成しているので、これらの動作に
は合計、 VTR≧3・VBE ・・・・・・・(2) の電圧が必要となる。
[Equation 1] K: Boltzmann's constant T: absolute temperature q: unit charge amount Here, the voltage of each part necessary for operating the circuit shown in FIG.
Find the required value of cc). The constant current circuit 5 is usually
Since the current mirror circuit 12 shown in the figure is used, it will be replaced with this here. Figure 2
All of the transistors in the circuit of FIG. 2 operate in class A, but assuming that the bias voltage V CE (collector-emitter voltage) required for this is V CE ≧ V BE (base-emitter voltage), Since the transistors 1, 2, 17 and 10 form a three-stage cascade circuit, a total voltage of V TR ≧ 3 · V BE ··· (2) is required for these operations. Become.

【0004】カレント・ミラー回路12により供給され
る直流バイアス電流Iは、制御信号Vc=0Vとする
と、トランジスタ1,2に2等分され、これら各々のト
ランジスタのコレクタには、I1=I2=I/2の直流バ
イアス電流が流れる。これら直流バイアス電流による各
部の電圧降下は、カレント・ミラー回路12において、
b・I、差動増幅器4の負荷抵抗3において、RL・I
2=RL・I/2となり、合計、 Vb=I・(Rb+RL/2) ・・・(3) となる。入力信号eiの振幅の最大値をei MAX、制御信
号Vc=0Vとすると、出力信号e0の振幅の最大値e
o MAXは(1)式より、eO MAX=ei MAX・RL/2RE
となる。したがって、図2の回路にて入・出力信号の所
要ダイナミックレンジを確保するためには、 Vs≧ei MAX・(1+RL/2RE) ・・・(4) の電圧が必要となる。以上の結果、図2の回路の電源電
圧Vccの所要値は、上記(2),(3),(4)式より、Vc
c≧(VTR+Vb+VS)/2、すなわち、 Vcc≧{3VBE+I・(Rb+RL/2)+ei MAX・(1+RL/2RE)}/2 ・・・(5) となる。
The DC bias current I supplied by the current mirror circuit 12 is equally divided into two transistors 1 and 2 when the control signal Vc = 0V, and I 1 = I 2 is applied to the collectors of the respective transistors. A DC bias current of = I / 2 flows. In the current mirror circuit 12, the voltage drop of each part due to these DC bias currents is
R b · I, in the load resistance 3 of the differential amplifier 4, R L · I
2 = RL · I / 2, and the total is Vb = I · ( Rb + RL / 2) (3). Assuming that the maximum amplitude of the input signal e i is e i MAX and the control signal Vc = 0V, the maximum amplitude e of the output signal e 0 is e.
o MAX is calculated from the equation (1), e O MAX = e i MAX · R L / 2R E
Becomes Therefore, in order to secure the required dynamic range of input / output signals in the circuit of FIG. 2, a voltage of Vs ≧ e i MAX · (1 + R L / 2R E ) (4) is required. As a result, the required value of the power supply voltage Vcc of the circuit of FIG. 2 is Vc from the above equations (2), (3) and (4).
c ≧ (V TR + V b + V S ) / 2, that is, Vcc ≧ {3V BE + I · (R b + R L / 2) + e i MAX · (1 + R L / 2R E )} / 2・ ・ (5)

【0005】[0005]

【発明が解決しようとする課題】ところで、今日、とり
わけ電池駆動を必要とする可搬型の機器を中心に、電子
機器の低消費電力化への要請がますます強まっている。
この電子機器の低消費電力化を図る手法としては、回路
電源の低電圧化が極めて有効である。ところが、図2に
示した乗算器は、正負電源間に多数のトランジスタをカ
スケード接続するという回路構成上、本質的に電源を低
電圧化しづらいという難点をもっている。すなわち、上
記(5)式によれば、同式右辺第1項は図2の回路中のト
ランジスタの動作に必要な最小限のバイアス電圧の総和
であり、同式左辺の電源電圧Vccの増減には無関係のい
わば固定分である。したがって、同式左辺の電源電圧V
ccを小さくしようとしても、同式右辺第1項により自ず
と下限が決まってしまう。この右辺第1項の実際の値
は、通常、VBE=0.6V〜0.8Vであるので、3×
BE=1.8V〜2.4Vとなる。この値は、場合によ
っては、僅か数Vという低圧電源下で動作する回路が求
められる昨今においては、極めて大きい値と言える。以
上の理由により、図2の回路と同等の機能を有し、か
つ、より低電圧の電源にて動作可能な回路の実現が望ま
れており、これが本発明の目的でもある。
By the way, today, there is an increasing demand for low power consumption of electronic devices, especially in portable devices that require battery drive.
As a method for reducing the power consumption of this electronic device, lowering the voltage of the circuit power supply is extremely effective. However, the multiplier shown in FIG. 2 has a drawback in that it is difficult to lower the voltage of the power source because of the circuit configuration in which a large number of transistors are cascade-connected between the positive and negative power sources. That is, according to the above equation (5), the first term on the right side of the equation is the sum of the minimum bias voltages necessary for the operation of the transistors in the circuit of FIG. Is a fixed part that has nothing to do with it. Therefore, the power supply voltage V on the left side of the equation
Even if we try to reduce cc, the first term on the right-hand side of the equation naturally determines the lower limit. The actual value of the first term on the right side is usually V BE = 0.6V to 0.8V, so 3 ×
V BE = 1.8V to 2.4V. This value can be said to be extremely large in recent years when a circuit that operates under a low voltage power supply of only a few volts is required. For the above reasons, it is desired to realize a circuit having the same function as that of the circuit of FIG. 2 and capable of operating with a lower voltage power source, and this is also an object of the present invention.

【0006】[0006]

【課題を解決するための手段】本発明は上記目的を達成
するために、図1に示すように、トランジスタ1,2と
その負荷抵抗3からなる差動増幅器4と、この差動増幅
器4に直流バイアス電流を供給する定電流回路5と、出
力端が上記差動増幅器4の共通エミッタに接続された電
圧−電流変換回路6より構成されており、電圧−電流変
換回路6に入力信号ei を印加し、トランジスタ1,2
のベース間に制御信号Vcを印加し、トランジスタ2の
コレクタより出力信号e0 を得るようにしたものであ
る。
In order to achieve the above object, the present invention provides a differential amplifier 4 comprising transistors 1 and 2 and a load resistor 3 thereof, as shown in FIG. A constant current circuit 5 for supplying a DC bias current and a voltage-current conversion circuit 6 whose output end is connected to the common emitter of the differential amplifier 4 are provided. The voltage-current conversion circuit 6 receives an input signal e i. Is applied, and transistors 1 and 2
The control signal Vc is applied between the bases of the two, and the output signal e 0 is obtained from the collector of the transistor 2.

【0007】[0007]

【作用】図1の回路において、電圧−電流変換回路6の
変換係数を1/RE とし、電圧−電流変換回路6に入力
信号ei が印加されると、トランジスタ1,2の共通エ
ミッタに信号電流i=ei/REが流れる。この信号電流
iはトランジスタ1,2に分流され、これらそれぞれの
トランジスタのコレクタには信号電流iL1,iL2(iL1
+iL2=i)が流れる。これにより、トランジスタ2の
コレクタより出力信号eo=−iL2・RLが得られる。一
方、トランジスタ1,2のそれぞれを流れる信号電流の
比(iL1:iL2)は、トランジスタ1,2のベース間の電
位差、すなわち、制御信号Vcの値によって変化する。
つまり、制御信号Vcの値を変えることにより信号電流
L2の値を変え、これにより、出力信号eo の利得を制
御できる。この出力信号eo は前述の図2の回路と同様
に、
In the circuit of FIG. 1, when the conversion coefficient of the voltage-current conversion circuit 6 is set to 1 / RE and the input signal e i is applied to the voltage-current conversion circuit 6, the common emitters of the transistors 1 and 2 are connected. The signal current i = e i / R E flows. This signal current i is shunted to the transistors 1 and 2, and the signal currents i L1 and i L2 (i L1
+ I L2 = i) flows. As a result, the output signal e o = −i L2 · R L is obtained from the collector of the transistor 2. On the other hand, the ratio (i L1 : i L2 ) of the signal currents flowing through the transistors 1 and 2 changes depending on the potential difference between the bases of the transistors 1 and 2, that is, the value of the control signal Vc.
That is, the value of the signal current i L2 is changed by changing the value of the control signal Vc, and thus the gain of the output signal e o can be controlled. This output signal e o is similar to the circuit of FIG.

【0008】[0008]

【数2】 K:ボルツマン定数 T:絶対温度 q:単位電荷量 なる式により求められる。ここで、前述の図2の回路の
場合と同様に、図1の回路を動作させるために必要な各
部の電圧を求め、電源電圧の所要値を求める。なお、定
電流回路5は図2の回路と同様にカレント・ミラー回路
12に置き換えて考えることにする。まず、図1の回路
中のトランジスタはすべてA級動作となるが、これに必
要なバイアス電圧VCEを、VCE≧VBEと仮定すると、図
1の回路のトランジスタ1,2,10は2段のカスケー
ド回路を構成しているので、これらの動作には合計、 VTR ≧2・VBE ・・・(7) の電圧が必要となる。
[Equation 2] K: Boltzmann's constant T: absolute temperature q: unit charge amount Here, similarly to the case of the circuit of FIG. 2 described above, the voltage of each part necessary for operating the circuit of FIG. 1 is obtained, and the required value of the power supply voltage is obtained. The constant current circuit 5 will be replaced with the current mirror circuit 12 as in the circuit of FIG. First, all the transistors in the circuit of FIG. 1 perform class A operation, but if the bias voltage V CE required for this is assumed to be V CE ≧ V BE , the transistors 1, 2, 10 of the circuit of FIG. Since a cascade circuit of stages is configured, a total of V TR ≧ 2 · V BE (7) is required for these operations.

【0009】次に、カレント・ミラー回路12により供
給される直流バイアス電流Iは、制御信号Vc=0Vと
すると、トランジスタ1,2に2等分され、これら各々
のトランジスタのコレクタには、I1=I2=I/2の直
流バイアス電流が流れる。これら直流バイアス電流によ
る各部の電圧降下は、カレント・ミラ−回路12におい
て、Rb・I、差動増幅器4の負荷抵抗3において、RL
・I2=RL・I/2となり、合計は前述の図2の回路と
同様に、 Vb=I・(Rb+RL/2) ・・・・(8) となる。また、入力信号eiの振幅の最大値をei MAX
制御信号Vc=0Vとすると、出力信号eoの振幅の最
大値eo MAXは、(6)式より、eO MAX=ei MAX・RL
/2REとなる。したがって、出力信号eoの所要ダイナ
ミックレンジを確保するためには、 Vs≧ei MAX・RL/2RE ・・・(9) の電圧が必要となる。
Next, the DC bias current I supplied by the current mirror circuit 12 is equally divided into two transistors 1 and 2, assuming that the control signal Vc = 0V, and the collector of each of these transistors has I 1 A DC bias current of = I 2 = I / 2 flows. The voltage drop in each part due to the DC bias current is R b · I in the current mirror circuit 12 and R L in the load resistance 3 of the differential amplifier 4.
· I 2 = R L · I / 2 , and the sum in the same manner as the circuit of aforementioned Figure 2, V b = I · ( R b + R L / 2) becomes ... (8). In addition, the maximum value of the amplitude of the input signal e i is represented by e i MAX ,
Assuming that the control signal Vc = 0V, the maximum value e o MAX of the amplitude of the output signal e o can be calculated from equation (6) as e o max = e i max RL
/ 2R E. Therefore, in order to secure the required dynamic range of the output signal e o , a voltage of Vs ≧ e i MAX · R L / 2R E (9) is required.

【0010】以上の結果、図1のトランジスタ1,2,
10により構成されるカスケード回路における電源電圧
Vccの所要値は、(7),(8),(9)式より、Vcc
≧(VTR+Vb+Vs)/2、すなわち、 Vcc≧{2・VBE+I・{Rb+RL/2)+ei MAX・RL/2RE)}/2 ・・・(10) となる。なお、図1の電圧−電流変換回路6は、同図に
示したベース接地増幅器15のような簡単な回路で構成
できる。この回路はトランジスタ1,2,10のカスケ
ード回路の電源電圧(Vcc)の所要値内で十分動作可能
であり、入力信号ei のダイナミックレンジも容易に確
保できる。したがって、図1の回路の電源電圧の所要値
は上記(10)式のみにて与えられると考えてよい。こ
こで、図2に示した従来の信号利得制御回路と、図1に
示した本発明回路の電源電圧の所要値を比較する。すな
わち、前記(5)式と上記(10)式におけるVccの値
を比較すると、明らかに(10)式の方が小さいことが
判る。両式よりその差は、(VBE+ei MAX)/2であ
り、これはei MAXの値によっては数Vにもなる。つま
り、その分、本発明回路の方が従来の回路よりも、より
低電圧の電源にて駆動できる。すなわち、昨今の技術課
題となっている回路電源の低電圧化に有利であるといえ
る。
As a result of the above, the transistors 1, 2,
The required value of the power supply voltage Vcc in the cascade circuit composed of 10 is Vcc from the equations (7), (8) and (9).
≧ (V TR + V b + Vs) / 2, that is, Vcc ≧ {2 · V BE + I · {R b + R L / 2) + e i MAX · R L / 2R E )} / 2 ( 10) becomes. The voltage-current conversion circuit 6 shown in FIG. 1 can be configured by a simple circuit such as the base-grounded amplifier 15 shown in FIG. This circuit can sufficiently operate within the required value of the power supply voltage (Vcc) of the cascade circuit of the transistors 1, 2 and 10, and the dynamic range of the input signal e i can be easily secured. Therefore, it may be considered that the required value of the power supply voltage of the circuit of FIG. 1 is given only by the above equation (10). Now, the required value of the power supply voltage between the conventional signal gain control circuit shown in FIG. 2 and the circuit of the present invention shown in FIG. 1 will be compared. That is, comparing the values of Vcc in the equation (5) and the equation (10), it is apparent that the equation (10) is smaller. From the two equations, the difference is (V BE + e i MAX ) / 2, which is several V depending on the value of e i MAX . That is, the circuit of the present invention can be driven by a power supply of a lower voltage than that of the conventional circuit. That is, it can be said that it is advantageous for lowering the voltage of the circuit power supply, which has been a technical problem in recent years.

【0011】[0011]

【実施例】以下、本発明の一実施例について説明する。
図3に示した回路は、図1に示した本発明の回路を応用
した信号利得制御回路である。すなわち、図3の回路
は、トランジスタ1,2,10,13により構成される
第1の乗算器と、同じくトランジスタ1′,2′,1
0′,13′により構成され、上記第1の乗算器と全く
対称な第2の乗算器により構成され、トランジスタ1,
2からなる差動増幅器4と、トランジスタ1′,2′か
らなる差動増幅器4′のベースとコレクタを各々共通接
続し、抵抗3(RL)を共通負荷としたものであり、ベー
ス接地増幅器15(15′)の入力端に入力信号ei を印
加し、上記差動増幅器4,4′の共通ベース間に制御信
号Vcを印加し、同じく共通コレクタより出力信号eo
を得るようにしたものである。上記第1、第2の乗算器
は各々図1に示した本発明の回路と基本的に同じもので
ある。図1の乗算器は制御信号Vcが変化すると負荷抵
抗3(RL)を流れる直流バイアス電流I2が変化し、出
力信号eoの直流電位が変化する。
EXAMPLES An example of the present invention will be described below.
The circuit shown in FIG. 3 is a signal gain control circuit to which the circuit of the present invention shown in FIG. 1 is applied. That is, the circuit shown in FIG. 3 has the same structure as the first multiplier constituted by the transistors 1, 2, 10 and 13 and the transistors 1 ′, 2 ′ and 1 similarly.
0 ', 13', and a second multiplier that is completely symmetrical to the first multiplier,
A differential amplifier 4 composed of 2 and a base and collector of a differential amplifier 4'composed of transistors 1'and 2'are connected in common, and a resistor 3 ( RL ) is used as a common load. An input signal e i is applied to the input terminal of 15 (15 '), a control signal Vc is applied between the common bases of the differential amplifiers 4 and 4', and an output signal e o is also from the common collector.
Is to get. The first and second multipliers are basically the same as the circuit of the present invention shown in FIG. In the multiplier of FIG. 1, when the control signal Vc changes, the DC bias current I 2 flowing through the load resistor 3 ( RL ) changes, and the DC potential of the output signal e o changes.

【0012】しかしながら、図3の回路は、トランジス
タ10,10′による定電流回路(カレント・ミラー回
路12′)より差動増幅器4,4′の各々へ供給される
直流バイアス電流I1,I2がI1=I2=Iと等しい場
合、制御信号Vcが変化しても、トランジスタ2,2′
より負荷抵抗3へ供給される直流バイアス電流I12,I
22の和が、I12+I22=Iと常に一定になるため、出力
信号eo の直流電位が変化しないという利点がある。図
3のような回路構成手法は公知の技術であり、図2に示
した従来の乗算器の場合にも広く用いられている。図3
の回路において、入力信号ei に対する実際の制御に関
与するのは、トランジスタ1,2,10,13により構
成される第1の乗算器のみである。したがって、出力信
号eoは図3の回路と同様に、
However, in the circuit of FIG. 3, DC bias currents I 1 and I 2 are supplied from the constant current circuit (current mirror circuit 12 ') formed by the transistors 10 and 10' to the differential amplifiers 4 and 4 ', respectively. Is equal to I 1 = I 2 = I, even if the control signal Vc changes, the transistors 2, 2 '
DC bias currents I 12 , I 3 supplied to the load resistor 3 from
Since the sum of 22 is always constant as I 12 + I 22 = I, there is an advantage that the DC potential of the output signal e o does not change. The circuit configuration method as shown in FIG. 3 is a known technique, and is widely used in the case of the conventional multiplier shown in FIG. Figure 3
In the circuit (1), only the first multiplier composed of the transistors 1, 2, 10, 13 is involved in the actual control of the input signal e i . Therefore, the output signal e o is similar to the circuit of FIG.

【0013】[0013]

【数3】 K:ボルツマン定数 T:絶対温度 q:単位電荷量 なる式により求められる。すなわち、図3の回路は、制
御信号Vcに応じて出力信号eoの利得を制御する、利
得制御回路としての機能を持つ。
[Equation 3] K: Boltzmann's constant T: absolute temperature q: unit charge amount That is, the circuit of FIG. 3 has a function as a gain control circuit that controls the gain of the output signal e o according to the control signal Vc.

【0014】[0014]

【発明の効果】本発明によれば、より低電圧の電源にて
動作する信号利得制御回路が実現できとりわけ、電池駆
動を必要とする可搬型の機器を中心とした電子機器の低
消費電力化を図る上での一助となる。
According to the present invention, it is possible to realize a signal gain control circuit which operates with a lower voltage power source, and in particular, to reduce the power consumption of electronic equipment centering on portable equipment which requires battery drive. It will help you in your efforts.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の信号利得制御回路の基本回路。FIG. 1 is a basic circuit of a signal gain control circuit of the present invention.

【図2】従来の信号利得制御回路の基本回路。FIG. 2 is a basic circuit of a conventional signal gain control circuit.

【図3】本発明を適用した信号利得制御回路の一実施
例。
FIG. 3 shows an embodiment of a signal gain control circuit to which the present invention is applied.

【符号の説明】[Explanation of symbols]

4,4′ 差動増幅器 5 定電流回路 6 電圧−電流変換回路 12,12′ カレント・ミラ−回路 15,15′ ベース接地増幅器 4,4 'Differential amplifier 5 Constant current circuit 6 Voltage-current conversion circuit 12, 12' Current mirror circuit 15, 15 'Grounded base amplifier

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 エミッタが共通接続された第1、第2の
トランジスタにより構成される差動増幅器と、該差動増
幅器の共通エミッタに接続され、上記第1、第2のトラ
ンジスタにバイアス電流を流すための定電流回路と、上
記第1、第2のトランジスタのコレクタに接続され、上
記差動増幅器の負荷を構成する負荷回路と、上記第1、
第2のトランジスタのベース間に制御信号を印加する制
御手段と、出力端が上記差動増幅器の共通エミッタに接
続され、入力端に印加される入力信号に応じて上記出力
端における電流を変化させる電圧−電流変換回路とを具
備し、上記入力信号を得て、上記負荷回路より上記制御
信号に応じて電圧利得が変化した出力信号を得ることを
特徴とする信号利得制御回路。
1. A differential amplifier composed of first and second transistors whose emitters are commonly connected, and a bias current which is connected to the common emitter of the differential amplifier and is supplied to the first and second transistors. A constant current circuit for flowing the current, a load circuit connected to the collectors of the first and second transistors and forming a load of the differential amplifier, and the first and second
Control means for applying a control signal between the bases of the second transistors and the output end are connected to the common emitter of the differential amplifier, and the current at the output end is changed according to the input signal applied to the input end. A signal gain control circuit comprising: a voltage-current conversion circuit, wherein the input signal is obtained and an output signal whose voltage gain is changed according to the control signal is obtained from the load circuit.
JP12195293A 1993-04-26 1993-04-26 Signal gain control circuit Pending JPH06310961A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12195293A JPH06310961A (en) 1993-04-26 1993-04-26 Signal gain control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12195293A JPH06310961A (en) 1993-04-26 1993-04-26 Signal gain control circuit

Publications (1)

Publication Number Publication Date
JPH06310961A true JPH06310961A (en) 1994-11-04

Family

ID=14823984

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12195293A Pending JPH06310961A (en) 1993-04-26 1993-04-26 Signal gain control circuit

Country Status (1)

Country Link
JP (1) JPH06310961A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003060456A (en) * 2001-08-16 2003-02-28 Matsushita Electric Ind Co Ltd Variable gain amplifier circuit
JP2012109801A (en) * 2010-11-17 2012-06-07 Sumitomo Electric Ind Ltd Signal amplification circuit, current-voltage conversion circuit and optical receiver
WO2015019525A1 (en) * 2013-08-07 2015-02-12 パナソニック株式会社 Cascode-type transconductance amplifier and variable gain circuit, and tuner system provided with same
JP2015192268A (en) * 2014-03-28 2015-11-02 日本電信電話株式会社 variable gain transimpedance amplifier
JP2015207923A (en) * 2014-04-22 2015-11-19 日本電信電話株式会社 transimpedance amplifier

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003060456A (en) * 2001-08-16 2003-02-28 Matsushita Electric Ind Co Ltd Variable gain amplifier circuit
JP2012109801A (en) * 2010-11-17 2012-06-07 Sumitomo Electric Ind Ltd Signal amplification circuit, current-voltage conversion circuit and optical receiver
WO2015019525A1 (en) * 2013-08-07 2015-02-12 パナソニック株式会社 Cascode-type transconductance amplifier and variable gain circuit, and tuner system provided with same
US9673769B2 (en) 2013-08-07 2017-06-06 Socionext Inc. Variable gain circuit and tuner system provided with same
JP2015192268A (en) * 2014-03-28 2015-11-02 日本電信電話株式会社 variable gain transimpedance amplifier
JP2015207923A (en) * 2014-04-22 2015-11-19 日本電信電話株式会社 transimpedance amplifier

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