WO2015136929A1 - Générateur de signal de fréquence - Google Patents

Générateur de signal de fréquence Download PDF

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Publication number
WO2015136929A1
WO2015136929A1 PCT/JP2015/001337 JP2015001337W WO2015136929A1 WO 2015136929 A1 WO2015136929 A1 WO 2015136929A1 JP 2015001337 W JP2015001337 W JP 2015001337W WO 2015136929 A1 WO2015136929 A1 WO 2015136929A1
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WO
WIPO (PCT)
Prior art keywords
signal
frequency
filter
output
random noise
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PCT/JP2015/001337
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English (en)
Japanese (ja)
Inventor
小林　薫
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日本電波工業株式会社
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Priority to JP2016507361A priority Critical patent/JP6463336B2/ja
Publication of WO2015136929A1 publication Critical patent/WO2015136929A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/02—Digital function generators
    • G06F1/03—Digital function generators working, at least partly, by table look-up
    • G06F1/0321—Waveform generators, i.e. devices for generating periodical functions of time, e.g. direct digital synthesizers
    • G06F1/0328—Waveform generators, i.e. devices for generating periodical functions of time, e.g. direct digital synthesizers in which the phase increment is adjustable, e.g. by using an adder-accumulator
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2211/00—Indexing scheme relating to details of data-processing equipment not covered by groups G06F3/00 - G06F13/00
    • G06F2211/902—Spectral purity improvement for digital function generators by adding a dither signal, e.g. noise

Definitions

  • the present invention relates to the technical field of an apparatus for generating an analog waveform based on waveform data consisting of digital values.
  • a DDS Direct Digital Synthesizer
  • a phase accumulator includes a phase accumulator, a waveform data memory, and a D / A (Digital / Analog) converter, and obtains an analog waveform of an arbitrary frequency.
  • an address is output from the phase accumulator based on the frequency setting data, and the waveform data (amplitude data) in the waveform data memory is read out according to the address and consists of a digital signal (digital value group), for example.
  • a sine wave is obtained and converted to an analog signal.
  • Quantization noise can be cited as the cause, and a periodic error generated from the relationship between the clock frequency and the DDS output frequency is also caused.
  • the time interval of the output timing of the analog signal corresponding to the input of each digital signal and the magnitude of the analog value are not strictly constant, which is also a factor of spurious. .
  • JP-A-8-97744 (paragraphs 0192 to 0195)
  • the present invention has been made under such circumstances, and an object thereof is to reduce spurious in a frequency signal generator that generates an analog waveform based on waveform data composed of digital value groups.
  • the frequency signal generator of the present invention includes a waveform output unit that outputs a periodic waveform signal composed of a digital signal, A noise generator that generates random noise composed of digital signals; A filter that performs processing for biasing the signal level of the frequency spectrum in the random noise to a frequency band that deviates from the frequency of the waveform signal, with respect to the output signal output from the noise generation unit, An adder for adding the output signal of the waveform output unit and the output signal of the filter; And a conversion unit for converting the digital signal obtained by the addition unit into an analog signal.
  • random noise consisting of a digital signal is added to a periodic waveform signal consisting of a digital signal output from the waveform output unit, so that spurious appearing in the analog output is diffused.
  • the random noise is processed by a filter so that the signal level of the frequency spectrum is biased to a frequency band that deviates from the frequency of the waveform signal. Therefore, the level of floor noise in the vicinity of the target output frequency (set frequency) can be suppressed low, and a high spurious suppression effect can be obtained.
  • FIG. 1 is a circuit diagram showing a first embodiment of a frequency signal generator of the present invention. It is a circuit diagram which shows a part of circuit of a random noise production
  • FIG. 1 shows an embodiment in which the frequency signal generator of the present invention is applied to a DDS.
  • Reference numeral 1 is a phase accumulator, and 2 is a waveform data memory.
  • the phase accumulator 1 includes an adder 11 and a latch circuit 12.
  • the adder 11 receives frequency setting data for setting a target frequency for the frequency signal output from the DDS. If the frequency setting data is N, for example, N is output from the latch circuit 12 by the first clock signal, and 2N, 3N, 4N... Are sequentially output from the latch circuit 12 by the subsequent clock signal.
  • the waveform data memory 2 stores, for example, waveform data (a digital value group corresponding to the amplitude value of the waveform) for generating a sine wave, and the waveform data is read using the output signal of the latch circuit 12 as an address. Accordingly, the frequency of the frequency signal specified by the waveform data is determined according to the value of N.
  • the phase accumulator 1 and the waveform data memory 2 correspond to a waveform output unit that outputs a periodic waveform signal.
  • random noise generation unit 3 is a random noise generation unit, which is constituted by, for example, a pseudo random noise generation circuit.
  • random noise includes pseudo-random noise.
  • the pseudo random noise generation circuit include a circuit that outputs a PN (Pseudo Noise) series signal in synchronization with a clock signal input to the DDS, for example, 200 MHz.
  • PN Pulseudo Noise
  • a shift register and Ex-OR exclusive logic
  • a circuit that generates a Gold sequence using an M sequence of a prefeed pair In this example, the logic “0” is converted to “1” and the logic “1” is changed to “ ⁇ 1” with respect to the time series signal including the logic “1” and the logic “0” which are PN sequence signals.
  • the random noise generation unit 3 includes a PN sequence generation circuit and a signal processing circuit provided on the output side of the PN sequence generation circuit.
  • FIG. 2 shows an example of the signal processing circuit.
  • FIG. 2 shows an example of the signal processing circuit described above.
  • the signal processing circuit 31 performs a process of adding a 1-bit logic “1” to the 1-bit input signal and outputs a 2-bit signal represented by 2's complement.
  • the signal processing circuit 32 is composed of a multiplexer, and 2-bit signals “01” and “11” expressed by two's complement numbers are input to one input end and the other input end of the multiplexer, respectively. Yes.
  • the multiplexer receives an input signal “11” at the other input terminal when “0”, which is a 1-bit signal, is input as a selection signal, and inputs one when “1” is input as a selection signal.
  • the input signal “01” at the end is output.
  • a noise processing filter 4 is provided on the output side of the random noise generator 3.
  • the filter 4 is configured to perform processing for biasing the signal level (power intensity) of the frequency spectrum of random noise output from the random noise generating unit 3 to a frequency band that deviates from the set frequency (output frequency) of the DDS. Has been. A specific configuration example of the filter 4 will be described later.
  • reference numeral 5 denotes an adder.
  • the adder 5 is a digital signal (amplitude value data) read from the waveform data memory 2, for example, a 32-bit digital signal, and a 32-bit output from the filter 4.
  • the digital signal (output signal) is added.
  • a D / A converter 6 that converts the added value, which is the output value of the adder 5, into an analog signal is provided.
  • a low-pass filter 7 is provided for removing harmonics contained in the analog waveform signal obtained from the D / A converter 6 to obtain a waveform with less distortion. Yes.
  • a high pass filter 8 is provided on the output side of the low pass filter 7.
  • the high-pass filter 8 is for removing noise existing in a frequency band away from the set frequency based on the filtering process performed by the filter 4.
  • FIG. 4 is obtained from the low-pass filter 7 when random noise is not added to the digital signal read from the waveform data memory 2 (a circuit obtained by removing the random noise generator 3 and the adder 5 from the circuit of FIG. 3).
  • This is the frequency spectrum of the frequency signal (DDS output signal).
  • the clock signal is 200 MHz.
  • the set frequency of the DDS output signal is 42 MHz.
  • FIG. 5 is an enlarged view of the vicinity of the set frequency in the frequency spectrum shown in FIG. In the series of frequency spectrum diagrams including FIG. 4, the signal level corresponding to the set frequency is 0 dB. As can be seen from FIGS. 4 and 5, spurious appears in the vicinity of the set frequency.
  • FIG. 6 is a frequency spectrum of random noise generated by the random noise generator 3.
  • FIG. 7 is a frequency spectrum of a frequency signal (DDS output signal) obtained from the low-pass filter 7 using the circuit of FIG.
  • FIG. 8 is an enlarged view of the vicinity of the set frequency (42 MHz) in the frequency spectrum shown in FIG. As can be seen from FIGS. 7 and 8, the floor noise level is high (floor noise is degraded) and the spurious improvement effect is low when only random noise is used.
  • FIG. 1 a frequency spectrum when the circuit shown in FIG. 1 which is an embodiment of the present invention is used will be described.
  • a circuit in which a random noise generating unit 3, a filter 4, and an adding unit 5 are added to the circuit when the frequency spectrum of FIG. 4 is collected is used.
  • the frequency spectrum of the random noise output from the random noise generator 3 is the same as that shown in FIG.
  • FIG. 9 is a frequency spectrum of random noise output from the filter 4.
  • the filter 4 performs processing for biasing the signal level of the frequency spectrum shown in FIG. 3 to a frequency band lower than 42 MHz.
  • FIG. 10 shows the frequency spectrum of the frequency signal obtained from the low-pass filter 7 of the circuit shown in FIG.
  • FIG. 11 is an enlarged view of the vicinity of the set frequency (42 MHz) in the frequency spectrum shown in FIG.
  • the spurious is improved by about 10 to 15 dB, and the floor noise near the set frequency of DDS is also reduced.
  • the floor noise that is increased in the low frequency band by biasing the frequency spectrum of the random noise by the filter 4 is far away from the set frequency, so that a simple filter such as an LC that combines an inductor and a capacitor is used. It can be removed by a filter or the like.
  • a high-pass filter is provided on the output side of the low-pass filter 7.
  • the filter 4 is configured by connecting 10 stages of moving average circuits in series as shown in FIG.
  • the moving average circuit in each stage is 9-n (n is an integer from 1 to 10), and averages a group of digital values consisting of 8 consecutive digital values as shown in FIG.
  • the first digital value of the digital value group is shifted to the next digital value.
  • a digital value group consisting of eight digital values from d0 to d7 by a certain clock signal. Is averaged for the digital value group from d1 to d8 by the next clock signal, and further averaged for the digital value group from d2 to d9 by the next clock signal.
  • FIG. 13 shows a first-stage moving average circuit, to which a 2-bit digital value output from the random noise generator 3 is input.
  • d0 to d7 indicate digital values output from the random noise generating unit 3 by the clock signal.
  • D is a delay circuit that delays and outputs an input value for each clock signal.
  • the digital signal input to the first-stage delay circuit D includes seven clock signals input to the moving averaging circuit. Sometimes, it is output from the delay circuit D at the final stage.
  • A is an adder circuit.
  • a circuit that multiplies a digital value by 1/8 that is, a rounding processing circuit that performs rounding processing to divide the digital value by “8” is provided after the final stage adder A. Yes.
  • a rounding processing circuit that performs rounding processing to divide the digital value by “8”
  • the moving average circuit as a filter used in the present embodiment is for biasing the signal level of the frequency spectrum of random noise to a low frequency band. The target signal can be obtained without dividing the added value of the obtained eight data by “8”. Then, by dividing the added value of the eight data by “8”, the signal level as noise can be made a necessary level.
  • moving averaging circuit Includes a circuit that does not perform rounding processing, and also includes a circuit that performs rounding processing.
  • rounding processing is not performed (when the added value of 8 data is not divided by “8”), the digital value is increased by 3 bits in the moving averaging circuit. Are input, and a 5-bit digital value is output.
  • the 10-stage moving averaging circuit 9-n shown in FIG. 12 uses the same circuit as that shown in FIG. 13 except for the number of bits of the digital value, and the number of bits of the digital value is 1. Since each stage increases by 3 bits, a 32-bit digital value is output from the 10th stage moving average circuit 9-10. 12 and 13, the numbers in parentheses represent the number of bits.
  • the number of samples subject to moving average in the moving average circuit is not limited to 8, and the number of stages in the moving average circuit is not limited to 10.
  • the filter 4 used when obtaining the frequency spectrum of FIG. 9 is configured by connecting a moving average circuit that does not perform rounding processing in a plurality of stages in series.
  • the number of connection stages of the averaging circuit is different from the examples of FIGS.
  • the frequency spectrum of the noise generated by the random noise generating unit 3 is distributed over a wide band, and therefore noise is generated even in a region where the set frequency of the DDS exists, and the floor noise is deteriorated.
  • the role of the filter 4 is to reduce the energy of noise in a region where the set frequency of the DDS exists and in the vicinity of the frequency spectrum of noise distributed over a wide band. Therefore, the filter 4 may be an FIR (Finite impulse response) filter or an IIR (Infinite Impulse Response) filter.
  • the low-pass filter characteristic is biased toward a lower frequency.
  • the number of data values may be selected.
  • the frequency characteristic may be adjusted by adjusting the weighting coefficient multiplied by each tap (each stage).
  • an address is output from the phase accumulator 1 according to the frequency setting data, and waveform data (waveform data such as sine wave data) is output from the waveform data memory 2 by this address.
  • a digital value group corresponding to the amplitude value) is output.
  • a PN sequence signal that is pseudo-random noise is output from the random noise generation unit 3, and the signal processing unit included in the random noise generation unit 3 converts the logic “0” of the signal into “1”. Logic “1” is converted to “ ⁇ 1”.
  • the filter 4 performs processing for biasing the signal level (power intensity) of the frequency spectrum of random noise to a frequency band that deviates from the set frequency of the DDS, and the processed random noise and the waveform data are added. .
  • the addition value is converted into an analog signal by the D / A converter 6 and the analog signal is passed through the low-pass filter 7 and the high-pass filter 8 to obtain a frequency signal that is an output of the DDS.
  • random noise is added to the digital signal output from the waveform data memory 2.
  • the random noise is processed by the filter 4 so that the signal level of the frequency spectrum is biased to a frequency band that deviates from the set frequency of the DDS. Accordingly, the floor noise level in the vicinity of the set frequency (output frequency) in the DDS can be suppressed to a low level, and a high spurious suppression effect can be obtained.
  • the DDS set frequency in the first embodiment is 42 MHz. Even when the set frequency is set to 21 MHz, for example, if the filter 4 used to obtain the frequency spectrum of FIG. There is concern that the level of floor noise will be high. Therefore, in the second embodiment, a process is performed in which a band that is biased in the frequency spectrum of the noise signal output from the filter 4 is moved to a band that is higher than the set frequency and sufficiently far away.
  • FIG. 14 shows a circuit according to the second embodiment, and a band shift processing unit 40 is provided on the output side of the filter 4.
  • the band shift processing unit 40 includes a multiplexer 402 including one input terminal to which input data is input and the other input terminal to which input data is input through a multiplication unit 401 that multiplies by ⁇ 1. A value input to one input terminal and a value input to the other input terminal are alternately output.
  • FIG. 15 is a time chart of the band shift processing unit 40, where d1, d2,... That are input data (output data of the filter 4) are multiplied by -1, and in other words, every other. The polarity of the digital value is reversed.
  • a frequency signal having “ ⁇ 1” and “1” amplitudes at a frequency 1 ⁇ 2 of the frequency fs of the clock signal is mixed (mixed) with the input data. Since the frequency of the clock signal is, for example, 200 MHz, to put it roughly, a portion biased by the filter 4 in the noise frequency spectrum moves to 100 MHz.
  • FIG. 16 is a frequency spectrum of random noise output from the band shift processing unit 40.
  • the frequency spectrum of the noise output from the filter 4 before being input to the band shift processing unit 40 is the same as that shown in FIG.
  • FIG. 17 shows the frequency spectrum of the frequency signal obtained from the low-pass filter 7 of the circuit shown in FIG.
  • FIG. 18 is an enlarged view of the vicinity of the set frequency (21 MHz) in the frequency spectrum shown in FIG.
  • the band shift processing unit 40 Wiped out.
  • the noise band can be distributed only in a limited region, for example, 10 MHz.
  • the band shift processing unit 40 is used, the configuration of the filter 4 is large. There is an advantage that a simple configuration is sufficient.
  • the part where the frequency spectrum is biased moves to 50 MHz.
  • the frequency signal to be mixed with the output of the filter 4 may be set arbitrarily according to the set frequency of the DDS shown in FIG. 1 by using another DDS for mixing processing.
  • the filter 4 in the frequency spectrum of random noise, energy is biased to a band higher than the set frequency (biased to a lower band in FIG. 9), and energy is biased (energy is other than that).
  • the band shift processing unit 40 may shift the band of the portion that is higher than the band to a lower level.
  • a switching unit 50 is provided, and a mode in which the output of the filter 4 is input to the adding unit 5 through the band shift processing unit 40 and an input to the adding unit 5 without passing through the band shift processing unit 40.
  • the mode to be performed may be selectable. According to such a configuration, spurious can be reduced with respect to a wider setting frequency of DDS.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Manipulation Of Pulses (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

Le problème traité par l'invention consiste à réduire les sorties parasites d'un DDS. La solution de l'invention concerne une unité d'addition (5) permettant d'ajouter un bruit aléatoire à un signal numérique produit en sortie par une mémoire de données de forme d'onde (2). Un circuit de production de données séquentielles PN est utilisé dans une unité de production de bruit aléatoire (3), qui est dotée d'un circuit permettant d'effectuer un traitement de données tel que des valeurs numériques qui constituent le bruit sont définies comme « -1 » et « 1 ». Ce traitement de données évite la production d'un décalage (0,5) dans la valeur de sortie du bruit. Un filtre (4) est composé, par exemple, d'une pluralité de circuits de calcul de moyenne mobile connectés en série, le filtre (4) effectue un traitement pour que le niveau de signal du spectre de fréquence du bruit aléatoire soit décalé vers une bande de fréquence qui dévie de la fréquence de réglage du DDS. Le bruit aléatoire produit en sortie par le filtre (4) est fourni en entrée de l'unité d'addition (5).
PCT/JP2015/001337 2014-03-12 2015-03-11 Générateur de signal de fréquence WO2015136929A1 (fr)

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JP2014-049392 2014-03-12

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04502092A (ja) * 1987-12-14 1992-04-09 クアルコム，インコーポレイテッド 周波数合成雑音に対する疑似ランダム振動
JPH0897744A (ja) * 1994-09-29 1996-04-12 Mitsubishi Electric Corp 通信装置、周波数シンセサイザ、通信方法及びシンセサイズ方法
JP2000252750A (ja) * 1999-03-02 2000-09-14 Matsushita Electric Ind Co Ltd 数値制御発振器

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5667596B2 (ja) * 2012-04-12 2015-02-12 旭化成エレクトロニクス株式会社 ダイレクトデジタルシンセサイザ

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04502092A (ja) * 1987-12-14 1992-04-09 クアルコム，インコーポレイテッド 周波数合成雑音に対する疑似ランダム振動
JPH0897744A (ja) * 1994-09-29 1996-04-12 Mitsubishi Electric Corp 通信装置、周波数シンセサイザ、通信方法及びシンセサイズ方法
JP2000252750A (ja) * 1999-03-02 2000-09-14 Matsushita Electric Ind Co Ltd 数値制御発振器

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JPWO2015136929A1 (ja) 2017-04-06

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