WO2015136769A1 - Circuit d'émission de signal et dispositif de conversion de courant équipé de ce dernier - Google Patents

Circuit d'émission de signal et dispositif de conversion de courant équipé de ce dernier Download PDF

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Publication number
WO2015136769A1
WO2015136769A1 PCT/JP2014/079327 JP2014079327W WO2015136769A1 WO 2015136769 A1 WO2015136769 A1 WO 2015136769A1 JP 2014079327 W JP2014079327 W JP 2014079327W WO 2015136769 A1 WO2015136769 A1 WO 2015136769A1
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WIPO (PCT)
Prior art keywords
signal
circuit
output
input
coil
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PCT/JP2014/079327
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English (en)
Japanese (ja)
Inventor
健一 諸熊
淳 冨澤
内田　哲也
西川　和康
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三菱電機株式会社
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Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to JP2016507265A priority Critical patent/JP6009719B2/ja
Publication of WO2015136769A1 publication Critical patent/WO2015136769A1/fr

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/04—Shaping pulses by increasing duration; by decreasing duration
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode

Definitions

  • the signal generation circuit 210 includes a rising edge detection circuit 230 as a first edge detection circuit, a falling edge detection circuit 240 as a second edge detection circuit, a first mask circuit 250, and a second mask circuit 260. .
  • the rising edge detection circuit 230 detects a change in the rising edge of the output signal VO of the comparator 220, and outputs a reference set signal VS1 having a pulse width of a predetermined period ⁇ 3.
  • the falling edge detection circuit 240 detects a change in the falling edge of the output signal VO of the comparator 220 and outputs a reference reset signal VR1 having a pulse width of a predetermined period ⁇ 3.
  • the AND circuit 127c outputs a signal DOUT1 that is an output of the rising edge detection circuit 127. As shown in FIG. 7, the rising edge detection circuit 127 outputs a signal DOUT1 having a width of a predetermined period ⁇ when the input signal DIN1 changes from low to high.
  • the pulse (signal VR) having a width of the predetermined period ⁇ 1 generated at time t4 is turned off, and the pulse having the width of the predetermined period ⁇ 2 (signal VS) is continuously generated.
  • a current change occurs in the first coil 11 and is induced by the current change, and is opposite to the induced voltage signal at the time t4 at the first and second ends of the second coil 12.
  • Directional bipolar induced voltage signals VRX + and VRX ⁇ are output.
  • the bipolar induced voltage signals VRX + and VRX ⁇ are input to the comparator 220, and the output signal VO of the comparator 220 changes from low to high.
  • the signals VRX + and VRX ⁇ output to the first end and the second end of the second coil 12 are input to the comparator 220.
  • the signals VRX + and VRX ⁇ Assume that in-phase noise 5 exceeding the operation region A occurs. For this reason, the comparator 220 does not operate, and the output signal VO of the comparator 220 continues to be in the low state.
  • the reference set signal VS1 from the rising edge detection circuit 230 at the subsequent stage of the comparator 220 is also in the low state, and the SR latch circuit 270 does not operate and the output signal OUT is maintained in the low state.
  • the pulse (signal VS) having a width of the predetermined period ⁇ 1 generated at time t1 is turned off, and the pulse (signal VR) having the width of the predetermined period ⁇ 2 is continuously generated.
  • the signal VR changes from low to high, a current change occurs in the first coil 11, which is induced by the current change, and is opposite to the induced voltage signal at the time t1 at the first and second ends of the second coil 12.
  • Directional bipolar induced voltage signals VRX + and VRX ⁇ are output. Bipolar induced voltage signals VRX + and VRX ⁇ are input to the comparator 220.
  • the two signals VRX + and VRX ⁇ are processed by only one comparator 220 and converted into a binary signal VO. Therefore, the circuit configuration of the signal transmission circuit 1000 can be simplified, and the circuit area can be reduced and the cost can be reduced. Further, the comparator 220 does not have a problem that the reference voltage is affected by noise and causes a malfunction, and noise tolerance is improved and the reliability of signal transmission is further improved.
  • FIG. 13 is a diagram showing a circuit configuration of a signal transmission circuit 2000 according to the second embodiment of the present invention, and its operation waveform is shown in FIG.
  • the first circuit 100a includes a second pulse conversion circuit 140, and the configuration of the second pulse conversion circuit 140 is shown in FIG.
  • the operation waveform of the second pulse conversion circuit 140 is shown in FIG.
  • Other configurations are the same as those of the first embodiment.
  • the configuration of the second pulse conversion circuit 140 shown in FIG. 15 is an example and is not limited.
  • the falling edge detection circuit 142g outputs a pulse (signal VH) having a width of a predetermined period ⁇ 2a.
  • the signals VA, VD, VE, and VH are input to the OR circuit 143, and the OR circuit 143 outputs the signal VS that is the output of the second pulse conversion circuit 140.
  • the signals VB, VC, VF, and VG are input to the OR circuit 144, and the OR circuit 144 outputs the signal VR that is the output of the second pulse conversion circuit 140.
  • the second pulse conversion circuit 140 turns off the pulse (signal VS) having a width of the predetermined period ⁇ 1a generated at time t3, and continuously applies pulses (signal VR) having the width of the predetermined period ⁇ 2a. Output to the second end of one coil 11.
  • the signal VR changes from low to high, a current change occurs in the first coil 11, which is induced by the current change, and is opposite to the induced voltage signal at time t3 at the first and second ends of the second coil 12.
  • Directional bipolar induced voltage signals VRX + and VRX ⁇ are output.
  • the bipolar induced voltage signals VRX + and VRX ⁇ are input to the comparator 220, and the output signal VO of the comparator 220 changes from high to low.
  • the second pulse conversion circuit 140 includes a transmission circuit 140b and two OR circuits 143 and 144.
  • the transmission circuit 140b includes four delay circuits 145 to 148, eight NOT circuits 149a to 149d and 150a to 150d, and eight AND circuits 151a to 151d and 152a to 152d.
  • the input signal IN input to the transmission circuit 140b is input to the delay circuit 145, the first end of the AND circuit 151a, and the second end of the AND circuit 152b via the NOT circuit 150b.
  • the signal generation circuit 280 includes a delay circuit 281, a third mask circuit 250 a, and a fourth mask circuit 260 a.
  • the delay circuit 281 outputs a signal Vd1 obtained by delaying the output signal VO of the comparator 220 by a predetermined period ⁇ 5.
  • the third mask circuit 250a includes a NOT circuit 283 and an AND circuit 284.
  • the output signal VO of the comparator 220 is input to the first terminal of the AND circuit 284 as the reference set signal VS1, and the output signal Vd1 of the delay circuit 281 is input to the second terminal of the AND circuit 284 via the NOT circuit 283.
  • the output of the AND circuit 284 is input to the set terminal S of the SR latch circuit 270a as the set signal VS2.
  • the third mask circuit 250a partially masks the reference set signal VS1, which is the output signal VO of the comparator 220, using the inverted signal of the output signal Vd1 of the delay circuit 281 as a mask signal. Then, only the set signal VS2 necessary for demodulating the signal corresponding to the input signal IN by the SR latch circuit 270a is output.
  • the output signal Vd1 of the delay circuit 281 in the signal generation circuit 280 continues in the low state, and the output of the AND circuit 285 (reset signal VR2) continues in the low state.
  • the inverted signal (not shown) of the output signal Vd1 is in a high state, but when the signal VO (reference set signal VS1) changes from high to low, the output of the AND circuit 284 (set signal VS2) changes from high to low.
  • the reset signal VR2 continues to be in the low state, the output signal VQ of the SR latch circuit 270a continues to be in the high state and is output as the output signal OUT of the signal transmission circuit 3000.
  • the pulse (signal VR) having a width of the predetermined period ⁇ 1 generated at time t7 is turned off, and the pulse having the width of the predetermined period ⁇ 2 (signal VS) is continuously generated.
  • a current change occurs in the first coil 11 and is induced by the current change, and is opposite to the induced voltage signal at the time t7 at the first end and the second end of the second coil 12.
  • Directional bipolar induced voltage signals VRX + and VRX ⁇ are output.
  • the bipolar induced voltage signals VRX + and VRX ⁇ are input to the comparator 220, and the output signal VO of the comparator 220 changes from low to high.
  • the output signal VO of the comparator 220 is input to the signal generation circuit 280.
  • the output signal Vd1 of the delay circuit 281 that is, the signal Vd1 obtained by delaying the output signal VO of the comparator 220 by a predetermined period ⁇ 5 changes from high to low.
  • the first pulse conversion circuit 120 of the first circuit 100 since the first pulse conversion circuit 120 of the first circuit 100 does not operate, no current change occurs in the first coil 11 and no induced voltage signal is generated in the second coil 12.
  • the output signal VO of the comparator 220 continues to be in the low state and is input to the signal generation circuit 280.
  • the output signal Vd1 of the delay circuit 281 changes from low to high.
  • the first pulse conversion circuit 120 of the first circuit 100 does not operate, no current change occurs in the first coil 11 and no induced voltage signal is generated in the second coil 12.
  • the output signal VO of the comparator 220 continues to be in the low state and is input to the signal generation circuit 280.
  • the output signal Vd1 of the delay circuit 281 changes from low to high, and the reference reset signal VR1 that is the inverted signal of the output signal VO of the comparator 220 continues to be in the high state.
  • the reset signal VR2) goes from low to high.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Inverter Devices (AREA)
  • Power Conversion In General (AREA)

Abstract

Dans un circuit d'émission de signal (1000) pour émettre un signal par l'intermédiaire d'un transformateur d'isolation (10), un premier circuit (100) relié à une bobine primaire (11) du transformateur d'isolation (10) émet une pluralité d'impulsions générées en continu de manière alternée aux première et seconde extrémités de la bobine primaire (11) par changement de la valeur logique d'un signal d'entrée (ENTRÉE). Un second circuit (200) relié à une bobine secondaire (12) comprend : un comparateur (220) ayant deux bornes d'entrée connectées aux première et seconde extrémités de la bobine secondaire (12) ; un circuit de verrou SR (270) pour délivrer un signal de sortie (SORTIE) ; et un circuit de génération de signal (210) pour générer un signal d'initialisation et un signal de réinitialisation, qui sont entrés dans le circuit de verrou SR (270), par masquage partiel de signaux d'initialisation et de réinitialisation de référence respectifs sur la base du signal de sortie du comparateur (220).
PCT/JP2014/079327 2014-03-13 2014-11-05 Circuit d'émission de signal et dispositif de conversion de courant équipé de ce dernier WO2015136769A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2016507265A JP6009719B2 (ja) 2014-03-13 2014-11-05 信号伝達回路およびそれを備えた電力変換装置

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2014050018 2014-03-13
JP2014-050018 2014-03-13

Publications (1)

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WO2015136769A1 true WO2015136769A1 (fr) 2015-09-17

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012124830A (ja) * 2010-12-10 2012-06-28 Toyota Motor Corp ゲート駆動回路
JP2012125100A (ja) * 2010-12-10 2012-06-28 Toyota Motor Corp ゲート駆動回路
WO2012157180A1 (fr) * 2011-05-18 2012-11-22 ルネサスエレクトロニクス株式会社 Circuit de réception de signal et procédé de réception de signal
JP2013051547A (ja) * 2011-08-31 2013-03-14 Renesas Electronics Corp 半導体集積回路及びそれを備えた駆動装置
JP2014003515A (ja) * 2012-06-20 2014-01-09 Rohm Co Ltd 信号伝達回路、集積回路およびそれを含む電気機器

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10205705C1 (de) * 2002-02-12 2003-05-08 Infineon Technologies Ag Integrierbare Schaltungsanordnung zur potenzialfreien Signalübertragung
JP2009060272A (ja) * 2007-08-30 2009-03-19 Toyota Industries Corp 信号伝達回路
JP4656263B1 (ja) * 2010-02-01 2011-03-23 トヨタ自動車株式会社 信号伝達装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012124830A (ja) * 2010-12-10 2012-06-28 Toyota Motor Corp ゲート駆動回路
JP2012125100A (ja) * 2010-12-10 2012-06-28 Toyota Motor Corp ゲート駆動回路
WO2012157180A1 (fr) * 2011-05-18 2012-11-22 ルネサスエレクトロニクス株式会社 Circuit de réception de signal et procédé de réception de signal
JP2013051547A (ja) * 2011-08-31 2013-03-14 Renesas Electronics Corp 半導体集積回路及びそれを備えた駆動装置
JP2014003515A (ja) * 2012-06-20 2014-01-09 Rohm Co Ltd 信号伝達回路、集積回路およびそれを含む電気機器

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JP6009719B2 (ja) 2016-10-19

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