WO2015128920A1 - El表示装置の製造方法 - Google Patents
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- WO2015128920A1 WO2015128920A1 PCT/JP2014/006425 JP2014006425W WO2015128920A1 WO 2015128920 A1 WO2015128920 A1 WO 2015128920A1 JP 2014006425 W JP2014006425 W JP 2014006425W WO 2015128920 A1 WO2015128920 A1 WO 2015128920A1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/44—Testing lamps
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
- G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
- G09G3/3241—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element the current through the light-emitting element being set using a data current provided by the data driver, e.g. by using a two-transistor current mirror
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
- G09G2300/0809—Several active elements per pixel in active matrix panels
- G09G2300/0814—Several active elements per pixel in active matrix panels used for selection purposes, e.g. logical AND for partial update
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
- G09G2300/0809—Several active elements per pixel in active matrix panels
- G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
- G09G2300/0809—Several active elements per pixel in active matrix panels
- G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
- G09G2300/0809—Several active elements per pixel in active matrix panels
- G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
- G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
- G09G2300/0866—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes by means of changes in the pixel supply voltage
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/04—Maintaining the quality of display appearance
- G09G2320/043—Preventing or counteracting the effects of ageing
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/08—Fault-tolerant or redundant circuits, or circuits in which repair of defects is prepared
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/12—Test circuits or failure detection circuits included in a display system, as permanent part thereof
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2340/00—Aspects of display data processing
- G09G2340/06—Colour space transformation
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/1201—Manufacture or treatment
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
- H10K71/861—Repairing
Definitions
- the present disclosure relates to a method for manufacturing an EL display device.
- AM active matrix
- a plurality of transistors are formed in a pixel, and an organic EL light emitting layer is formed on the transistor.
- the EL display panel emits light by supplying current from the transistor to the organic EL light emitting layer.
- the defect may be defective in an EL element such as an organic EL light emitting layer or a pixel circuit such as a TFT.
- the pixel is repaired in the defect repair process.
- the present disclosure provides an EL display device manufacturing method capable of determining whether or not a defective pixel can be repaired and a repair location.
- a method for manufacturing an EL display device is a method for manufacturing an EL display device having a display screen in which a plurality of pixels are arranged in a matrix, and each of the plurality of pixels includes an EL element and a display screen.
- the transistor includes a gate terminal connected to a gate signal line, a third terminal connected to the second terminal, and a fourth terminal to which a second voltage having a potential higher than the first voltage is applied.
- a lighting inspection is performed to inspect whether the panel is normally lit.
- the present invention it is possible to determine whether the defect of the EL display panel is due to the defect of the organic EL light emitting layer or the defect of the TFT in the lighting inspection, and it is possible to determine the repair location of the defect and whether repair is possible. Become. Therefore, since defect repair can be carried out accurately, the yield of panel manufacturing can be improved and the manufacturing cost can be suppressed.
- FIG. 1 is an external view of an EL display display according to an embodiment.
- FIG. 2 is a configuration diagram of the EL display device according to the embodiment.
- FIG. 3 is a diagram illustrating an example of a pixel circuit in the EL display device according to the embodiment.
- FIG. 4 is a circuit diagram illustrating a non-light emission period of the pixel circuit according to the embodiment.
- FIG. 5 is a circuit diagram illustrating an offset cancellation correction preparation period of the pixel circuit according to the embodiment.
- FIG. 6 is a circuit diagram illustrating an offset cancellation correction period of the pixel circuit according to the embodiment.
- FIG. 7 is a circuit diagram illustrating a writing period of the pixel circuit according to the embodiment.
- FIG. 8 is a circuit diagram illustrating a light emission period of the pixel circuit according to the embodiment.
- FIG. 9 is a diagram for explaining a method of manufacturing the EL display device according to the embodiment.
- FIG. 10 is a diagram for explaining a defect determination method of the EL display device according to the embodiment.
- FIG. 11 is a diagram for explaining an inspection (manufacturing) method for another pixel circuit according to the embodiment.
- FIG. 12 is a diagram illustrating a structure of a light emitting element of an EL display device.
- FIG. 1 is an external view showing an example of the external appearance of the organic EL display in the present embodiment.
- the organic EL display in the present embodiment includes an EL display panel 21 having a display screen 20.
- EL elements composed of three primary colors of red (R), green (G), and blue (B) are formed in a matrix.
- a color filter composed of red (R), green (G), and blue (B) can be formed.
- the color filter is not limited to RGB, and pixels of cyan (C), magenta (M), and yellow (Y) may be formed.
- white (W) pixels may be formed. That is, R, G, B, and W pixels are arranged in a matrix on the display screen.
- the pixel aperture ratios of R, G, and B may be different. By making the aperture ratios different, the current densities flowing in the EL elements 15 for each RGB can be made different. By making the current densities different, the degradation rates of the RGB EL elements 15 can be made the same. If the deterioration rates are the same, the white balance deviation of the EL display panel 21 does not occur.
- the pixel is composed of R, G, B, and W.
- R, G, B, and W high luminance can be achieved.
- configurations of R, G, B, and G are also exemplified.
- the colorization of the EL display panel 21 is performed by mask vapor deposition, but the embodiment of the present invention is not limited to this.
- a blue light emitting EL layer may be formed, and the emitted blue light may be converted into R, G, B light by an R, G, B color conversion layer (CCM: Color Change Mediums).
- a circularly polarizing plate (circularly polarizing film) (not shown) can be disposed on the light exit surface of the EL display panel 21. What integrated the polarizing plate and the phase film is called a circularly polarizing plate (circularly polarizing film).
- FIG. 12 is a cross-sectional view schematically showing an example of the structure of the light emitting pixel.
- the light emitting pixel 215 described in FIG. 12 includes a substrate 202, a drive circuit layer 301, a light emitting layer 302, and a transparent sealing film 310.
- the EL display panel 21 is an EL display device having a display screen 20 in which the light emitting pixels 215 are arranged in a matrix.
- the substrate 202 is a plate-like member on which a plurality of light emitting pixels 215 are arranged in a matrix, for example, a glass substrate.
- the substrate 202 may be a flexible substrate made of a resin.
- a driving circuit layer 301 including a thin film transistor (TFT) is formed on the surface of the substrate 202.
- TFT thin film transistor
- a non-transparent substrate such as a silicon substrate can also be used.
- the drive circuit layer 301 includes a drive transistor (transistor 11a in FIG. 3), a capacitor (capacitor 19a in FIG. 3), and a selection transistor (transistor 11b in FIG. 3) formed on the substrate 202. .
- the drive circuit layer 301 has a flat surface to ensure flatness.
- the light emitting layer 302 is a layer constituting the EL element 15 shown in FIG. 3 to be described later, and includes an anode 361, a hole injection layer 362, a hole transport layer 363, an organic light emitting layer 364, a bank layer 365, An electron injection layer 366 and a transparent cathode 367 are provided.
- the light emitting pixel 215 shown in FIG. 12 has a top emission structure.
- a voltage is applied to the light emitting layer 302
- light is generated in the organic light emitting layer 364, and light is emitted upward through the transparent cathode 367 and the transparent sealing film 310.
- light emitted downward from the organic light emitting layer 364 is reflected by the anode 361, and light is emitted upward through the transparent cathode 367 and the transparent sealing film 310.
- the anode 361 is an electrode that is laminated on the surface of the planarization film of the drive circuit layer 301 and applies a positive voltage to the light emitting layer 302 with respect to the transparent cathode 367.
- the anode material constituting the anode 361 for example, Al, Ag, or an alloy thereof, which is a highly reflective metal, is preferable.
- the thickness of the anode 361 is, for example, 100 to 300 nm.
- the hole injection layer 362 is formed on the surface of the anode 361 and has a function of injecting holes into the organic light emitting layer 364 stably or by assisting the generation of holes. As a result, the driving voltage of the light emitting layer 302 is lowered, and the lifetime of the element is extended by stabilizing the hole injection.
- a material of the hole injection layer 362 for example, PEDOT (polyethylenedioxythiophene) can be used.
- the film thickness of the hole injection layer 362 is, for example, about 10 nm to 100 nm.
- the hole transport layer 363 is formed on the surface of the hole injection layer 362, and efficiently transports holes injected from the hole injection layer 362 into the organic light emitting layer 364. It has a function of preventing deactivation of excitons at the interface with the layer 362 and further blocking electrons.
- the hole transport layer 363 is, for example, an organic polymer material having a property of transmitting generated holes by a charge transfer reaction between molecules, and examples thereof include triferamine and polyaniline.
- the thickness of the hole transport layer 363 is, for example, about 5 to 50 nm.
- hole transport layer 363 may be omitted depending on the material of the hole injection layer 362 and the organic light emitting layer 364 which are adjacent layers.
- the organic light emitting layer 364 is formed on the surface of the hole transport layer 363 and has a function of emitting light by generating an excited state when holes and electrons are injected and recombined.
- the organic light emitting layer 364 not only a low molecular organic material but also a light emitting polymer organic material that can be formed by a wet film forming method such as ink jet or spin coating is used.
- the polymer organic material include a simple device structure, excellent film reliability, and a low-voltage driven device.
- a polymer having a conjugated system such as an aromatic ring or a condensed ring or a ⁇ -conjugated polymer has fluorescence
- it can be used as a polymer organic material constituting the organic light emitting layer 364.
- the polymer light emitting material constituting the organic light emitting layer 364 include polyphenylene vinylene (PPV) or a derivative thereof (PPV derivative), polyfluorene (PFO) or a derivative thereof (PFO derivative), a polyspirofluorene derivative, and the like. Can do. It is also possible to use polythiophene or a derivative thereof.
- the bank layer 365 is formed on the surface of the drive circuit layer 301 or the anode 361, and functions as a bank for forming the hole transport layer 363 and the organic light emitting layer 364 formed by a wet film forming method in a predetermined region.
- the material used for the bank layer 365 may be either an inorganic substance or an organic substance, but the organic substance is generally more preferable because it has a higher water repellency. Examples of such materials include resins such as polyimide and polyacryl.
- the thickness of the bank layer 365 is, for example, about 100 to 3000 nm.
- the electron injection layer 366 is formed on the organic light emitting layer 364, reduces the barrier for electron injection into the organic light emitting layer 364, lowers the driving voltage of the light emitting layer 302, and suppresses exciton deactivation. Have As a result, it is possible to stabilize the electron injection and prolong the life of the device, enhance the adhesion with the transparent cathode 367, improve the uniformity of the light emitting surface, and reduce device defects.
- the electron injection layer 366 is not particularly limited, but is preferably made of barium, aluminum, phthalocyanine, lithium fluoride, and a barium-aluminum laminate. The thickness of the electron injection layer 366 is, for example, about 2 to 50 nm.
- the transparent cathode 367 is laminated on the surface of the electron injection layer 366, and has a function of applying a negative voltage to the light emitting layer 302 with respect to the anode 361 to inject electrons into the device (particularly the organic light emitting layer 364).
- the transparent cathode 367 is not particularly limited, but it is preferable to use a substance and structure having a high transmittance. Thereby, a top emission organic EL element with high luminous efficiency can be realized.
- the configuration of the transparent cathode 367 is not particularly limited, but a metal oxide layer is used.
- the metal oxide layer is not particularly limited, and a layer made of indium tin oxide (hereinafter referred to as ITO) or indium zinc oxide (hereinafter referred to as IZO) is used.
- ITO indium tin oxide
- IZO indium zinc oxide
- the thickness of the transparent cathode 367 is, for example, about 5 to 200 nm.
- the transparent sealing film 310 is formed on the surface of the transparent cathode 367 and has a function of protecting the element from moisture. Further, the transparent sealing film 310 is required to be transparent.
- the transparent sealing film 310 is made of, for example, SiN, SiON, or an organic film. Further, the thickness of the transparent sealing film 310 is, for example, about 20 to 5000 nm.
- the EL display panel 21 has a function as an active matrix EL display device.
- the circuit configuration of the light-emitting pixel described above is not limited to the circuit configuration illustrated in FIG.
- the transistor 11b and the transistor 11a are circuit components necessary for flowing a driving current corresponding to the signal voltage to the EL element 15, but are not limited to the above-described embodiments. Further, a case where another circuit component is added to the circuit components described above is also included in the light emitting pixel circuit of the organic EL display device according to the present disclosure.
- FIG. 2 is a block diagram showing an electrical configuration of the EL display device according to the embodiment.
- the EL display device according to the present embodiment includes a display screen 20 in which pixels 16 are arranged in a matrix, and gate signal lines arranged for each pixel row of the display screen 20. 17a, 17b, 17c and 17d, source signal lines 18 arranged for each pixel column of the display screen 20, and gate drivers for driving gate signal lines 17a, 17b, 17c and 17d, which are peripheral circuits of the display screen 20.
- gate driver ICs gate driver ICs 12a and 12b
- source driver IC source driver circuit
- the display screen 20 displays an image based on a video signal input from the outside to the image display device.
- the gate signal lines 17a, 17b, 17c and 17d are connected to at least one of the gate driver circuits 12a and 12b, and are connected to the pixels 16 belonging to each pixel row.
- the gate signal lines 17a, 17b, 17c and 17d control the function of controlling the timing of writing the signal voltage to the pixels 16 belonging to each pixel row and the timing of applying various voltages such as the initialization voltage and the reference voltage to the pixels 16. It has a function to do.
- the gate driver circuits 12a and 12b are connected to at least one of the gate signal lines 17a, 17b, 17c and 17d. By outputting a selection signal to the gate signal lines 17a, 17b, 17c and 17d, the gate driver circuits 12a and 12b A driver circuit having a function of controlling conduction (on) and non-conduction (off) of a transistor including the transistor.
- the gate driver circuits 12a and 12b are arranged on the left and right of the display screen 20, respectively.
- gate driver circuits 12a and 12b arranged on the left and right of the display screen 20 are connected to both ends of the gate signal lines 17a and 17b.
- a gate driver circuit 12a disposed on the left side of the display screen 20 is connected to one side of the gate signal lines 17c and 17d.
- the gate driver circuits 12a and 12b are mounted on a COF (Chip On Film) (not shown).
- the gate signal line 17a (gate signal line GS) is preferably connected to both gate driver circuits 12a and 12b.
- the source signal line 18 is provided for each pixel column of the display screen 20, that is, the number of pixel columns, is connected to the source driver circuit 14, and is connected to the pixel 16 belonging to each pixel column.
- the source driver circuit 14 is connected to one end of the source signal line 18 and is a drive circuit having a function of outputting a video signal and supplying or applying the video signal to the pixel 16 via the source signal line 18.
- the source driver circuit 14 is mounted on a COF (Chip On Film) (not shown).
- the control circuit not shown is a control circuit having a function of controlling the gate driver circuits 12a and 12b and the source driver circuit 14.
- the control circuit includes a memory (not shown) in which correction data of each EL element 15 is stored, reads the correction data written in the memory, and uses an externally input video signal based on the correction data. It is also possible to correct the output and output to the source driver circuit 14.
- a plurality of types of on-voltage (Von) may be required, and a plurality of voltages may be required for the off-voltage (Voff).
- an initial voltage (Vini), a reference voltage (Vref), and the like are required depending on the configuration of the pixel circuit.
- FIG. 3 is a diagram illustrating an example of a pixel circuit in the EL display device according to the embodiment.
- the pixels 16 are arranged in a matrix on the display screen 20.
- the pixel circuit shown in FIG. 3 includes an EL element 15, a transistor 11a for supplying a driving current to the EL element 15, a transistor 11d, a transistor 11b, a transistor 11c, a transistor 11e, and a capacitor 19a.
- pixels having EL elements 15 are arranged in a matrix.
- the transistor 11a has a drain terminal electrically connected to the anode voltage Vdd as the first power supply line via the first switching transistor 11d, and a source terminal electrically connected to the anode terminal of the EL element 15. Transistor.
- the transistor 11a converts a voltage corresponding to the signal voltage applied between the gate terminal and the source terminal into a drain current corresponding to the signal voltage. Then, this drain current is supplied to the EL element 15 as a signal current.
- the transistor 11a is composed of, for example, an n-type thin film transistor (n-type TFT).
- the EL element 15 is a light emitting element in which an anode terminal as a second terminal is electrically connected to a source terminal of the transistor 11a and a cathode terminal as a first terminal is electrically connected to a second power supply line.
- the voltage of the second power supply line is the cathode voltage Vss that is the first voltage.
- the EL element 15 emits light based on the magnitude of the signal current when the signal current flows through the transistor 11a. The magnitude of the signal current is determined by applying the video signal applied to the source signal line 18 to the pixel 16 by the transistor 11b.
- the transistor 11d has a gate terminal electrically connected to the gate signal line 17b, a source terminal electrically connected to the drain terminal of the transistor 11a, and a drain terminal electrically connected to the anode voltage Vdd which is the first power supply line. This is the first switching transistor.
- the transistor 11d When the on voltage is applied to the gate signal line 17b, the transistor 11d is turned on, and the light emission drive current from the transistor 11a is supplied to the EL element 15.
- the transistor 11d may be disposed or formed between the source terminal of the transistor 11a and the anode terminal of the EL element 15.
- the transistor 11b has a gate terminal electrically connected to the gate signal line 17a, a source terminal electrically connected to the gate terminal of the transistor 11a, and a drain terminal electrically connected to the source signal line 18. This is a switch transistor.
- the transistor 11c has a gate terminal electrically connected to the gate signal line 17d, a source terminal which is a third terminal electrically connected to the anode terminal (second terminal) of the EL element 15 and the source terminal of the transistor 11a.
- the drain terminal which is the fourth terminal, is a third switching transistor to which an initial voltage (initializing voltage, Vini), which is the second voltage, is applied or supplied.
- the transistor 11c has a function of determining the timing of applying the initial voltage (Vini) to the source terminal of the transistor 11a and one electrode of the capacitor 19a.
- the transistor 11e has a gate terminal electrically connected to the gate signal line 17c, a source terminal electrically connected to the gate terminal of the transistor 11a, and a drain terminal to which a reference voltage (reference voltage, Vref) is applied or supplied.
- Vref reference voltage
- electrically connected means a state in which a voltage path and a current path are formed or a state in which a path can be formed.
- connection may be used as an electrical connection meaning.
- the source terminal and the drain terminal may be a first terminal, a second terminal, or the like.
- the transistors including the driving transistor 11a and the switching transistors 11b to 11e have been described as thin film transistors (TFTs), but are not limited thereto.
- the transistor may be a FET, a MOS-FET, a MOS transistor, or a bipolar transistor.
- the transistor is not limited to a thin film element, and may be a transistor formed on a silicon wafer.
- a transistor formed of a silicon wafer, peeled off and transferred to a glass substrate is exemplified.
- a display panel in which a transistor chip is formed using a silicon wafer and a glass substrate is mounted by bonding is exemplified.
- the transistors 11a to 11e adopt an LDD (Lightly Doped Drain) structure regardless of whether they are n-type or p-type transistors.
- the transistors 11a to 11e include high-temperature polysilicon (HTPS), low-temperature polysilicon (LTPS), continuous grain boundary silicon (CGS: Continous amorphous silicon, CGS). Any one of semiconductors (TAOS: Transient Amorphous Oxide Semiconductors, IZO), amorphous silicon (AS: Amorphous Silicon), and infrared RTA (RTA: Rapid Thermal Annealing) may be used.
- HTPS high-temperature polysilicon
- LTPS low-temperature polysilicon
- CGS continuous grain boundary silicon
- TAOS Transient Amorphous Oxide Semiconductors
- AS Amorphous Silicon
- RTA Rapid Thermal Annealing
- all the transistors constituting the pixel are n-type.
- the present invention is not limited to the n-type pixel transistors. You may comprise only n type and may comprise only p type. Moreover, you may comprise using both n-type and p-type.
- the transistor 11a may be configured using both a p-type transistor and an n-type transistor.
- the transistor preferably has a top gate structure.
- the parasitic capacitance is reduced, and the gate electrode pattern of the top gate becomes a light shielding layer, and the light emitted from the EL element 15 is blocked by the light shielding layer, so that malfunction of the transistor and off-leakage current can be reduced. It is.
- the transistor has a top gate structure and a small parasitic capacitance, so that n-type and p-type transistors can be manufactured, and a copper wiring or copper alloy wiring process can be used for the process.
- the copper wiring preferably employs a three-layer structure of Ti—Cu—Ti.
- the wiring such as the gate signal lines 17a to 17d or the source signal line 18 preferably adopts a three-layer structure of Mo—Cu—Mo when the transistors 11a to 11e are transparent amorphous oxide semiconductor TAOS.
- the capacitor 19a is a capacitor whose first electrode is electrically connected to the gate terminal of the transistor 11a and whose second electrode is electrically connected to the source terminal of the transistor 11a.
- the capacitor 19a first stores the gate-source electrode potential of the transistor 11a (the potential of the source signal line 18) in a steady state in a state where the transistor 11b is conductive. Thereafter, even when the transistor 11b is turned off, the potential of the capacitor 19a is determined, so that the gate voltage of the transistor 11a is determined.
- the capacitor 19a is formed or arranged so as to overlap (overlap) the source signal line 18 and the gate signal lines 17a to 17d. In this case, the degree of freedom in layout is improved, a wider space between elements can be secured, and the yield is improved.
- the pixel electrode (for example, the anode 361 shown in FIG. 12) is formed on an insulating film (planarization film) made of an acrylic film or an insulating film formed on the source signal line 18 and the gate signal lines 17a to 17d.
- insulating film planarization film
- the anode voltage Vdd, the cathode voltage Vss, the reference voltage (Vref), and the initialization voltage (Vini) are connected to all the pixels 16 in common. And is connected to a voltage generation circuit (not shown).
- Vini When the voltage obtained by adding the light emission start voltage of the EL element 15 to the threshold voltage of the transistor 11a is larger than 0V, Vini may be substantially the same voltage as the cathode voltage Vss. As a result, the types of output voltages of the voltage generation circuit (not shown) are reduced, and the circuit becomes simpler.
- anode voltage Vdd 10 to 18 (V)
- reference voltage Vref 1.5 to 3 (V)
- cathode voltage Vss 0.5 to 2.5 (V)
- initial voltage Vini 0 to -3 (V).
- the gate signal line 17a and the gate signal line 17b are preferably connected to the two gate driver circuits 12a and 12b. This is due to the following reason.
- the gate signal line 17a is connected to the transistor 11b. This is because the transistor 11b is a transistor for writing a video signal to the pixel 16, and the transistor 11b needs to be turned on / off at high speed (high slew rate operation).
- the gate signal line 17a can be driven by the two gate driver circuits 12a and 12b, thereby realizing a high slew rate operation.
- the gate driver circuit 12a is disposed on the left side of the display screen 20, and the gate driver circuit 12b is disposed on the right side of the display screen 20.
- the gate signal line 17b is connected to the transistor 11d. This is because the transistor 11d is a transistor that performs the offset cancel operation of the transistor 11a, and it is necessary to turn on and off the transistor 11d at high speed (high slew rate operation).
- the gate signal lines 17a and 17b can be driven by two gate driver circuits 12a and 12b (both sides drive), thereby realizing a high slew rate operation. Therefore, even in the defect inspection, the pixel defect position can be detected well without depending on the screen position of the pixel to be inspected. In addition, high-speed defect inspection can be realized.
- One gate driver circuit 12a is connected to the gate signal lines 17c and 17d.
- the transistor 11e is connected to the gate signal line 17c.
- the transistor 11e has a function of applying the reference voltage Vref to the transistor 11a.
- the transistor 11c is connected to the gate signal line 17d.
- the transistor 11c has a function of applying the initial voltage Vini to the source terminal of the transistor 11a.
- a low slew rate is sufficient for the operation of turning on and off the transistor for applying the initial voltage Vini.
- the gate signal lines 17a to 17d may be driven by the two gate driver circuits 12a and 12b.
- anode voltage Vdd 10 to 18 (V)
- reference voltage Vref 1.5 to 3 (V)
- cathode voltage Vss 0.5 to 2.5 (V)
- initial voltage Vini 0 to -3 (V).
- FIG. 4 is a circuit diagram showing a non-light emission period of the pixel circuit according to the embodiment. As shown in FIG. 4, by turning off the transistor 11d, the current flowing through the EL element 15 is cut off, and the light emission of the EL element 15 is stopped (non-light emission).
- FIG. 5 is a circuit diagram illustrating an offset cancellation correction preparation period of the pixel circuit according to the embodiment.
- the transistor 11e is turned on, the reference voltage Vref is applied to the gate terminal of the transistor 11a, the transistor 11c is turned on, and the initial voltage Vini is applied to the anode terminal of the EL element 15.
- the gate potential Vg of the transistor 11a becomes the reference voltage Vref.
- the source potential Vs of the transistor 11a is at the initial voltage Vini that is sufficiently lower than the reference voltage Vref.
- the initial voltage Vini is set so that the gate-source voltage Vgs of the transistor 11a is larger than the offset cancel voltage Vth of the transistor 11a.
- the preparation for the offset cancel correction operation is completed by initializing the gate potential Vg of the transistor 11a to the reference voltage Vref and the source potential Vs to the low potential Vini.
- FIG. 6 is a circuit diagram illustrating an offset cancellation correction period of the pixel circuit according to the embodiment.
- a selection voltage on voltage
- an anode voltage Vdd is applied to the drain terminal of the transistor 11a.
- the transistor 11c is turned off.
- the source potential Vs of the transistor 11a starts to rise.
- the gate-source voltage Vgs of the transistor 11a becomes the offset cancel voltage Vth of the transistor 11a, and a voltage corresponding to the offset cancel voltage Vth is written into the capacitor 19a.
- an offset cancel correction period a period during which a voltage corresponding to the offset cancel voltage Vth is written to the capacitor 19a is referred to as an offset cancel correction period.
- the transistors 11d and 11e are turned off.
- the gate of the transistor 11a is in a floating state, but since the gate-source voltage Vgs is equal to the offset cancel voltage Vth of the transistor 11a, the transistor 11a is in a cut-off state. Therefore, the drain-source current Id does not flow.
- the video signal voltage Vsig is applied to the source signal line 18 from the source driver circuit 14.
- the transistor 11b becomes conductive, and the video signal voltage Vsig is applied to the gate terminal of the transistor 11a of the pixel 16.
- the EL element 15 is an EL element.
- the EL element 15 is in a cut-off state (high impedance state), and thus can be regarded as a capacitor (referred to as Cel).
- the video signal voltage Vsig applied to the gate terminal of the transistor 11a is divided by the capacitance Cs of the capacitor 19a and the capacitance Cel of the light emitting element, and applied between the gate and source terminals of the transistor 11a. Since the capacitance Cel of the light emitting element is smaller than the capacitance Cs of the capacitor 19a, most of the video signal voltage Vsig is applied between the gate and source terminals of the transistor 11a.
- the EL element 15 is used as the capacitor Cel.
- the present invention is not limited to this. Needless to say, a capacitor may be separately formed in parallel with the EL element 15.
- FIG. 8 is a circuit diagram illustrating a light emission period of the pixel circuit according to the embodiment. As shown in FIG. 8, when the transistor 11d is turned on, the anode voltage Vdd is applied to the drain terminal of the transistor 11a. By applying the anode voltage Vdd, the current Id starts to flow. The EL element 15 emits light in proportion to the current Id.
- the offset cancellation correction is performed on the transistor 11a in each pixel 16, and each pixel is controlled to be turned on / off.
- FIG. 9 is a diagram for explaining a method of manufacturing the EL display device according to the embodiment.
- the EL display device is inspected by the pixel circuit operation indicated by 1-4.
- the transistors 11a, 11b, 11d and 11e are turned off and only the transistor 11c is turned on. Is turned on, Vini is applied to the drain terminal of the transistor 11c, and the EL element 15 emits light.
- the voltage Vini is applied to the anode terminal of the EL element 15 through the transistor 11c. If the EL element 15 is normal, the EL element 15 is lit by the voltage Vini applied to the anode terminal of the EL element 15.
- the potential difference between the Vini voltage and the cathode voltage Vss is a voltage at which a current flows through the EL element 15. Therefore, as an example, if the cathode voltage Vss is +2 (V), the Vini voltage is set to +5 (V) or more.
- the voltage Vini is applied to the anode terminal of the EL element 15 via the transistor 11c (voltage application step).
- the initial voltage Vini is 0 to -3 (V).
- the cathode voltage Vss is set to +2 to 8 (V). If the cathode voltage Vss is +2 (V), the Vini voltage at the time of inspection is set to 4 to 10 (V). Therefore, in this embodiment, the initial voltage Vini is configured so that two voltages (offset canceling operation and inspection time (manufacturing time) can be set.
- the initial voltage Vini is configured to be manually variable. If the initial voltage Vini is increased, the current flowing through the EL element 15 is increased, and if the initial voltage Vini is decreased, the current flowing through the EL element 15 is decreased. Therefore, the quality and performance of the EL element 15 can be determined or determined by optically confirming the correlation between the adjustment of the initial voltage Vini and the light emission luminance of the EL element 15.
- the luminance characteristics and the terminal voltage of the EL element 15 differ depending on the color of the EL element 15 (for example, red, green, and blue).
- the initial voltage Vini can be set independently corresponding to the colors (red, green, blue) of the EL element 15.
- the transistors 11c connected to the red EL element, the green EL element, and the blue EL element are made independent, the initial voltage Vini (R) for the red EL element, and the initial for the green EL element.
- the voltage Vini (G) and the initial voltage Vini (B) for the blue EL element can be independently adjusted or set.
- the EL element 15 even when the transistor 11c is turned on and the initial voltage Vini is applied to the EL element 15, if the corresponding EL element 15 does not emit light, the EL element 15 often has a short-circuit defect. . Therefore, a defect (defect) of the EL element 15 can be detected, and it can be determined that the cause of the pixel defect is a defect of the EL element 15. Further, when the luminance is lower than the assumed luminance, it can be detected or determined that a minute pinhole is generated in the EL element.
- the light emission of the EL element 15 is detected by the optical detection means in a state in which the ON voltage is applied to the gate signal line 17a (light emission detection step). And about the defective pixel which did not detect light emission of the EL element 15 in the light emission detection process, it determines with the EL element 15 having a defect cause.
- the gate signal line 17d connected to the gate terminal of the transistor 11c is selected for each pixel row and the transistor 11c is turned on for each pixel row, a defect occurs in the EL element 15 for each pixel row.
- the pixel row position can be specified.
- the degree of defect can be detected or judged.
- a transistor defect can also be detected by changing the ON voltage or OFF voltage of the gate signal line 17d. For example, if the luminance of the pixel to be inspected does not change even when the off-voltage is changed from ⁇ 15 (V) to ⁇ 5 (V), a defect has occurred in one of the transistors in the pixel circuit. Can be detected or judged.
- the light emitting state of the EL element 15 does not change even when the on-voltage of the gate signal line 17d is lowered, it can be determined or determined that a defect has occurred in the transistor 11d or another pixel position. Further, even if the gate signal line 17d is always in an off state, if the EL element 15 is in a light emitting state, it can be determined or determined that a defect has occurred in the transistor 11d or another pixel position.
- the light emission state of the EL element 15 does not change even when the initial voltage Vini is changed, it can be determined or determined that a defect has occurred in the transistor 11d or another pixel position.
- the defect of the corresponding pixel transistor, EL can be detected or specified.
- Pixel defects include those relating to TFTs and those relating to organic EL light emitting elements.
- Defective panels can be made non-defective by discriminating whether a TFT or an organic EL light-emitting element has a defect, and performing defect trimming by laser trimming.
- FIG. 10 is an explanatory diagram for explaining a defect determination method of the EL display device according to the embodiment.
- FIG. 10 in the lighting inspection process of the EL display panel 21, when the pixel 16 is not defective by the conventional lighting inspection method (normal drive inspection), it is a non-defective product, and when the pixel 16 is defective, FIG. Only the transistor 11c shown in FIG. 5 is turned on, and an initial voltage Vin is applied to the EL element to emit light (Vini lighting inspection).
- the defect when a pixel defect is detected in the Vini lighting inspection, it can be determined that the defect is an organic EL light-emitting element, and the product can be improved by repairing the organic EL light-emitting element. Can do.
- the defect when a pixel defect is not detected in the Vini lighting inspection, it can be determined that the defect is a TFT, and if the TFT is repaired, the product can be improved.
- the light emission of the EL element 15 is detected by the optical detection means in a state in which the ON voltage is applied to the gate signal line 17a (light emission detection step).
- the EL element 15 and the transistor is defective (determination step). More specifically, in the determination step, among the defective pixels, the defective pixel in which the light emission of the EL element 15 is detected in the light emission detection step is caused in the transistor (TFT) which is a pixel circuit element other than the EL element 15. It is determined that the EL element 15 has a defect cause for the defective pixel for which the light emission of the EL element 15 is not detected in the light emission detection step.
- TFT transistor
- FIG. 11 Examples of other pixel circuits] [1-7-1. Other pixel circuits] In FIG. 11, two pixels 16a and 16b are illustrated. Actually, the pixels 16 a and 16 b are arranged in a matrix on the display screen 20.
- Each of the pixels 16a and 16b shown in FIG. 11 includes an EL element 15, a driving transistor 11a for supplying a driving current to the EL element 15, a transistor 11d, a transistor 11b, a transistor 11c, and a capacitor. 19a.
- the transistor 11a is a driving transistor whose drain terminal is electrically connected to the anode voltage Vdd as the first power supply line via the transistor 11d and whose source terminal is connected to the drain terminal of the transistor 11d.
- the drain terminal of the transistor 11 d is connected to the source terminal of the transistor 11 a, and the source terminal of the transistor 11 d is electrically connected to the anode terminal of the EL element 15.
- the transistor 11a converts a voltage corresponding to the signal voltage applied between the gate terminal and the source terminal into a drain current corresponding to the signal voltage. Then, this drain current is supplied to the EL element 15 as a signal current.
- the transistor 11a is composed of, for example, an n-type thin film transistor (n-type TFT).
- the EL element 15 is a light emitting element whose anode terminal is electrically connected to the source terminal of the transistor 11a and whose cathode terminal is electrically connected to the cathode voltage Vss which is the second power supply line.
- the EL element 15 emits light based on the magnitude of the signal current when the signal current flows through the transistor 11a.
- the magnitude of the signal current is determined by applying the video signal applied to the source signal line 18 to the pixel 16a or 16b via the transistor 11c.
- the transistor 11b is a second switch transistor whose drain terminal is connected to the source terminal of the transistor 11a and whose source terminal is connected to the source signal line 18.
- the drain terminal of the transistor 11c of the pixel 16a is connected to the source signal line 18a
- the source terminal of the transistor 11b of the pixel 16a is connected to the source signal line 18b.
- the drain terminal of the transistor 11c of the pixel 16b is connected to the source signal line 18b
- the source terminal of the transistor 11b of the pixel 16b is connected to the source signal line 18c.
- the source terminal of the transistor 11c is connected to the gate terminal of the transistor 11a.
- the transistor 11c is applied to the source signal line and applies a video signal to the gate terminal of the transistor 11a.
- the capacitor 19a is connected between the gate terminal and the source terminal of the transistor 11a.
- the transistor 11d is a first switch transistor whose gate terminal is electrically connected to the gate signal line 17c. When an on voltage is applied to the gate signal line 17c, the transistor 11d is turned on, and the light emission drive current from the transistor 11a is supplied to the EL element 15.
- the transistor 11d may be disposed or formed between the drain terminal of the transistor 11a and the anode voltage Vdd terminal.
- the transistor 11c has a gate terminal electrically connected to the gate signal line 17a, a source terminal electrically connected to the gate terminal of the transistor 11a, and a drain terminal electrically connected to the source signal line 18. This is a switch transistor. When the on voltage is applied to the gate signal line 17a, the video signal applied to the source signal line 18 is applied to the gate terminal of the transistor 11a.
- the transistor 11b of the pixel 16a has a gate terminal electrically connected to the gate signal line 17b1, and the transistor 11b of the pixel 16b has a gate terminal electrically connected to the gate signal line 17b2. That is, the transistors 11b of the adjacent pixels are connected to different gate signal lines.
- the channels of the transistors 11a to 11d are bidirectional, the names of the source terminal and the drain terminal are for ease of explanation, and the source terminal and the drain terminal may be interchanged.
- the source terminal and the drain terminal may be a first terminal, a second terminal, or the like.
- the capacitor 19a first stores the gate-source electrode voltage (the potential of the source signal line) of the transistor 11a in a steady state in a state where the transistor 11b is conductive. Thereafter, even when the transistor 11b is turned off, the potential of the capacitor 19a is determined, so that the gate voltage of the transistor 11a is determined.
- the transistor 11b is a transistor that reads the characteristics of the transistor 11a.
- the transistor 11d When reading the characteristics of the transistor 11a of the pixel 16a, the transistor 11d is turned off and the transistor 11b is turned on. Further, the output of the source driver circuit 14 is not connected to the source signal line 18b (set to a high impedance state).
- the current flowing between the channels of the transistor 11a is output to the source signal line 18b via the channel of the transistor 11b. By measuring the current flowing through the source signal line 18b, the characteristics of the transistor 11a can be measured or evaluated.
- the pixel 16a will be described for ease of description. Note that the matter described for the pixel 16a also applies to the pixel 16b or other pixels arranged in a matrix on the display screen 20.
- Vsg (j + 1) is an inspection voltage. This inspection voltage corresponds to the initial voltage Vini in the circuit shown in FIG.
- a Vsg (j + 1) voltage is applied to the anode terminal of the EL element 15 via the transistors 11b and 11d (voltage application step). If the EL element 15 is normal, the EL element 15 is lit by the Vsg (j + 1) voltage applied to the anode terminal of the EL element 15. A current corresponding to the potential difference between the Vsg (j + 1) voltage and the cathode voltage Vss flows through the EL element 15. As an example, if the cathode voltage Vss is +2 (V), the Vsg (j + 1) voltage is set to +5 (V) or more.
- the Vsig voltage is a video signal voltage, and a video signal is applied to the source signal line 18 from the source driver circuit 14 (not shown).
- Vsg voltages (Vsg (j), Vsg (j + 1), Vsg (j + 2) etc.
- the video signal voltage is applied from the source driver circuit 14 to the source signal lines 18a to 18c, and the EL element 15 is inspected.
- a probe (not shown) is pressed against the source signal lines 18a to 18c, and an inspection voltage is applied to each source signal line.
- the drain terminal of the transistor 11b belonging to the pixel 16a is connected to the source signal line 18b disposed in the adjacent pixel column, and in the voltage application step, an on-voltage is applied to the gate signal line 18a, whereby the transistor 11b Then, the inspection voltage, which is the second voltage applied to the source signal line 18b, is applied to the anode terminal of the EL element 15.
- the Vsg voltage is configured to be manually variable.
- the current flowing through the EL element 15 is increased, and when the Vsg voltage is decreased, the current flowing through the EL element 15 is decreased. Therefore, the quality and performance of the EL element 15 can be determined or determined by optically confirming the correlation between the adjustment of the Vsg voltage and the light emission luminance of the EL element 15.
- the light emission luminance characteristics and the terminal voltage of the EL element 15 differ depending on the color (red, green, blue) of the EL element 15.
- the Vsg voltage can be set independently corresponding to the colors (red, green, blue) of the EL element 15. This operation is easy when the source driver circuit 14 outputs the Vsg voltage.
- a defect (defect) of the EL element 15 can be detected, and it can be determined that the cause of the pixel defect is a defect of the EL element 15.
- the gate signal lines 17b1 and 17b2 connected to the gate terminals of the transistor 11b of the pixel 16a and the transistor 11b of the pixel 16b are selected simultaneously or alternately one pixel row at a time. With this operation, if the transistors 11b and 11d are turned on, the pixel row position where the EL element 15 is defective can be specified for each pixel row.
- transistor defects can also be detected by changing the on-voltage or off-voltage applied to the gate signal lines 17b1 and 17b2.
- the light emission state of the EL element 15 of the pixel 16a does not change even if the on-voltage of the gate signal line 17b1 is lowered, a defect has occurred in the transistor 11b of the pixel 16a or another pixel position. Judgment or judgment can be made. Further, even if the gate signal line 17d is always in an off state, if the EL element 15 is in a light emitting state, it can be determined or determined that a defect has occurred in the transistor 11d or another pixel position. If the light emission state of the EL element 15 does not change even when the Vsg voltage is changed, it can be determined or determined that a defect has occurred in the transistors 11a and 11d or other pixel positions.
- a defect or a defect of the EL element 15 can be detected or specified.
- This disclosure is particularly useful for a manufacturing method and an inspection method of an active organic EL flat panel display.
Abstract
Description
本発明者は、「背景技術」の欄において記載したEL表示装置に関し、以下の問題が生じることを見出した。
以下、図面を参照しながら、実施の形態を説明する。
[1-1.発光画素構成]
図12は、発光画素の構造の一例を概略的に示す断面図である。
図2は、実施の形態に係るEL表示装置の電気的な構成を示したブロック図である。図2に示したように、本実施の形態に係るEL表示装置は、画素16がマトリックス状に配置されて構成された表示画面20と、表示画面20の画素行ごとに配置されたゲート信号線17a、17b、17cおよび17dと、表示画面20の画素列ごとに配置されたソース信号線18と、表示画面20の周辺回路である、ゲート信号線17a、17b、17cおよび17dを駆動するゲートドライバ回路(ゲートドライバIC)12aおよび12bと、映像信号をソース信号線18に出力するソースドライバ回路(ソースドライバIC)14と、ゲートドライバ回路12aおよび12bおよびソースドライバ回路14などを制御する制御回路(図示せず)を具備する。表示画面20は、外部から画像表示装置へ入力された映像信号に基づいて画像を表示する。
図3は、実施の形態に係るEL表示装置における画素回路の例を示した図である。なお、図3などにおいて、画素16は1画素のみを図示している。実際には画素16は表示画面20にマトリックス状に配置されている。図3に示した画素回路は、EL素子15と、EL素子15に駆動電流を供給するためのトランジスタ11aと、トランジスタ11dと、トランジスタ11bと、トランジスタ11cと、トランジスタ11eと、コンデンサ19aとを備える。表示画面20には、EL素子15を有する画素がマトリックス状に配置されている。
次に、図4~図8などを用いて、図3の画素回路の動作を説明する。
図3の画素回路において、トランジスタ11dがオン状態のとき、EL素子15にアノード電圧Vddから電流が供給され、EL素子15が発光状態にある(発光期間)。アノード電圧Vddからトランジスタ11aを通してEL素子15に駆動電流(ドレイン・ソース間電流)Idが供給されるため、EL素子15が駆動電流Idに応じた輝度で発光する。
図5は、実施の形態に係る画素回路のオフセットキャンセル補正準備期間を表す回路図である。オフセットキャンセル補正の準備期間では、トランジスタ11eがオンし、リファレンス電圧Vrefがトランジスタ11aのゲート端子に印加され、トランジスタ11cがオンし、イニシャル電圧ViniがEL素子15のアノード端子に印加される。これにより、トランジスタ11aのゲート電位Vgがリファレンス電圧Vrefになる。また、トランジスタ11aのソース電位Vsは、リファレンス電圧Vrefよりも十分に低いイニシャル電圧Viniにある。
図6は、実施の形態に係る画素回路のオフセットキャンセル補正期間を表す回路図である。図6に示すように、ゲート信号線17bに選択電圧(オン電圧)が印加され、トランジスタ11dがオンすると、トランジスタ11aのドレイン端子にアノード電圧Vddが印加される。また、トランジスタ11cをオフ状態にする。すると、トランジスタ11aのソース電位Vsが上昇を開始する。やがて、トランジスタ11aのゲート-ソース間電圧Vgsが当該トランジスタ11aのオフセットキャンセル電圧Vthになり、当該オフセットキャンセル電圧Vthに相当する電圧がコンデンサ19aに書き込まれる。
図7に示すように、ソース信号線18にソースドライバ回路14から映像信号電圧Vsigが印加される。ゲート信号線17aに選択電圧が印加されることにより、トランジスタ11bが導通状態になって映像信号電圧Vsigが、画素16のトランジスタ11aのゲート端子に印加される。本実施の形態において、EL素子15はEL素子であり、また、このとき、EL素子15はカットオフ状態(ハイインピーダンス状態)にあるために、コンデンサ(Celと呼ぶ)とみなすことができる。
図8は、実施の形態に係る画素回路の発光期間を表す回路図である。図8示すように、トランジスタ11dがオンすることにより、トランジスタ11aのドレイン端子にアノード電圧Vddが印加される。アノード電圧Vddの印加により、電流Idが流れ始める。電流Idに比例して、EL素子15が発光する。
図9は、実施の形態に係るEL表示装置の製造方法を説明する図である。
画素の欠陥は、TFTに関するものと、有機EL発光素子に関するものがある。
[1-7-1.他の画素回路]
図11では、2つの画素16aおよび16bを図示している。実際には、画素16aおよび16bは表示画面20にマトリックス状に配置されている。
図11に示された、実施の形態に係る他の画素回路の検査(製造)方法について説明する。
12a、12b ゲートドライバ回路
14 ソースドライバ回路
15 EL素子
16、16a、16b 画素
17a、17b、17c、17d ゲート信号線
18、18a、18b、18c ソース信号線
19a コンデンサ
20 表示画面
21 EL表示パネル
202 基板
215 発光画素
301 駆動回路層
302 発光層
310 透明封止膜
361 陽極
362 正孔注入層
363 正孔輸送層
364 有機発光層
365 バンク層
366 電子注入層
367 透明陰極
Claims (5)
- 複数の画素がマトリックス状に配置された表示画面を有するEL表示装置の製造方法であって、
前記複数の画素のそれぞれは、EL素子と、前記EL素子に電流を供給する駆動用トランジスタと、スイッチ用トランジスタとを備え、
前記EL素子は、第1電圧が印加されている第1端子と、第2端子とを有し、
前記スイッチ用トランジスタは、ゲート信号線と接続されているゲート端子と、前記第2端子と接続された第3端子と、前記第1電圧よりも高い電位を有する第2電圧が印加されている第4端子とを有し、
前記ゲート信号線にオン電圧を印加することにより、前記スイッチ用トランジスタを介して、前記第2電圧を前記第2端子に印加する電圧印加工程と、
前記ゲート信号線に前記オン電圧を印加した状態で、前記EL素子の発光を、光学的検出手段で検出する発光検出工程とを含む
EL表示装置の製造方法。 - さらに、
前記発光検出工程で検出した前記EL素子の発光の有無に基づいて、(1)前記EL素子、ならびに(2)前記スイッチ用トランジスタおよび前記駆動用トランジスタを含む前記EL素子以外の画素回路素子、のいずれに欠陥があるかを判定する判定工程を含む
請求項1に記載のEL表示装置の製造方法。 - 前記電圧印加工程では、前記ゲート信号線にオン電圧を印加することにより、前記スイッチ用トランジスタを介し、かつ、前記駆動用トランジスタを介さないで、前記第2電圧を前記第2端子に印加する
請求項1または2に記載のEL表示装置の製造方法。 - さらに、
前記電圧印加工程の前に、前記表示画面に配置された全ての画素を一斉点灯させることにより、欠陥画素を検出する欠陥画素検出工程を含み、
前記判定工程では、前記欠陥画素のうち、前記発光検出工程で前記EL素子の発光を検出した欠陥画素については前記画素回路素子に欠陥原因があると判定し、前記発光検出工程で前記EL素子の発光を検出しなかった欠陥画素については前記EL素子に欠陥原因があると判定する
請求項2に記載のEL表示装置の製造方法。 - 前記EL表示装置は、
前記複数の画素の画素列ごとに配置され、前記駆動用トランジスタのゲート端子に映像信号を反映した信号電圧を伝達するためのソース信号線を備え、
前記第4端子は、隣接する画素列に配置された前記ソース信号線に接続され、
前記電圧印加工程では、前記ゲート信号線にオン電圧を印加することにより、前記スイッチ用トランジスタを介して、隣接する画素列に配置された前記ソース信号線に印加された前記第2電圧を前記第2端子に印加する
請求項1~4のいずれか1項に記載のEL表示装置の製造方法。
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