WO2015122299A1 - Dispositif d'imagerie a semi-conducteurs, appareil electronique et procede de fabrication d'un dispositif d'imagerie a semi-conducteurs - Google Patents

Dispositif d'imagerie a semi-conducteurs, appareil electronique et procede de fabrication d'un dispositif d'imagerie a semi-conducteurs Download PDF

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Publication number
WO2015122299A1
WO2015122299A1 PCT/JP2015/052796 JP2015052796W WO2015122299A1 WO 2015122299 A1 WO2015122299 A1 WO 2015122299A1 JP 2015052796 W JP2015052796 W JP 2015052796W WO 2015122299 A1 WO2015122299 A1 WO 2015122299A1
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WO
WIPO (PCT)
Prior art keywords
solid
imaging device
state imaging
package
pattern
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PCT/JP2015/052796
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English (en)
Japanese (ja)
Inventor
賢治 三島
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ソニー株式会社
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Publication of WO2015122299A1 publication Critical patent/WO2015122299A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14618—Containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof

Definitions

  • the present disclosure relates to a solid-state imaging device, an electronic device, and a manufacturing method of the solid-state imaging device, and more particularly, to a solid-state imaging device, an electronic device, and a manufacturing method of the solid-state imaging device that can be downsized.
  • the most common package for image sensors is a hollow package.
  • sufficient clearance is required to prevent contact between the wire bonding tool (capillary) and the package.
  • the COG (Chip On Glass) structure allows the substrate to be removed by making the glass also have the function of a substrate, and can be made thinner.
  • the signal needs to be taken out from the side by the flexible substrate instead of the back side of the sensor, and the dimension in the planar direction becomes large.
  • the image sensor package is required to be further downsized.
  • the present disclosure has been made in view of such a situation, and can reduce the size of the package.
  • a solid-state imaging device includes a glass in which a first pattern corresponding to a sensor pad, a second pattern corresponding to a wiring pattern of a package, and a wiring that connects a pair of patterns to each other are formed.
  • a substrate, a sensor mounted on the glass substrate face down, and the package.
  • the wiring pattern of the package is a lead frame in which a front surface pattern and a back surface pattern are formed in a U-shape.
  • the package is formed of a thermoplastic resin or a thermosetting resin.
  • the package is formed of ceramic.
  • the package is formed of an organic substrate.
  • the first pattern is formed on the inner side of the second pattern on the glass substrate.
  • the electrical joint in mounting is flip chip joining.
  • NCP Non-Conductive-Paste
  • ACP (Anisotropic Conductive Paste) is used for the flip chip bonding.
  • An electronic device is a glass substrate on which a first pattern corresponding to a sensor pad, a second pattern corresponding to a wiring pattern of a package, and a wiring connecting the paired patterns are formed.
  • a solid-state imaging device having a sensor and the package mounted face-down on the glass substrate, a signal processing circuit for processing an output signal output from the solid-state imaging device, and incident light to the solid-state imaging device And an incident optical system.
  • the wiring pattern of the package is a lead frame in which a front surface pattern and a back surface pattern are formed in a U-shape.
  • the package is formed of a thermoplastic resin or a thermosetting resin.
  • the package is formed of ceramic.
  • the package is formed of an organic substrate.
  • the first pattern is formed on the inner side of the second pattern on the glass substrate.
  • the electrical joint in mounting is flip chip joining.
  • NCP Non-Conductive-Paste
  • ACP (Anisotropic Conductive Paste) is used for the flip chip bonding.
  • the manufacturing device pairs a glass substrate with a first pattern corresponding to the sensor pad and a second pattern corresponding to the wiring pattern of the package. Wiring for connecting the patterns is formed, and the sensor and the package are mounted face-down on the glass substrate.
  • a first pattern corresponding to the sensor pad, a second pattern corresponding to the wiring pattern of the package, and a wiring connecting the paired patterns are formed on the glass substrate. .
  • the sensor and the package are mounted face down on the glass substrate.
  • a package can be manufactured. Moreover, according to this technique, a package can be reduced in size.
  • FIG. 1 illustrates a schematic configuration example of an example of a complementary metal oxide semiconductor (CMOS) solid-state imaging device applied to each embodiment of the present technology.
  • CMOS complementary metal oxide semiconductor
  • a solid-state imaging device (element chip) 1 includes a pixel region (a pixel region in which pixels 2 including a plurality of photoelectric conversion elements are regularly arranged two-dimensionally on a semiconductor substrate 11 (for example, a silicon substrate). A so-called imaging region) 3 and a peripheral circuit section.
  • the pixel 2 includes a photoelectric conversion element (for example, a photodiode) and a plurality of pixel transistors (so-called MOS transistors).
  • the plurality of pixel transistors can be constituted by three transistors, for example, a transfer transistor, a reset transistor, and an amplifying transistor, and can further be constituted by four transistors by adding a selection transistor. Since the equivalent circuit of each pixel 2 (unit pixel) is the same as a general one, detailed description thereof is omitted here.
  • the pixel 2 can have a shared pixel structure.
  • the pixel sharing structure includes a plurality of photodiodes, a plurality of transfer transistors, one shared floating diffusion, and one other pixel transistor that is shared.
  • the peripheral circuit section includes a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, and a control circuit 8.
  • the control circuit 8 receives data for instructing an input clock, an operation mode, and the like, and outputs data such as internal information of the solid-state imaging device 1. Specifically, the control circuit 8 is based on the vertical synchronization signal, the horizontal synchronization signal, and the master clock, and the clock signal or the reference signal for the operations of the vertical drive circuit 4, the column signal processing circuit 5, and the horizontal drive circuit 6 Generate a control signal. The control circuit 8 inputs these signals to the vertical drive circuit 4, the column signal processing circuit 5, and the horizontal drive circuit 6.
  • the vertical drive circuit 4 is composed of, for example, a shift register, selects a pixel drive wiring, supplies a pulse for driving the pixel 2 to the selected pixel drive wiring, and drives the pixels 2 in units of rows. Specifically, the vertical drive circuit 4 selectively scans each pixel 2 in the pixel region 3 sequentially in the vertical direction in units of rows, and generates the signal according to the amount of light received by the photoelectric conversion element of each pixel 2 through the vertical signal line 9. A pixel signal based on the signal charge is supplied to the column signal processing circuit 5.
  • the column signal processing circuit 5 is disposed, for example, for each column of the pixels 2 and performs signal processing such as noise removal on the signal output from the pixels 2 for one row for each pixel column. Specifically, the column signal processing circuit 5 performs signal processing such as CDS (Correlated Double Sampling) for removing fixed pattern noise specific to the pixel 2, signal amplification, A / D (Analog / Digital) conversion, and the like. .
  • a horizontal selection switch (not shown) is provided connected to the horizontal signal line 10.
  • the horizontal drive circuit 6 is constituted by, for example, a shift register, and sequentially outputs horizontal scanning pulses to select each of the column signal processing circuits 5 in order, and the pixel signal is output from each of the column signal processing circuits 5 to the horizontal signal line. 10 to output.
  • the output circuit 7 performs signal processing on the signals sequentially supplied from each of the column signal processing circuits 5 through the horizontal signal line 10 and outputs the signals.
  • the output circuit 7 may perform only buffering, or may perform black level adjustment, column variation correction, various digital signal processing, and the like.
  • the input / output terminal 12 is provided for exchanging signals with the outside.
  • FIG. 2 is a cross-sectional view illustrating an example of a solid-state imaging device to which the present technology is applied.
  • an image sensor 62 and a package 63 are mounted face down on a glass substrate 61.
  • a pattern group 71 is formed on the glass substrate 61 of the solid-state imaging device 51.
  • an outer pattern 71-1 is arranged outside the glass substrate 61
  • an inner pattern 71-2 is arranged inside the glass substrate 61.
  • the same number of outer patterns 71-1 and inner patterns 71-2 are formed so as to be paired, and a pair of patterns from the outer pattern 71-1 and inner pattern 71-2 is a wiring pattern 71-. 3 connected.
  • the inner pattern 71-2 is formed corresponding to the 1st pad 81 of the image sensor 62.
  • the outer pattern 71-1 is formed corresponding to the wiring pattern 91 on the package 63.
  • the pattern group 71 is a conductive material (for example, aluminum, gold, copper, silver, or a material containing them), and is formed by vapor deposition or coating.
  • the image sensor 62 and the package 63 are electrically joined to the glass substrate 61.
  • a light receiving surface 82 is formed on the image sensor 62.
  • the 1st pad 81 is formed around the light receiving surface 82.
  • the image sensor 62 and the package 63 are joined by an insulating adhesive 101 inside the package 63.
  • the package 63 may be made of any material made of ceramic, organic substrate, or plastic.
  • the package 63 can be manufactured by integrally molding a lead frame having a U-shaped shape of a katakana as the wiring pattern 91 by molding with a thermosetting resin or a thermoplastic resin.
  • the mounting portion (that is, the electrical joint portion) of the image sensor 62, the package 63, and the glass substrate 61 is electrically connected by the bumps 72 and sealed by the sealing resin 73.
  • the material of the bump 72 may be Au, Cu, Ag, or solder, but the height is about 60 ⁇ m in order to fill the height difference between the 1st pad 81 on the image sensor 62 and the wiring pattern 91 of the package 63. Is desirable.
  • the sealing resin 73 can be sealed at the same time as improving the reliability of connectivity by using an anisotropic conductive resin (ACP: Anisotropic Conductive Paste). Further, if sufficient connection reliability can be obtained with only the bumps 72, NCP (Non Conductive Paste) without conductive particles may be used. NCP is a cheaper material than ACP.
  • ACP Anisotropic Conductive Paste
  • step S11 the manufacturing apparatus performs a die bond resin coating process. That is, the manufacturing apparatus applies the insulating adhesive 101 with the dispense 111 inside the package 63 as shown in FIG.
  • step S12 the manufacturing apparatus performs die bonding processing. That is, as shown in FIG. 5B, the manufacturing apparatus bonds the image sensor 62 to the package 63 in which the insulating adhesive material 101 is applied on the inside. Thereafter, the insulating adhesive 101 is cured by heating for a predetermined time.
  • step S13 the manufacturing apparatus performs stud bump processing. That is, the manufacturing apparatus forms bumps 72 corresponding to the outer patterns 71-1 and 71-2 on the glass substrate 61 as shown in FIG. 5C.
  • the processing in this step can be performed after the glass substrate 61 is singulated, or can be performed in a large format before the singulation.
  • step S14 the manufacturing apparatus performs a sealing resin coating process. That is, the manufacturing apparatus applies the sealing resin (ACP or NCP) 73 so as to cover the outer patterns 71-1 and 71-2 of the glass substrate 61 subjected to the stud bump process, as shown in FIG. 6A. To do.
  • ACP or NCP the sealing resin
  • step S15 the manufacturing apparatus performs a flip chip bonding process. That is, as shown in FIG. 6B, the manufacturing apparatus performs a face-down process on a semi-finished product in which the image sensor 62 and the package 63 are integrated on the glass substrate 61 coated with the bumps 72 and the sealing resin 73. Implement. At that time, sealing and electrical joining are completed by applying a predetermined load and thermal conditions. Then, in step S16, as shown in FIG. 6C, they are inverted by the manufacturing apparatus, and the solid-state imaging device 51 is manufactured.
  • the solid-state imaging device 51 of the present technology has a COG (Chip On Glass) structure that also has a substrate function on glass, but easily arranges output terminals on the back surface of the package (the surface opposite to the light receiving surface). can do. As a result, the package can be made thinner / smaller.
  • COG Chip On Glass
  • the wire bond is not required by conducting the image sensor and the wiring pattern (lead frame) of the package through the flip chip bonding process through the pattern provided on the glass substrate. Therefore, since it is not necessary to consider contact with the wire bond tool, the package can be reduced in size.
  • the solid-state imaging device 51 of the present technology hits a bump instead of a wire, the amount of wire material used can be reduced and the cost can be reduced.
  • the lead frame of the package is exposed to the outer periphery of the package, so that it can be mounted on either the back surface or the side surface, and the degree of freedom of mounting is increased.
  • the image sensor since the image sensor is used as a part of the structure, it is advantageous in strength that the image sensor is thick. As a result, the back grinding process is omitted or simplified. be able to.
  • the present technology may be applied to a solid-state imaging device such as a CCD (Charge Coupled Device) solid-state imaging device.
  • CCD Charge Coupled Device
  • the solid-state imaging device may be a backside illumination type or a frontside illumination type.
  • the imaging apparatus refers to a camera system such as a digital still camera or a digital video camera, or an electronic apparatus having an imaging function such as a mobile phone.
  • a module-like form mounted on an electronic device that is, a camera module is used as an imaging device.
  • Second Embodiment> ⁇ Configuration example of electronic equipment>
  • FIG. 7 the structural example of the electronic device of the 2nd Embodiment of this technique is demonstrated.
  • the 7 is provided with a solid-state imaging device (element chip) 301, an optical lens 302, a shutter device 303, a drive circuit 304, and a signal processing circuit 305.
  • a solid-state imaging device element chip
  • the solid-state imaging device 51 according to the first embodiment of the present technology described above is provided.
  • the electronic device 300 can be reduced in size.
  • the electronic device 300 can be provided at low cost.
  • the optical lens 302 forms image light (incident light) from the subject on the imaging surface of the solid-state imaging device 301. As a result, signal charges are accumulated in the solid-state imaging device 301 for a certain period.
  • the shutter device 303 controls the light irradiation period and the light shielding period for the solid-state imaging device 301.
  • the drive circuit 304 supplies a drive signal for controlling the signal transfer operation of the solid-state imaging device 301 and the shutter operation of the shutter device 303.
  • the solid-state imaging device 301 performs signal transfer by a drive signal (timing signal) supplied from the drive circuit 304.
  • the signal processing circuit 305 performs various signal processing on the signal output from the solid-state imaging device 301.
  • the video signal subjected to the signal processing is stored in a storage medium such as a memory or output to a monitor.
  • steps describing the series of processes described above are not limited to the processes performed in time series according to the described order, but are not necessarily performed in time series, either in parallel or individually.
  • the process to be executed is also included.
  • each step described in the above flowchart can be executed by one device or can be shared by a plurality of devices.
  • the plurality of processes included in the one step can be executed by being shared by a plurality of apparatuses in addition to being executed by one apparatus.
  • the configuration described as one device (or processing unit) may be divided and configured as a plurality of devices (or processing units).
  • the configurations described above as a plurality of devices (or processing units) may be combined into a single device (or processing unit).
  • a configuration other than that described above may be added to the configuration of each device (or each processing unit).
  • a part of the configuration of a certain device (or processing unit) may be included in the configuration of another device (or other processing unit). . That is, the present technology is not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the present technology.
  • this technique can also take the following structures.
  • a solid-state imaging device comprising: a sensor mounted face-down on the glass substrate; and the package.
  • the wiring pattern of the package is a lead frame in which a front surface pattern and a back surface pattern are formed in a U-shape.
  • NCP Non Conductive Paste
  • ACP Anisotropic Conductive Paste
  • (10) a glass substrate on which a first pattern corresponding to a sensor pad, a second pattern corresponding to a wiring pattern of a package, and a wiring connecting each pair of patterns are formed;
  • a solid-state imaging device having the sensor and the package mounted face-down on the glass substrate;
  • a signal processing circuit for processing an output signal output from the solid-state imaging device;
  • an optical system that makes incident light incident on the solid-state imaging device.
  • the wiring pattern of the package is a lead frame in which a front surface pattern and a back surface pattern are formed in a U-shape.
  • (12) The electronic device according to (10) or (11), wherein the package is formed of a thermoplastic resin or a thermosetting resin.
  • the electronic device according to (10) or (11), wherein the package is formed of ceramic.
  • the electronic device according to (10) or (11), wherein the package is formed of an organic substrate.
  • the electronic device according to any one of (10) to (14), wherein the first pattern is formed inside the second pattern on the glass substrate.
  • the electrical joint portion in mounting is flip-chip joint.
  • NCP Non Conductive Paste
  • ACP Anisotropic Conductive Paste
  • the manufacturing equipment is On the glass substrate, a first pattern corresponding to the sensor pad, a second pattern corresponding to the wiring pattern of the package, and a wiring connecting the paired patterns are formed.
  • 1 solid-state imaging device 2 pixels, 3 pixel area, 11 semiconductor substrate, 51 solid-state imaging device, 61 glass substrate, 62 image sensor, 63 package, 71 pattern group, 71-1 outer pattern, 71-2 inner pattern, 71- 3 Wiring pattern, 72 bumps, 73 sealing resin, 81 1st pad, 82 light receiving surface, 91 wiring pattern, 300 electronic equipment, 301 solid-state imaging device, 302 optical lens, 303 shutter device, 304 drive circuit, 305 signal processing circuit

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

La présente invention concerne un dispositif d'imagerie à semi-conducteurs permettant de réduire la taille d'un boîtier, un appareil électronique et un procédé de fabrication d'un dispositif d'imagerie à semi-conducteurs. Un groupe de motifs est formé sur un substrat en verre d'un dispositif d'imagerie à semi-conducteurs. Dans le groupe de motifs, des motifs extérieurs formés chacun de manière à correspondre à un motif de câblage formé sur un boîtier, sont placés sur la face extérieure du substrat de verre, et des motifs intérieurs formés chacun de manière à correspondre à un capteur d'image, sont placés sur la face intérieure du substrat de verre. Le même nombre de motifs extérieurs et intérieurs sont formés en vue d'être appariés, et les motifs extérieurs et intérieurs à apparier sont connectés par le motif de câblage. La présente invention peut s'appliquer, par exemple, à un dispositif d'imagerie à semi-conducteurs CMOS utilisé en tant que dispositif d'imagerie.
PCT/JP2015/052796 2014-02-13 2015-02-02 Dispositif d'imagerie a semi-conducteurs, appareil electronique et procede de fabrication d'un dispositif d'imagerie a semi-conducteurs WO2015122299A1 (fr)

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JP2014-025076 2014-02-13
JP2014025076 2014-02-13

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WO2015122299A1 true WO2015122299A1 (fr) 2015-08-20

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108701696A (zh) * 2016-02-08 2018-10-23 索尼公司 玻璃中介层模块、成像装置和电子设备
WO2023002656A1 (fr) * 2021-07-21 2023-01-26 ソニーセミコンダクタソリューションズ株式会社 Boîtier de semi-conducteur

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Publication number Priority date Publication date Assignee Title
JP2005353803A (ja) * 2004-06-10 2005-12-22 Sharp Corp 電子回路素子の製造方法
JP2006320943A (ja) * 2005-05-19 2006-11-30 Sony Corp はんだペースト及びはんだ印刷方法
JP2007299929A (ja) * 2006-04-28 2007-11-15 Matsushita Electric Ind Co Ltd 光学デバイス装置とそれを用いた光学デバイスモジュール
JP2008235616A (ja) * 2007-03-22 2008-10-02 Matsushita Electric Ind Co Ltd 半導体装置および半導体装置の製造方法
JP2010177600A (ja) * 2009-01-30 2010-08-12 Panasonic Corp 光学デバイス
JP2010185747A (ja) * 2009-02-12 2010-08-26 Casio Computer Co Ltd パネル及びｉｃチップの搭載状態の検査方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005353803A (ja) * 2004-06-10 2005-12-22 Sharp Corp 電子回路素子の製造方法
JP2006320943A (ja) * 2005-05-19 2006-11-30 Sony Corp はんだペースト及びはんだ印刷方法
JP2007299929A (ja) * 2006-04-28 2007-11-15 Matsushita Electric Ind Co Ltd 光学デバイス装置とそれを用いた光学デバイスモジュール
JP2008235616A (ja) * 2007-03-22 2008-10-02 Matsushita Electric Ind Co Ltd 半導体装置および半導体装置の製造方法
JP2010177600A (ja) * 2009-01-30 2010-08-12 Panasonic Corp 光学デバイス
JP2010185747A (ja) * 2009-02-12 2010-08-26 Casio Computer Co Ltd パネル及びｉｃチップの搭載状態の検査方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108701696A (zh) * 2016-02-08 2018-10-23 索尼公司 玻璃中介层模块、成像装置和电子设备
CN108701696B (zh) * 2016-02-08 2022-11-18 索尼公司 玻璃中介层模块、成像装置和电子设备
WO2023002656A1 (fr) * 2021-07-21 2023-01-26 ソニーセミコンダクタソリューションズ株式会社 Boîtier de semi-conducteur

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