WO2015122096A1 - Appareil de conversion photoélectrique - Google Patents

Appareil de conversion photoélectrique Download PDF

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WO2015122096A1
WO2015122096A1 PCT/JP2014/083337 JP2014083337W WO2015122096A1 WO 2015122096 A1 WO2015122096 A1 WO 2015122096A1 JP 2014083337 W JP2014083337 W JP 2014083337W WO 2015122096 A1 WO2015122096 A1 WO 2015122096A1
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region
electrode
semiconductor layer
photoelectric conversion
conversion device
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PCT/JP2014/083337
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English (en)
Japanese (ja)
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善之 奈須野
和仁 西村
伊坂　隆行
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シャープ株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H01L31/022441—Electrode arrangements specially adapted for back-contact solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
    • H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
    • H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to a photoelectric conversion device.
  • FIG. 43 shows a schematic cross-sectional view of the solar cell element described in Patent Document 1.
  • the solar cell element described in Patent Document 1 shown in FIG. 43 includes an n-type polycrystalline silicon substrate 101 and an i-type silicon made of intrinsic hydrogenated amorphous silicon or the like provided on the back side of the n-type polycrystalline silicon substrate 101.
  • a thin film layer 102, a p-type silicon thin film layer 103 provided on a part of the i-type silicon thin film layer 102, and a positive electrode 105 provided on the p-type silicon thin film layer 103 are provided.
  • n-type diffusion layer 112 in which phosphorus is diffused as a dopant is formed on a part of the back surface of the n-type polycrystalline silicon substrate 101, and is in contact with the n-type diffusion layer 112 on the i-type silicon thin film layer 102.
  • the negative electrode 106 is formed.
  • a concavo-convex structure 101a is formed on the light-receiving surface side surface of the n-type polycrystalline silicon substrate 101, and an antireflection layer 111 is formed on the concavo-convex structure 101a.
  • the solar cell element described in Patent Document 1 is manufactured as follows. First, the n-type diffusion layer 112 is formed on a part of the back surface of the n-type polycrystalline silicon substrate 101. Next, an i-type silicon thin film layer 102 is formed on the entire back surface of the n-type polycrystalline silicon substrate 101.
  • a mask having an opening at a position where the n-type diffusion layer 112 is exposed is formed on the i-type silicon thin film layer 102.
  • a part of the i-type silicon thin film layer 102 is etched using the mask as a mask to expose a part of the surface of the n-type diffusion layer 112.
  • the mask on the i-type silicon thin film layer 102 is removed.
  • a mask having an opening at a position where the p-type silicon thin film layer 103 remains is formed on the i-type silicon thin film layer 102.
  • a p-type silicon thin film layer 103 is formed on the entire back surface of the i-type silicon thin film layer 102 on which the mask is formed.
  • the mask on the back surface side of the i-type silicon thin film layer 102 is removed, the positive electrode 105 is formed on the p-type silicon thin film layer 103, and the negative electrode 106 is formed on the n-type diffusion layer 112, thereby obtaining a patent document. 1 is produced.
  • the solar cell element described in Patent Document 1 has poor productivity because it requires a patterning step in each of the formation process of the i-type silicon thin film layer 102 and the formation process of the p-type silicon thin film layer 103. There was a problem, so improvement was desired.
  • an embodiment described later is to provide a photoelectric conversion device capable of improving productivity.
  • a semiconductor substrate an i-type semiconductor layer above a first surface of the semiconductor substrate, a first conductivity type semiconductor layer on the i-type semiconductor layer, and a first conductivity type
  • An electrode on the semiconductor layer the electrode having a first electrode and a second electrode that are electrically separated, and the first surface is a second region that is a region other than the first region and the first region
  • a second conductivity type region having a second conductivity type impurity concentration higher than that of the semiconductor substrate is provided on the semiconductor substrate below the second region, and a first electrode is provided above the first region.
  • the second electrode is provided above the second region, and there is a portion where the i-type semiconductor layer and the first conductivity type semiconductor layer are interposed between the second conductivity type region and the second electrode.
  • a photoelectric conversion device that can improve productivity can be provided.
  • FIG. 1 is a schematic cross-sectional view of a photoelectric conversion device according to a first embodiment.
  • (A)-(i) is typical sectional drawing illustrating an example of the manufacturing method of the photoelectric conversion apparatus of Embodiment 1.
  • FIG. (A)-(d) is typical sectional drawing illustrating an example of the manufacturing method of the photoelectric conversion apparatus of Embodiment 1.
  • FIG. FIG. 6 is a schematic top perspective view of the photoelectric conversion device according to the second embodiment.
  • FIG. 5A is a schematic cross-sectional view taken along the line Va-Va in FIG. 4, and FIG.
  • FIG. 5B is a diagram illustrating a process of removing portions of an i-type semiconductor layer and a p-type semiconductor layer in a laser light irradiation region by laser light irradiation. It is typical sectional drawing illustrating an example of a process, (c) is i when projecting the laminated body of an i-type semiconductor layer and a p-type semiconductor layer on the 1st surface from the perpendicular upper part of the 1st surface. It is a typical top view of an example of the relationship between the projected area of a p-type semiconductor layer, and the projected area of a p-type semiconductor layer.
  • FIG. 6 is a schematic top perspective view of a photoelectric conversion device according to a third embodiment. FIG.
  • FIG. 6 is a schematic cross-sectional view of a photoelectric conversion device according to a fourth embodiment.
  • (A)-(h) is typical sectional drawing illustrated about an example of the manufacturing method of the photoelectric conversion apparatus of Embodiment 4.
  • FIG. FIG. 6 is a schematic cross-sectional view of a photoelectric conversion device according to a fifth embodiment.
  • FIG. 10 is a schematic cross-sectional view of a photoelectric conversion device according to a sixth embodiment.
  • FIG. 10 is a schematic cross-sectional view of a photoelectric conversion device according to a seventh embodiment.
  • FIG. 10 is a schematic cross-sectional view of a photoelectric conversion device according to an eighth embodiment.
  • FIG. 10 is a schematic cross-sectional view of a photoelectric conversion device according to a ninth embodiment.
  • FIG. 10 is a schematic cross-sectional view of the photoelectric conversion device according to the tenth embodiment.
  • FIG. 16 is a schematic cross-sectional view of a photoelectric conversion device according to an eleventh embodiment.
  • 22 is a schematic cross-sectional view of the photoelectric conversion device according to the twelfth embodiment.
  • FIG. FIG. 16 is a schematic cross-sectional view of a photoelectric conversion device according to a thirteenth embodiment.
  • FIG. 16 is a schematic cross-sectional view of a photoelectric conversion device according to a fourteenth embodiment.
  • FIG. 16 is a schematic cross-sectional view of the photoelectric conversion device according to the fifteenth embodiment.
  • 18 is a schematic cross-sectional view of the photoelectric conversion device according to the sixteenth embodiment.
  • FIG. 20 is a schematic cross-sectional view of a photoelectric conversion device according to a seventeenth embodiment.
  • FIG. 20 is a schematic cross-sectional view of a photoelectric conversion device according to an eighteenth embodiment.
  • 20 is a schematic cross-sectional view of the photoelectric conversion device according to the nineteenth embodiment.
  • FIG. FIG. 38 is a schematic cross-sectional view of the photoelectric conversion device according to the twentieth embodiment.
  • FIG. 38 is a schematic cross-sectional view of the photoelectric conversion device according to the twenty-first embodiment.
  • (A)-(j) is typical sectional drawing illustrating an example of the manufacturing method of the photoelectric conversion apparatus of Embodiment 21.
  • FIG. FIG. 38 is a schematic cross-sectional view of a photoelectric conversion device according to a twenty-second embodiment.
  • FIG. 27 is a schematic cross-sectional view of a photoelectric conversion device according to a twenty-third embodiment.
  • FIG. FIG. 25 is a schematic cross-sectional view of a photoelectric conversion device according to a twenty-fourth embodiment.
  • (A)-(j) is typical sectional drawing illustrating an example of the manufacturing method of the photoelectric conversion apparatus of Embodiment 24.
  • FIG. FIG. 26 is a schematic cross-sectional view of a photoelectric conversion device according to a twenty-fifth embodiment.
  • FIG. 38 is a schematic cross-sectional view of a photoelectric conversion device according to a twenty-sixth embodiment.
  • A) And (b) is typical sectional drawing illustrating about an example of the manufacturing method of the photoelectric conversion apparatus of Embodiment 26.
  • FIG. 38 is a schematic cross-sectional view of a photoelectric conversion device according to a twenty-seventh embodiment.
  • FIG. (A) is typical sectional drawing of the modification of the photoelectric conversion apparatus of Embodiment 27,
  • (b) is the 2nd conductivity type in the 1st area
  • (A) is typical sectional drawing of the further modification of the photoelectric conversion apparatus of Embodiment 27, (b) is the dielectric material on the 1st area
  • FIG. 38 is a diagram comparing current-voltage characteristics of a photoelectric conversion device according to Embodiment 27 with current-voltage characteristics of a photoelectric conversion device that does not have an overlap region.
  • FIG. FIG. 38 is a schematic plan view when the first surface of the n-type single crystal silicon substrate of the photoelectric conversion device according to the tenth embodiment is viewed from above.
  • FIG. 38 is a schematic cross-sectional view of a modification of the photoelectric conversion device according to the twenty-fourth embodiment.
  • FIG. 38 is a schematic cross-sectional view of the photoelectric conversion device according to the twenty-eighth embodiment.
  • FIG. 38 is a schematic cross-sectional view of a modification of the photoelectric conversion device according to the twenty-eighth embodiment.
  • 2 is a schematic cross-sectional view of a solar cell element described in Patent Document 1.
  • Embodiment 1 a method for forming an n + region by diffusion on an n-type single crystal substrate is described, but the present invention is not limited to this.
  • a p + region is formed by boron diffusion on an n-type single crystal substrate.
  • the i layer and the n layer may be deposited in this order.
  • a p-type single crystal substrate may be used in place of the n-type single crystal substrate, and after an n + region is formed by diffusion on the p-type single crystal substrate, the i layer and the p layer may be deposited in this order.
  • the i layer and the n layer may be deposited in this order.
  • FIG. 1 is a schematic cross-sectional view of the photoelectric conversion device of Embodiment 1 which is an example of the photoelectric conversion device of the present invention.
  • the photoelectric conversion device according to the first embodiment includes an n-type single crystal silicon substrate 1 and an i-type made of i-type amorphous silicon above a first surface 1a that is one surface of the n-type single crystal silicon substrate 1.
  • Two electrodes 5 are provided.
  • the first surface 1 a of the n-type single crystal silicon substrate 1 has a first region 12 and a second region 11 that is a region other than the first region 12, and the n-type below the second region 11.
  • An n-type region 2 having an n-type impurity concentration higher than that of the n-type single crystal silicon substrate 1 is formed in the single crystal silicon substrate 1. Since the n-type impurity concentration of the first region 12 is the same as that of the n-type single crystal silicon substrate 1, the n-type impurity concentration of the second region 11 is higher than the n-type impurity concentration of the first region 12. ing.
  • the second electrode 5 is provided in the region of the p-type semiconductor layer 4 above the second region 11, and the first electrode 6 is provided in the region of the p-type semiconductor layer 4 above the first region 12. ing.
  • the i-type semiconductor layer 3 and the p-type semiconductor layer 4 are interposed between the second electrode 5 and the second region 11, and the second electrode 5 and the second region are interposed.
  • 11 is conducting. Note that the state in which the second electrode 5 and the second region 11 are in conduction is a case where the second electrode 5 and the second region 11 are not in physical contact with each other due to a tunnel current or the like. It means that a current flows.
  • the thickness of the i-type semiconductor layer 3 is preferably 0.5 nm or more and 6 nm or less.
  • the i-type semiconductor layer 3 can be made a more uniform layer, and thus the passivation property by the i-type semiconductor layer 3 can be improved. Therefore, the open circuit voltage can be improved.
  • the thickness of the i-type semiconductor layer 3 is 6 nm or less, a good tunnel current flows through the i-type semiconductor layer 3, so that a good short-circuit current and FF (fill factor) can be obtained.
  • i-type means not only a completely intrinsic state but also a state in which n-type or p-type impurities are mixed if the concentration is sufficiently low.
  • the n-type or p-type conductivity may be exhibited by unavoidably diffusing n-type or p-type impurities after the photoelectric conversion device is manufactured.
  • amorphous silicon includes not only amorphous silicon in which dangling bonds of silicon atoms are not terminated with hydrogen, but also silicon atoms such as hydrogenated amorphous silicon. This includes those whose hands are terminated with hydrogen.
  • FIG. 2A a texture structure is formed on the second surface 1b which is the surface opposite to the first surface 1a of the n-type single crystal silicon substrate 1.
  • the texture structure is formed by forming a texture mask such as a silicon nitride film on the first surface 1a of the n-type single crystal silicon substrate 1 by a CVD (Chemical Vapor Deposition) method, a sputtering method, or the like.
  • the first second surface 1b can be formed by texture etching. Texture etching can be performed, for example, by wet etching using, as an etchant, a solution obtained by adding isopropyl alcohol to an alkaline aqueous solution such as sodium hydroxide or potassium hydroxide and heating to 70 ° C. or higher and 80 ° C. or lower.
  • the texture mask is removed from the second surface 1b of the n-type single crystal silicon substrate 1.
  • a diffusion mask 21 made of silicon oxide is formed on the first surface 1 a of the n-type single crystal silicon substrate 1.
  • the diffusion mask 21 is, for example, inkjet or screen-printed with a masking paste containing a solvent, a thickener, and a silicon oxide precursor in a region that becomes the first region 12 of the first surface 1a of the n-type single crystal silicon substrate 1. It can be formed by coating with heat treatment.
  • the n-type impurity concentration in the first surface 1a of the n-type single crystal silicon substrate 1 is more than that in the n-type single crystal silicon substrate 1 using the diffusion mask 21 as a mask.
  • High n-type region 2 is formed.
  • N-type region 2 diffuses phosphorus, which is an n-type impurity, into the exposed surface from diffusion mask 21 on first surface 1a of n-type single crystal silicon substrate 1, for example, by vapor phase diffusion using POCl 3. Can be formed.
  • Diffusion mask 21 formed on the first surface 1a of the n-type single crystal silicon substrate 1 is removed.
  • Diffusion mask 21 can be removed with hydrofluoric acid together with a glass layer formed by phosphorus diffusing into first surface 1a of n-type single crystal silicon substrate 1, for example.
  • a diffusion mask 26 made of silicon oxide is formed on the first surface 1a of the n-type single crystal silicon substrate 1, and the texture structure of the n-type single crystal silicon substrate 1 is as follows.
  • a mixed liquid containing at least a phosphorus compound, titanium alkoxide and alcohol is applied onto the formed second surface 1b by spin coating or the like and dried.
  • the phosphorus compound contained in the mixed solution for example, phosphorus pentoxide can be used
  • the titanium alkoxide for example, tetraisopropyl titanate can be used
  • the alcohol for example, isopropyl alcohol can be used.
  • the n-type single crystal silicon substrate 1 after the application and drying of the above mixed solution is heat-treated to diffuse phosphorus, whereby the second of the n-type single crystal silicon substrate 1 is obtained as shown in FIG.
  • the sheet resistance value of the light-receiving surface diffusion layer 28 is preferably 30 ⁇ / ⁇ to 100 ⁇ / ⁇ , and more preferably 60 ⁇ 20 ⁇ / ⁇ .
  • the diffusion mask 26 is removed from the first surface 1a of the n-type single crystal silicon substrate 1 by etching using hydrofluoric acid.
  • the antireflection layer 27 on the second surface 1b is made of a titanium oxide film containing phosphorus, the acid resistance to hydrogen fluoride is high. Thereby, only the convex part of the concavo-convex structure of the second surface 1b of the n-type single crystal silicon substrate 1 where the antireflection layer 27 is thin is exposed.
  • a dielectric layer 29 made of a silicon oxide film is formed on the second surface 1b of the n-type single crystal silicon substrate 1 as shown in FIG. 3D, and as shown in FIG.
  • a silicon oxide film 30 is formed on the first surface 1 a of the n-type single crystal silicon substrate 1. Thereafter, the silicon oxide film 30 formed on the first surface 1a of the n-type single crystal silicon substrate 1 is removed by hydrofluoric acid treatment.
  • the configuration in which the antireflection layer 27 made of a titanium oxide film and the dielectric layer 29 made of a silicon oxide film are formed in this order on the light receiving surface of the n-type single crystal silicon substrate 1 has been described.
  • a silicon nitride film may be formed on the light receiving surface of the silicon substrate 1.
  • the thickness of the silicon nitride film is preferably 80 nm or more and 120 nm or less.
  • an i-type semiconductor layer 3 is laminated on the entire first surface 1a of the n-type single crystal silicon substrate 1 by, for example, a plasma CVD method, and then the i-type semiconductor layer 3 A p-type semiconductor layer 4 is laminated on the entire surface by, eg, plasma CVD.
  • the photoelectric conversion device of the first embodiment the case where the i-type semiconductor layer 3 made of i-type amorphous silicon and the p-type semiconductor layer 4 made of p-type amorphous silicon are used has been described. It is not limited to this configuration.
  • the i-type semiconductor layer 3 and the p-type semiconductor layer 4 may be, for example, the same type of silicon-based semiconductor layer or different types of silicon-based semiconductor layers.
  • both the i-type semiconductor layer 3 and the p-type semiconductor layer 4 may be amorphous silicon.
  • the i-type semiconductor layer 3 is made of i-type amorphous silicon, and a p-type semiconductor is used.
  • the layer 4 may be p-type microcrystalline silicon.
  • the contact resistance between the p-type semiconductor layer 4 and the first electrode 6 can be reduced, so that the FF of the photoelectric conversion device of Embodiment 1 and Conversion efficiency can be improved.
  • the p-type semiconductor layer 4 has a two-layer structure in which the side in contact with the i-type semiconductor layer 3 is amorphous silicon and the side not in contact with the i-type semiconductor layer 3 is a microcrystalline silicon layer. Since the band connection between the layers can be made smooth and the contact resistance between the p-type semiconductor layer 4 and the first electrode 6 can be reduced, the open circuit voltage and the FF can be improved.
  • microcrystal means a substance containing both an amorphous phase and a crystalline phase.
  • the p-type semiconductor layer 4 may be a p-type amorphous silicon carbide layer or a p-type amorphous silicon nitride layer, and the i-type semiconductor layer 3 may be amorphous silicon.
  • the optical loss in the p-type semiconductor layer 4 can be reduced by the p-type semiconductor layer 4 having a wide band gap, the short-circuit current value of the photoelectric conversion device of the first embodiment is increased. be able to.
  • Examples of the i-type semiconductor layer 3 include i-type amorphous silicon carbide (i-type a-SiC), i-type amorphous silicon nitride (i-type a-SiN), i-type amorphous silicon (i-type a -Si), i-type amorphous germanium silicide (i-type a-SiGe), i-type amorphous germanium (i-type a-Ge), i-type microcrystalline silicon carbide (i-type ⁇ c-SiC), i-type micro Crystalline silicon nitride (i-type ⁇ c-SiN), i-type microcrystalline silicon (i-type ⁇ c-Si), i-type microcrystalline germanium silicide (i-type ⁇ c-SiGe) or i-type microcrystalline germanium (i-type ⁇ c-Ge) Etc.
  • i-type amorphous silicon carbide i-type a-
  • the i-type semiconductor layer 3 is made of any of i-type a-SiC, i-type a-SiN, i-type a-SiGe, i-type ⁇ c-SiC, i-type ⁇ c-SiN, or i-type ⁇ c-SiGe.
  • the i-type semiconductor layer 3 may be formed so that the optical band gap gradually decreases as the distance from the first surface 1a of the n-type single crystal silicon substrate 1 increases.
  • the thickness of the i-type semiconductor layer 3 made of i-type a-Si can be, for example, not less than 0.5 nm and not more than 10 nm, and more preferably not less than 3 nm and not more than 7 nm.
  • a source gas for the i-type semiconductor layer 3 made of i-type a-Si for example, a mixed gas of silane (SiH 4 ) gas and hydrogen (H 2 ) gas can be used.
  • various bands such as an LF frequency in the region of 20 kHz to 100 kHz and an RF frequency of 10 MHz to 14 MHz can be used, and it is preferable to use an RF frequency of 11 MHz to 13 MHz.
  • the pressure at the time of forming the i-type semiconductor layer 3 made of i-type a-Si can be, for example, 200 Pa or more and 800 Pa or less, preferably 400 Pa or more and 600 Pa or less.
  • the temperature during the deposition of the i-type semiconductor layer 3 made of i-type a-Si for example be a 180 ° C. or higher 210 ° C. or less, power density and for example 45 mW / cm 2 or more 105 mW / cm 2 or less can do.
  • Examples of the p-type semiconductor layer 4 include p-type amorphous silicon carbide (p-type a-SiC), p-type amorphous silicon nitride (p-type a-SiN), and p-type amorphous silicon (p-type a -Si), p-type amorphous germanium silicide (p-type a-SiGe), p-type microcrystalline silicon carbide (p-type ⁇ c-SiC), p-type microcrystalline silicon nitride (p-type ⁇ c-SiN), p-type micro Crystalline silicon (p-type ⁇ c-Si) or p-type microcrystalline germanium silicide (p-type ⁇ c-SiGe) can be used.
  • p-type a-SiC p-type amorphous silicon carbide
  • p-type a-SiN p-type amorphous silicon nitride
  • the thickness of the p-type semiconductor layer 4 made of p-type a-Si can be, for example, not less than 10 nm and not more than 30 nm, and preferably not less than 15 nm and not more than 25 nm.
  • a source gas of the p-type semiconductor layer 4 made of p-type a-Si for example, a mixed gas of silane (SiH 4 ) gas, hydrogen (H 2 ) gas, and diborane (B 2 H 6 ) gas is used. it can.
  • an RF frequency of 10 MHz to 14 MHz can be used for plasma excitation, and it is preferable to use an RF frequency of 11 MHz to 13 MHz.
  • the pressure at the time of forming the p-type semiconductor layer 4 made of p-type a-Si can be, for example, 200 Pa or more and 800 Pa or less, preferably 400 Pa or more and 600 Pa or less.
  • the temperature at the time of forming the p-type semiconductor layer 4 made of p-type a-Si can be, for example, 180 ° C. or more and 210 ° C. or less, and the power density is, for example, 10 mW / cm 2 or more and 40 mW / cm 2 or less. can do.
  • a conductive layer 22 is formed on the entire surface of the p-type semiconductor layer 4.
  • the conductive layer 22 can be formed, for example, by forming a transparent conductive layer on the entire surface of the p-type semiconductor layer 4 and then forming a reflective electrode layer on the entire surface of the transparent conductive layer.
  • the transparent conductive layer for example, indium tin oxide (ITO), zinc oxide (ZnO), or a combination thereof can be used.
  • ITO indium tin oxide
  • ZnO zinc oxide
  • a reflective electrode layer silver (Ag), aluminum (Al), nickel (Ni), or these at least 2 types of alloys etc. can be used, for example.
  • the transparent conductive layer made of ITO can be formed by, for example, DC magnetron sputtering.
  • the thickness of the transparent conductive layer made of ITO can be set to 4 nm or more and 10 nm or less, for example.
  • the substrate temperature at the time of forming the transparent conductive layer made of ITO can be, for example, 140 ° C. or more and 200 ° C. or less.
  • the reflective electrode layer made of Ag can be formed by, for example, DC magnetron sputtering. Moreover, the thickness of the reflective electrode layer made of Ag can be set to 40 nm or more and 80 nm or less, for example. Moreover, the substrate temperature at the time of formation of the reflective electrode layer made of Ag can be set to 140 ° C. or more and 200 ° C. or less, for example.
  • the reflective electrode layer made of Ag can also be formed, for example, by printing a silver paste by a screen printing method and then baking it.
  • the region of the conductive layer 22 where the second electrode 5 and the first electrode 6 are formed is covered, and the other regions are exposed so that the surface of the conductive layer 22 is exposed.
  • An etching mask 23 is formed on the surface of the conductive layer 22.
  • the etching mask 23 can be formed as follows, for example. First, after the surface of the conductive layer 22 is heated to a temperature of 100 ° C. or higher and 120 ° C. or lower and prebaked, a resist is applied by spin coating, and the resist is dried at a temperature of 100 ° C. or higher and 120 ° C. or lower. Then, the resist is patterned by exposing the pattern to the dried resist and developing it. And it can form by post-baking at the temperature of 100 to 120 degreeC, after washing the resist after patterning with water.
  • the conductive layer 22 is etched using the etching mask 23 as a mask, thereby forming the second electrode 5 and the first electrode 6 as shown in FIG.
  • the etching of the second electrode 5 and the first electrode 6 can be performed, for example, by wet etching using a mixed solution of nitric acid and acetic acid as an etchant.
  • the etching mask 23 is removed from the surfaces of the second electrode 5 and the first electrode 6 to complete the photoelectric conversion device of the first embodiment.
  • the etching mask 23 can be removed by, for example, washing with acetone, washing with ethanol, washing with water, and drying.
  • the i-type semiconductor layer 3 and the p-type semiconductor layer 4 are stacked in this order on the second region 11 (n-type region 2) of the n-type single crystal silicon substrate 1, and the second The electrode 5 is formed, and the first electrode 6 is formed on the first region 12 after the i-type semiconductor layer 3 and the p-type semiconductor layer 4 are laminated in this order. Therefore, in the photoelectric conversion device of the first embodiment, unlike the solar cell element described in Patent Document 1, it is not necessary to perform the patterning process for both the i-type semiconductor layer 3 and the p-type semiconductor layer 4. Compared with the solar cell element described in Patent Document 1, productivity can be improved.
  • the second electrode 5 and the first electrode 6 may be formed by laser patterning.
  • the second electrode 5 and the first electrode 6 may be formed by laser patterning.
  • the second electrode 5 and the first electrode 6 are formed by separating the conductive layer 22.
  • the laser light applied to the conductive layer 22 is the third harmonic of an Nd: YAG laser (generally using a YAG crystal doped with neodymium), and the oscillation pulse width is, for example, 10 picoseconds.
  • the spot diameter of the laser beam can be, for example, 30 ⁇ m to 50 ⁇ m, and the patterning line can be, for example, 50 ⁇ m or more and 100 ⁇ m or less.
  • FIG. 4 is a schematic top perspective view of the photoelectric conversion device according to Embodiment 2, which is another example of the photoelectric conversion device of the present invention.
  • FIG. 5A shows a schematic cross-sectional view along Va-Va in FIG.
  • the second region 11 of the first surface 1a of the n-type single crystal silicon substrate 1 is partly in contact with the second electrode 5 in the third region.
  • 31 and the fourth region 32 that is not in physical contact with the second electrode 5, and the third region 31 and the fourth region 32 exist alternately along the longitudinal direction of the second region 11. It is characterized by that.
  • the second region 11 of the first surface 1a of the n-type single crystal silicon substrate 1 has a third region 31 in physical contact with the second electrode 5. Yes.
  • the third region 31 since the series resistance between the second electrode 5 and the second region 11 can be reduced, the FF of the photoelectric conversion device is improved.
  • the second region 11 of the first surface 1a of the n-type single crystal silicon substrate 1 is not in physical contact with the second electrode 5, and the i-type semiconductor layer 3 and a fourth region 32 covered with a stacked body 33 of the p-type semiconductor layer 4 on the i-type semiconductor layer 3.
  • region 32 since passivation property can be improved, the open circuit voltage of a photoelectric conversion apparatus improves.
  • both reduction in series resistance between the second electrode 5 and the second region 11 and improvement in passivation in the second region 11 can be achieved. Both the FF and open circuit voltage of the device can be improved.
  • the photoelectric conversion device includes, for example, laser light after laminating the i-type semiconductor layer 3 and the p-type semiconductor layer 4 in this order over the entire first surface 1a of the n-type single crystal silicon substrate 1.
  • the portions of the i-type semiconductor layer 3 and the p-type semiconductor layer 4 in the laser light irradiation region 34 are removed, and then the second electrode 5 can be produced.
  • FIG. 5C shows the projection of the i-type semiconductor layer 3 when the stacked body 33 of the i-type semiconductor layer 3 and the p-type semiconductor layer 4 is projected onto the first surface 1a from vertically above the first surface 1a.
  • the typical top view of an example of the relationship between an area and the projection area of the p-type semiconductor layer 4 is shown.
  • the projected area 4a when the p-type semiconductor layer 4 of the stacked body 33 is projected onto the first surface 1a from vertically above the first surface 1a is the i-type of the stacked body 33. It is smaller than the projected area 3a when the semiconductor layer 3 is projected.
  • the adhesion between the second electrode 5 and the second region 11 can be improved, and the contact resistance between the second electrode 5 and the second region 11 can be reduced. Long-term reliability can be improved by suppressing peeling of the electrode 5.
  • the projected area of the i-type semiconductor layer 3 can be increased, the passivation property of the second region 11 by the i-type semiconductor layer 3 is improved and the open circuit voltage can be increased.
  • the adhesiveness of the fourth region 32 (i-type semiconductor layer 3 / p-type semiconductor layer 4 / second electrode 5) is greater in the third region 31 (second region 11 / second electrode). 5) Since the height is higher, it is preferable that the laminated body 33 has a textured structure in order to periodically exist the fourth region 32 and to enhance the anchor effect of the second electrode 5.
  • FIG. 6 is a schematic top perspective view of the photoelectric conversion device according to Embodiment 3, which is another example of the photoelectric conversion device of the present invention.
  • the entire region of the second region 11 of the first surface 1a of the n-type single crystal silicon substrate 1 is in contact with the third region 31 that is in physical contact with the second electrode 5.
  • the fourth region 32 is not in physical contact with the second electrode 5, and the third region 31 and the fourth region 32 are alternately present along the longitudinal direction of the second region 11. It is characterized by being.
  • the area of the third region 31 in which the second region 11 is in physical contact with the second electrode 5 is increased, and the series resistance between the second electrode 5 and the second region 11 is increased. Therefore, the FF of the photoelectric conversion device can be further improved.
  • FIG. 7 is a schematic cross-sectional view of a photoelectric conversion device according to Embodiment 4, which is another example of the photoelectric conversion device of the present invention.
  • the photoelectric conversion device of the fourth embodiment along the direction (hereinafter referred to as “width direction”) orthogonal to the longitudinal direction of the second region 11 of the first surface 1a of the n-type single crystal silicon substrate 1.
  • the second region 11 of the first surface 1a of the n-type single crystal silicon substrate 1 has a third region 31 that is in physical contact with the second electrode 5. Yes.
  • the third region 31 since the series resistance between the second electrode 5 and the second region 11 can be reduced, the FF of the photoelectric conversion device is improved.
  • the second region 11 of the first surface 1a of the n-type single crystal silicon substrate 1 is not in physical contact with the second electrode 5, and the i-type semiconductor layer 4 has a fourth region 32 covered by 3.
  • region 32 since passivation property can be improved, the open circuit voltage of a photoelectric conversion apparatus improves.
  • both reduction in series resistance between the second electrode 5 and the second region 11 and improvement in passivation of the second region 11 can be achieved. Both the FF and the open circuit voltage can be improved.
  • FIGS. 8 (a) to 8 (h) schematic cross-sectional views of FIGS. 8 (a) to 8 (h).
  • the i-type semiconductor layer 3 and the p-type semiconductor layer 4 are formed on the entire surface of the first surface 1a of the n-type single crystal silicon substrate 1. Laminate sequentially.
  • a diffusion mask 21 made of silicon oxide is formed on the p-type semiconductor layer 4.
  • the i-type semiconductor layer 3 and the p-type semiconductor layer 4 exposed from the diffusion mask 21 are removed by etching using the diffusion mask 21 as a mask.
  • etching using a mixed solution of hydrofluoric acid and nitric acid is performed, only the i-type semiconductor layer 3 and the p-type semiconductor layer 4 made of amorphous silicon can be etched.
  • the diffusion mask 21 is removed from the p-type semiconductor layer 4.
  • a conductive layer 22 is formed on the entire surface of the p-type semiconductor layer 4.
  • the region of the conductive layer 22 where the second electrode 5 and the first electrode 6 are formed is covered, and other regions are exposed so that the surface of the conductive layer 22 is exposed.
  • An etching mask 23 is formed on the surface of the conductive layer 22.
  • the conductive layer 22 is etched using the etching mask 23 as a mask, thereby separating the second electrode 5 and the first electrode 6 as shown in FIG. Thereafter, as shown in FIG. 8H, the etching mask 23 is removed from the surfaces of the second electrode 5 and the first electrode 6 to complete the photoelectric conversion device of the fourth embodiment.
  • FIG. 9 is a schematic cross-sectional view of the photoelectric conversion device according to Embodiment 5, which is another example of the photoelectric conversion device of the present invention.
  • the photoelectric conversion device of Embodiment 5 is characterized in that the shape of the second electrode 5 is different.
  • the third electrode that is in physical contact with the second electrode 5 along the width direction of the second region 11 of the first surface 1a of the n-type single crystal silicon substrate 1 is also used.
  • the region 31 and the fourth region 32 that is not in physical contact with the second electrode 5 exist.
  • both reduction in series resistance between the second electrode 5 and the second region 11 and improvement in passivation of the second region 11 can be achieved. Both the FF and open circuit voltage of the device can be improved.
  • FIG. 10 is a schematic cross-sectional view of a photoelectric conversion device according to Embodiment 6, which is another example of the photoelectric conversion device of the present invention.
  • a plurality of through holes 61 penetrating the i-type semiconductor layer 3 and the p-type semiconductor layer 4 in the thickness direction are provided with a space between each other.
  • the electrode 5 is in physical contact with the second region 11.
  • the second region 11 of the first surface 1a of the n-type single crystal silicon substrate 1 includes the third region 31 in physical contact with the second electrode 5 and the second region 11.
  • the second region 5 is not in physical contact with the two electrodes 5.
  • both reduction in series resistance between the second electrode 5 and the second region 11 and improvement in passivation of the second region 11 can be achieved. Both the FF and the open circuit voltage can be improved.
  • the second electrode 5 in physical contact with the second region 11 through the through hole 61 and the through hole 61 is formed on the first surface 1 a of the n-type single crystal silicon substrate 1 with the i-type semiconductor layer 3 and the p-type semiconductor layer 4.
  • a conductive paste serving as a precursor of the second electrode 5 and the first electrode 6 is applied on the p-type semiconductor layer 4, and the conductive paste positioned above the second region 11 is applied.
  • the conductive paste can be heated only by irradiating a laser beam, and the second region 11 can be selectively fired through.
  • a paste having a conductive metal and glass frit can be used as the conductive paste for performing the fire-through.
  • the glass in the conductive paste is used.
  • the frit can break through the i-type semiconductor layer 3 and the p-type semiconductor layer 4 to achieve electrical connection between the second electrode 5 and the second region 11.
  • the glass frit it is preferable to use a glass frit containing at least one low melting point metal selected from the group consisting of lead (Pb), zinc (Zn), bismuth (Bi) and aluminum (Al). .
  • the conductive paste applied on the p-type semiconductor layer 4 is a conductive material that can be fired at a low temperature. It is preferable to use an adhesive paste.
  • a conductive paste containing a glass frit containing at least one low melting point metal selected from the group consisting of Pb, Zn, Bi and Al the fire-through property at low temperature is improved, and the first electrode 6 and p Since the contact resistance with the type semiconductor layer 4 can be further reduced, the FF of the photoelectric conversion device can be improved.
  • FIG. 11 is a schematic cross-sectional view of a photoelectric conversion device according to Embodiment 7, which is another example of the photoelectric conversion device of the present invention.
  • the photoelectric conversion device according to the seventh embodiment is characterized in that a separation groove is provided so as to electrically separate the second electrode 5 and the first electrode 6 (prevent electrical contact).
  • the separation groove is constituted by a first side wall surface 51c and a second side wall surface 51d provided so as to face each other with a space W1 therebetween, and a bottom surface 51e.
  • the bottom surface 51e is not limited to a flat surface as shown in FIG. 11, and may be a curved surface.
  • electrical contact means that the shunt resistance component is 1 k ⁇ or less. The reason for this is that electrical contact with a shunt resistance component of 1 k ⁇ or more causes little reduction in conversion efficiency, and the generation of leakage current through the shunt resistance can be suppressed to heat generation that does not cause quality problems. Because.
  • the separation groove is provided between the second electrode 5 and the first electrode 6 to prevent physical contact between the second electrode 5 and the first electrode 6.
  • physical contact between the p-type semiconductor layer 4a on the second electrode 5 side and the p-type semiconductor layer 4b on the first electrode 6 side is prevented.
  • the second electrode 5 and the first electrode 6 are electrically separated, and the p-type semiconductor layer 4a on the second electrode 5 side and the first electrode 6 are also separated.
  • the p-type semiconductor layer 4b on the side is electrically isolated.
  • the length of the interval W1 between the first side wall surface 51c and the second side wall surface 51d is preferably in the range of 20 ⁇ m or more and 100 ⁇ m or less, and can be set to 40 ⁇ m, for example, in the present embodiment. . Since the first sidewall surface 51c and the second sidewall surface 51d of the separation groove may be inclined with respect to a surface perpendicular to the n-type single crystal silicon substrate 1, the first sidewall surface of the separation groove.
  • the interval W1 between 51c and the second side wall surface 51d is defined as the interval between the uppermost part of the second electrode 5 and the uppermost part of the first electrode 6.
  • the separation groove reaches the p-type semiconductor layers 4a and 4b.
  • the contact resistance between the p-type semiconductor layer 4b and the first electrode 6 is reduced by using the p-type semiconductor layer 4b made of a microcrystalline semiconductor such as microcrystalline silicon. be able to. This is because the conductivity of the p-type semiconductor layer 4b is higher when a microcrystalline semiconductor such as microcrystalline silicon is used for the p-type semiconductor layer 4b than when an amorphous semiconductor such as amorphous silicon is used. It is to become.
  • the p-type semiconductor layer 4a on the second electrode 5 side and the p-type semiconductor layer 4b on the first electrode 6 side are electrically separated by the separation groove.
  • the amount of leakage current generated between the second electrode 5 and the first electrode 6 can be reduced, and the FF of the photoelectric conversion device can be improved. That is, when the p-type semiconductor layer 4 is made of an amorphous semiconductor such as amorphous silicon, the conductivity of the p-type semiconductor layer 4 is low, so that the amount of current flowing in the width direction of the p-type semiconductor layer 4 is small. .
  • the conductivity of the p-type semiconductor layer 4b increases, and the amount of current flowing in the width direction of the p-type semiconductor layer 4 also increases. . Therefore, not only the second electrode 5 and the first electrode 6 are electrically separated by the separation groove, but also the p-type semiconductor layer 4 is separated from the p-type semiconductor layer 4a on the second electrode 5 side and the first electrode 6 side. By electrically separating the p-type semiconductor layer 4b, the amount of leakage current generated between the second electrode 5 and the first electrode 6 can be reduced, and the FF of the photoelectric conversion device can be improved. it can.
  • the i-type semiconductor layer 3 and the p-type semiconductor layer 4 are stacked in this order on the first surface 1a of the n-type single crystal silicon substrate 1, and then the p-type semiconductor layer 4 is formed.
  • the conductive layer 22 is formed, and then a laser beam is irradiated to remove the conductive layer 22 and the p-type semiconductor layer 4 in the thickness direction, thereby forming a separation groove. Then, the conductive layer 22 is electrically separated by the separation groove, whereby the second electrode 5 and the first electrode 6 are obtained.
  • the p-type semiconductor layer 4 is electrically separated by the separation groove, and the p on the second electrode 5 side is obtained.
  • the first side wall surface 51c includes an exposed surface of the first electrode 6 and an exposed surface of the p-type semiconductor layer 4b.
  • the second side wall surface 51d is composed of an exposed surface of the second electrode 5 and an exposed surface of the p-type semiconductor layer 4a.
  • the third harmonic of an Nd: YAG laser can be used as the laser beam, and the oscillation pulse width can be set to, for example, 10 picoseconds to 50 picoseconds.
  • the spot diameter can be 20 ⁇ m to 50 ⁇ m, for example, and the patterning line can be 20 ⁇ m or more and 100 ⁇ m or less, for example.
  • FIG. 12 is a schematic cross-sectional view of the photoelectric conversion device according to Embodiment 8, which is another example of the photoelectric conversion device of the present invention.
  • the separation grooves are provided between the second electrode 5 and the first electrode 6 and the p-type semiconductor layer 4a on the second electrode 5 side and the p-type semiconductor layer 4b on the first electrode 6 side.
  • the i-type semiconductor layer 3a on the second electrode 5 side and the i-type semiconductor layer 3b on the first electrode 6 side are electrically separated from each other.
  • the separation groove reaches the i-type semiconductor layers 3a and 3b.
  • the contact resistance between the p-type semiconductor layer 4b and the first electrode 6 is reduced by using the p-type semiconductor layer 4b made of a microcrystalline semiconductor such as microcrystalline silicon. be able to.
  • the p-type semiconductor layer 4a on the second electrode 5 side and the p-type semiconductor layer 4b on the first electrode 6 side are only electrically separated by the separation groove.
  • the i-type semiconductor layer 3a on the second electrode 5 side and the i-type semiconductor layer 3b on the first electrode 6 side are also electrically separated.
  • an oxide film can be formed in the n-type region 2 by the heat of laser light described later, and the passivation property of the n-type region 2 can be enhanced by the oxide film. .
  • the effect of improving the open-circuit voltage due to the improvement in passivation. can be obtained.
  • the i-type semiconductor layer 3 and the p-type semiconductor layer 4 are stacked in this order on the first surface 1a of the n-type single crystal silicon substrate 1, and then the p-type semiconductor layer 4 is formed.
  • a conductive layer 23 is formed, and then a laser beam is irradiated to remove the conductive layer 22, the p-type semiconductor layer 4, and the i-type semiconductor layer 3 in the thickness direction, thereby forming a separation groove.
  • the conductive layer 22 is electrically separated by the separation groove, whereby the second electrode 5 and the first electrode 6 are obtained.
  • the p-type semiconductor layer 4 is electrically separated by the separation groove, and the p on the second electrode 5 side is obtained.
  • the first side wall surface 51c includes an exposed surface of the first electrode 6, an exposed surface of the p-type semiconductor layer 4b, and an exposed surface of the i-type semiconductor layer 3b.
  • the second sidewall surface 51d is composed of an exposed surface of the second electrode 5, an exposed surface of the p-type semiconductor layer 4a, and an exposed surface of the i-type semiconductor layer 3a.
  • an oxide film can be formed on the surface of n-type region 2 by increasing the irradiation power of laser light in the range of + 10% to + 100% compared to the case of the seventh embodiment.
  • FIG. 13 is a schematic cross-sectional view of a photoelectric conversion device according to Embodiment 9, which is another example of the photoelectric conversion device of the present invention.
  • the separation groove is between the second electrode 5 and the first electrode 6, the p-type semiconductor layer 4a on the second electrode 5 side, and the p-type semiconductor layer 4b on the first electrode 6 side.
  • the i-type semiconductor layer 3a on the second electrode 5 side and the i-type semiconductor layer 3b on the first electrode 6 side are electrically separated and reach the n-type region 2 It is a feature.
  • the contact resistance between the p-type semiconductor layer 4b and the first electrode 6 is reduced by using the p-type semiconductor layer 4b made of a microcrystalline semiconductor such as microcrystalline silicon. be able to.
  • the p-type semiconductor layer 4a on the second electrode 5 side and the p-type semiconductor layer 4b on the first electrode 6 side are only electrically separated by the separation groove.
  • the i-type semiconductor layer 3a on the second electrode 5 side and the i-type semiconductor layer 3b on the first electrode 6 side are also electrically separated.
  • an oxide film is formed on the n-type region 2 exposed by removing a part of the second region 11 by laser light irradiation, as will be described later, by the heat of the laser light. And the passivation property of the n-type region 2 can be enhanced by the oxide film.
  • the leakage current amount similar to that of the photoelectric conversion device according to the eighth embodiment can be reduced, so that the effect of improving the FF of the photoelectric conversion device can be exhibited. Furthermore, in the photoelectric conversion device of the ninth embodiment, since the passivation property of the n-type region 2 can be improved by forming an oxide film on the surface of the n-type region 2, the open-circuit voltage of the photoelectric conversion device is also high. can do.
  • the i-type semiconductor layer 3 and the p-type semiconductor layer 4 are stacked in this order on the first surface 1a of the n-type single crystal silicon substrate 1, and then the p-type semiconductor layer 4 is formed.
  • a conductive layer 22 is formed, and then a laser beam is irradiated to remove the conductive layer 22, the p-type semiconductor layer 4, the i-type semiconductor layer 3, and the n-type region 2 in the thickness direction, thereby forming a separation groove. To do. Then, the conductive layer 22 is electrically separated by the separation groove, whereby the second electrode 5 and the first electrode 6 are obtained.
  • the p-type semiconductor layer 4 is electrically separated by the separation groove, and the p on the second electrode 5 side is obtained.
  • Type semiconductor layer 4a and p-type semiconductor layer 4b on the first electrode 6 side, and the i-type semiconductor layer 3 is electrically separated by the separation groove, and the i-type semiconductor layer 3a on the second electrode 5 side and the first electrode 6 side I-type semiconductor layer 3b.
  • FIG. 14 is a schematic cross-sectional view of the photoelectric conversion device according to Embodiment 10, which is another example of the photoelectric conversion device of the present invention.
  • FIG. 39 is a schematic plan view of the first surface 1a of the n-type single crystal silicon substrate 1 of the photoelectric conversion device according to the tenth embodiment as viewed from above.
  • the photoelectric conversion device according to the tenth embodiment is characterized in that the center line 51 b of the separation groove shown in FIG. 39 is included in a region corresponding to the second region 11. As shown in FIG.
  • the center line 51b of the separation groove is a straight line drawn as a set of midpoints 51f of the interval W1 between the first side wall surface 51c and the second side wall surface 51d of the separation groove.
  • This is an imaginary line perpendicular to the width direction of the interval W1 formed by projecting the curve from the direction perpendicular to the first surface 1a of the n-type single crystal silicon substrate 1 onto the first surface 1a.
  • the areas corresponding to the second area 11 are areas above and below the second area 11.
  • the photoelectric conversion device of Embodiment 10 can be manufactured as follows, for example. First, after the i-type semiconductor layer 3 and the p-type semiconductor layer 4 are stacked in this order on the first surface 1a of the n-type single crystal silicon substrate 1, one of each of the i-type semiconductor layer 3 and the p-type semiconductor layer 4 is stacked. The portion is removed by etching in the thickness direction. Thereafter, a conductive layer 22 is formed on the exposed surface of the i-type semiconductor layer 3, the p-type semiconductor layer 4 and the second region 11 by etching, and then a portion of the conductive layer 22 is made thick by irradiating with laser light.
  • the photoelectric conversion device of Embodiment 10 can be manufactured by forming separation grooves by removing in the direction.
  • a separation groove for electrically separating the second electrode 5 and the first electrode 6 is formed by laser light irradiation, and when the second electrode 5 and the first electrode 6 are formed. Since the resist patterning step is unnecessary, the number of steps can be reduced, and thus the manufacturing cost of the photoelectric conversion device can be reduced.
  • the first electrode 6 covers the entire surface of the p-type semiconductor layer 4 located above the first region 12, the first electrode 6 and the p-type semiconductor layer 4 are covered. Can be reduced, and the FF of the photoelectric conversion device can be improved.
  • the first electrode 6 covers the entire surface of the p-type semiconductor layer 4 located above the first region 12, the p-type semiconductor above the first region 12 is used.
  • the entire layer 4 can function as a p + region.
  • FIG. 15 is a schematic cross-sectional view of the photoelectric conversion device according to Embodiment 11, which is another example of the photoelectric conversion device of the present invention.
  • the photoelectric conversion device according to the eleventh embodiment is characterized in that the center line 51 b of the separation groove shown in FIG. 39 is included in a region corresponding to the first region 12.
  • the areas corresponding to the first area 12 are areas above and below the first area 12.
  • the area of the second electrode 5 can be increased.
  • the contact area between the n wiring 72 of the wiring sheet 70 shown in FIG. 15 for taking out the current generated in the photoelectric conversion device of the eleventh embodiment and the second electrode 5 of the photoelectric conversion device of the eleventh embodiment. 15 and the contact area between the p wiring 73 of the wiring sheet 70 shown in FIG. 15 and the first electrode 6 of the photoelectric conversion device of the eleventh embodiment can be increased.
  • the FF of the photoelectric conversion device in Embodiment 11 can be improved and the conversion efficiency can be improved.
  • the area ratio between the first region 12 and the second region 11 is such that the area of the first region 12 that is a p-type region is an n-type region in order to increase the carrier collection efficiency of holes that are easily recombined.
  • the area is designed to be larger than the area 11. That is, when the area of the second region 11 which is an n-type region is relatively small, the integration pitch becomes finer for the purpose of improving the short circuit current and the FF, and the second region 11 may be particularly small. .
  • the area of the second region 11 is reduced by providing the separation groove above the first region 12 as in the photoelectric conversion device of the eleventh embodiment, the area of the second electrode 5 is increased.
  • FIG. 16 is a schematic cross-sectional view of the photoelectric conversion device according to Embodiment 12, which is another example of the photoelectric conversion device of the present invention.
  • the center line 51b of the separation groove shown in FIG. 39 is included in the region corresponding to the second region 11, and the separation groove reaches the p-type semiconductor layers 4a and 4b. It is characterized by being.
  • the leakage current can be reduced by increasing the shunt resistance between the second electrode 5 and the first electrode 6. That is, by using a microcrystalline semiconductor such as microcrystalline silicon for the p-type semiconductor layer 4b, the contact resistance between the p-type semiconductor layer 4b and the first electrode 6 can be reduced. In this case, If the p-type semiconductor layer 4b is not separated, the shunt resistance is reduced and the leakage current is increased. That is, since the p-type semiconductor layer 4b made of a microcrystalline semiconductor such as microcrystalline silicon and the separation of the p-type semiconductor layer 4b are used in combination, the contact resistance can be reduced without shunt leakage. The FF of the conversion device can be further improved.
  • FIG. 17 is a schematic cross-sectional view of a photoelectric conversion device according to a thirteenth embodiment which is another example of the photoelectric conversion device of the present invention.
  • the center line 51b of the separation groove shown in FIG. 39 is included in the region corresponding to the first region 12, and the separation groove reaches the i-type semiconductor layers 4a and 4b. It is characterized by being.
  • the area of the second electrode 5 can be increased.
  • the contact area between the second electrode 5 and the collector electrode such as the wiring of the wiring sheet for taking out the current generated in the photoelectric conversion device to the outside can be increased.
  • the contact resistance between the second electrode 5 and the first electrode 6 due to the displacement of the collector electrode can be reduced. Thereby, FF of a photoelectric conversion apparatus can be improved and conversion efficiency can be improved.
  • FIG. 18 is a schematic cross-sectional view of the photoelectric conversion device of Embodiment 14 which is another example of the photoelectric conversion device of the present invention.
  • the center line 51b of the separation groove shown in FIG. 39 is included in the region corresponding to the second region 11, and the separation groove reaches the i-type semiconductor layer 3. It is characterized by.
  • the p-type semiconductor layer 4a on the second electrode 5 side and the p-type semiconductor layer 4b on the first electrode 6 side are only electrically separated by the separation groove.
  • the i-type semiconductor layer 3 is also electrically isolated.
  • the passivation property of the surface of the second region 11 can be improved. Therefore, in the photoelectric conversion device according to the fourteenth embodiment, the amount of leakage current generated between the second electrode 5 and the first electrode 6 can be further reduced, so that the FF of the photoelectric conversion device is further improved. Can do.
  • FIG. 19 is a schematic cross-sectional view of a photoelectric conversion device according to a fifteenth embodiment, which is another example of the photoelectric conversion device of the present invention.
  • the center line 51b of the separation groove shown in FIG. 39 is included in the region corresponding to the first region 12, and the separation groove reaches the i-type semiconductor layer 3. It is characterized by.
  • the area of the second electrode 5 can be increased.
  • the contact area between the second electrode 5 and the collector electrode such as the wiring of the wiring sheet for taking out the current generated in the photoelectric conversion device to the outside can be increased.
  • the contact resistance between the second electrode 5 and the first electrode 6 due to the displacement of the collector electrode can be reduced. Thereby, FF of a photoelectric conversion apparatus can be improved and conversion efficiency can be improved.
  • FIG. 20 is a schematic cross-sectional view of the photoelectric conversion device of Embodiment 16 which is another example of the photoelectric conversion device of the present invention.
  • the center line 51b of the separation groove shown in FIG. 39 is included in the region corresponding to the second region 11, and the separation groove reaches the i-type semiconductor layers 3a and 3b. It is characterized by being.
  • the p-type semiconductor layer 4a on the second electrode 5 side and the p-type semiconductor layer 4b on the first electrode 6 side are only electrically separated by the separation groove.
  • the i-type semiconductor layer 3a on the second electrode 5 side and the i-type semiconductor layer 3b on the first electrode 6 side are also electrically separated.
  • FIG. 21 is a schematic cross-sectional view of the photoelectric conversion device according to the seventeenth embodiment which is another example of the photoelectric conversion device of the present invention.
  • the center line 51b of the separation groove shown in FIG. 39 is included in the region corresponding to the first region 12, and the separation groove reaches the i-type semiconductor layers 3a and 3b. It is characterized by being.
  • the separation groove is located above the first region 12, the area of the second electrode 5 can be increased.
  • the contact area between the second electrode 5 and the collector electrode such as the wiring of the wiring sheet for taking out the current generated in the photoelectric conversion device to the outside can be increased.
  • the contact resistance between the second electrode 5 and the first electrode 6 due to the displacement of the collector electrode can be reduced. Thereby, FF of a photoelectric conversion apparatus can be improved and conversion efficiency can be improved.
  • FIG. 22 is a schematic cross-sectional view of a photoelectric conversion device according to an eighteenth embodiment which is another example of the photoelectric conversion device of the present invention.
  • the center line 51b of the separation groove shown in FIG. 39 is included in the region corresponding to the second region 11, and the separation groove reaches the n-type region 2. It is a feature.
  • the contact resistance between the p-type semiconductor layer 4b and the first electrode 6 is reduced by using the p-type semiconductor layer 4b made of a microcrystalline semiconductor such as microcrystalline silicon. be able to.
  • the p-type semiconductor layer 4a on the second electrode 5 side and the p-type semiconductor layer 4b on the first electrode 6 side are only electrically separated by the separation groove.
  • the i-type semiconductor layer 3a on the second electrode 5 side and the i-type semiconductor layer 3b on the first electrode 6 side are also electrically separated.
  • an oxide film is applied to the n-type region 2 exposed by removing a part of the second region 11 by laser light irradiation as will be described later by the heat of the laser light.
  • the oxide film By forming the oxide film, the passivation property of the n-type region 2 can be improved.
  • the amount of leakage current similar to that of the photoelectric conversion device according to the eighteenth embodiment can be reduced. Therefore, the same FF improvement effect as that of the photoelectric conversion device according to the eighteenth embodiment. Can be expressed. Furthermore, in the photoelectric conversion device of the eighteenth embodiment, by forming an oxide film on the surface of the n-type region 2, the passivation property of the n-type region 2 can be improved, so that the open-circuit voltage of the photoelectric conversion device is also high. can do. Thereby, in the photoelectric conversion device of Embodiment 18, the characteristics of the photoelectric conversion device can be enhanced.
  • FIG. 23 is a schematic cross-sectional view of the photoelectric conversion device of Embodiment 19 which is another example of the photoelectric conversion device of the present invention.
  • the center line 51b of the separation groove shown in FIG. 39 is included in the region corresponding to the first region 12, and the separation groove is the n-type of the n-type single crystal silicon substrate 1. It is characterized by reaching to an area other than the area 2.
  • the separation groove is located above the first region 12, the area of the second electrode 5 can be increased.
  • the contact area between the second electrode 5 and the collector electrode such as the wiring of the wiring sheet for taking out the current generated in the photoelectric conversion device to the outside can be increased.
  • the contact resistance between the second electrode 5 and the first electrode 6 due to the displacement of the collector electrode can be reduced. Thereby, FF of a photoelectric conversion apparatus can be improved and conversion efficiency can be improved.
  • FIG. 24 is a schematic cross-sectional view of the photoelectric conversion device according to the twentieth embodiment which is another example of the photoelectric conversion device of the present invention.
  • the periphery of the n-type single crystal silicon substrate 1 has a portion where the i-type semiconductor layer 3 and the p-type semiconductor layer 4 protrude outward from the first electrode 6. It is characterized by.
  • the first electrode 6, the n-type single crystal silicon substrate 1, and the protrusions of the i-type semiconductor layer 3 and the p-type semiconductor layer 4 at the periphery of the n-type single crystal silicon substrate 1 Therefore, the occurrence of leakage current at the peripheral edge of the n-type single crystal silicon substrate 1 can be reduced. Thereby, FF of a photoelectric conversion apparatus can be improved.
  • FIG. 25 is a schematic cross-sectional view of the photoelectric conversion device of Embodiment 21, which is another example of the photoelectric conversion device of the present invention.
  • the dielectric layer 41 is formed on the entire surface of the second region 11, and the dielectric layer 41 made of a silicon oxide film is formed between the second electrode 5 and the second region 11. It is characterized by having an intervening portion.
  • the dielectric layer 41 includes a region 41a in physical contact with the second region 11 and the second electrode 5, and a region 41b in physical contact with the second region 11 and the i-type semiconductor layer 3. And have.
  • the thickness of the dielectric layer 41 can be, for example, not less than 0.5 nm and not more than 5 nm.
  • a silicon nitride film or an aluminum oxide film may be used as the dielectric layer 41.
  • the second electrode 5 and the second region 11 are electrically connected by the tunnel current, while in the region 41b of the dielectric layer 41, the dielectric material is used.
  • the layer 41 enhances the passivation of the second region 11.
  • FIG. 26A in the same manner as in the first embodiment, an n-type single crystal silicon substrate in which the second region 11 is formed in a part of the first surface 1a using the diffusion mask 21 as a mask.
  • a dielectric layer 41 made of a silicon oxide film is formed on the first first surface 1 a so as to cover the diffusion mask 21.
  • the diffusion mask 21 and the dielectric layer 41 on the n-type single crystal silicon substrate 1 are removed by hydrofluoric acid treatment.
  • the dielectric layer 41 made of a silicon oxide film is formed thicker on the n-type region 2 because the growth rate is different between the n-type region 2 and the diffusion mask 21.
  • the dielectric layer 41 made of a silicon oxide film can be selectively left only on the mold region 2.
  • the i-type semiconductor layer 3 and the p-type semiconductor layer 4 are stacked in this order on the n-type single crystal silicon substrate 1 so as to cover the dielectric layer 41.
  • an etching mask 23 patterned so as to have an opening at a predetermined position is formed on the p-type semiconductor layer 4.
  • a part of the n-type region 2, the i-type semiconductor layer 3 and the p-type semiconductor layer 4 are removed by etching in the thickness direction using the etching mask 23 as a mask. .
  • the etching mask 23 is removed from the p-type semiconductor layer 4 as shown in FIG.
  • the conductive layer 22 is formed so as to cover the surface of the n-type region 2 and the surface of the p-type semiconductor layer 4 exposed by the etching.
  • an etching mask 24 patterned so as to have an opening at a predetermined position is formed on the surface of the conductive layer 22.
  • the etching mask 24 the same one as the etching mask 23 can be used.
  • the conductive layer 22 is etched using the etching mask 24 as a mask, and a part of the conductive layer 22 is removed, whereby the second electrode 5 and the first electrode 6 are removed.
  • the etching mask 24 is removed from the conductive layer 22 to manufacture the photoelectric conversion device of the twenty-first embodiment.
  • FIG. 27 is a schematic cross-sectional view of the photoelectric conversion device of Embodiment 22 which is another example of the photoelectric conversion device of the present invention.
  • the photoelectric conversion device according to the twenty-second embodiment is characterized in that the dielectric layer 41 has only the region 41 a that is in physical contact with the second region 11 and the second electrode 5.
  • the second electrode 5 and the second region 11 are electrically connected by a tunnel current, and the second electrode 5 is in contact with the second region 11. Even if not, it can function as a photoelectric conversion device.
  • FIG. 28 is a schematic cross-sectional view of a photoelectric conversion device according to a twenty-third embodiment which is another example of the photoelectric conversion device of the present invention.
  • the dielectric layer 41 is physically in contact with the second region 11 and the second electrode 5, the second region 11 and the i-type semiconductor layer 3.
  • a through hole 61 that penetrates the dielectric layer 41 in the thickness direction is formed in the region 41 a of the dielectric layer 41, and the second electrode 5 passes through the through hole 61.
  • the second region 11 are in physical contact with each other.
  • the second electrode 5 and the second region 11 are in contact with each other in the region 41a of the dielectric layer 41, the second electrode 5 and the second region 11 are caused by the tunnel current. There is no need to establish conduction between them. Therefore, in the photoelectric conversion device of the twenty-third embodiment, the FF can be further improved by reducing the series resistance between the second electrode 5 and the second region 11.
  • FIG. 29 is a schematic cross-sectional view of the photoelectric conversion device of Embodiment 24, which is another example of the photoelectric conversion device of the present invention.
  • the photoelectric conversion device according to the twenty-fourth embodiment is characterized in that a dielectric layer 41 is formed on the fourth region 32.
  • the photoelectric conversion device since the passivation property of the fourth region 32 can be improved by forming the thick dielectric layer 41 on the fourth region 32, the photoelectric conversion device is opened.
  • the voltage can be improved.
  • the thickness of the dielectric layer 41 can be, for example, not less than 50 nm and not more than 100 nm.
  • FIG. 30A in the same manner as in the first embodiment, an n-type single crystal silicon substrate in which the second region 11 is formed in a part of the first surface 1a using the diffusion mask 21 as a mask.
  • a dielectric layer 41 made of a silicon oxide film is formed on the first first surface 1 a so as to cover the diffusion mask 21.
  • the diffusion mask 21 and the dielectric layer 41 on the n-type single crystal silicon substrate 1 are removed by hydrofluoric acid treatment.
  • the dielectric layer 41 is left on the n-type region 2 by utilizing the difference in the etching rate between the region on the n-type region 2 and the region other than on the n-type region 2.
  • the i-type semiconductor layer 3 and the p-type semiconductor layer 4 are stacked in this order on the n-type single crystal silicon substrate 1 so as to cover the dielectric layer 41.
  • an etching mask 23 patterned so as to have an opening at a predetermined position is formed on the p-type semiconductor layer 4.
  • a part of the n-type region 2, the i-type semiconductor layer 3 and the p-type semiconductor layer 4 are removed by etching in the thickness direction using the etching mask 23 as a mask. .
  • the etching mask 23 is removed from the p-type semiconductor layer 4.
  • the conductive layer 22 is formed so as to cover the surface of the n-type region 2 and the surface of the p-type semiconductor layer 4 exposed by the etching.
  • an etching mask 24 patterned so as to have an opening at a predetermined position is formed on the surface of the conductive layer 22.
  • the conductive layer 22 is etched using the etching mask 24 as a mask, and a part of the conductive layer 22 is removed, whereby the second electrode 5 and the first electrode 6 are formed. Form.
  • the etching mask 24 is removed from the conductive layer 22 to produce the photoelectric conversion device of the twenty-fourth embodiment.
  • FIG. 40 shows a schematic cross-sectional view of a modified example of the photoelectric conversion device of the twenty-fourth embodiment.
  • the modification of the photoelectric conversion device according to the twenty-fourth embodiment shown in FIG. 40 is characterized in that the second electrode 5 and the n-type region 2 have a portion that conducts through the dielectric layer 41. Yes.
  • a modification of the photoelectric conversion device in Embodiment 24 can be formed by a method using laser scribing.
  • FIG. 31 is a schematic cross-sectional view of the photoelectric conversion device of Embodiment 25, which is another example of the photoelectric conversion device of the present invention.
  • the separation groove reaches the dielectric layer 41, and the p-type semiconductor layer 4a on the second electrode 5 side between the second electrode 5 and the first electrode 6 is separated by the separation groove.
  • the p-type semiconductor layer 4b on the first electrode 6 side and the i-type semiconductor layer 3a on the second electrode 5 side and the i-type semiconductor layer 3b on the first electrode 6 side are electrically separated. It is a feature.
  • the electrical separation step of the conductive layer 22, the electrical separation step of the p-type semiconductor layer 4, and the electrical separation step of the i-type semiconductor layer 3 are performed once by laser. Since it can be performed only by light irradiation, the man-hours can be further reduced. Furthermore, in the photoelectric conversion device of the twenty-fifth embodiment, since dielectric layer 41 exists on first surface 1a of n-type single crystal silicon substrate 1 corresponding to the irradiated portion of laser light, the dielectric layer 41 can suppress the laser beam irradiation damage to the n-type single crystal silicon substrate 1.
  • the passivation property of the fourth region 32 can be improved by forming the thick dielectric layer 41 on the fourth region 32.
  • the open circuit voltage can be improved.
  • the patterning process of the etching mask 23 for etching the i-type semiconductor layer 3 and the p-type semiconductor layer 4 in the thickness direction, and the conductive layer 22 in the thickness direction Since it is not necessary to perform the patterning process of the etching mask 24 for etching, man-hours can be reduced and manufacturing costs can be reduced.
  • FIG. 32 is a schematic cross-sectional view of the photoelectric conversion device according to the twenty-sixth embodiment.
  • an n-type semiconductor layer 81 made of n-type amorphous silicon is provided between the second electrode 5 and the first electrode 6 and the p-type semiconductor layer 4a. It is a feature.
  • the n-type semiconductor layer 81 is provided between the second electrode 5 and the n-type region 2, the second electrode 5 and the n-type region are formed by the n-type semiconductor layer 81. 2 can be improved, and the contact resistance can be reduced.
  • the conductivity of the n-type semiconductor layer 81 is preferably 1 ⁇ 10 ⁇ 7 S / cm or more and 1 ⁇ 10 ⁇ 4 S / cm or less.
  • the n-type semiconductor layer 81 is a layer containing amorphous silicon.
  • the layer containing amorphous silicon can be confirmed by observing a broad peak in the vicinity of 480 cm ⁇ 1 in the Raman spectroscopic measurement of the n-type semiconductor layer 81.
  • the layer containing amorphous silicon may be microcrystalline silicon in which a broad peak is observed in the vicinity of 480 cm ⁇ 1 in the Raman spectroscopic measurement of the n-type semiconductor layer 81.
  • the conductivity of the n-type semiconductor layer 81 is 1 ⁇ 10 ⁇ 7 S / cm or more, an increase in series resistance can be suppressed, so that a decrease in FF of the photoelectric conversion device can be suppressed.
  • the conductivity of the n-type semiconductor layer 81 is 1 ⁇ 10 ⁇ 4 S / cm or less, a decrease in the shunt resistance between the second electrode 5 and the first electrode 6 can be suppressed, so that the photoelectric conversion A reduction in the FF of the apparatus can be suppressed.
  • the leakage current between the second electrode 5 and the first electrode 6 can be reduced by setting the conductivity of the n-type semiconductor layer 81 to 1 ⁇ 10 ⁇ 4 S / cm or less.
  • the FF of the photoelectric conversion device can be improved.
  • the i-type semiconductor layer 3 and the p-type semiconductor layer 4 are formed on the entire surface of the first surface 1a of the n-type single crystal silicon substrate 1. Laminate sequentially.
  • a diffusion mask 21 made of silicon oxide is formed on the p-type semiconductor layer 4.
  • the i-type semiconductor layer 3 and the p-type semiconductor layer 4 exposed from the diffusion mask 21 are removed by etching using the diffusion mask 21 as a mask.
  • the diffusion mask 21 is removed from the p-type semiconductor layer 4.
  • the n-type semiconductor layer 81 is covered so as to cover the surfaces of the n-type region 2 and the p-type semiconductor layer 4 exposed by the etching.
  • the conductive layer 22 is formed on the surface of the n-type semiconductor layer 81. Thereafter, the conductive layer 22 is separated by laser etching, and the second electrode 5 and the first electrode 6 are formed on the surface of the p-type semiconductor layer 4, thereby completing the photoelectric conversion device of the twenty-sixth embodiment.
  • FIG. 34 is a schematic cross-sectional view of the photoelectric conversion device of Embodiment 27.
  • the photoelectric conversion device according to the twenty-seventh embodiment shown in FIG. 34 includes a second i-type semiconductor layer 92 made of i-type amorphous silicon on the first surface 1a of the n-type single crystal silicon substrate 1, and a second The n-type region 2 (second conductivity type semiconductor layer) made of n-type amorphous silicon on the i-type semiconductor layer 92 is included, and a part of the first electrode 6 is located above the second region 11. It is characterized by being provided.
  • the region of the second region 11 that overlaps the first electrode 6 is defined as an overlap region 91, and the overlap region 91 extends from the inner end 93 of the second region 11 to the boundary 94 with the first region 12. It is an area.
  • FIG. 35A shows a schematic cross-sectional view of a modification of the photoelectric conversion device of the embodiment 27.
  • FIG. The photoelectric conversion device according to the twenty-seventh embodiment shown in FIG. 35A is replaced with the second i-type semiconductor layer 92 and the n-type region 2 on the second i-type semiconductor layer 92 shown in FIG.
  • An n-type region 2 is provided below the second region 11 of the n-type single crystal silicon substrate 1.
  • FIG. 35B shows the second conductivity type impurity concentration (phosphorus) in the second region 11 of the first surface 1a of the n-type single crystal silicon substrate 1 of the photoelectric conversion device of the embodiment 27 shown in FIG. (Concentration) change.
  • the vertical axis indicates the second conductivity type impurity concentration [atoms / cm 3 ], and the horizontal axis indicates the position of the second region 11.
  • FIG. 36 (a) shows a schematic cross-sectional view of a further modification of the photoelectric conversion device according to the twenty-seventh embodiment.
  • the photoelectric conversion device according to the twenty-seventh embodiment shown in FIG. 36A is characterized by including a dielectric layer 41 between the n-type region 2 and the i-type semiconductor layer 3 shown in FIG. Yes.
  • FIG. 36B shows the film thickness of the dielectric layer 41 on the second region 11 of the first surface 1a of the n-type single crystal silicon substrate 1 of the photoelectric conversion device of the embodiment 27 shown in FIG. Shows changes.
  • the vertical axis indicates the film thickness of the dielectric layer 41
  • the horizontal axis indicates the position of the second region 11.
  • the photoelectric conversion device of Embodiment 27 has the overlap region 91, as shown in FIG. 38 as compared with the photoelectric conversion device shown in the schematic cross-sectional view of FIG.
  • the reverse saturation current can be increased and the breakdown voltage can be reduced. Therefore, in this case, resistance to a hot spot, which is a local heating phenomenon that occurs when a shadow is added to a part of the photoelectric conversion module in which a plurality of the photoelectric conversion devices of Embodiment 27 are electrically connected, is provided. Can be high.
  • the photoelectric conversion device with the shadow has reverse characteristics as shown by the curve B in FIG. 38
  • a high voltage is applied to the photoelectric conversion device with the shadow
  • the photoelectric conversion device with the shadow has a difference.
  • the sealing material for sealing the photoelectric conversion device is denatured and discolored, and worse, the photoelectric conversion device may be destroyed.
  • the photoelectric conversion device of Embodiment 27 shows reverse characteristics having a small breakdown voltage as shown by the curve A in FIG. 38, the calorific value of the photoelectric conversion device shaded can be reduced. Since the sealing material that seals the photoelectric conversion device is denatured or discolored, and the possibility that the photoelectric conversion device is destroyed can be suppressed to a low level, the photoelectric conversion module has high hot spot resistance and high reliability. .
  • the second conductivity type impurity concentration of the second region 11 is set to 1 ⁇ 10 19 [atoms / cm 3 ] or more, and the boundary 94 between the second region 11 and the first region 12 is the second region 11 of the second region 11. More preferably, the two-conductivity type impurity concentration (phosphorus concentration) is less than 1 ⁇ 10 17 [atoms / cm 3 ].
  • an n-type region 2 having a taper at the periphery can be formed.
  • the breakdown current flows in the vicinity of the breakdown voltage of the curve A in FIG. 38, the breakdown current does not concentrate only on the boundary 94 between the first region 12 and the second region 11, and the inside of the second region 11. It flows through the entire tapered portion of the n-type region 2 of the overlap region 91 extending from the side end portion 93 to the boundary 94. Therefore, since the current density of the breakdown current flowing at the interface between the first region 12 and the second region 11 can be reduced and the device can be prevented from being destroyed due to the heat generated by the breakdown current, a highly reliable photoelectric conversion module can be obtained. Can be provided.
  • the film thickness of the dielectric layer 41 is reduced from the end 93 on the inner side of the second region 11 toward the boundary 94 between the second region 11 and the first region 12.
  • the amount of heat generated when the photoelectric conversion device is shaded can be reduced, and the possibility that the sealing material sealing the photoelectric conversion device is denatured or discolored and the photoelectric conversion device is destroyed is kept low. Therefore, the photoelectric conversion module having high hot spot resistance and high reliability can be obtained.
  • the width of the overlap region 91 (the length of the double arrow in the overlap region 91 in FIGS. 34 to 36) is narrowed, the absolute value of the breakdown voltage shown in FIG.
  • the absolute value of the breakdown voltage shown in FIG. When the width of the region 91 is increased, the absolute value of the breakdown voltage shown in FIG. 38 can be reduced. Therefore, the breakdown voltage can be controlled by controlling the width of the overlap region 91. Note that if the absolute value of the breakdown voltage of the photoelectric conversion device is made too small, the reverse saturation current becomes too large and the open-circuit voltage is lowered and the conversion efficiency is lowered.
  • the width of the overlap region 91 is preferably 10 ⁇ m or more and 100 ⁇ m or less.
  • FIG. 41 is a schematic cross-sectional view of the photoelectric conversion device according to the twenty-eighth embodiment.
  • the photoelectric conversion device according to the twenty-eighth embodiment shown in FIG. 41 includes a second i-type semiconductor layer 92 made of i-type amorphous silicon on the first region 12 of the n-type single crystal silicon substrate 1, and a second a p-type region 95 (first conductivity type semiconductor layer) made of p-type amorphous silicon on the i-type semiconductor layer 92, and a part of the second electrode 5 is located above the first region 12. It is characterized by being provided.
  • the region of the first region 12 that overlaps the second electrode 5 is defined as an overlap region 91, and the overlap region 91 extends from the inner end 93 of the first region 12 to the boundary 94 with the second region 11. It is an area.
  • FIG. 42 is a schematic cross-sectional view of a modification of the photoelectric conversion device according to the twenty-eighth embodiment.
  • the photoelectric conversion device according to the twenty-eighth embodiment shown in FIG. 42 is replaced with the second i-type semiconductor layer 92 and the p-type region 95 on the second i-type semiconductor layer 92 shown in FIG.
  • a p-type region 95 is provided below the first region 12 of the crystalline silicon substrate 1.
  • the photoelectric conversion device of the twenty-eighth embodiment is also shaded by some of the photoelectric conversion modules in which a plurality of the photoelectric conversion devices of the twenty-eighth embodiment are electrically connected for the same reason as the photoelectric conversion device of the twenty-seventh embodiment.
  • the hot spot resistance can be increased.
  • Embodiment 28 Since the explanation other than the above in Embodiment 28 is the same as that in Embodiments 1 to 27, the explanation thereof is omitted.
  • the present invention can be used for a photoelectric conversion device, particularly for a back electrode type solar cell.

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Abstract

L'invention concerne un appareil de conversion photoélectrique présentant une meilleure productivité. Cet appareil de conversion photoélectrique comprend : une couche de semi-conducteur de type i (3) et une couche de semi-conducteur d'un premier type de conductivité (4) qui se trouvent au-dessus d'une première surface (1a) d'un substrat semi-conducteur (1) ; ainsi qu'une première électrode (6) et une seconde électrode (5) qui se trouvent sur la couche de semi-conducteur d'un premier type de conductivité (4). La première surface (1a) comporte une première région (12) et une seconde région (11) qui est la première région de surface autre que la première région (12). Une partie du substrat semi-conducteur (1) au-dessous de la seconde région (11) comporte une région d'un second type de conductivité (2) ayant une plus grande concentration d'impureté du second type de conductivité que le substrat semi-conducteur (1). La seconde électrode (5) est agencée au-dessus de la seconde région (11) et la première électrode (6) est agencée au-dessus de la première région (12). L'appareil de conversion photoélectrique comporte une partie ayant la couche de semi-conducteur de type i (3) et la couche de semi-conducteur d'un premier type de conductivité (4) entre la seconde région (11) et la seconde électrode (5) et la seconde électrode (5) et la seconde région (11) sont raccordées électriquement l'une à l'autre.
PCT/JP2014/083337 2014-02-17 2014-12-17 Appareil de conversion photoélectrique WO2015122096A1 (fr)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3336905A4 (fr) * 2016-10-25 2018-11-21 Shin-Etsu Chemical Co., Ltd Cellule solaire à haut rendement de conversion photoélectrique et procédé de fabrication de cellule solaire à haut rendement de conversion photoélectrique
CN117727838A (zh) * 2024-02-07 2024-03-19 晶科能源(海宁)有限公司 太阳能电池及其制备方法、光伏组件

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6706779B2 (ja) * 2015-09-30 2020-06-10 パナソニックＩｐマネジメント株式会社 太陽電池および太陽電池モジュール
US10784396B2 (en) 2015-09-30 2020-09-22 Panasonic Intellectual Property Management Co., Ltd. Solar cell, solar cell module, and production method for solar cell
US10923610B2 (en) 2015-09-30 2021-02-16 Panasonic Intellectual Property Management Co., Ltd. Solar cell and solar cell module
JP2021129085A (ja) * 2020-02-17 2021-09-02 パナソニック株式会社 太陽電池セル

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001111080A (ja) * 1999-10-14 2001-04-20 Sony Corp 半導体素子の製造方法
JP2010123859A (ja) * 2008-11-21 2010-06-03 Kyocera Corp 太陽電池素子および太陽電池素子の製造方法
JP2013197538A (ja) * 2012-03-22 2013-09-30 Sharp Corp 光電変換素子の製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001111080A (ja) * 1999-10-14 2001-04-20 Sony Corp 半導体素子の製造方法
JP2010123859A (ja) * 2008-11-21 2010-06-03 Kyocera Corp 太陽電池素子および太陽電池素子の製造方法
JP2013197538A (ja) * 2012-03-22 2013-09-30 Sharp Corp 光電変換素子の製造方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3336905A4 (fr) * 2016-10-25 2018-11-21 Shin-Etsu Chemical Co., Ltd Cellule solaire à haut rendement de conversion photoélectrique et procédé de fabrication de cellule solaire à haut rendement de conversion photoélectrique
US11049988B2 (en) 2016-10-25 2021-06-29 Shin-Etsu Chemical Co., Ltd. High photoelectric conversion efficiency solar cell and method for manufacturing high photoelectric conversion efficiency solar cell
CN117727838A (zh) * 2024-02-07 2024-03-19 晶科能源(海宁)有限公司 太阳能电池及其制备方法、光伏组件
CN117727838B (zh) * 2024-02-07 2024-05-10 晶科能源(海宁)有限公司 太阳能电池及其制备方法、光伏组件

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