WO2015111923A1 - Carte de circuit imprimé à composants incrustés - Google Patents

Carte de circuit imprimé à composants incrustés Download PDF

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Publication number
WO2015111923A1
WO2015111923A1 PCT/KR2015/000650 KR2015000650W WO2015111923A1 WO 2015111923 A1 WO2015111923 A1 WO 2015111923A1 KR 2015000650 W KR2015000650 W KR 2015000650W WO 2015111923 A1 WO2015111923 A1 WO 2015111923A1
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WO
WIPO (PCT)
Prior art keywords
insulating substrate
printed circuit
circuit board
thickness
insulating
Prior art date
Application number
PCT/KR2015/000650
Other languages
English (en)
Korean (ko)
Inventor
김우영
Original Assignee
엘지이노텍 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 엘지이노텍 주식회사 filed Critical 엘지이노텍 주식회사
Publication of WO2015111923A1 publication Critical patent/WO2015111923A1/fr

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    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F16—ENGINEERING ELEMENTS AND UNITS; GENERAL MEASURES FOR PRODUCING AND MAINTAINING EFFECTIVE FUNCTIONING OF MACHINES OR INSTALLATIONS; THERMAL INSULATION IN GENERAL
    • F16K—VALVES; TAPS; COCKS; ACTUATING-FLOATS; DEVICES FOR VENTING OR AERATING
    • F16K1/00—Lift valves or globe valves, i.e. cut-off apparatus with closure members having at least a component of their opening and closing motion perpendicular to the closing faces
    • F16K1/32—Details
    • F16K1/34—Cutting-off parts, e.g. valve members, seats
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F16—ENGINEERING ELEMENTS AND UNITS; GENERAL MEASURES FOR PRODUCING AND MAINTAINING EFFECTIVE FUNCTIONING OF MACHINES OR INSTALLATIONS; THERMAL INSULATION IN GENERAL
    • F16K—VALVES; TAPS; COCKS; ACTUATING-FLOATS; DEVICES FOR VENTING OR AERATING
    • F16K1/00—Lift valves or globe valves, i.e. cut-off apparatus with closure members having at least a component of their opening and closing motion perpendicular to the closing faces
    • F16K1/32—Details
    • F16K1/52—Means for additional adjustment of the rate of flow
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0313—Organic insulating material
    • H05K1/0353—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement
    • H05K1/036—Multilayers with layers of different types
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92144—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/145—Organic substrates, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0313—Organic insulating material
    • H05K1/0353—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement
    • H05K1/0366—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement reinforced, e.g. by fibres, fabrics
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09881—Coating only between conductors, i.e. flush with the conductors

Definitions

  • Embodiments of the present invention relate to embedded printed circuit boards.
  • PCB printed circuit board
  • a printed circuit board is a printed circuit printed on a electrically insulating substrate using a conductive material. In order to mount many kinds of devices on a flat plate, the mounting position of each device is determined and the devices are connected. And a circuit line to be printed and fixed on the surface of the flat plate.
  • a buried printed circuit board including an element therein was formed by forming a cavity in an insulating substrate and mounting a device in a single layer in the cavity.
  • a terminal connected to the device is formed only on one surface of a buried printed circuit board, such that a bend occurs in an upper surface on which the device is disposed and the device is buried printed.
  • a warpage phenomenon occurs due to a symmetrical structure in the circuit board, and a high-density miniaturized design is difficult.
  • Embodiments of the present invention have been made to solve the above-described problems, and the first and second devices, which are thinner than the thickness of the conventional devices, are disposed on both sides of the insulating boards at positions corresponding to each other, thereby miniaturizing more highly integrated.
  • the first and second devices are disposed on both sides at positions corresponding to each other on an insulating substrate, thereby providing a more compact miniaturized embedded printed circuit board. Can provide.
  • the first and second devices having the same thickness are arranged in a printed circuit board so as to have a symmetrical structure, so that a warpage phenomenon may occur on the printed circuit board or the first and second devices may be disposed on an upper surface of the first and second devices. It is possible to prevent the occurrence of a bulge.
  • FIG. 1 is a cross-sectional view of a buried printed circuit board according to an embodiment of the present invention.
  • FIGS. 2 to 9 are views for explaining a method of manufacturing a buried printed circuit board according to an embodiment of the present invention.
  • insulating substrate 121 first insulating substrate
  • first element 132 metal via
  • conductive portion 135 protective layer
  • first insulating substrate 142 insulating layer
  • FIG. 1 is a cross-sectional view of a buried printed circuit board according to an embodiment of the present invention.
  • the buried printed circuit board includes an insulating substrate 110 and a junction insulating layer 160 that is included in the insulating substrate and divides the insulating substrate in the width direction.
  • the first device 130 disposed on one surface side and the second device 150 disposed on the other surface side of the junction insulating layer may be disposed to be symmetrical with the first device.
  • the buried printed circuit board includes an insulating substrate 110, a first device 130, and a second device 150.
  • the insulating substrate 110 has a structure in which a plurality of insulating substrates are bonded to each other to form a laminate, and in the embodiment of the present invention, the plurality of insulating substrates 121 and 141 and the bonding insulating layer 160 and the other insulating layers 122 are formed. 142 is laminated.
  • the junction insulating layer 160 is disposed at the center of the insulating substrate 110, and the arrangement position may be disposed at the horizontal portion when the horizontal portion is drawn based on the center point of the entire insulating substrate. That is, the insulating substrate may be disposed at a position bisecting in the width direction.
  • the junction material insulating layer 160 may be a resin material having a bonding property, various insulating resin materials such as a synthetic resin material containing an epoxy glass component may be applied.
  • the first device 130 and the second device 150 are disposed on both surfaces of the junction insulating layer 160 to be symmetrical with each other to be balanced.
  • the sum of the thickness a1 of the first element 130 and the thickness a2 of the second element 150 may be less than 1/2 of the thickness b of the insulating substrate 100. have.
  • the sum of the thickness a1 of the first element 130 and the thickness a2 of the second element 150 exceeds 1/2 of the thickness b of the insulation substrate 100, the entire insulation substrate The center of gravity of the 110 is distorted to cause bending on the surface of the insulating substrate.
  • the thicknesses (a, b) of the first device 130 and the second device 150 used in the present embodiment may be applied to the device having a thickness thinner than the thickness of the device according to the prior art, respectively.
  • the thicknesses a and b of the first element 130 and the second element 150 may each be configured to have a thickness of 1/2 or less than the thickness of the element according to the prior art.
  • the substantially same thickness of the first device and the second device which is symmetrical center of gravity in the vertical direction around the junction insulating layer to achieve a balance overall This makes it possible to evenly distribute the stresses generated in the entire printed circuit board.
  • substantially the same as described in the embodiments of the present invention means that the thickness of the device is the same, but an error within 0.01% of the actual thickness is an error range caused by an error in a manufacturing process or a minute pollution source.
  • the first device and the second device may be arranged in a structure accommodated in the first insulating substrate and the second insulating substrate included in the insulating substrate, respectively. That is, the first device 130 is disposed on the cavity of the first insulating substrate 121 adjacent to the upper portion of the junction insulating layer 160, and the second element 150 is the junction insulating layer 160. It may be formed in a structure disposed on the cavity of the second insulating substrate 141 adjacent to the lower portion.
  • the first insulating substrate 121 and the second insulating substrate 141 are formed at the same position with the cavity having substantially the same width, and are substantially the same to correct the overall balance. It is more preferable to have a thickness.
  • first insulating substrate 121 and the second insulating substrate 141 may be formed of the same material, and more preferably, the first insulating substrate 121 and the second insulating substrate 141.
  • the junction insulating layer 160 may be made of a material having the same mutual expansion coefficient. In order to minimize the distortion between the joining layers due to thermal expansion in the future.
  • the first insulating substrate 121, the second insulating substrate 141, and the junction insulating layer 160 may be formed of the same material.
  • the thicknesses of the first element 130, the second element 150, and the insulating substrate 110 may be in a ratio of 1: 4. Can be configured.
  • the insulating substrate 110 may have a thickness of 380 ⁇ m to 400 ⁇ m
  • the first element 130 and the second element 150 may have a thickness (a1, of 30 ⁇ m to 120 ⁇ m). a2).
  • the first element 130 and the second element 150 are disposed on one side and the other side of one insulating substrate 110, respectively, wherein the first and second elements are disposed.
  • Each of the devices 130 and 150 is formed to have a thickness that is 1/2 of the thickness of the device according to the prior art, and the first and second devices 130 and 150 are double-sided at positions corresponding to each other on the insulating substrate 110.
  • the conventional technology arranges the element only on one side of the printed circuit board, and can provide a more compact miniaturized embedded printed circuit board.
  • the printed circuit board has a symmetrical structure by forming the same thickness a1 of the first device 130 and the thickness a2 of the second device 150.
  • a warpage phenomenon does not occur on the circuit board, or a bend does not occur on an upper surface of the insulating substrate 110 on which the first device 130 or the second device 150 is disposed.
  • the insulating substrate 110 of the buried printed circuit board may include a first insulating substrate 121 and a second insulating substrate 141.
  • the first insulating substrate 121 may include a cavity 125, and a first element 130 may be disposed in the cavity 125.
  • the second insulating substrate 141 may include a cavity 145, and a second element 150 may be disposed in the cavity 145.
  • the first device 130 and the second device 150 may be disposed at positions corresponding to each other on the insulating substrate 110.
  • the first device 130 and the second device 150 may be composed of a thickness (a1, a2) of 30 ⁇ m to 120 ⁇ m, which is the thickness of the first, second device (130, 150) Breakage may occur when (a1, a2) is less than 30 ⁇ m, and when the thickness (a1, a2) of the first and second elements 130, 150 is greater than 120 ⁇ m, the first, This is because it is difficult to form the cavities 125 and 145 in which the two devices 130 and 150 are disposed.
  • the thicknesses a1 and a2 of the first and second elements 130 and 150 are formed to have thicknesses a1 and a2 of 30 ⁇ m to 120 ⁇ m, the first, The second elements 130 and 150 are not damaged and the cavity 125 and 145 for forming the first and second elements 130 and 150 can be easily formed.
  • a bonding layer 160 is disposed between the first insulating substrate 121 and the second insulating substrate 141 to bond the first insulating substrate 121 and the second insulating substrate 141 to each other. Can be.
  • the first insulating substrate 121, the second insulating substrate 141, and the bonding layer 160 may be made of the same material, and for example, the first insulating substrate 121 and the second insulating substrate 141.
  • the bonding layer 160 may be formed of a material including a glass fiber and a resin material.
  • first insulating substrate 121 and the second insulating substrate 141 may be configured to be directly bonded to each other without a separate member.
  • first insulating substrate 121 and the second insulating layer may be similarly formed.
  • the substrate 141 may be made of the same material, and may be formed of, for example, a material including glass fiber and a resin material.
  • insulating layers 122 and 142 may be disposed on the first insulating substrate 121 and the second insulating substrate 141, respectively, and the first and second elements 130 may be disposed on the insulating layers 122 and 142, respectively.
  • the metal vias 132 and 152 and the conductive parts 133 and 153 connected to the terminals 131 and 151 of 150 may be formed, respectively, and further include protective layers 135 and 155 thereon. have.
  • the insulating layers 122 and 142 may be formed of the same material as the first insulating substrate 121, the second insulating substrate 141, and the bonding layer 160.
  • the first element 130 has a terminal 131 disposed on one side of the insulating substrate 110 connected to the conductive portion 133 on one surface of the insulating substrate 110, and the second element 150 is The terminal 151 disposed on the other surface side of the insulating substrate 110 may be connected to the conductive portion 153 on the other surface of the insulating substrate 110.
  • the thinner first and second elements 130 and 150 are disposed on both sides of the insulating substrate 110 at positions corresponding to each other, thereby further miniaturizing the buried printed circuit.
  • the substrate may be provided, and the first and second devices 130 and 150 having the same thickness may be disposed to form a symmetrical structure in the printed circuit board, thereby causing a warpage phenomenon on the printed circuit board or the first and second devices 130. , 150 may be prevented from generating a bend (bulge) on the upper surface.
  • the insulating substrate 110 may further include protective layers 135 and 155 adjacent to the conductive portion 133 on one surface and the other surface of the insulating substrate 110. This protects the internal insulating board.
  • FIGS. 2 to 9 are views for explaining a method of manufacturing a buried printed circuit board according to an embodiment of the present invention.
  • the cavity 125 is formed in the insulating substrate 121, and the first element 130 is disposed in the cavity 125 of the insulating substrate 121 as shown in FIG. 3.
  • the insulating substrate 121 may be formed of a material including glass fiber and a resin material.
  • the first element 130 may be composed of a thickness (a1) of 30 ⁇ m to 120 ⁇ m, as described above if the thickness (a1) of the first element 130 is configured to 30 ⁇ m to 120 ⁇ m, The first device 130 may be prevented from being damaged, and the cavity 125 for disposing the first device 130 may be easily formed.
  • an insulating layer 122 is formed on upper surfaces of the insulating substrate 121 and the first element 130 as shown in FIG. 4, and vias are formed in the insulating layer 122 as shown in FIG. 5. (via: 136).
  • the via 136 and the upper portion of the via 136 are plated to form a metal via 132 and a conductive portion 133 connected to the terminal 131 of the first device 130.
  • the upper layer 200 is formed by forming the protective layer 135 on the insulating layer 122 again.
  • the lower substrate 300 according to an embodiment of the present invention may be formed by the same method as the manufacturing method of the upper substrate 200.
  • the buried printed circuit board may be formed by bonding the upper substrate 200 and the lower substrate 300 to each other.
  • the bonding layer 160 may be further included between the upper substrate 200 and the lower substrate 300.
  • the bonding layer 160 is a member for easily bonding the upper substrate 200 and the lower substrate 300.
  • the first insulating substrate 121, the second insulating substrate 141, and the bonding layer 160 may be It may be made of the same material.
  • the first insulating substrate 121, the second insulating substrate 141, and the bonding layer 160 may be formed of a material including glass fiber and a resin material.
  • first insulating substrate 121 and the second insulating substrate 141 may be configured to be directly bonded to each other without a separate member, and likewise, the first insulating substrate 121 and the second insulating substrate ( 141 may be composed of the same material.
  • the insulating layers 122 and 142 may be formed of the same material as the first insulating substrate 121, the second insulating substrate 141, and the bonding layer 160.
  • FIG. 9 is a cross-sectional view of an embedded PCB having the upper substrate 200 and the lower substrate 300 bonded thereto.
  • the sum of the thickness a1 of the first element 130 and the thickness a2 of the second element 150 is 1/2 of the thickness b of the insulating substrate 100.
  • the thickness of each of the first element 130, the second element 150, and the insulating substrate 110 may be formed in a ratio of 1: 1, thereby forming a thinner thickness.
  • the first and second elements 130 and 150 may be disposed on both sides of the insulating substrate 110 at positions corresponding to each other, thereby providing a more compact miniaturized embedded printed circuit board.
  • first and second devices 130 and 150 having the same thickness may be arranged in a printed circuit board to form a symmetrical structure, such that warpage may occur on the printed circuit board, or the first and second devices 130 and 150 may be It is possible to prevent the occurrence of a bend (bulge) on the top surface disposed.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

La présente invention concerne une carte de circuit imprimé à composants incrustés comprenant : un substrat isolant ; un premier élément déposé sur une face du substrat isolant ; et un deuxième élément déposé sur l'autre face du substrat isolant.
PCT/KR2015/000650 2014-01-22 2015-01-21 Carte de circuit imprimé à composants incrustés WO2015111923A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2014-0007905 2014-01-22
KR1020140007905A KR102237778B1 (ko) 2014-01-22 2014-01-22 임베디드 인쇄회로기판

Publications (1)

Publication Number Publication Date
WO2015111923A1 true WO2015111923A1 (fr) 2015-07-30

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PCT/KR2015/000650 WO2015111923A1 (fr) 2014-01-22 2015-01-21 Carte de circuit imprimé à composants incrustés

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KR (1) KR102237778B1 (fr)
WO (1) WO2015111923A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019239030A1 (fr) * 2018-06-13 2019-12-19 Institut Vedecom Élément modulaire de commutation de puissance et ensemble démontable de plusieurs éléments modulaires

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US20070000687A1 (en) * 2005-06-30 2007-01-04 Brist Gary A Apparatus and method for an embedded air dielectric for a package and a printed circuit board
KR20090002718A (ko) * 2007-07-04 2009-01-09 삼성전기주식회사 캐리어 및 인쇄회로기판 제조방법
JP2011138869A (ja) * 2009-12-28 2011-07-14 Ngk Spark Plug Co Ltd 多層配線基板の製造方法及び多層配線基板
KR20120036044A (ko) * 2010-10-07 2012-04-17 대덕전자 주식회사 칩 매립형 다층회로 인쇄회로기판 제조방법
JP2013038374A (ja) * 2011-01-20 2013-02-21 Ibiden Co Ltd 配線板及びその製造方法

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Publication number Priority date Publication date Assignee Title
KR100656751B1 (ko) * 2005-12-13 2006-12-13 삼성전기주식회사 전자소자 내장 인쇄회로기판 및 그 제조방법
KR101119303B1 (ko) * 2010-01-06 2012-03-20 삼성전기주식회사 전자부품 내장형 인쇄회로기판 및 그 제조방법

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070000687A1 (en) * 2005-06-30 2007-01-04 Brist Gary A Apparatus and method for an embedded air dielectric for a package and a printed circuit board
KR20090002718A (ko) * 2007-07-04 2009-01-09 삼성전기주식회사 캐리어 및 인쇄회로기판 제조방법
JP2011138869A (ja) * 2009-12-28 2011-07-14 Ngk Spark Plug Co Ltd 多層配線基板の製造方法及び多層配線基板
KR20120036044A (ko) * 2010-10-07 2012-04-17 대덕전자 주식회사 칩 매립형 다층회로 인쇄회로기판 제조방법
JP2013038374A (ja) * 2011-01-20 2013-02-21 Ibiden Co Ltd 配線板及びその製造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019239030A1 (fr) * 2018-06-13 2019-12-19 Institut Vedecom Élément modulaire de commutation de puissance et ensemble démontable de plusieurs éléments modulaires
FR3082660A1 (fr) * 2018-06-13 2019-12-20 Institut Vedecom Element modulaire de commutation de puissance et ensemble demontable de plusieurs elements modulaires

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