WO2015111923A1 - Embedded printed circuit board - Google Patents

Embedded printed circuit board Download PDF

Info

Publication number
WO2015111923A1
WO2015111923A1 PCT/KR2015/000650 KR2015000650W WO2015111923A1 WO 2015111923 A1 WO2015111923 A1 WO 2015111923A1 KR 2015000650 W KR2015000650 W KR 2015000650W WO 2015111923 A1 WO2015111923 A1 WO 2015111923A1
Authority
WO
WIPO (PCT)
Prior art keywords
insulating substrate
printed circuit
circuit board
thickness
insulating
Prior art date
Application number
PCT/KR2015/000650
Other languages
French (fr)
Korean (ko)
Inventor
김우영
Original Assignee
엘지이노텍 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 엘지이노텍 주식회사 filed Critical 엘지이노텍 주식회사
Publication of WO2015111923A1 publication Critical patent/WO2015111923A1/en

Links

Images

Classifications

    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F16—ENGINEERING ELEMENTS AND UNITS; GENERAL MEASURES FOR PRODUCING AND MAINTAINING EFFECTIVE FUNCTIONING OF MACHINES OR INSTALLATIONS; THERMAL INSULATION IN GENERAL
    • F16K—VALVES; TAPS; COCKS; ACTUATING-FLOATS; DEVICES FOR VENTING OR AERATING
    • F16K1/00—Lift valves or globe valves, i.e. cut-off apparatus with closure members having at least a component of their opening and closing motion perpendicular to the closing faces
    • F16K1/32—Details
    • F16K1/34—Cutting-off parts, e.g. valve members, seats
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F16—ENGINEERING ELEMENTS AND UNITS; GENERAL MEASURES FOR PRODUCING AND MAINTAINING EFFECTIVE FUNCTIONING OF MACHINES OR INSTALLATIONS; THERMAL INSULATION IN GENERAL
    • F16K—VALVES; TAPS; COCKS; ACTUATING-FLOATS; DEVICES FOR VENTING OR AERATING
    • F16K1/00—Lift valves or globe valves, i.e. cut-off apparatus with closure members having at least a component of their opening and closing motion perpendicular to the closing faces
    • F16K1/32—Details
    • F16K1/52—Means for additional adjustment of the rate of flow
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0313—Organic insulating material
    • H05K1/0353—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement
    • H05K1/036—Multilayers with layers of different types
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92144—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/145—Organic substrates, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0313—Organic insulating material
    • H05K1/0353—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement
    • H05K1/0366—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement reinforced, e.g. by fibres, fabrics
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09881—Coating only between conductors, i.e. flush with the conductors

Definitions

  • Embodiments of the present invention relate to embedded printed circuit boards.
  • PCB printed circuit board
  • a printed circuit board is a printed circuit printed on a electrically insulating substrate using a conductive material. In order to mount many kinds of devices on a flat plate, the mounting position of each device is determined and the devices are connected. And a circuit line to be printed and fixed on the surface of the flat plate.
  • a buried printed circuit board including an element therein was formed by forming a cavity in an insulating substrate and mounting a device in a single layer in the cavity.
  • a terminal connected to the device is formed only on one surface of a buried printed circuit board, such that a bend occurs in an upper surface on which the device is disposed and the device is buried printed.
  • a warpage phenomenon occurs due to a symmetrical structure in the circuit board, and a high-density miniaturized design is difficult.
  • Embodiments of the present invention have been made to solve the above-described problems, and the first and second devices, which are thinner than the thickness of the conventional devices, are disposed on both sides of the insulating boards at positions corresponding to each other, thereby miniaturizing more highly integrated.
  • the first and second devices are disposed on both sides at positions corresponding to each other on an insulating substrate, thereby providing a more compact miniaturized embedded printed circuit board. Can provide.
  • the first and second devices having the same thickness are arranged in a printed circuit board so as to have a symmetrical structure, so that a warpage phenomenon may occur on the printed circuit board or the first and second devices may be disposed on an upper surface of the first and second devices. It is possible to prevent the occurrence of a bulge.
  • FIG. 1 is a cross-sectional view of a buried printed circuit board according to an embodiment of the present invention.
  • FIGS. 2 to 9 are views for explaining a method of manufacturing a buried printed circuit board according to an embodiment of the present invention.
  • insulating substrate 121 first insulating substrate
  • first element 132 metal via
  • conductive portion 135 protective layer
  • first insulating substrate 142 insulating layer
  • FIG. 1 is a cross-sectional view of a buried printed circuit board according to an embodiment of the present invention.
  • the buried printed circuit board includes an insulating substrate 110 and a junction insulating layer 160 that is included in the insulating substrate and divides the insulating substrate in the width direction.
  • the first device 130 disposed on one surface side and the second device 150 disposed on the other surface side of the junction insulating layer may be disposed to be symmetrical with the first device.
  • the buried printed circuit board includes an insulating substrate 110, a first device 130, and a second device 150.
  • the insulating substrate 110 has a structure in which a plurality of insulating substrates are bonded to each other to form a laminate, and in the embodiment of the present invention, the plurality of insulating substrates 121 and 141 and the bonding insulating layer 160 and the other insulating layers 122 are formed. 142 is laminated.
  • the junction insulating layer 160 is disposed at the center of the insulating substrate 110, and the arrangement position may be disposed at the horizontal portion when the horizontal portion is drawn based on the center point of the entire insulating substrate. That is, the insulating substrate may be disposed at a position bisecting in the width direction.
  • the junction material insulating layer 160 may be a resin material having a bonding property, various insulating resin materials such as a synthetic resin material containing an epoxy glass component may be applied.
  • the first device 130 and the second device 150 are disposed on both surfaces of the junction insulating layer 160 to be symmetrical with each other to be balanced.
  • the sum of the thickness a1 of the first element 130 and the thickness a2 of the second element 150 may be less than 1/2 of the thickness b of the insulating substrate 100. have.
  • the sum of the thickness a1 of the first element 130 and the thickness a2 of the second element 150 exceeds 1/2 of the thickness b of the insulation substrate 100, the entire insulation substrate The center of gravity of the 110 is distorted to cause bending on the surface of the insulating substrate.
  • the thicknesses (a, b) of the first device 130 and the second device 150 used in the present embodiment may be applied to the device having a thickness thinner than the thickness of the device according to the prior art, respectively.
  • the thicknesses a and b of the first element 130 and the second element 150 may each be configured to have a thickness of 1/2 or less than the thickness of the element according to the prior art.
  • the substantially same thickness of the first device and the second device which is symmetrical center of gravity in the vertical direction around the junction insulating layer to achieve a balance overall This makes it possible to evenly distribute the stresses generated in the entire printed circuit board.
  • substantially the same as described in the embodiments of the present invention means that the thickness of the device is the same, but an error within 0.01% of the actual thickness is an error range caused by an error in a manufacturing process or a minute pollution source.
  • the first device and the second device may be arranged in a structure accommodated in the first insulating substrate and the second insulating substrate included in the insulating substrate, respectively. That is, the first device 130 is disposed on the cavity of the first insulating substrate 121 adjacent to the upper portion of the junction insulating layer 160, and the second element 150 is the junction insulating layer 160. It may be formed in a structure disposed on the cavity of the second insulating substrate 141 adjacent to the lower portion.
  • the first insulating substrate 121 and the second insulating substrate 141 are formed at the same position with the cavity having substantially the same width, and are substantially the same to correct the overall balance. It is more preferable to have a thickness.
  • first insulating substrate 121 and the second insulating substrate 141 may be formed of the same material, and more preferably, the first insulating substrate 121 and the second insulating substrate 141.
  • the junction insulating layer 160 may be made of a material having the same mutual expansion coefficient. In order to minimize the distortion between the joining layers due to thermal expansion in the future.
  • the first insulating substrate 121, the second insulating substrate 141, and the junction insulating layer 160 may be formed of the same material.
  • the thicknesses of the first element 130, the second element 150, and the insulating substrate 110 may be in a ratio of 1: 4. Can be configured.
  • the insulating substrate 110 may have a thickness of 380 ⁇ m to 400 ⁇ m
  • the first element 130 and the second element 150 may have a thickness (a1, of 30 ⁇ m to 120 ⁇ m). a2).
  • the first element 130 and the second element 150 are disposed on one side and the other side of one insulating substrate 110, respectively, wherein the first and second elements are disposed.
  • Each of the devices 130 and 150 is formed to have a thickness that is 1/2 of the thickness of the device according to the prior art, and the first and second devices 130 and 150 are double-sided at positions corresponding to each other on the insulating substrate 110.
  • the conventional technology arranges the element only on one side of the printed circuit board, and can provide a more compact miniaturized embedded printed circuit board.
  • the printed circuit board has a symmetrical structure by forming the same thickness a1 of the first device 130 and the thickness a2 of the second device 150.
  • a warpage phenomenon does not occur on the circuit board, or a bend does not occur on an upper surface of the insulating substrate 110 on which the first device 130 or the second device 150 is disposed.
  • the insulating substrate 110 of the buried printed circuit board may include a first insulating substrate 121 and a second insulating substrate 141.
  • the first insulating substrate 121 may include a cavity 125, and a first element 130 may be disposed in the cavity 125.
  • the second insulating substrate 141 may include a cavity 145, and a second element 150 may be disposed in the cavity 145.
  • the first device 130 and the second device 150 may be disposed at positions corresponding to each other on the insulating substrate 110.
  • the first device 130 and the second device 150 may be composed of a thickness (a1, a2) of 30 ⁇ m to 120 ⁇ m, which is the thickness of the first, second device (130, 150) Breakage may occur when (a1, a2) is less than 30 ⁇ m, and when the thickness (a1, a2) of the first and second elements 130, 150 is greater than 120 ⁇ m, the first, This is because it is difficult to form the cavities 125 and 145 in which the two devices 130 and 150 are disposed.
  • the thicknesses a1 and a2 of the first and second elements 130 and 150 are formed to have thicknesses a1 and a2 of 30 ⁇ m to 120 ⁇ m, the first, The second elements 130 and 150 are not damaged and the cavity 125 and 145 for forming the first and second elements 130 and 150 can be easily formed.
  • a bonding layer 160 is disposed between the first insulating substrate 121 and the second insulating substrate 141 to bond the first insulating substrate 121 and the second insulating substrate 141 to each other. Can be.
  • the first insulating substrate 121, the second insulating substrate 141, and the bonding layer 160 may be made of the same material, and for example, the first insulating substrate 121 and the second insulating substrate 141.
  • the bonding layer 160 may be formed of a material including a glass fiber and a resin material.
  • first insulating substrate 121 and the second insulating substrate 141 may be configured to be directly bonded to each other without a separate member.
  • first insulating substrate 121 and the second insulating layer may be similarly formed.
  • the substrate 141 may be made of the same material, and may be formed of, for example, a material including glass fiber and a resin material.
  • insulating layers 122 and 142 may be disposed on the first insulating substrate 121 and the second insulating substrate 141, respectively, and the first and second elements 130 may be disposed on the insulating layers 122 and 142, respectively.
  • the metal vias 132 and 152 and the conductive parts 133 and 153 connected to the terminals 131 and 151 of 150 may be formed, respectively, and further include protective layers 135 and 155 thereon. have.
  • the insulating layers 122 and 142 may be formed of the same material as the first insulating substrate 121, the second insulating substrate 141, and the bonding layer 160.
  • the first element 130 has a terminal 131 disposed on one side of the insulating substrate 110 connected to the conductive portion 133 on one surface of the insulating substrate 110, and the second element 150 is The terminal 151 disposed on the other surface side of the insulating substrate 110 may be connected to the conductive portion 153 on the other surface of the insulating substrate 110.
  • the thinner first and second elements 130 and 150 are disposed on both sides of the insulating substrate 110 at positions corresponding to each other, thereby further miniaturizing the buried printed circuit.
  • the substrate may be provided, and the first and second devices 130 and 150 having the same thickness may be disposed to form a symmetrical structure in the printed circuit board, thereby causing a warpage phenomenon on the printed circuit board or the first and second devices 130. , 150 may be prevented from generating a bend (bulge) on the upper surface.
  • the insulating substrate 110 may further include protective layers 135 and 155 adjacent to the conductive portion 133 on one surface and the other surface of the insulating substrate 110. This protects the internal insulating board.
  • FIGS. 2 to 9 are views for explaining a method of manufacturing a buried printed circuit board according to an embodiment of the present invention.
  • the cavity 125 is formed in the insulating substrate 121, and the first element 130 is disposed in the cavity 125 of the insulating substrate 121 as shown in FIG. 3.
  • the insulating substrate 121 may be formed of a material including glass fiber and a resin material.
  • the first element 130 may be composed of a thickness (a1) of 30 ⁇ m to 120 ⁇ m, as described above if the thickness (a1) of the first element 130 is configured to 30 ⁇ m to 120 ⁇ m, The first device 130 may be prevented from being damaged, and the cavity 125 for disposing the first device 130 may be easily formed.
  • an insulating layer 122 is formed on upper surfaces of the insulating substrate 121 and the first element 130 as shown in FIG. 4, and vias are formed in the insulating layer 122 as shown in FIG. 5. (via: 136).
  • the via 136 and the upper portion of the via 136 are plated to form a metal via 132 and a conductive portion 133 connected to the terminal 131 of the first device 130.
  • the upper layer 200 is formed by forming the protective layer 135 on the insulating layer 122 again.
  • the lower substrate 300 according to an embodiment of the present invention may be formed by the same method as the manufacturing method of the upper substrate 200.
  • the buried printed circuit board may be formed by bonding the upper substrate 200 and the lower substrate 300 to each other.
  • the bonding layer 160 may be further included between the upper substrate 200 and the lower substrate 300.
  • the bonding layer 160 is a member for easily bonding the upper substrate 200 and the lower substrate 300.
  • the first insulating substrate 121, the second insulating substrate 141, and the bonding layer 160 may be It may be made of the same material.
  • the first insulating substrate 121, the second insulating substrate 141, and the bonding layer 160 may be formed of a material including glass fiber and a resin material.
  • first insulating substrate 121 and the second insulating substrate 141 may be configured to be directly bonded to each other without a separate member, and likewise, the first insulating substrate 121 and the second insulating substrate ( 141 may be composed of the same material.
  • the insulating layers 122 and 142 may be formed of the same material as the first insulating substrate 121, the second insulating substrate 141, and the bonding layer 160.
  • FIG. 9 is a cross-sectional view of an embedded PCB having the upper substrate 200 and the lower substrate 300 bonded thereto.
  • the sum of the thickness a1 of the first element 130 and the thickness a2 of the second element 150 is 1/2 of the thickness b of the insulating substrate 100.
  • the thickness of each of the first element 130, the second element 150, and the insulating substrate 110 may be formed in a ratio of 1: 1, thereby forming a thinner thickness.
  • the first and second elements 130 and 150 may be disposed on both sides of the insulating substrate 110 at positions corresponding to each other, thereby providing a more compact miniaturized embedded printed circuit board.
  • first and second devices 130 and 150 having the same thickness may be arranged in a printed circuit board to form a symmetrical structure, such that warpage may occur on the printed circuit board, or the first and second devices 130 and 150 may be It is possible to prevent the occurrence of a bend (bulge) on the top surface disposed.

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mechanical Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

An embedded printed circuit board of the present invention comprises: an insulating substrate; a first element disposed at one surface side of the insulating substrate; and a second element disposed at the other surface side of the insulating substrate.

Description

매립형 인쇄회로기판Flush printed circuit board
본 발명의 실시예는 매립형 인쇄회로기판에 관한 것이다.Embodiments of the present invention relate to embedded printed circuit boards.
최근에는 휴대 단말에 다양한 기능이 추가되고 있으며, 그에 따라 휴대 단말에 다양한 센서 소자가 추가되고 있다.Recently, various functions have been added to the portable terminal, and accordingly, various sensor elements have been added to the portable terminal.
휴대 단말에 포함되는 인쇄회로기판(PCB: Printed Circuit Board)에 센서 소자를 실장 시에는 상기 인쇄회로기판의 제한된 면적으로 인하여 새로운 센서 소자의 추가가 어려운 실정이다.When a sensor element is mounted on a printed circuit board (PCB) included in a portable terminal, it is difficult to add a new sensor element due to the limited area of the printed circuit board.
인쇄회로기판(PCB: Printed Circuit Board)은 전기 절연성 기판에 전도성 재료로 인쇄회로를 인쇄한 것으로, 여러 종류의 많은 소자를 평판 위에 밀집 탑재시키기 위해, 각 소자의 장착 위치를 확정하고, 소자를 연결하는 회로 라인을 평판 표면에 인쇄하여 고정하는 구조로 구성된다.A printed circuit board (PCB) is a printed circuit printed on a electrically insulating substrate using a conductive material. In order to mount many kinds of devices on a flat plate, the mounting position of each device is determined and the devices are connected. And a circuit line to be printed and fixed on the surface of the flat plate.
소자를 내부에 포함하는 매립형 인쇄회로기판은 절연 기판 내에 캐비티를 형성하고 캐비티 내에 소자를 단층으로 실장하여 구성하였다.A buried printed circuit board including an element therein was formed by forming a cavity in an insulating substrate and mounting a device in a single layer in the cavity.
그러나, 종래 기술에 따르면 소자가 캐비티 내에 단층으로 실장되므로 상기 소자와 연결되는 단자가 매립형 인쇄회로기판의 일면으로만 형성되어, 소자가 배치된 상면에 굴곡(bulge)이 발생하고 상기 소자가 매립형 인쇄회로기판 내에서 대칭구조를 이루지 못하여 뒤틀림(warpage) 현상이 발생하며, 고집적의 소형화된 설계가 어려운 문제점이 있었다.However, according to the related art, since a device is mounted in a single layer in a cavity, a terminal connected to the device is formed only on one surface of a buried printed circuit board, such that a bend occurs in an upper surface on which the device is disposed and the device is buried printed. There is a problem in that a warpage phenomenon occurs due to a symmetrical structure in the circuit board, and a high-density miniaturized design is difficult.
본 발명의 실시예들은 전술한 문제를 해결하기 위해 안출된 것으로서, 종래의 소자의 두께보다 얇은 두께인 제1, 2 소자를 절연 기판 상에서 상호 간에 대응되는 위치에 양면으로 배치하여, 보다 고집적의 소형화된 매립형 인쇄회로기판을 제공하고, 동일한 두께의 제1, 2 소자를 인쇄회로기판 내에 대칭구조를 이루도록 배치하여 인쇄회로기판에 뒤틀림(warpage) 현상이 발생하거나 제1, 2 소자가 배치된 상면에 굴곡(bulge)이 발생하지 않도록 하고자 한다.Embodiments of the present invention have been made to solve the above-described problems, and the first and second devices, which are thinner than the thickness of the conventional devices, are disposed on both sides of the insulating boards at positions corresponding to each other, thereby miniaturizing more highly integrated. Providing a buried printed circuit board and arranging the first and second devices having the same thickness so as to have a symmetrical structure in the printed circuit board so that warpage occurs on the printed circuit board or on the upper surface on which the first and second devices are disposed. It is intended that no bends occur.
상술한 과제를 해결하기 위한 수단으로서, 본 발명의 실시예에서는 절연기판; 상기 절연기판의 내부에 포함되며, 상기 절연기판을 폭방향으로 양분하는 접합 절연층; 상기 절연층의 일면 측에 배치되는 제1소자; 및 상기 절연층의 타면 측에 배치되며, 상기 제1소자와 대칭되는 위치에 배치되는 제2소자;를 포함하는 매립형 인쇄회로기판을 제공할 수 있도록 한다.As a means for solving the above problems, in the embodiment of the present invention; A junction insulation layer included in the insulation substrate and bisecting the insulation substrate in a width direction; A first element disposed on one side of the insulating layer; And a second element disposed on the other surface side of the insulating layer and disposed at a position symmetrical with the first element.
본 발명의 실시예에 따르면, 종래의 소자의 두께의 1/2의 두께인 제1, 2 소자를 절연 기판 상에서 상호간에 대응되는 위치에 양면으로 배치하여, 보다 고집적의 소형화된 매립형 인쇄회로기판을 제공할 수 있다.According to an embodiment of the present invention, the first and second devices, each of which is 1/2 the thickness of a conventional device, are disposed on both sides at positions corresponding to each other on an insulating substrate, thereby providing a more compact miniaturized embedded printed circuit board. Can provide.
또한, 본 발명의 실시예에 따르면 동일한 두께의 제1, 2 소자를 인쇄회로기판 내에 대칭구조를 이루도록 배치하여 인쇄회로기판에 뒤틀림(warpage) 현상이 발생하거나 제1, 2 소자가 배치된 상면에 굴곡(bulge)이 발생하지 않도록 할 수 있다.Further, according to an embodiment of the present invention, the first and second devices having the same thickness are arranged in a printed circuit board so as to have a symmetrical structure, so that a warpage phenomenon may occur on the printed circuit board or the first and second devices may be disposed on an upper surface of the first and second devices. It is possible to prevent the occurrence of a bulge.
도 1은 본 발명의 일실시예에 따른 매립형 인쇄회로기판의 단면도이다.1 is a cross-sectional view of a buried printed circuit board according to an embodiment of the present invention.
도 2 내지 도 9는 본 발명의 일실시예에 따른 매립형 인쇄회로기판의 제조 방법을 설명하기 위한 도면이다.2 to 9 are views for explaining a method of manufacturing a buried printed circuit board according to an embodiment of the present invention.
110: 절연 기판 121: 제1 절연 기판110: insulating substrate 121: first insulating substrate
122: 절연층 125: 캐비티122: insulating layer 125: cavity
130: 제1 소자 132: 금속 비아130: first element 132: metal via
133: 도전부 135: 보호층133: conductive portion 135: protective layer
141: 제1 절연 기판 142: 절연층141: first insulating substrate 142: insulating layer
145: 캐비티 150: 제2 소자145: cavity 150: second element
152: 금속 비아 153: 회로 단자152: metal via 153: circuit terminal
155: 보호층 160: 접합층155: protective layer 160: bonding layer
이하에서는 첨부한 도면을 참조하여 바람직한 본 발명의 일실시예에 대해서 상세히 설명한다. 다만, 실시형태를 설명함에 있어서, 관련된 공지 기능 혹은 구성에 대한 구체적인 설명이 본 발명의 요지를 불필요하게 흐릴 수 있다고 판단되는 경우 그에 대한 상세한 설명은 생략한다. 또한, 도면에서의 각 구성요소들의 크기는 설명을 위하여 과장될 수 있으며, 실제로 적용되는 크기를 의미하는 것은 아니다.Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention. However, in describing the embodiments, when it is determined that detailed descriptions of related known functions or configurations may unnecessarily obscure the subject matter of the present invention, detailed descriptions thereof will be omitted. In addition, the size of each component in the drawings may be exaggerated for description, it does not mean the size that is actually applied.
도 1은 본 발명의 일실시예에 따른 매립형 인쇄회로기판의 단면도이다.1 is a cross-sectional view of a buried printed circuit board according to an embodiment of the present invention.
도 1을 참조하여 본 발명의 일실시예에 따른 매립형 인쇄회로기판의 구성을 설명하기로 한다.Referring to Figure 1 will be described the configuration of a buried printed circuit board according to an embodiment of the present invention.
본 발명의 일실시예에 따른 매립형 인쇄회로기판은 절연기판(110)과, 상기 절연기판의 내부에 포함되며, 상기 절연기판을 폭방향으로 양분하는 접합 절연층(160), 상기 접합 절연층의 일면 측에 배치되는 제1소자(130) 및 상기 접합 절연층의 타면 측에 배치되며, 상기 제1소자와 대칭되는 위치에 배치되는 제2소자(150)를 포함하여 구성될 수 있다.The buried printed circuit board according to an embodiment of the present invention includes an insulating substrate 110 and a junction insulating layer 160 that is included in the insulating substrate and divides the insulating substrate in the width direction. The first device 130 disposed on one surface side and the second device 150 disposed on the other surface side of the junction insulating layer may be disposed to be symmetrical with the first device.
구체적으로는, 도 1에 도시된 바와 같이 본 발명의 일실시예에 따른 매립형 인쇄회로기판은 절연 기판(110), 제1 소자(130) 및 제2 소자(150)를 포함한다. Specifically, as shown in FIG. 1, the buried printed circuit board according to the exemplary embodiment of the present invention includes an insulating substrate 110, a first device 130, and a second device 150.
상기 절연기판(110)은 다수의 절연성 기판들이 접합되어 적층되는 구조를 이루고 있으며, 본 발명의 실시예에서는 다수의 절연기판(121, 141)과 접합절연층(160), 다른 절연층(122, 142)이 적층되는 구조를 구비하고 있다.The insulating substrate 110 has a structure in which a plurality of insulating substrates are bonded to each other to form a laminate, and in the embodiment of the present invention, the plurality of insulating substrates 121 and 141 and the bonding insulating layer 160 and the other insulating layers 122 are formed. 142 is laminated.
이 경우, 상기 절연기판(110)의 중심부에는 접합절연층(160)이 배치되며, 그 배치 위치는 전체 절연기판의 중심점을 기준으로 수평선분을 그었을 때의 수평선분의 위치에 배치될 수 있다. 즉, 상기 절연기판을 폭방향으로 양분하는 위치에 배치될 수 있다.In this case, the junction insulating layer 160 is disposed at the center of the insulating substrate 110, and the arrangement position may be disposed at the horizontal portion when the horizontal portion is drawn based on the center point of the entire insulating substrate. That is, the insulating substrate may be disposed at a position bisecting in the width direction.
상기 접합합절연층(160)은 접합성을 가지는 수지재가 적용될 수 있으며, 에폭시니 유리 성분을 포함하는 합성수지재 등 다양한 절연성 수지재가 적용될 수 있다. 아울러, 상기 접합절연층(160)의 양 표면에는 상호 대칭되는 위치에, 제1소자(130)와 제2소자(150)가 배치되어 균형을 이루고 있도록 형성된다.The junction material insulating layer 160 may be a resin material having a bonding property, various insulating resin materials such as a synthetic resin material containing an epoxy glass component may be applied. In addition, the first device 130 and the second device 150 are disposed on both surfaces of the junction insulating layer 160 to be symmetrical with each other to be balanced.
이 경우, 상기 제1 소자(130)의 두께(a1)와 상기 2 소자(150)의 두께(a2)의 합은 상기 절연 기판(100)의 두께(b)의 1/2 이하로 형성될 수 있다. 상기 제1 소자(130)의 두께(a1)와 상기 2 소자(150)의 두께(a2)의 합은 상기 절연 기판(100)의 두께(b)의 1/2을 초과하는 경우에는 전체적인 절연 기판(110)의 무게 중심이 틀어져서 절연기판 표면에 굴곡이 발생하게 된다.In this case, the sum of the thickness a1 of the first element 130 and the thickness a2 of the second element 150 may be less than 1/2 of the thickness b of the insulating substrate 100. have. When the sum of the thickness a1 of the first element 130 and the thickness a2 of the second element 150 exceeds 1/2 of the thickness b of the insulation substrate 100, the entire insulation substrate The center of gravity of the 110 is distorted to cause bending on the surface of the insulating substrate.
특히, 본 실시예에 사용되는 상기 제1 소자(130)와 제2 소자(150)의 두께(a, b)는 각각 종래 기술에 따른 소자의 두께 보다 얇은 두께의 소자를 적용할 수 있다. 일예로, 상기 제1 소자(130)와 제2 소자(150)의 두께(a, b)는 각각 종래 기술에 따른 소자의 두께 보다 1/2 이하의 두께로 구성될 수 있다. In particular, the thicknesses (a, b) of the first device 130 and the second device 150 used in the present embodiment may be applied to the device having a thickness thinner than the thickness of the device according to the prior art, respectively. For example, the thicknesses a and b of the first element 130 and the second element 150 may each be configured to have a thickness of 1/2 or less than the thickness of the element according to the prior art.
본 발명의 실시예에서는, 상기 제1소자와 상기 제2소자의 두께가 실질적으로 동일한 것을 사용함이 바람직하며, 이는 접합절연층을 중심으로 상하 방향으로 대칭적인 무게 중심이 잡혀, 전체적을 균형감을 이룰 수 있게 되어, 인쇄회로기판 전체에 발생하는 응력의 분포를 고르게 할 수 있기 때문이다. 본 발명의 실시예등에서 설명하는 '실질적으로 동일하다'는 의미는 소자의 두께는 동일하나, 제조공정상의 오차나 미세한 오염원 등에 의해 발생하는 오차 범위로 실질적인 두께의 0.01% 이내의 오차를 의미한다.In the embodiment of the present invention, it is preferable to use the substantially same thickness of the first device and the second device, which is symmetrical center of gravity in the vertical direction around the junction insulating layer to achieve a balance overall This makes it possible to evenly distribute the stresses generated in the entire printed circuit board. The term "substantially the same" as described in the embodiments of the present invention means that the thickness of the device is the same, but an error within 0.01% of the actual thickness is an error range caused by an error in a manufacturing process or a minute pollution source.
상기 제1소자 및 상기 제2소자는 상기 절연기판 내에 포함되는 제1절연기판 및 제2절연기판 내에 각각 수용되는 구조로 배치될 수 있다. 즉, 상기 제1소자(130)는 상기 접합절연층(160)의 상부에 인접하는 제1절연기판(121)의 캐비티 상에 배치되며, 상기 제2소자(150)는 상기 접합절연층(160)의 하부에 인접하는 제2절연기판(141)의 캐비티 상에 배치되는 구조로 형성될 수 있다.The first device and the second device may be arranged in a structure accommodated in the first insulating substrate and the second insulating substrate included in the insulating substrate, respectively. That is, the first device 130 is disposed on the cavity of the first insulating substrate 121 adjacent to the upper portion of the junction insulating layer 160, and the second element 150 is the junction insulating layer 160. It may be formed in a structure disposed on the cavity of the second insulating substrate 141 adjacent to the lower portion.
이 경우, 상기 제1절연기판(121) 및 상기 제2절연기판(141)은 각각에 형성되는 캐비티가 실질적으로 동일한 폭으로 동일한 위치에 형성되는 것이 바람직하며, 전체적인 균형을 바로 잡기 위해 실질적으로 동일한 두께를 가지는 것이 더욱 바람직하다.In this case, it is preferable that the first insulating substrate 121 and the second insulating substrate 141 are formed at the same position with the cavity having substantially the same width, and are substantially the same to correct the overall balance. It is more preferable to have a thickness.
아울러, 상기 제1절연기판(121) 및 상기 제2절연기판(141)은 상호 동일한 재료로 형성될 수 있으며, 더욱 바람직하게는 상기 제1절연기판(121) 및 상기 제2절연기판(141)과 상기 접합절연층(160)은 상호 열팽창계수가 동일한 재료로 구현될 수 있도록 한다. 추후 열팽창으로 인해 접합하는 층간의 뒤틀림을 최소화할 수 있게 하기 위함이다. 물론, 이 경우 상기 제1절연기판(121) 및 상기 제2절연기판(141)과 상기 접합절연층(160)은 동일한 재료로 구성될 수 있다.In addition, the first insulating substrate 121 and the second insulating substrate 141 may be formed of the same material, and more preferably, the first insulating substrate 121 and the second insulating substrate 141. And the junction insulating layer 160 may be made of a material having the same mutual expansion coefficient. In order to minimize the distortion between the joining layers due to thermal expansion in the future. In this case, the first insulating substrate 121, the second insulating substrate 141, and the junction insulating layer 160 may be formed of the same material.
도 1의 구조에 도시된 본 발명의 실시예에 따른, 상기 제1 소자(130), 상기 제2 소자(150)와 상기 절연 기판(110)의 각각의 두께는 1: 1: 4의 비율로 구성될 수 있다. 예를 들어, 상기 절연 기판(110)의 두께는 380 ㎛ 내지 400 ㎛로 형성될 수 있으며, 상기 제1 소자(130)와 상기 제2 소자(150)는 30 ㎛ 내지 120 ㎛의 두께(a1, a2)로 구성될 수 있다.According to the exemplary embodiment of the present invention illustrated in the structure of FIG. 1, the thicknesses of the first element 130, the second element 150, and the insulating substrate 110 may be in a ratio of 1: 4. Can be configured. For example, the insulating substrate 110 may have a thickness of 380 μm to 400 μm, and the first element 130 and the second element 150 may have a thickness (a1, of 30 μm to 120 μm). a2).
보다 상세하게 설명하면, 본 발명의 일실시예에 따르면 하나의 절연 기판(110)의 일면 및 타면 측에 각각 제1 소자(130)와 제2 소자(150)를 배치하되, 상기 제1, 2 소자(130, 150)를 각각 종래 기술에 따른 소자의 두께 보다 1/2의 두께로 구성하고, 상기 제1, 2 소자(130, 150)를 절연 기판(110) 상에서 상호간에 대응되는 위치에 양면으로 배치함으로써, 종래기술이 인쇄회로기판의 한쪽 면 측에만 소자를 배치하는데 반하여, 보다 고집적의 소형화된 매립형 인쇄회로기판을 제공할 수 있다.In more detail, according to an embodiment of the present invention, the first element 130 and the second element 150 are disposed on one side and the other side of one insulating substrate 110, respectively, wherein the first and second elements are disposed. Each of the devices 130 and 150 is formed to have a thickness that is 1/2 of the thickness of the device according to the prior art, and the first and second devices 130 and 150 are double-sided at positions corresponding to each other on the insulating substrate 110. By disposing the structure, the conventional technology arranges the element only on one side of the printed circuit board, and can provide a more compact miniaturized embedded printed circuit board.
한편, 본 발명의 일실시예에 따르면 상기 제1 소자(130)의 두께(a1)와 상기 2 소자(150)의 두께(a2)가 동일하게 구성함으로써 인쇄회로기판이 대칭구조를 이루도록 하여, 인쇄회로기판에 뒤틀림(warpage) 현상이 발생하거나 상기 제1 소자(130) 또는 제2 소자(150)가 배치된 절연 기판(110)의 상면에 굴곡(bulge)이 발생하지 않도록 한다.Meanwhile, according to the exemplary embodiment of the present invention, the printed circuit board has a symmetrical structure by forming the same thickness a1 of the first device 130 and the thickness a2 of the second device 150. A warpage phenomenon does not occur on the circuit board, or a bend does not occur on an upper surface of the insulating substrate 110 on which the first device 130 or the second device 150 is disposed.
이후부터는 상기와 같이 구성된 매립형 인쇄회로기판의 구성을 보다 상세하게 설명하기로 한다.Hereinafter, the configuration of the buried printed circuit board configured as described above will be described in more detail.
본 발명의 일실시예에 따른 상기 매립형 인쇄회로기판의 절연 기판(110)은 제1 절연 기판(121)과 제2 절연 기판(141)을 포함할 수 있다.The insulating substrate 110 of the buried printed circuit board according to the exemplary embodiment of the present invention may include a first insulating substrate 121 and a second insulating substrate 141.
상기 제1 절연 기판(121)은 캐비티(125)를 포함하고, 상기 캐비티(125) 내에는 제1 소자(130)가 배치될 수 있다.The first insulating substrate 121 may include a cavity 125, and a first element 130 may be disposed in the cavity 125.
마찬가지로, 상기 제2 절연 기판(141)은 캐비티(145)를 포함하고, 상기 캐비티(145) 내에는 제2 소자(150)가 배치될 수 있다.Similarly, the second insulating substrate 141 may include a cavity 145, and a second element 150 may be disposed in the cavity 145.
이때, 상기 제1 소자(130)와 상기 제2 소자(150)는 상기 절연 기판(110) 상에서 상호 대응되는 위치에 배치될 수 있다.In this case, the first device 130 and the second device 150 may be disposed at positions corresponding to each other on the insulating substrate 110.
이때, 상기 제1 소자(130)와 상기 제2 소자(150)는 30 ㎛ 내지 120 ㎛의 두께(a1, a2)로 구성될 수 있으며, 이는 상기 제1, 2 소자(130, 150)의 두께(a1, a2)가 30 ㎛ 미만으로 구성되는 경우 파손이 발생할 수 있으며, 상기 제1, 2 소자(130, 150)의 두께(a1, a2)가 120 ㎛ 초과로 구성되는 경우에는 상기 제1, 2 소자(130, 150)가 배치되기 위한 캐비티(cavity: 125, 145)의 형성이 어려운 문제점이 발생하기 때문이다.In this case, the first device 130 and the second device 150 may be composed of a thickness (a1, a2) of 30 ㎛ to 120 ㎛, which is the thickness of the first, second device (130, 150) Breakage may occur when (a1, a2) is less than 30 μm, and when the thickness (a1, a2) of the first and second elements 130, 150 is greater than 120 μm, the first, This is because it is difficult to form the cavities 125 and 145 in which the two devices 130 and 150 are disposed.
따라서, 본 발명의 일실시예에서와 같이 상기 제1, 2 소자(130, 150)의 두께(a1, a2)를 30 ㎛ 내지 120 ㎛의 두께(a1, a2)로 형성하면, 상기 제1, 2 소자(130, 150)가 파손되지 않도록 하고 상기 제1, 2 소자(130, 150)를 배치하기 위한 캐비티(125, 145)의 형성이 용이한 장점이 있다.Therefore, as in the embodiment of the present invention, when the thicknesses a1 and a2 of the first and second elements 130 and 150 are formed to have thicknesses a1 and a2 of 30 μm to 120 μm, the first, The second elements 130 and 150 are not damaged and the cavity 125 and 145 for forming the first and second elements 130 and 150 can be easily formed.
또한, 상기 제1 절연 기판(121)과 제2 절연 기판(141)의 사이에는 접합층(160)이 배치되어 상기 제1 절연 기판(121)과 제2 절연 기판(141)을 상호 간에 접합할 수 있다.In addition, a bonding layer 160 is disposed between the first insulating substrate 121 and the second insulating substrate 141 to bond the first insulating substrate 121 and the second insulating substrate 141 to each other. Can be.
이때, 상기 제1 절연 기판(121), 제2 절연 기판(141) 및 접합층(160)은 동일한 재료로 구성될 수 있으며, 예를 들어 제1 절연 기판(121), 제2 절연 기판(141) 및 접합층(160)은 유리 섬유와 수지재를 포함하는 재료로 형성될 수 있다.In this case, the first insulating substrate 121, the second insulating substrate 141, and the bonding layer 160 may be made of the same material, and for example, the first insulating substrate 121 and the second insulating substrate 141. ) And the bonding layer 160 may be formed of a material including a glass fiber and a resin material.
또 다른 실시예에서는 상기 제1 절연 기판(121)과 제2 절연 기판(141)이 별도의 부재 없이 상호 간에 직접 접합되도록 구성될 수도 있으며, 이때도 마찬가지로 제1 절연 기판(121)과 제2 절연 기판(141)은 동일한 재료로 구성할 수 있으며, 예를 들어 유리 섬유와 수지재를 포함하는 재료로 형성될 수 있다.In another embodiment, the first insulating substrate 121 and the second insulating substrate 141 may be configured to be directly bonded to each other without a separate member. In this case, the first insulating substrate 121 and the second insulating layer may be similarly formed. The substrate 141 may be made of the same material, and may be formed of, for example, a material including glass fiber and a resin material.
또한, 상기 제1 절연 기판(121)과 제2 절연 기판(141) 상에는 각각 절연층(122, 142)이 배치될 수 있으며, 상기 각 절연층(122, 142)에는 제1, 2 소자(130, 150)의 단자(131, 151)와 연결되는 금속 비아(132, 152)와 도전부(133, 153)가 각각 형성될 수 있고, 그 상부에 보호층(135, 155)을 더 포함할 수 있다.In addition, insulating layers 122 and 142 may be disposed on the first insulating substrate 121 and the second insulating substrate 141, respectively, and the first and second elements 130 may be disposed on the insulating layers 122 and 142, respectively. The metal vias 132 and 152 and the conductive parts 133 and 153 connected to the terminals 131 and 151 of 150 may be formed, respectively, and further include protective layers 135 and 155 thereon. have.
이때, 상기 절연층(122, 142)은 상기 제1 절연 기판(121)과 제2 절연 기판(141), 그리고 접합층(160)과 동일한 재료로 형성될 수 있다.In this case, the insulating layers 122 and 142 may be formed of the same material as the first insulating substrate 121, the second insulating substrate 141, and the bonding layer 160.
그에 따라, 제1 소자(130)는 절연 기판(110)의 일면 측으로 배치된 단자(131)가 상기 절연 기판(110)의 일면 상의 도전부(133)와 연결되고, 제2 소자(150)는 절연 기판(110)의 타면 측으로 배치된 단자(151)가 상기 절연 기판(110)의 타면 상의 도전부(153)와 연결될 수 있다.Accordingly, the first element 130 has a terminal 131 disposed on one side of the insulating substrate 110 connected to the conductive portion 133 on one surface of the insulating substrate 110, and the second element 150 is The terminal 151 disposed on the other surface side of the insulating substrate 110 may be connected to the conductive portion 153 on the other surface of the insulating substrate 110.
따라서, 본 발명의 일실시예에 따르면 보다 얇은 두께의 제1, 2 소자(130, 150)를 절연 기판(110) 상에서 상호간에 대응되는 위치에 양면으로 배치하여, 보다 고집적의 소형화된 매립형 인쇄회로기판을 제공할 수 있으며, 동일한 두께의 제1, 2 소자(130, 150)를 인쇄회로기판 내에 대칭구조를 이루도록 배치하여 인쇄회로기판에 뒤틀림(warpage) 현상이 발생하거나 제1, 2 소자(130, 150)가 배치된 상면에 굴곡(bulge)이 발생하지 않도록 할 수 있다.Therefore, according to the exemplary embodiment of the present invention, the thinner first and second elements 130 and 150 are disposed on both sides of the insulating substrate 110 at positions corresponding to each other, thereby further miniaturizing the buried printed circuit. The substrate may be provided, and the first and second devices 130 and 150 having the same thickness may be disposed to form a symmetrical structure in the printed circuit board, thereby causing a warpage phenomenon on the printed circuit board or the first and second devices 130. , 150 may be prevented from generating a bend (bulge) on the upper surface.
아울러, 상기 절연기판(110)의 일면 및 타면 상에는 상기 도전부(133)와 인접하는 보호층(135, 155)을 더 포함하여 구성될 수 있다. 이를 통해 내부의 절연기판을 보호할 수 있다.In addition, the insulating substrate 110 may further include protective layers 135 and 155 adjacent to the conductive portion 133 on one surface and the other surface of the insulating substrate 110. This protects the internal insulating board.
도 2 내지 도 9는 본 발명의 일실시예에 따른 매립형 인쇄회로기판의 제조 방법을 설명하기 위한 도면이다.2 to 9 are views for explaining a method of manufacturing a buried printed circuit board according to an embodiment of the present invention.
도 2 내지 도 9를 참조하여 본 발명의 일실시예에 따른 매립형 인쇄회로기판의 제조 방법을 설명하기로 한다.With reference to Figures 2 to 9 will be described a method of manufacturing a buried printed circuit board according to an embodiment of the present invention.
도 2에 도시된 바와 같이 절연 기판(121)에 캐비티(125)를 형성하고, 도 3에 도시된 바와 같이 상기 절연 기판(121)의 캐비티(125)에 제1 소자(130)를 배치한다.As shown in FIG. 2, the cavity 125 is formed in the insulating substrate 121, and the first element 130 is disposed in the cavity 125 of the insulating substrate 121 as shown in FIG. 3.
이때, 상기 절연 기판(121)은 유리 섬유와 수지재를 포함하는 재료로 형성될 수 있다.In this case, the insulating substrate 121 may be formed of a material including glass fiber and a resin material.
또한, 상기 제1 소자(130)는 30 ㎛ 내지 120 ㎛의 두께(a1)로 구성될 수 있으며, 이와 같이 제1 소자(130)의 두께(a1)를 30 ㎛ 내지 120 ㎛로 구성하면, 상기 제1 소자(130)가 파손되지 않도록 할 수 있으며, 상기 제1 소자(130)를 배치하기 위한 캐비티(125)의 형성이 용이한 장점이 있다.In addition, the first element 130 may be composed of a thickness (a1) of 30 ㎛ to 120 ㎛, as described above if the thickness (a1) of the first element 130 is configured to 30 ㎛ to 120 ㎛, The first device 130 may be prevented from being damaged, and the cavity 125 for disposing the first device 130 may be easily formed.
이후에는, 도 4에 도시된 바와 같이 상기 절연 기판(121) 및 제1 소자(130)의 상면에 절연층(122)을 형성하고, 도 5에 도시된 바와 같이 상기 절연층(122)에 비아(via: 136)를 형성한다.Subsequently, an insulating layer 122 is formed on upper surfaces of the insulating substrate 121 and the first element 130 as shown in FIG. 4, and vias are formed in the insulating layer 122 as shown in FIG. 5. (via: 136).
이후, 도 6에 도시된 바와 같이 상기 비아(136)와 그 상부에 도금을 실시하여 제1 소자(130)의 단자(131)와 연결되는 금속 비아(132)와 도전부(133)를 형성하고, 도 7에 도시된 바와 같이 다시 상기 절연층(122) 상에 보호층(135)을 형성하여 상부 기판(200)을 형성한다.Subsequently, as shown in FIG. 6, the via 136 and the upper portion of the via 136 are plated to form a metal via 132 and a conductive portion 133 connected to the terminal 131 of the first device 130. As shown in FIG. 7, the upper layer 200 is formed by forming the protective layer 135 on the insulating layer 122 again.
또한, 본 발명의 일실시예에 따른 하부 기판(300)은 상기 상부 기판(200)의 제조 방법과 동일한 방법으로 형성할 수 있다.In addition, the lower substrate 300 according to an embodiment of the present invention may be formed by the same method as the manufacturing method of the upper substrate 200.
이후에는 도 8에 도시된 바와 같이 상부 기판(200)과 하부 기판(300)을 상호간에 접합하여 매립형 인쇄회로기판을 형성할 수 있다.Thereafter, as illustrated in FIG. 8, the buried printed circuit board may be formed by bonding the upper substrate 200 and the lower substrate 300 to each other.
이때, 상부 기판(200)과 하부 기판(300)의 사이에는 접합층(160)을 더 포함할 수 있다.In this case, the bonding layer 160 may be further included between the upper substrate 200 and the lower substrate 300.
상기 접합층(160)은 상부 기판(200)과 하부 기판(300)을 용이하게 접합하기 위한 부재로서, 상기 제1 절연 기판(121), 제2 절연 기판(141) 및 접합층(160)은 동일한 재료로 구성될 수 있다.The bonding layer 160 is a member for easily bonding the upper substrate 200 and the lower substrate 300. The first insulating substrate 121, the second insulating substrate 141, and the bonding layer 160 may be It may be made of the same material.
예를 들어 제1 절연 기판(121), 제2 절연 기판(141) 및 접합층(160)은 유리 섬유와 수지재를 포함하는 재료로 형성될 수 있다.For example, the first insulating substrate 121, the second insulating substrate 141, and the bonding layer 160 may be formed of a material including glass fiber and a resin material.
또 다른 실시예에서는 상기 제1 절연 기판(121)과 제2 절연 기판(141)이 별도의 부재 없이 상호간에 직접 접합되도록 구성될 수도 있으며, 마찬가지로 제1 절연 기판(121)과 제2 절연 기판(141)은 동일한 재료로 구성될 수 있다.In another embodiment, the first insulating substrate 121 and the second insulating substrate 141 may be configured to be directly bonded to each other without a separate member, and likewise, the first insulating substrate 121 and the second insulating substrate ( 141 may be composed of the same material.
따라서, 상기 절연층(122, 142)은 상기 제1 절연 기판(121)과 제2 절연 기판(141), 그리고 접합층(160)과 동일한 재료로 형성될 수 있다.Therefore, the insulating layers 122 and 142 may be formed of the same material as the first insulating substrate 121, the second insulating substrate 141, and the bonding layer 160.
도 9는 상부 기판(200)과 하부 기판(300)이 접합된 매립형 인쇄회로기판의 단면도이다.9 is a cross-sectional view of an embedded PCB having the upper substrate 200 and the lower substrate 300 bonded thereto.
도 9에 도시된 바와 같이, 상기 제1 소자(130)의 두께(a1)와 상기 2 소자(150)의 두께(a2)의 합은 상기 절연 기판(100)의 두께(b)의 1/2로 형성될 수 있으며, 그에 따라 상기 제1 소자(130), 상기 제2 소자(150)와 상기 절연 기판(110)의 각각의 두께는 1: 1: 4의 비율로 형성함으로써, 보다 얇은 두께의 제1, 2 소자(130, 150)를 절연 기판(110) 상에서 상호간에 대응되는 위치에 양면으로 배치하여, 보다 고집적의 소형화된 매립형 인쇄회로기판을 제공할 수 있다.As shown in FIG. 9, the sum of the thickness a1 of the first element 130 and the thickness a2 of the second element 150 is 1/2 of the thickness b of the insulating substrate 100. The thickness of each of the first element 130, the second element 150, and the insulating substrate 110 may be formed in a ratio of 1: 1, thereby forming a thinner thickness. The first and second elements 130 and 150 may be disposed on both sides of the insulating substrate 110 at positions corresponding to each other, thereby providing a more compact miniaturized embedded printed circuit board.
또한, 동일한 두께의 제1, 2 소자(130, 150)를 인쇄회로기판 내에 대칭구조를 이루도록 배치하여, 인쇄회로기판에 뒤틀림(warpage) 현상이 발생하거나 제1, 2 소자(130, 150)가 배치된 상면에 굴곡(bulge)이 발생하지 않도록 할 수 있다.In addition, the first and second devices 130 and 150 having the same thickness may be arranged in a printed circuit board to form a symmetrical structure, such that warpage may occur on the printed circuit board, or the first and second devices 130 and 150 may be It is possible to prevent the occurrence of a bend (bulge) on the top surface disposed.
전술한 바와 같은 본 발명의 상세한 설명에서는 구체적인 실시예에 관해 설명하였다. 그러나 본 발명의 범주에서 벗어나지 않는 한도 내에서는 여러 가지 변형이 가능하다. 본 발명의 기술적 사상은 본 발명의 전술한 실시예에 국한되어 정해져서는 안 되며, 특허청구범위뿐만 아니라 이 특허청구범위와 균등한 것들에 의해 정해져야 한다.In the detailed description of the invention as described above, specific embodiments have been described. However, many modifications are possible without departing from the scope of the invention. The technical spirit of the present invention should not be limited to the above-described embodiments of the present invention, but should be determined not only by the claims, but also by those equivalent to the claims.

Claims (17)

  1. 절연기판;Insulating substrate;
    상기 절연기판의 내부에 포함되며, 상기 절연기판을 폭방향으로 양분하는 접합 절연층;A junction insulation layer included in the insulation substrate and bisecting the insulation substrate in a width direction;
    상기 접합 절연층의 일면 측에 배치되는 제1소자; 및A first element disposed on one side of the junction insulating layer; And
    상기 접합 절연층의 타면 측에 배치되며, 상기 제1소자와 대칭되는 위치에 배치되는 제2소자;A second element disposed at the other surface side of the junction insulating layer and disposed at a position symmetrical with the first element;
    를 포함하는 매립형 인쇄회로기판.Embedded printed circuit board comprising a.
  2. 청구항 1에 있어서,The method according to claim 1,
    상기 제1소자의 두께와 상기 제2소자의 두께의 합은,The sum of the thickness of the first element and the thickness of the second element is
    상기 절연기판의 두께의 1/2 이하인 매립형 인쇄회로기판.A buried printed circuit board having a thickness of 1/2 or less of the insulation board.
  3. 청구항 2에 있어서,The method according to claim 2,
    상기 제1소자와 상기 제2소자의 두께가 실질적으로 동일한 매립형 인쇄회로기판.A buried printed circuit board having substantially the same thickness as the first element and the second element.
  4. 청구항 1에 있어서,The method according to claim 1,
    상기 제1소자 및 상기 제2소자는,The first device and the second device,
    상기 절연기판 내에 포함되는 제1절연기판 및 제2절연기판 내에 각각 수용되는 매립형 인쇄회로기판.A buried printed circuit board respectively accommodated in the first insulating substrate and the second insulating substrate included in the insulating substrate.
  5. 청구항 3에 있어서,The method according to claim 3,
    상기 제1소자는 상기 접합절연층의 상부에 인접하는 제1절연기판의 캐비티 상에 배치되며,The first element is disposed on a cavity of the first insulating substrate adjacent to the upper portion of the junction insulating layer,
    상기 제2소자는 상기 접합절연층의 하부에 인접하는 제2절연기판의 캐비티 상에 배치되는 매립형 인쇄회로기판.The second device is a buried printed circuit board is disposed on the cavity of the second insulating substrate adjacent to the lower portion of the junction insulating layer.
  6. 청구항 3에 있어서,The method according to claim 3,
    상기 제1절연기판의 캐비티 및 상기 제2절연기판의 캐비티는 상호 대응되는 위치에 형성되는 매립형 인쇄회로기판.The buried printed circuit board of the cavity of the first insulating substrate and the cavity of the second insulating substrate are formed at positions corresponding to each other.
  7. 청구항 4에 있어서,The method according to claim 4,
    상기 제1절연기판 및 상기 제2절연기판의 캐비티의 폭이 서로 동일한 매립형 인쇄회로기판.A buried printed circuit board having the same width as a cavity of the first insulating substrate and the second insulating substrate.
  8. 청구항 4에 있어서,The method according to claim 4,
    상기 제1절연기판 및 상기 제2절연기판은 상호 동일한 재료로 형성되는 매립형 인쇄회로기판.The buried printed circuit board of which the first insulating substrate and the second insulating substrate are formed of the same material.
  9. 청구항 6에 있어서,The method according to claim 6,
    상기 접합 절연층은,The junction insulating layer,
    상기 제1절연기판 및 상기 제2절연기판과 열팽창 계수가 실질적으로 동일한 소재인 매립형 인쇄회로기판.A buried printed circuit board having a material having substantially the same thermal expansion coefficient as the first insulating substrate and the second insulating substrate.
  10. 청구항 4에 있어서,The method according to claim 4,
    상기 제1절연기판 및 상기 제2절연기판은 실질적으로 상호 동일한 두께인 매립형 인쇄회로기판.The buried printed circuit board of which the first insulating substrate and the second insulating substrate have substantially the same thickness.
  11. 청구항 10에 있어서,The method according to claim 10,
    상기 제1소자의 두께: 상기 제2소자의 두께: 상기 절연기판 의 두께의 비율은, 1:1:4인 매립형 인쇄회로기판.The thickness of the first element: the thickness of the second element: the ratio of the thickness of the insulating substrate is a buried printed circuit board is 1: 1: 4.
  12. 청구항 4에 있어서,The method according to claim 4,
    상기 제1소자 및 상기 제2 소자의 두께는,The thickness of the first device and the second device,
    30 ㎛ 내지 120 ㎛인 매립형 인쇄회로기판.An embedded printed circuit board having a thickness of 30 μm to 120 μm.
  13. 청구항 12에 있어서,The method according to claim 12,
    상기 절연 기판의 두께는,The thickness of the insulating substrate,
    380 ㎛ 내지 400 ㎛인 매립형 인쇄회로기판.An embedded PCB having a thickness of 380 µm to 400 µm.
  14. 청구항 4에 있어서,The method according to claim 4,
    상기 제1절연기판 및 상기 제2절연기판은,The first insulating substrate and the second insulating substrate,
    유리 섬유와 수지재를 포함하는 매립형 인쇄회로기판.An embedded printed circuit board comprising glass fiber and a resin material.
  15. 청구항 4에 있어서,The method according to claim 4,
    상기 제1 소자는,The first element,
    상기 절연 기판의 일면 측으로 배치된 단자가 상기 절연 기판의 일면 상의 도전부와 연결되고,A terminal disposed on one side of the insulating substrate is connected to a conductive part on one surface of the insulating substrate,
    상기 제2 소자는,The second element,
    상기 절연 기판의 타면 측으로 배치된 단자가 상기 절연 기판의 타면 상의 도전부와 연결되는 매립형 인쇄회로기판.A buried printed circuit board having a terminal disposed on the other side of the insulating substrate connected to a conductive part on the other surface of the insulating substrate.
  16. 청구항 15에 있어서,The method according to claim 15,
    상기 절연기판의 일면 및 타면 상에는 상기 도전부와 인접하는 보호층을 더 포함하는 매립형 인쇄회로기판.A buried printed circuit board further comprising a protective layer adjacent to the conductive portion on one surface and the other surface of the insulating substrate.
  17. 청구항 4에 있어서,The method according to claim 4,
    상기 접합절연층에 상기 제1소자 및 상기 제2소자의 단자가 형성되는 받대면이 밀착하는 구조로 배치되는 매립형 인쇄회로기판.A buried printed circuit board having a structure in which a support surface on which the terminals of the first device and the second device are formed is in close contact with the junction insulating layer.
PCT/KR2015/000650 2014-01-22 2015-01-21 Embedded printed circuit board WO2015111923A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2014-0007905 2014-01-22
KR1020140007905A KR102237778B1 (en) 2014-01-22 2014-01-22 Embedded printed circuit substrate

Publications (1)

Publication Number Publication Date
WO2015111923A1 true WO2015111923A1 (en) 2015-07-30

Family

ID=53681671

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/KR2015/000650 WO2015111923A1 (en) 2014-01-22 2015-01-21 Embedded printed circuit board

Country Status (2)

Country Link
KR (1) KR102237778B1 (en)
WO (1) WO2015111923A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019239030A1 (en) * 2018-06-13 2019-12-19 Institut Vedecom Power switching modular element and dismountable assembly of a plurality of modular elements

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070000687A1 (en) * 2005-06-30 2007-01-04 Brist Gary A Apparatus and method for an embedded air dielectric for a package and a printed circuit board
KR20090002718A (en) * 2007-07-04 2009-01-09 삼성전기주식회사 Carrier and method for manufacturing printed circuit board
JP2011138869A (en) * 2009-12-28 2011-07-14 Ngk Spark Plug Co Ltd Method of manufacturing multilayer wiring substrate, and multilayer wiring substrate
KR20120036044A (en) * 2010-10-07 2012-04-17 대덕전자 주식회사 Method of manufacturing a chip-embedded multi-level printed circuit board
JP2013038374A (en) * 2011-01-20 2013-02-21 Ibiden Co Ltd Wiring board and manufacturing method of the same

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100656751B1 (en) * 2005-12-13 2006-12-13 삼성전기주식회사 Electronic components embedded pcb and the method for manufacturing thereof
KR101119303B1 (en) * 2010-01-06 2012-03-20 삼성전기주식회사 A printed circuit board comprising embedded electronic component within and a method for manufacturing the same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070000687A1 (en) * 2005-06-30 2007-01-04 Brist Gary A Apparatus and method for an embedded air dielectric for a package and a printed circuit board
KR20090002718A (en) * 2007-07-04 2009-01-09 삼성전기주식회사 Carrier and method for manufacturing printed circuit board
JP2011138869A (en) * 2009-12-28 2011-07-14 Ngk Spark Plug Co Ltd Method of manufacturing multilayer wiring substrate, and multilayer wiring substrate
KR20120036044A (en) * 2010-10-07 2012-04-17 대덕전자 주식회사 Method of manufacturing a chip-embedded multi-level printed circuit board
JP2013038374A (en) * 2011-01-20 2013-02-21 Ibiden Co Ltd Wiring board and manufacturing method of the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019239030A1 (en) * 2018-06-13 2019-12-19 Institut Vedecom Power switching modular element and dismountable assembly of a plurality of modular elements
FR3082660A1 (en) * 2018-06-13 2019-12-20 Institut Vedecom MODULAR POWER SWITCHING ELEMENT AND DEMOUNTABLE ASSEMBLY OF SEVERAL MODULAR ELEMENTS

Also Published As

Publication number Publication date
KR20150087682A (en) 2015-07-30
KR102237778B1 (en) 2021-04-09

Similar Documents

Publication Publication Date Title
WO2012169866A2 (en) Printed circuit board and method for manufacturing the same
WO2014104654A1 (en) Printed circuit board, and method for manufacturing same
WO2012141541A2 (en) Interposer for optical module, optical module using the same, method for manufacturing the same
WO2017052046A1 (en) Flexible circuit board having enhanced bending durability
WO2012150817A2 (en) Method for manufacturing printed circuit board
WO2017146394A1 (en) Flexible printed circuit board
WO2012050333A2 (en) Radiant heat circuit board, method of manufacturing the same, heat generating device package having the same, and backlight
WO2013062289A1 (en) Light emitting diode package and light emitting module comprising the same
WO2017052274A1 (en) Flexible circuit board having three-layer dielectric body and four-layer ground layer structure
WO2021010581A1 (en) Electronic device including interposer
WO2014069734A1 (en) Printed circuit board
WO2012047024A2 (en) Optical printed circuit board and method for manufacturing the same
WO2019160240A1 (en) Flexible circuit board and electronic device comprising same
WO2012047002A2 (en) Radiant heat circuit board, heat generating device package having the same, and backlight unit
WO2015111923A1 (en) Embedded printed circuit board
WO2013032277A2 (en) Method of manufacturing substrate for chip packages and method of manufacturing chip package
WO2012150777A2 (en) The printed circuit board and the method for manufacturing the same
WO2014126287A1 (en) Soldered joint structure of separable printed circuit board
WO2022045729A1 (en) Printed circuit board module and electronic device comprising same
WO2021225290A1 (en) Electronic device comprising interposer
WO2019164118A1 (en) Circuit board
WO2020085639A1 (en) Electronic device comprising ground reinforcement structure
WO2020054943A1 (en) Tape member and electronic apparatus including same
WO2009108030A2 (en) Printed circuit board and method of manufacturing the same
WO2016093520A2 (en) Wiring interposer and electronic module having same

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15739944

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 15739944

Country of ref document: EP

Kind code of ref document: A1