WO2015109986A1 - 显示面板 - Google Patents

显示面板 Download PDF

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Publication number
WO2015109986A1
WO2015109986A1 PCT/CN2015/071072 CN2015071072W WO2015109986A1 WO 2015109986 A1 WO2015109986 A1 WO 2015109986A1 CN 2015071072 W CN2015071072 W CN 2015071072W WO 2015109986 A1 WO2015109986 A1 WO 2015109986A1
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WO
WIPO (PCT)
Prior art keywords
dummy
pixel
pin
scan
data
Prior art date
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PCT/CN2015/071072
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English (en)
French (fr)
Inventor
柴立
Original Assignee
深圳市华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to US14/647,107 priority Critical patent/US9799247B2/en
Publication of WO2015109986A1 publication Critical patent/WO2015109986A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133388—Constructional arrangements; Manufacturing methods with constructional differences between the display region and the peripheral region
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136254—Checking; Testing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0413—Details of dummy pixels or dummy lines in flat panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections

Definitions

  • the present invention relates to the field of display panels, and in particular, to a test circuit structure of a display panel.
  • the present invention provides a display panel including a plurality of scanning lines extending in a first direction, a plurality of data lines extending in a second direction and intersecting the scanning lines, and disposed adjacent to each other a common electrode line between the two scan lines and parallel to the scan line, a wiring area surrounding the scan line, the data line, and the common electrode line, and a plurality of test pins for testing.
  • the scan lines and data lines define a plurality of pixel units arranged in a matrix.
  • a pixel electrode connected to the corresponding data line is disposed in each of the pixel units.
  • the pixel unit includes a display pixel located in the display area for displaying an image and a virtual pixel located at an edge of the display area.
  • the pixel electrode of the display pixel and the common electrode line are insulated from each other.
  • the pixel electrode of the dummy pixel is connected to the common electrode line through a connection hole, and the scan line, the data line and the common electrode line of the dummy pixel are respectively connected to corresponding test pins through connection lines in the wiring area.
  • each of the pixel units is provided with a thin film transistor disposed at a intersection of the scan line and the data line, the thin film transistor including a gate connected to the scan line, a gate insulating layer disposed on the gate, and a setting a semiconductor layer on the gate insulating layer, a source and a drain electrically connected to the semiconductor layer, and a passivation layer covering the source and the drain, respectively.
  • a recessed hole extending inwardly to the semiconductor layer is disposed between the source and the drain.
  • the passivation layer is filled into the recess to insulate the source and drain from each other.
  • One end of the source is connected to the data line.
  • the other end of the source is connected to the drain through a semiconductor layer.
  • the other end of the drain opposite to the semiconductor layer is connected to the pixel electrode.
  • An ohmic contact layer is disposed between the source and the drain and the semiconductor layer.
  • the gate insulating layer and the passivation layer covering the common electrode line in the dummy pixel are provided with connection holes corresponding to the common electrode line.
  • a pixel electrode in the dummy pixel is connected to the common electrode through the connection hole.
  • the materials of the gate insulating layer and the passivation layer are all nitrogen silicon compounds.
  • the material of the semiconductor layer is amorphous silicon.
  • the test pin includes an odd-numbered virtual scan pin connected to a scan line of an odd-order virtual pixel, an even-numbered virtual scan pin connected to a scan line of an even-numbered dummy pixel, and a data line connected to an odd-numbered virtual pixel.
  • the virtual pixels are first virtual pixels, second virtual pixels, third virtual pixels, and fourth virtual pixels respectively disposed at four corners of the display area.
  • a scan line of the first dummy pixel is connected to the odd dummy scan pin.
  • the data line of the first dummy pixel is connected to the even dummy data pin.
  • the common electrode line of the first dummy pixel is connected to the common pin.
  • a scan line of the second dummy pixel is connected to the even-numbered virtual scan pin.
  • the data line of the second dummy pixel is connected to the even dummy data pin.
  • the common electrode line of the second dummy pixel is connected to the common pin.
  • a scan line of the third dummy pixel is connected to the even-numbered virtual scan pin.
  • the data line of the third dummy pixel is connected to the odd dummy data pin.
  • the common electrode line of the third dummy pixel is connected to the common pin.
  • a scan line of the fourth dummy pixel is connected to the odd dummy scan pin.
  • the data line of the fourth dummy pixel is connected to the odd dummy data pin.
  • the common electrode line of the fourth dummy pixel is connected to the common pin.
  • the virtual pixel includes a first virtual pixel group and a second virtual pixel group respectively disposed along two long side edges of the rectangular display area parallel to each other.
  • the first virtual pixel group and the second virtual pixel group respectively comprise a plurality of sequentially arranged virtual pixels.
  • the plurality of dummy pixels in the first virtual pixel group share one scan line and are connected to the odd virtual scan pins.
  • the data lines of the plurality of dummy pixels in the first virtual pixel group are respectively connected to a red data pin, a green data pin or a blue data pin.
  • the common electrode lines of the plurality of dummy pixels in the first dummy pixel group are connected to a common pin.
  • the second A plurality of dummy pixels in the virtual pixel group share one scan line and are connected to even-numbered virtual scan pins.
  • the data lines of the plurality of dummy pixels in the second virtual pixel group are respectively connected to a red data pin, a green data pin or a blue data pin.
  • the common electrode lines of the plurality of dummy pixels in the first dummy pixel group are connected to a common pin.
  • the virtual pixel includes a third virtual pixel group and a fourth virtual pixel group respectively disposed along two short side edges of the rectangular display area parallel to each other.
  • the third virtual pixel group and the fourth virtual pixel group respectively include a plurality of sequentially arranged virtual pixels.
  • the scan lines of the plurality of dummy pixels in the third virtual pixel group are respectively connected to the odd virtual scan pins or the even virtual scan pins.
  • the data lines of the plurality of dummy pixels in the third virtual pixel group are connected to the even dummy data pins.
  • the common electrode lines of the plurality of dummy pixels in the third dummy pixel group are connected to a common pin.
  • the scan lines of the plurality of dummy pixels in the fourth dummy pixel group are respectively connected to the odd virtual scan pins or the even virtual scan pins.
  • the data lines of the plurality of dummy pixels in the fourth virtual pixel group are connected to the even virtual data pins.
  • the common electrode lines of the plurality of dummy pixels in the fourth dummy pixel group are connected to a common pin.
  • the display panel provided by the invention can flexibly select and test corresponding virtual pixels in the display area by matching different test pins. Secondly, by connecting the pixel electrode and the common electrode line in the dummy pixel, the display panel can test the telecommunications of the pixel unit in the display area only by means of the peripheral pins.
  • FIG. 1 is a schematic structural view of a display panel according to a first embodiment of the present invention
  • FIG. 2 is a schematic structural view of the display pixel of FIG. 1;
  • FIG. 3 is a schematic structural diagram of a virtual pixel in FIG. 1;
  • Figure 4 is a cross-sectional view taken along line IV-IV of Figure 2;
  • Figure 5 is a cross-sectional view taken along line V-V of Figure 2;
  • Figure 6 is a cross-sectional view taken along line VI-VI of Figure 3;
  • Figure 7 is an enlarged view of a portion VII of Figure 1;
  • FIG. 8 is a schematic structural diagram of a display panel according to a second embodiment of the present invention.
  • FIG. 9 is a schematic structural diagram of a display panel according to a third embodiment of the present invention.
  • the display panel 1 includes a plurality of scanning lines 10 extending in a first direction, extending along a second direction and the scanning lines. 10 intersecting plurality of data lines 12, common electrode lines 14 disposed between adjacent two scan lines 10 and parallel to the scan lines 10, surrounding the scan lines 10, the data lines 12, and the common electrode lines 14. Wiring area 16 and a plurality of test pins 18 for testing.
  • the scan line 10 and the data line 12 define a plurality of pixel units 20 arranged in a matrix.
  • a pixel electrode 15 connected to the corresponding data line 12 is disposed in each of the pixel units 20.
  • the pixel unit 20 includes a display pixel 22 for displaying an image in the display area 21 and a dummy pixel 24 located at an edge of the display area 21.
  • the pixel electrode 15 of the display pixel 22 and the common electrode line 14 are insulated from each other.
  • the pixel electrode 15 of the dummy pixel 24 is connected to the common electrode line 14 through a connection hole.
  • the scan line 10, the data line 12, and the common electrode line 14 of the dummy pixel 24 are connected to the test pin 18 through connection lines in the wiring area 16, respectively.
  • the display panel 1 is a Thin Film Transistor (TFT) array substrate.
  • TFT Thin Film Transistor
  • a TFT structure 11 is disposed in each of the pixel units 20 at a intersection of the scan line 10 and the data line 12.
  • the TFT structure 11 includes a gate electrode 110, a gate insulating layer 111, a semiconductor layer 112, an ohmic contact layer 113, a source electrode 114, a drain electrode 115, and a passivation layer 116.
  • the gate 110 is connected to the scan line 10.
  • the gate insulating layer 111 is disposed on the gate 110.
  • the semiconductor layer 112 is disposed on the gate insulating layer 111.
  • the ohmic contact layer 113 is disposed on the semiconductor layer 112.
  • a conductor layer is disposed on the ohmic contact layer 113.
  • a position of the corresponding gate 110 on the conductor layer defines a recess 117 extending into the semiconductor layer 112 to separate the conductor layer into the source 114 and the drain. Extreme 115.
  • One end of the source 114 is connected to the data line 12, and the other end is connected to the drain 115 through the semiconductor layer 112.
  • the passivation layer 116 covers the conductor layer and fills the recess 117 to insulate the source 114 and the drain 115 from each other.
  • the passivation layer 116 defines a via 118 corresponding to the other side of the drain 115 opposite to the semiconductor layer 112.
  • One end of the pixel electrode 15 is connected to the drain 115 through the via 118.
  • the gate insulating layer 111 is two layers.
  • the materials of the gate insulating layer 111 and the passivation layer 116 are all nitrogen silicon compounds.
  • the material of the semiconductor layer 112 is amorphous silicon. It can be understood that in other embodiments, the material of the semiconductor layer 112 can also be made of polysilicon.
  • the common electrode line 14 is passed by the middle of each pixel unit 20 in the direction parallel to the scanning line 10.
  • the gate insulating layer 111 in the display pixel 22 extends and covers the common electrode line 14.
  • the passivation layer 116 in the display pixel 22 also extends and covers the gate insulating layer 111.
  • the pixel electrode 15 in the display pixel 22 is disposed on the passivation layer 116 to be insulated from the common electrode line 14.
  • a gate insulating layer 111 and a passivation layer 116 overlying the common electrode line 14 in the dummy pixel 24 are provided with a connection hole 119 corresponding to the common electrode line 14.
  • the pixel electrode 15 in the dummy pixel 24 is connected to the common electrode through the connection hole 119.
  • the display area 21 is a rectangular area located at the center of the display panel 1.
  • the pixel unit 20 in the display area 21 is the display pixel 22.
  • the dummy pixels 24 are first dummy pixels 241, second dummy pixels 242, third dummy pixels 243, and fourth dummy pixels 244 respectively disposed at four corners of the display area 21.
  • the test pin 18 includes an odd-numbered virtual scan pin gate_dummy_odd connected to the scan line 10 of the odd-numbered dummy pixel 24, and an even-numbered virtual scan pin gate_dummy_even connected to the scan line 10 of the even-numbered dummy pixel 24.
  • the data line 12 is connected to the green data pin data_green, the blue data pin data_blue connected to the data line 12 transmitting the blue display signal, and the common pin A_comm connected to the common electrode line 14.
  • the scan line 10 of the first dummy pixel 241 is connected to the odd-numbered virtual scan pin gate_dummy_odd.
  • the data line 12 of the first dummy pixel 241 is connected to the even dummy data pin data_dummy_even.
  • the common electrode line 14 of the first dummy pixel 241 is connected to the common pin A_comm.
  • the scan line 10 of the second dummy pixel 242 is connected to the even-numbered virtual scan pin gate_dummy_even.
  • the data line 12 of the second dummy pixel 242 is connected to the even dummy data pin data_dummy_even.
  • the common electrode line 14 of the second dummy pixel 242 Connected to the common pin A_comm.
  • the scan line 10 of the third dummy pixel 243 is connected to the even-numbered virtual scan pin gate_dummy_even.
  • the data line 12 of the third dummy pixel 243 is connected to the odd dummy data pin data_dummy_odd.
  • the common electrode line 14 of the third dummy pixel 243 is connected to the common pin A_comm.
  • the scan line 10 of the fourth dummy pixel 244 is connected to the odd-numbered virtual scan pin gate_dummy_odd.
  • the data line 12 of the fourth dummy pixel 244 is connected to the odd dummy data pin data_dummy_odd.
  • the common electrode line 14 of the fourth dummy pixel 244 is connected to the common pin A_comm.
  • the pixel electrode 15 of the dummy pixel 24 is connected to the common electrode line 14, a combination of different odd/even virtual scan pins and odd/even dummy data pins is tested to select the corresponding dummy pixel 24 and input for testing.
  • the signal, and then the common pin A_comm connected to the common electrode line 14 of the dummy pixel 24, can measure the test signal received on the pixel electrode 15 of the virtual pixel 24, thereby judging via the same manufacturing process as the dummy pixel 24.
  • the electrical quality of the resulting display pixels 22 can be measured.
  • the structure of the display panel 2 provided by the second embodiment of the present invention is substantially the same as that of the display panel 1 of the first embodiment, and the difference is that the virtual pixels 25 are respectively included along the display area.
  • the first virtual pixel group 251 and the second virtual pixel group 252 are disposed at two long side edges which are parallel to each other.
  • the first virtual pixel group 251 and the second virtual pixel group 252 respectively include a plurality of sequentially arranged virtual pixels 25.
  • the plurality of dummy pixels 25 in the first dummy pixel group 251 share one scan line 10 and are connected to the odd virtual scan pin gate_dummy_odd.
  • the data lines 12 of the plurality of dummy pixels 25 in the first virtual pixel 251 group are respectively connected to the red data pin data_red, the green data pin data_green or the blue data pin data_blue.
  • the common electrode line 14 of the plurality of dummy pixels 25 in the group of the first dummy pixels 251 is connected to the common pin A_comm.
  • the plurality of dummy pixels 25 in the second dummy pixel group 252 share one scan line 10 and are connected to the even-numbered virtual scan pin gate_dummy_even.
  • the data lines 12 of the plurality of dummy pixels in the second dummy pixel group 252 are respectively connected to the red data pin data_red, the green data pin data_green or the blue data pin data_blue.
  • the common electrode line 14 of the plurality of dummy pixels in the group of the first dummy pixels 251 is connected to the common pin A_comm.
  • the display panel 2 provided by the second embodiment of the present invention can test the electrical average of the two sets of dummy pixels 25 disposed along the length direction of the display panel 2 by switching the odd/even virtual scan pins.
  • the structure of the display panel 3 according to the third embodiment of the present invention is substantially the same as that of the display panel 1 of the first embodiment, except that the virtual pixels 34 are respectively included along the
  • the third virtual pixel group 341 and the fourth virtual pixel group 342 are disposed on the two short side edges of the display area 31 which are parallel to each other.
  • the third virtual pixel group 341 and the fourth virtual pixel group 342 respectively include a plurality of sequentially arranged virtual pixels 34.
  • the scan lines 10 of the plurality of dummy pixels 34 in the third dummy pixel group 341 are respectively connected to the odd-numbered virtual scan pins gate_dummy_odd or the even-numbered virtual scan pins gate_dummy_even.
  • the data lines 12 of the plurality of dummy pixels 34 in the third dummy pixel group 341 are connected to the even dummy data pin data_dummy_even.
  • the common electrode line 14 of the plurality of dummy pixels 34 in the third dummy pixel group 341 is connected to the common pin A_comm.
  • the scan lines 10 of the plurality of dummy pixels 34 in the fourth dummy pixel group 342 are respectively connected to the odd-numbered virtual scan pins gate_dummy_odd or the even-numbered virtual scan pins gate_dummy_even.
  • the data lines 12 of the plurality of dummy pixels 34 in the fourth dummy pixel group 342 are connected to the even dummy data pin data_dummy_even.
  • the common electrode line 14 of the plurality of dummy pixels 34 in the fourth dummy pixel group 342 is connected to the common pin A_comm.
  • the display panel 3 provided by the third embodiment of the present invention can test the electrical average of the two sets of dummy pixels 34 disposed along the short side of the display panel 3 by switching the odd/even virtual data pins.
  • the display panel 1 provided in this embodiment can flexibly select and test the corresponding virtual pixels 24 in the display area 21 by matching different test pins 18. Secondly, by connecting the pixel electrode 15 and the common electrode line 14 in the dummy pixel 24, the display panel 1 can test the telecommunications of the pixel unit 20 in the display area 21 by means of only the peripheral pins.

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  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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  • Theoretical Computer Science (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

一种显示面板（1），其包括扫描线（10）、数据线（12）、设置于相邻扫描线（100之间的公共电极线（14）、包围扫描线（10）、数据线（12）及公共电极线（14）的布线区（16）及测试引脚（18）。扫描线（10）与数据线（12）相交以定义呈矩阵排列的像素单元（20）。每个像素单元（20）内设置有与对应数据线（12）相连的像素电极（15）。像素单元（20）包括位于显示区域（21）内以显示图像的显示像素（22）及位于显示区域（21）边缘处的虚拟像素（24）。显示像素（22）的像素电极（15）与公共电极线（14）绝缘间隔。该虚拟像素（24）的像素电极（15）与公共电极线（14）通过一连接孔（119）相连。虚拟像素（24）的扫描线（10）、数据线（12）及公共电极线（14）分别通过布线区（16）内的连接线与对应的测试引脚（18）相连。

Description

显示面板 技术领域
本发明涉及显示面板领域，尤其涉及一种显示面板的测试线路结构。
背景技术
现有显示面板一般会在面板的边缘区域设置用于测试的引脚以对面板线路的电学特性进行测试。然而，现有显示面板上的这些测试引脚大多设置在面板的成膜有效区外，其电学特性与成膜有效区内的线路差异较大，从而导致通过该引脚测得的结果不可靠。
因此，需要提供能够解决上述问题的线路修补方法及线路修补结构。
发明内容
为了解决上述技术问题，本发明提供了一种显示面板，其包括沿第一方向延伸的多条扫描线、沿第二方向延伸并与所述扫描线相交的多条数据线、设置于相邻两条扫描线之间并与所述扫描线平行的公共电极线、包围所述扫描线、数据线及公共电极线的布线区及用于测试的多个测试引脚。所述扫描线及数据线定义出多个呈矩阵排列的像素单元。每个像素单元内设置有与对应数据线相连接的像素电极。所述像素单元包括位于显示区域内用于显示图像的显示像素及位于所述显示区域边缘处的虚拟像素。所述显示像素的像素电极与公共电极线相互绝缘间隔。所述虚拟像素的像素电极与公共电极线通过一连接孔相连接，所述虚拟像素的扫描线、数据线及公共电极线分别通过布线区内的连接线路与对应的测试引脚相连。
其中，所述每个像素单元内于扫描线与数据线相交处设置有的薄膜电晶体，所述薄膜电晶体包括与扫描线相连的栅极、设置在栅极上的栅极绝缘层、设置在栅极绝缘层上的半导体层、分别与所述半导体层电连接的源极与漏极以及覆盖所述源极与漏极的钝化层。
其中，所述源极与漏极之间开设有向内延伸至所述半导体层的凹孔。所述钝化层填充入所述凹孔内以将所述源极与漏极相互绝缘。所述源极的一端与数据线相连接。所述源极的另一端通过半导体层与漏极相连接。所述漏极与半导体层相对的另一端与所述像素电极相连接。
其中，所述源极及漏极与所述半导体层之间设置有欧姆接触层。
其中，所述虚拟像素内覆盖在所述公共电极线上的栅极绝缘层及钝化层对应所述公共电极线开设有连接孔。所述虚拟像素内的像素电极通过所述连接孔与公共电极相连接。
其中，所述栅极绝缘层及钝化层的材料均为氮硅化合物。所述半导体层的材料为非晶硅。
其中，所述测试引脚包括与奇数排虚拟像素的扫描线连接的奇数虚拟扫描引脚、与偶数排虚拟像素的扫描线连接的偶数虚拟扫描引脚、与奇数列虚拟像素的数据线连接的奇数虚拟数据引脚、与偶数列虚拟像素的数据线连接的偶数虚拟数据引脚、与奇数排显示像素的扫描线连接的奇数显示扫描引脚、与偶数排显示像素的扫描线连接的偶数显示扫描引脚、与传输红色显示信号的数据线相连接的红色数据引脚、与传输绿色显示信号的数据线相连接的绿色数据引脚、与传输蓝色显示信号的数据线相连接的蓝色数据引脚以及与所述公共电极线连接的公共引脚。
其中，所述虚拟像素为分别设置在显示区域的四个边角处的第一虚拟像素、第二虚拟像素、第三虚拟像素及第四虚拟像素。所述第一虚拟像素的扫描线与所述奇数虚拟扫描引脚连接。所述第一虚拟像素的数据线与所述偶数虚拟数据引脚连接。所述第一虚拟像素的公共电极线与所述公共引脚连接。所述第二虚拟像素的扫描线与所述偶数虚拟扫描引脚连接。所述第二虚拟像素的数据线与所述偶数虚拟数据引脚连接。所述第二虚拟像素的公共电极线与所述公共引脚连接。所述第三虚拟像素的扫描线与所述偶数虚拟扫描引脚连接。所述第三虚拟像素的数据线与所述奇数虚拟数据引脚连接。所述第三虚拟像素的公共电极线与所述公共引脚连接。所述第四虚拟像素的扫描线与所述奇数虚拟扫描引脚连接。所述第四虚拟像素的数据线与所述奇数虚拟数据引脚连接。所述第四虚拟像素的公共电极线与所述公共引脚连接。
其中，所述虚拟像素包括分别沿矩形显示区域相互平行的两条长边边缘设置的第一虚拟像素组及第二虚拟像素组。所述第一虚拟像素组及第二虚拟像素组分别包括多个依次排列的虚拟像素。所述第一虚拟像素组内的多个虚拟像素共用一条扫描线并连接至奇数虚拟扫描引脚。所述第一虚拟像素组内的多个虚拟像素的数据线分别连接至红色数据引脚、绿色数据引脚或蓝色数据引脚。所述第一虚拟像素组内的多个虚拟像素的公共电极线连接至公共引脚。所述第二 虚拟像素组内的多个虚拟像素共用一条扫描线并连接至偶数虚拟扫描引脚。所述第二虚拟像素组内的多个虚拟像素的数据线分别连接至红色数据引脚、绿色数据引脚或蓝色数据引脚。所述第一虚拟像素组内的多个虚拟像素的公共电极线连接至公共引脚。
其中，所述虚拟像素包括分别沿矩形显示区域相互平行的两条短边边缘设置的第三虚拟像素组及第四虚拟像素组。所述第三虚拟像素组及第四虚拟像素组分别包括多个依次排列的虚拟像素。所述第三虚拟像素组内的多个虚拟像素的扫描线分别连接至奇数虚拟扫描引脚或偶数虚拟扫描引脚。所述第三虚拟像素组内的多个虚拟像素的数据线连接至偶数虚拟数据引脚。所述第三虚拟像素组内的多个虚拟像素的公共电极线连接至公共引脚。所述第四虚拟像素组内的多个虚拟像素的扫描线分别连接至奇数虚拟扫描引脚或偶数虚拟扫描引脚。所述第四虚拟像素组内的多个虚拟像素的数据线连接至偶数虚拟数据引脚。所述第四虚拟像素组内的多个虚拟像素的公共电极线连接至公共引脚。
本发明所提供的显示面板通过搭配不同的测试引脚可灵活地选择对显示区域内对应的虚拟像素进行测试。其次，通过在虚拟像素中穿孔连接像素电极及公共电极线使得所述显示面板仅借助外围的引脚便可以对显示区域内像素单元的电信进行测试。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1是本发明第一实施例所提供的显示面板的结构示意图；
图2是图1中的显示像素的结构示意图；
图3是图1中的虚拟像素的结构示意图；
图4是图2中沿IV-IV线的剖视图；
图5是图2中沿V-V线的剖视图；
图6是图3中沿VI-VI线的剖视图；
图7是图1中VII部分的放大图；
图8本发明第二实施例所提供的显示面板的结构示意图；
图9是本发明第三实施例所提供的显示面板的结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请一并参阅图1、图2及图3所示，本发明第一实施例所提供显示面板1包括沿第一方向延伸的多条扫描线10、沿第二方向延伸并与所述扫描线10相交的多条数据线12、设置于相邻两条扫描线10之间并与所述扫描线10平行的公共电极线14、包围所述扫描线10、数据线12及公共电极线14的布线区16及用于测试的多个测试引脚18。所述扫描线10及数据线12定义出多个呈矩阵排列的像素单元20。每个像素单元20内设置有与对应数据线12相连接的像素电极15。所述像素单元20包括位于显示区域21内用于显示图像的显示像素22及位于所述显示区域21边缘处的虚拟像素24。所述显示像素22的像素电极15与公共电极线14相互绝缘间隔。所述虚拟像素24的像素电极15与公共电极线14通过一连接孔相连接。所述虚拟像素24的扫描线10、数据线12及公共电极线14分别通过布线区16内的连接线路与测试引脚18相连。在本实施例中，所述显示面板1为薄膜电晶体(Thin Film Transistor，TFT)阵列基板。
如图4所示，所述每个像素单元20内于扫描线10与数据线12相交处设置有的TFT结构11。所述TFT结构11包括栅极110、栅极绝缘层111、半导体层112、欧姆接触层113、源极114、漏极115及钝化层116。所述栅极110与扫描线10相连接。所述栅极绝缘层111设置在所述栅极110上。所述半导体层112设置在所述栅极绝缘层111上。所述欧姆接触层113设置在半导体层112上。所述欧姆接触层113上铺设有一导体层，所述导体层上对应栅极110的位置开设有一延伸至半导体层112内的凹孔117以将所述导体层分隔为所述源极114与漏极115。所述源极114的一端与数据线12相连接，另一端通过所述半导体层112与所述漏极115相连接。所述钝化层116覆盖所述导体层并填充入所述凹孔117内以将所述源极114与漏极115相互绝缘。所述钝化层116对应于漏极115与半导体层112相对的另一侧开设有通孔118，所述像素电极15的一端通过该通孔118与漏极115相连接。
在本实施例中，所述栅极绝缘层111为两层。所述栅极绝缘层111及钝化层116的材料均为氮硅化合物。所述半导体层112的材料为非晶硅。可以理解的是，在其他实施例中，所述半导体层112的材料还可以采用多晶硅。
如图5及图6所示，所述公共电极线14由每个像素单元20的中部沿平行扫描线10的方向穿过。所述显示像素22内的栅极绝缘层111延伸并覆盖公共电极线14。所述显示像素22内的钝化层116同样延伸并覆盖所述栅极绝缘层111上。所述显示像素22内的像素电极15设置在钝化层116上与所述公共电极线14绝缘。所述虚拟像素24内覆盖在所述公共电极线14上的栅极绝缘层111及钝化层116对应所述公共电极线14开设有连接孔119。所述虚拟像素24内的像素电极15通过所述连接孔119与公共电极相连接。
在本实施例，所述显示区域21为位于显示面板1中心的矩形区域。所述显示区域21内的像素单元20为显示像素22。所述虚拟像素24为分别设置在显示区域21的四个边角处的第一虚拟像素241、第二虚拟像素242、第三虚拟像素243及第四虚拟像素244。
如图7所示，所述测试引脚18包括与奇数排虚拟像素24的扫描线10连接的奇数虚拟扫描引脚gate_dummy_odd、与偶数排虚拟像素24的扫描线10连接的偶数虚拟扫描引脚gate_dummy_even、与奇数列虚拟像素24的数据线12连接的奇数虚拟数据引脚data_dummy_odd、与偶数列虚拟像素24的数据线12连接的偶数虚拟数据引脚data_dummy_even、与奇数排显示像素22的扫描线10连接的奇数显示扫描引脚gate_odd、与偶数排显示像素22的扫描线10连接的偶数显示扫描引脚gate_even、与传输红色显示信号的数据线12相连接的红色数据引脚data_red、与传输绿色显示信号的数据线12相连接的绿色数据引脚data_green、与传输蓝色显示信号的数据线12相连接的蓝色数据引脚data_blue以及与所述公共电极线14连接的公共引脚A_comm。
所述第一虚拟像素241的扫描线10与所述奇数虚拟扫描引脚gate_dummy_odd连接。所述第一虚拟像素241的数据线12与所述偶数虚拟数据引脚data_dummy_even连接。所述第一虚拟像素241的公共电极线14与所述公共引脚A_comm连接。所述第二虚拟像素242的扫描线10与所述偶数虚拟扫描引脚gate_dummy_even连接。所述第二虚拟像素242的数据线12与所述偶数虚拟数据引脚data_dummy_even连接。所述第二虚拟像素242的公共电极线14 与所述公共引脚A_comm连接。所述第三虚拟像素243的扫描线10与所述偶数虚拟扫描引脚gate_dummy_even连接。所述第三虚拟像素243的数据线12与所述奇数虚拟数据引脚data_dummy_odd连接。所述第三虚拟像素243的公共电极线14与所述公共引脚A_comm连接。所述第四虚拟像素244的扫描线10与所述奇数虚拟扫描引脚gate_dummy_odd连接。所述第四虚拟像素244的数据线12与所述奇数虚拟数据引脚data_dummy_odd连接。所述第四虚拟像素244的公共电极线14与所述公共引脚A_comm连接。因所述虚拟像素24的像素电极15与公共电极线14相连接，所以配合测试不同的奇/偶虚拟扫描引脚及奇/偶虚拟数据引脚的组合以选中对应的虚拟像素24并输入测试信号，再通过与虚拟像素24的公共电极线14相连接的公共引脚A_comm可测得虚拟像素24的像素电极15上所接收的测试信号，从而判断经由与所述虚拟像素24相同制作工艺一起制成的显示像素22的电学品质。
如图8所示，本发明第二实施例所提供的显示面板2的结构与第一实施例的显示面板1的结构基本相同，其区别在于：所述虚拟像素25包括分别沿所述显示区域26相互平行的两条长边边缘设置的第一虚拟像素组251及第二虚拟像素组252。所述第一虚拟像素组251及第二虚拟像素组252分别包括多个依次排列的虚拟像素25。所述第一虚拟像素组251内的多个虚拟像素25共用一条扫描线10并连接至奇数虚拟扫描引脚gate_dummy_odd。所述第一虚拟像素251组内的多个虚拟像素25的数据线12分别连接至红色数据引脚data_red、绿色数据引脚data_green或蓝色数据引脚data_blue。所述第一虚拟像素251组内的多个虚拟像素25的公共电极线14连接至公共引脚A_comm。所述第二虚拟像素组252内的多个虚拟像素25共用一条扫描线10并连接至偶数虚拟扫描引脚gate_dummy_even。所述第二虚拟像素组252内的多个虚拟像素的数据线12分别连接至红色数据引脚data_red、绿色数据引脚data_green或蓝色数据引脚data_blue。所述第一虚拟像素251组内的多个虚拟像素的公共电极线14连接至公共引脚A_comm。本发明第二实施例所提供的显示面板2通过切换奇/偶虚拟扫描引脚可以测试沿显示面板2长度方向设置的两组虚拟像素25的电学平均值。
如图9所示，本发明第三实施例所提供的显示面板3的结构与第一实施例的显示面板1的结构基本相同，其区别在于：所述虚拟像素34包括分别沿所述 显示区域31相互平行的两条短边边缘设置的第三虚拟像素组341及第四虚拟像素组342。所述第三虚拟像素组341及第四虚拟像素组342分别包括多个依次排列的虚拟像素34。所述第三虚拟像素组341内的多个虚拟像素34的扫描线10分别连接至奇数虚拟扫描引脚gate_dummy_odd或偶数虚拟扫描引脚gate_dummy_even。所述第三虚拟像素组341内的多个虚拟像素34的数据线12连接至偶数虚拟数据引脚data_dummy_even。所述第三虚拟像素组341内的多个虚拟像素34的公共电极线14连接至公共引脚A_comm。所述第四虚拟像素组342内的多个虚拟像素34的扫描线10分别连接至奇数虚拟扫描引脚gate_dummy_odd或偶数虚拟扫描引脚gate_dummy_even。所述第四虚拟像素组342内的多个虚拟像素34的数据线12连接至偶数虚拟数据引脚data_dummy_even。所述第四虚拟像素组342内的多个虚拟像素34的公共电极线14连接至公共引脚A_comm。本发明第三实施例所提供的显示面板3通过切换奇/偶虚拟数据引脚可以测试沿显示面板3短边设置的两组虚拟像素34的电学平均值。
本实施例所提供的显示面板1通过搭配不同的测试引脚18可灵活地选择对显示区域21内对应的虚拟像素24进行测试。其次，通过在虚拟像素24中穿孔连接像素电极15及公共电极线14使得所述显示面板1仅借助外围的引脚便可以对显示区域21内像素单元20的电信进行测试。
以上所揭露的仅为本发明一种较佳实施例而已，当然不能以此来限定本发明之权利范围，因此依本发明权利要求所作的等同变化，仍属本发明所涵盖的范围。

Claims (15)

  1. 一种显示面板，其包括沿第一方向延伸的多条扫描线、沿第二方向延伸并与所述扫描线相交的多条数据线、设置于相邻两条扫描线之间并与所述扫描线平行的公共电极线、包围所述扫描线、数据线及公共电极线的布线区及用于测试的多个测试引脚，所述扫描线及数据线定义出多个呈矩阵排列的像素单元，每个像素单元内设置有与对应数据线相连接的像素电极，所述像素单元包括位于显示区域内用于显示图像的显示像素及位于所述显示区域边缘处的虚拟像素，所述显示像素的像素电极与公共电极线相互绝缘间隔，所述虚拟像素的像素电极与公共电极线通过一连接孔相连接，所述虚拟像素的扫描线、数据线及公共电极线分别通过布线区内的连接线路与对应的测试引脚相连。
  2. 如权利要求1所述的显示面板，其中，所述每个像素单元内于扫描线与数据线相交处设置有的薄膜电晶体，所述薄膜电晶体包括与扫描线相连的栅极、设置在栅极上的栅极绝缘层、设置在栅极绝缘层上的半导体层、分别与所述半导体层电连接的源极与漏极以及覆盖所述源极与漏极的钝化层。
  3. 如权利要求2所述的显示面板，其中，所述源极与漏极之间开设有向内延伸至所述半导体层的凹孔，所述钝化层填充入所述凹孔内以将所述源极与漏极相互绝缘，所述源极的一端与数据线相连接，所述源极的另一端通过半导体层与漏极相连接，所述漏极与半导体层相对的另一端与所述像素电极相连接。
  4. 如权利要求2所述的显示面板，其中，所述源极及漏极与所述半导体层之间设置有欧姆接触层。
  5. 如权利要求2所述的显示面板，其中，所述虚拟像素内覆盖在所述公共电极线上的栅极绝缘层及钝化层对应所述公共电极线开设有连接孔，所述虚拟像素内的像素电极通过所述连接孔与公共电极线相连接。
  6. 如权利要求2所述的显示面板，其中，所述栅极绝缘层及钝化层的材料均为氮硅化合物，所述半导体层的材料为非晶硅。
  7. 如权利要求1所述的显示面板，其中，所述测试引脚包括与奇数排虚拟像素的扫描线连接的奇数虚拟扫描引脚、与偶数排虚拟像素的扫描线连接的偶数虚拟扫描引脚、与奇数列虚拟像素的数据线连接的奇数虚拟数据引脚、与偶数列虚拟像素的数据线连接的偶数虚拟数据引脚、与奇数排显示像素的扫描线 连接的奇数显示扫描引脚、与偶数排显示像素的扫描线连接的偶数显示扫描引脚、与传输红色显示信号的数据线相连接的红色数据引脚、与传输绿色显示信号的数据线相连接的绿色数据引脚、与传输蓝色显示信号的数据线相连接的蓝色数据引脚以及与所述公共电极线连接的公共引脚。
  8. 如权利要求2所述的显示面板，其中，所述测试引脚包括与奇数排虚拟像素的扫描线连接的奇数虚拟扫描引脚、与偶数排虚拟像素的扫描线连接的偶数虚拟扫描引脚、与奇数列虚拟像素的数据线连接的奇数虚拟数据引脚、与偶数列虚拟像素的数据线连接的偶数虚拟数据引脚、与奇数排显示像素的扫描线连接的奇数显示扫描引脚、与偶数排显示像素的扫描线连接的偶数显示扫描引脚、与传输红色显示信号的数据线相连接的红色数据引脚、与传输绿色显示信号的数据线相连接的绿色数据引脚、与传输蓝色显示信号的数据线相连接的蓝色数据引脚以及与所述公共电极线连接的公共引脚。
  9. 如权利要求3所述的显示面板，其中，所述测试引脚包括与奇数排虚拟像素的扫描线连接的奇数虚拟扫描引脚、与偶数排虚拟像素的扫描线连接的偶数虚拟扫描引脚、与奇数列虚拟像素的数据线连接的奇数虚拟数据引脚、与偶数列虚拟像素的数据线连接的偶数虚拟数据引脚、与奇数排显示像素的扫描线连接的奇数显示扫描引脚、与偶数排显示像素的扫描线连接的偶数显示扫描引脚、与传输红色显示信号的数据线相连接的红色数据引脚、与传输绿色显示信号的数据线相连接的绿色数据引脚、与传输蓝色显示信号的数据线相连接的蓝色数据引脚以及与所述公共电极线连接的公共引脚。
  10. 如权利要求4所述的显示面板，其中，所述测试引脚包括与奇数排虚拟像素的扫描线连接的奇数虚拟扫描引脚、与偶数排虚拟像素的扫描线连接的偶数虚拟扫描引脚、与奇数列虚拟像素的数据线连接的奇数虚拟数据引脚、与偶数列虚拟像素的数据线连接的偶数虚拟数据引脚、与奇数排显示像素的扫描线连接的奇数显示扫描引脚、与偶数排显示像素的扫描线连接的偶数显示扫描引脚、与传输红色显示信号的数据线相连接的红色数据引脚、与传输绿色显示信号的数据线相连接的绿色数据引脚、与传输蓝色显示信号的数据线相连接的蓝色数据引脚以及与所述公共电极线连接的公共引脚。
  11. 如权利要求5所述的显示面板，其中，所述测试引脚包括与奇数排虚拟像素的扫描线连接的奇数虚拟扫描引脚、与偶数排虚拟像素的扫描线连接的偶 数虚拟扫描引脚、与奇数列虚拟像素的数据线连接的奇数虚拟数据引脚、与偶数列虚拟像素的数据线连接的偶数虚拟数据引脚、与奇数排显示像素的扫描线连接的奇数显示扫描引脚、与偶数排显示像素的扫描线连接的偶数显示扫描引脚、与传输红色显示信号的数据线相连接的红色数据引脚、与传输绿色显示信号的数据线相连接的绿色数据引脚、与传输蓝色显示信号的数据线相连接的蓝色数据引脚以及与所述公共电极线连接的公共引脚。
  12. 如权利要求6所述的显示面板，其中，所述测试引脚包括与奇数排虚拟像素的扫描线连接的奇数虚拟扫描引脚、与偶数排虚拟像素的扫描线连接的偶数虚拟扫描引脚、与奇数列虚拟像素的数据线连接的奇数虚拟数据引脚、与偶数列虚拟像素的数据线连接的偶数虚拟数据引脚、与奇数排显示像素的扫描线连接的奇数显示扫描引脚、与偶数排显示像素的扫描线连接的偶数显示扫描引脚、与传输红色显示信号的数据线相连接的红色数据引脚、与传输绿色显示信号的数据线相连接的绿色数据引脚、与传输蓝色显示信号的数据线相连接的蓝色数据引脚以及与所述公共电极线连接的公共引脚。
  13. 如权利要求7所述的显示面板，其中，所述虚拟像素为分别设置在显示区域的四个边角处的第一虚拟像素、第二虚拟像素、第三虚拟像素及第四虚拟像素，所述第一虚拟像素的扫描线与所述奇数虚拟扫描引脚连接，所述第一虚拟像素的数据线与所述偶数虚拟数据引脚连接，所述第一虚拟像素的公共电极线与所述公共引脚连接，所述第二虚拟像素的扫描线与所述偶数虚拟扫描引脚连接，所述第二虚拟像素的数据线与所述偶数虚拟数据引脚连接，所述第二虚拟像素的公共电极线与所述公共引脚连接，所述第三虚拟像素的扫描线与所述偶数虚拟扫描引脚连接，所述第三虚拟像素的数据线与所述奇数虚拟数据引脚连接，所述第三虚拟像素的公共电极线与所述公共引脚连接，所述第四虚拟像素的扫描线与所述奇数虚拟扫描引脚连接，所述第四虚拟像素的数据线与所述奇数虚拟数据引脚连接，所述第四虚拟像素的公共电极线与所述公共引脚连接。
  14. 如权利要求7所述的显示面板，其中，所述虚拟像素包括分别沿矩形显示区域相互平行的两条长边边缘设置的第一虚拟像素组及第二虚拟像素组，所述第一虚拟像素组及第二虚拟像素组分别包括多个依次排列的虚拟像素，所述第一虚拟像素组内的多个虚拟像素共用一条扫描线并连接至奇数虚拟扫描引 脚，所述第一虚拟像素组内的多个虚拟像素的数据线分别连接至红色数据引脚、绿色数据引脚或蓝色数据引脚，所述第一虚拟像素组内的多个虚拟像素的公共电极线连接至公共引脚，所述第二虚拟像素组内的多个虚拟像素共用一条扫描线并连接至偶数虚拟扫描引脚，所述第二虚拟像素组内的多个虚拟像素的数据线分别连接至红色数据引脚、绿色数据引脚或蓝色数据引脚，所述第一虚拟像素组内的多个虚拟像素的公共电极线连接至公共引脚。
  15. 如权利要求7所述的显示面板，其中，所述虚拟像素包括分别沿矩形显示区域相互平行的两条短边边缘设置的第三虚拟像素组及第四虚拟像素组，所述第三虚拟像素组及第四虚拟像素组分别包括多个依次排列的虚拟像素，所述第三虚拟像素组内的多个虚拟像素的扫描线分别连接至奇数虚拟扫描引脚或偶数虚拟扫描引脚，所述第三虚拟像素组内的多个虚拟像素的数据线连接至偶数虚拟数据引脚，所述第三虚拟像素组内的多个虚拟像素的公共电极线连接至公共引脚，所述第四虚拟像素组内的多个虚拟像素的扫描线分别连接至奇数虚拟扫描引脚或偶数虚拟扫描引脚，所述第四虚拟像素组内的多个虚拟像素的数据线连接至偶数虚拟数据引脚，所述第四虚拟像素组内的多个虚拟像素的公共电极线连接至公共引脚。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108305576A (zh) * 2017-01-13 2018-07-20 元太科技工业股份有限公司 显示装置
CN115097675A (zh) * 2022-07-21 2022-09-23 合肥京东方显示技术有限公司 一种阵列基板及其制作方法、液晶显示面板、显示装置

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103761935B (zh) 2014-01-21 2016-01-06 深圳市华星光电技术有限公司 显示面板
CN104111549A (zh) * 2014-07-16 2014-10-22 深圳市华星光电技术有限公司 液晶面板及其制备方法
CN104282248B (zh) * 2014-09-28 2017-01-25 京东方科技集团股份有限公司 阵列基板及其测试方法、显示面板、显示装置
CN106875879B (zh) * 2017-04-24 2020-05-22 上海天马有机发光显示技术有限公司 一种显示面板、电子设备以及测试方法
CN107767772A (zh) * 2017-09-16 2018-03-06 合肥惠科金扬科技有限公司 一种显示装置的显示面板组件
CN107749414A (zh) * 2017-09-16 2018-03-02 合肥惠科金扬科技有限公司 一种显示装置
CN107610663B (zh) * 2017-09-25 2019-12-03 武汉华星光电技术有限公司 平板显示装置的虚拟电路及驱动电路
CN108428434B (zh) * 2018-02-27 2020-06-23 上海天马有机发光显示技术有限公司 像素电路、有机发光显示面板及显示装置
CN110164935B (zh) * 2019-05-28 2022-04-29 京东方科技集团股份有限公司 显示面板和显示装置
CN110596967A (zh) * 2019-08-26 2019-12-20 深圳市华星光电半导体显示技术有限公司 显示面板
CN110718180B (zh) * 2019-11-15 2023-07-18 京东方科技集团股份有限公司 一种显示基板及其制造方法
CN111399293A (zh) 2020-04-09 2020-07-10 深圳市华星光电半导体显示技术有限公司 液晶显示面板及液晶显示装置
CN114927111B (zh) * 2022-04-21 2023-10-24 滁州惠科光电科技有限公司 基板、显示面板及其电子设备
CN116884985B (zh) * 2023-09-08 2024-05-28 无锡鉴微华芯科技有限公司 一种像素探测器的读出像素芯片

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1438521A (zh) * 2002-02-12 2003-08-27 精工爱普生株式会社 电光装置、电子设备和电光装置的制造方法
US7098987B1 (en) * 2005-08-24 2006-08-29 Chunghwa Picture Tubes, Ltd. Array of active devices and method for testing an array of active devices
CN101515102A (zh) * 2008-02-19 2009-08-26 乐金显示有限公司 平板显示器件及该类器件的制造方法
CN103761935A (zh) * 2014-01-21 2014-04-30 深圳市华星光电技术有限公司 显示面板

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100662780B1 (ko) * 2002-12-18 2007-01-02 엘지.필립스 엘시디 주식회사 테스트화소를 구비한 액정표시장치 및 이를 이용한 블랙 매트릭스를 제작하는 방법
KR100991954B1 (ko) * 2003-04-30 2010-11-04 크로스텍 캐피탈, 엘엘씨 씨모스 이미지 센서의 픽셀 특성 평가용 테스트 패턴 및 그 모듈
KR101055209B1 (ko) * 2004-12-30 2011-08-08 엘지디스플레이 주식회사 액정표시장치 및 이의 제조방법
KR101127826B1 (ko) * 2005-06-14 2012-03-20 엘지디스플레이 주식회사 액정표시패널 및 그 제조방법
KR100708715B1 (ko) * 2005-09-30 2007-04-17 삼성에스디아이 주식회사 유기 발광 디스플레이 장치
KR101450796B1 (ko) * 2008-02-15 2014-10-14 삼성디스플레이 주식회사 표시 기판 및 이를 구비한 표시 패널
KR101569766B1 (ko) * 2009-01-29 2015-11-17 삼성디스플레이 주식회사 박막 트랜지스터 표시판 및 그 제조 방법
CN102487042B (zh) * 2010-12-03 2014-06-11 北京京东方光电科技有限公司 阵列基板及其制造方法和检测方法、液晶面板
JP6004560B2 (ja) * 2011-10-06 2016-10-12 株式会社ジャパンディスプレイ 表示装置
KR20130070723A (ko) * 2011-12-20 2013-06-28 삼성디스플레이 주식회사 테스트 패드를 구비하는 유기발광 표시장치
KR101262984B1 (ko) * 2012-03-05 2013-05-09 엘지디스플레이 주식회사 프린지 필드 스위칭 모드 액정표시장치용 어레이 기판
CN202837763U (zh) * 2012-10-29 2013-03-27 北京京东方光电科技有限公司 阵列基板和显示装置
CN103268879B (zh) * 2012-12-26 2016-05-18 厦门天马微电子有限公司 一种阵列基板
CN103337501B (zh) * 2013-06-24 2015-11-25 深圳市华星光电技术有限公司 阵列基板及其制作方法、平板显示装置
CN103337510B (zh) 2013-08-08 2016-03-16 南京中电熊猫液晶显示科技有限公司 一种镜面可切换显示器及其制造方法
CN103474396B (zh) * 2013-09-24 2015-09-02 深圳市华星光电技术有限公司 Tft-lcd阵列基板的制造方法
KR102284142B1 (ko) * 2015-01-13 2021-07-30 삼성디스플레이 주식회사 표시 패널 및 그 리페어 방법

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1438521A (zh) * 2002-02-12 2003-08-27 精工爱普生株式会社 电光装置、电子设备和电光装置的制造方法
US7098987B1 (en) * 2005-08-24 2006-08-29 Chunghwa Picture Tubes, Ltd. Array of active devices and method for testing an array of active devices
CN101515102A (zh) * 2008-02-19 2009-08-26 乐金显示有限公司 平板显示器件及该类器件的制造方法
CN103761935A (zh) * 2014-01-21 2014-04-30 深圳市华星光电技术有限公司 显示面板

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108305576A (zh) * 2017-01-13 2018-07-20 元太科技工业股份有限公司 显示装置
CN115097675A (zh) * 2022-07-21 2022-09-23 合肥京东方显示技术有限公司 一种阵列基板及其制作方法、液晶显示面板、显示装置
CN115097675B (zh) * 2022-07-21 2024-04-16 合肥京东方显示技术有限公司 一种阵列基板及其制作方法、液晶显示面板、显示装置

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