WO2015109574A1 - Procédé d'encapsulation au niveau tranche de del - Google Patents
Procédé d'encapsulation au niveau tranche de del Download PDFInfo
- Publication number
- WO2015109574A1 WO2015109574A1 PCT/CN2014/071502 CN2014071502W WO2015109574A1 WO 2015109574 A1 WO2015109574 A1 WO 2015109574A1 CN 2014071502 W CN2014071502 W CN 2014071502W WO 2015109574 A1 WO2015109574 A1 WO 2015109574A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- led
- recess
- positive
- led wafer
- level packaging
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 23
- 238000005538 encapsulation Methods 0.000 title abstract 4
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 239000004020 conductor Substances 0.000 claims abstract description 21
- 238000004806 packaging method and process Methods 0.000 claims description 17
- 239000003292 glue Substances 0.000 claims description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 239000000741 silica gel Substances 0.000 claims description 11
- 229910002027 silica gel Inorganic materials 0.000 claims description 11
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 9
- 239000000919 ceramic Substances 0.000 claims description 8
- 239000011521 glass Substances 0.000 claims description 6
- 239000010931 gold Substances 0.000 claims description 6
- 229910052737 gold Inorganic materials 0.000 claims description 6
- 229910052594 sapphire Inorganic materials 0.000 claims description 6
- 239000010980 sapphire Substances 0.000 claims description 6
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 6
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 6
- 239000000463 material Substances 0.000 abstract description 6
- 230000017525 heat dissipation Effects 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 24
- 239000007787 solid Substances 0.000 description 3
- 239000000084 colloidal system Substances 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000002708 enhancing effect Effects 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- 230000004907 flux Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012858 packaging process Methods 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000012780 transparent material Substances 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/483—Containers
- H01L33/486—Containers adapted for surface mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
- H01L2933/0058—Processes relating to semiconductor body packages relating to optical field-shaping elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
- H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/52—Encapsulations
- H01L33/54—Encapsulations having a particular shape
Definitions
- the invention belongs to the technical field of LED packaging, and in particular relates to an LED wafer level packaging method.
- the packaging method of the white LED product is to fix the LED chip on the support by means of solid crystal bonding or eutectic soldering, and the positive electrode of the wafer is connected to the positive electrode of the bracket by a gold wire, and the negative electrode of the chip is connected to the negative electrode of the bracket. , and then fill the phosphor that meets the target color zone. Due to the different thermal expansion coefficients of the wafer colloid, the reliability problems of the stent, the solid crystal glue, the gold wire, and the colloid are prone to occur.
- the material of the positive and negative electrodes of the bonding bracket is PPA, PCT, EMC material, which has large defects in high temperature resistance and air tightness, which affects the reliability of LED products; ceramic brackets have better resistance. High temperature and good air tightness, but the cost of the bracket is close to the cost of the wafer, and the ceramic bracket package LED is expensive, the equipment investment is large, and the production capacity is small. In short, the LED lighting products of the bracket package structure have greatly hindered the replacement of the traditional lighting of the LED lighting products in terms of reliability and service life.
- the object of the embodiments of the present invention is to provide an LED wafer level packaging method, wherein the LED packaged by the method can be directly soldered to the application end substrate, and the thermal resistance of the support layer required for the conventional package is subtracted, thereby facilitating the wafer PN junction. Cooling and enhancing the reliability of LED products.
- a transparent substrate having a recess with the opening of the recess facing upward, the bottom surface of the recess being provided with two electrically isolated conductive layers, the conductive layer extending to the bottom surface of the transparent substrate via the side of the recess;
- An LED chip having positive and negative conductors is placed in the recess, and the positive and negative conductors are fixed to the corresponding conductive layer.
- a transparent substrate having a recess is obtained, and the recess opening is upward, and the bottom surface of the recess is provided with two electrically isolated conductive layers, and the conductive layer is extended to the transparent base through the side of the recess.
- the LED thus packaged can be directly soldered to the application end substrate, which reduces the thermal resistance of the bracket layer required for the conventional package, facilitates heat dissipation of the PN junction of the wafer, and enhances the reliability of the LED product.
- FIG. 1 is a flowchart of an implementation of an LED wafer level packaging method according to an embodiment of the present invention
- FIG. 2 is a schematic structural view of a transparent substrate provided by an embodiment of the present invention (the upper surface is a flat surface);
- FIG 3 is a schematic structural view of a transparent substrate provided by an embodiment of the present invention (the upper surface is a curved surface);
- FIG. 4 is a schematic structural view of a transparent substrate provided by an embodiment of the present invention (the surface is roughened);
- FIG. 5 is a schematic diagram of an LED wafer level packaging process (not filled with transparent silica gel or fluorescent glue) according to an embodiment of the present invention
- FIG. 6 is a schematic structural view of an LED produced by an LED wafer level packaging method according to an embodiment of the present invention (unfilled with transparent silica gel or fluorescent glue, the upper surface of the LED is flat);
- FIG. 7 is a schematic diagram of an LED wafer level packaging process (after filling a transparent silica gel or a fluorescent glue) according to an embodiment of the present invention
- FIG. 8 is a schematic structural view of an LED produced by an LED wafer level packaging method according to an embodiment of the present invention (filled with transparent silica gel or fluorescent glue, the upper surface of the LED is flat);
- FIG. 9 is a schematic structural view of an LED produced by an LED wafer level packaging method according to an embodiment of the present invention (filled with transparent silica gel or fluorescent glue, the upper surface of the LED is curved);
- FIG. 10 is a schematic structural view of an LED produced by an LED wafer level packaging method according to an embodiment of the present invention (filled with transparent silica gel or fluorescent glue, and the upper surface of the LED is roughened).
- a transparent substrate having a recess is obtained, and the recess opening is upward, and the bottom surface of the recess is provided with two electrically isolated conductive layers, and the conductive layer is extended to the transparent base through the side of the recess.
- the LED thus packaged can be directly soldered to the application end substrate, which reduces the thermal resistance of the bracket layer required for the conventional package, facilitates heat dissipation of the PN junction of the wafer, and enhances the reliability of the LED product.
- FIG. 1 shows an implementation flow of an LED wafer level packaging method according to an embodiment of the present invention, which is described in detail below.
- step S101 a transparent substrate having a recess is obtained with the recess opening facing upward, and the bottom surface of the recess is provided with two electrically isolated conductive layers, and the conductive layer is extended to the side of the recess to The bottom surface of the transparent substrate.
- the transparent substrate 2 having the recess 1 is first obtained, and the opening of the recess 1 is facing upward, and the bottom surface of the recess 1 is provided with two electrically conductive layers 3 electrically isolated from each other.
- the side of the pocket 1 extends to the bottom surface of the transparent substrate 2.
- the transparent substrate 2 is a high-transparent material that can be ball-stitched in a solid state, preferably a transparent glass, ceramic, sapphire or silicon carbide having a plurality of pockets 1 larger than the LED wafer 4,
- the transparent glass, ceramic, sapphire or silicon carbide is plated with a conductive layer 3 at a suitable position, or a conductive layer is first plated on the bottom of the entire transparent substrate, and then the unnecessary conductive layer is removed.
- the transparent glass, ceramic, sapphire or silicon carbide is divided to obtain a single LED product, as shown in FIGS. 2 to 4.
- the pockets 1 are generally formed by physical or chemical methods such as etching.
- the upper surface of the transparent substrate 2 can be formed into a curved surface which is advantageous for enhancing light extraction and reducing the light exit angle, as shown in FIG.
- the upper surface of the transparent substrate 2 and the middle portion of the bottom surface of the recess 1 may be roughened in advance to enhance the light extraction efficiency and uniformity of the packaged LED, as shown in FIG. 4 .
- step S102 an LED chip having positive and negative conductors is placed in the recess, and the positive and negative conductors are fixed to the corresponding conductive layer.
- the LED chips 4 having the positive and negative conductors 6, 7 are placed in the recesses 1 of the transparent substrate, and the positive and negative conductors 6, 7 are fixed to the corresponding conductive layers 3.
- the LED chip 4 having the positive and negative conductors 6, 7 is formed by gold balls soldered to the positive and negative electrodes 8, 9 of the LED wafer 4; the LED wafer 4 is hot pressed into the cavity 1 by a gold ball.
- Each gold ball is fixed to the corresponding conductive layer 3 and forms an electrical connection, as shown in FIGS.
- Gold ball welding is used instead of gold wire soldering, which greatly improves the reliability of the connection between the horizontal and positive wafer electrodes and the positive and negative terminals of the package.
- the LED chip 4 is preferably a horizontal structure wafer or a vertical structure wafer which requires a bonding wire.
- LED obtained in this way 12 does not contain fluorescent glue or transparent silica gel, and its illuminating color is the LED chip illuminating color.
- the manufactured LED 12 is light in weight and suitable for backlighting and/or illumination of portable electronic products.
- the stentless integrated package of the LED chip 4 (especially the horizontal structure wafer) is realized in this way, and the cost of the LED product is reduced through mass integration production.
- the LED chip 4 and the transparent substrate 2 can be directly soldered on the application end substrate, the thermal resistance of the support layer in the conventional package is reduced, the heat conduction of the PN junction of the wafer is greatly shortened, and the thermal reliability of the LED product is improved, and the heat efficiency is effectively Controlling the junction temperature of the PN junction of the wafer greatly increases the efficiency and lifetime of the LED device.
- the LED package product is soldered at the application end, and the bottom of the LED chip 4 is directly soldered to the heat sink to shorten the heat conduction path and reduce the thermal resistance.
- the conductive layer drawn from both ends of the substrate is soldered to the corresponding electrode of the circuit board, and the package device is thermally and electrically separated. Improve the thermal and electrical reliability of the product.
- the LED chip 4 having the positive and negative conductors 6, 7 is placed in the recess 1 and the positive and negative conductors 6, 7 are fixed to the corresponding conductive layer.
- the step of 3 further comprises: filling the cavity 1 with a transparent silica gel or a fluorescent glue 11 until the fluorescent glue 11 is flush with the bottom surface of the LED wafer 4, and then curing the transparent silica gel or the fluorescent glue 11 as shown in the figure. 7 ⁇ 10 is shown.
- LED The gap between the wafer 3 and the substrate recess 1 is a controllable uniform thickness space, and the transparent silica gel or the fluorescent glue 11 is filled in the space to obtain a uniform thickness of the fluorescent adhesive layer, which is excited by the blue light of the wafer. A uniform white light is obtained, and the blue light emitted from the wafer is utilized to the utmost, and there is no phenomenon that the luminous flux is low due to the uneven excitation of the blue light, and finally the maximum luminous flux is obtained.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Led Device Packages (AREA)
Abstract
L'invention concerne un procédé d'encapsulation au niveau tranche de DEL, qui s'applique au domaine technique d'encapsulation des diodes électroluminescentes (DEL). Le procédé comprend les étapes suivantes consistant : à acquérir un matériau de base transparent pourvu d'un évidement, et à permettre à l'évidement de s'ouvrir vers le haut, deux couches conductrices électriquement isolées étant disposées sur la face inférieure de l'évidement et s'étendant jusqu'à la face inférieure du matériau de base à travers la face latérale de l'évidement; et à placer une tranche de DEL munie de conducteurs électriques d'électrode positive et d'électrode négative dans l'évidement, et à permettre aux conducteurs électriques d'électrode positive et d'électrode négative d'être connectés de manière fixe à des couches conductrices correspondantes. Une DEL encapsulée de cette manière peut être directement soudée sur un substrat d'extrémité d'application, ce qui permet de réduire la résistance thermique d'une couche de support nécessaire dans l'encapsulation classique, de faciliter la dissipation de chaleur d'une jonction PN de la tranche, et d'augmenter la fiabilité d'un produit à DEL.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/CN2014/071502 WO2015109574A1 (fr) | 2014-01-26 | 2014-01-26 | Procédé d'encapsulation au niveau tranche de del |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/CN2014/071502 WO2015109574A1 (fr) | 2014-01-26 | 2014-01-26 | Procédé d'encapsulation au niveau tranche de del |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2015109574A1 true WO2015109574A1 (fr) | 2015-07-30 |
Family
ID=53680676
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/CN2014/071502 WO2015109574A1 (fr) | 2014-01-26 | 2014-01-26 | Procédé d'encapsulation au niveau tranche de del |
Country Status (1)
Country | Link |
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WO (1) | WO2015109574A1 (fr) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107331752A (zh) * | 2017-07-06 | 2017-11-07 | 庞绮琪 | 提高耐压能力的led封装结构 |
CN107507898A (zh) * | 2017-08-16 | 2017-12-22 | 广东聚科照明股份有限公司 | 一种led照明cob封装结构 |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6531328B1 (en) * | 2001-10-11 | 2003-03-11 | Solidlite Corporation | Packaging of light-emitting diode |
CN1661823A (zh) * | 2004-02-23 | 2005-08-31 | 斯坦雷电气株式会社 | Led及其制造方法 |
CN101427389A (zh) * | 2006-04-21 | 2009-05-06 | 雷克斯爱帝斯照明股份有限公司 | 具有置于薄膜上的发光二极管芯片的发光二极管平台 |
CN103441198A (zh) * | 2013-09-09 | 2013-12-11 | 聚灿光电科技(苏州)有限公司 | 一种led高亮度倒装芯片以及制作方法 |
CN103855280A (zh) * | 2014-01-26 | 2014-06-11 | 上海瑞丰光电子有限公司 | 一种led晶片级封装方法 |
CN103855282A (zh) * | 2014-01-26 | 2014-06-11 | 上海瑞丰光电子有限公司 | 一种led |
CN203746897U (zh) * | 2014-01-26 | 2014-07-30 | 上海瑞丰光电子有限公司 | 一种led |
-
2014
- 2014-01-26 WO PCT/CN2014/071502 patent/WO2015109574A1/fr active Application Filing
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6531328B1 (en) * | 2001-10-11 | 2003-03-11 | Solidlite Corporation | Packaging of light-emitting diode |
CN1661823A (zh) * | 2004-02-23 | 2005-08-31 | 斯坦雷电气株式会社 | Led及其制造方法 |
CN101427389A (zh) * | 2006-04-21 | 2009-05-06 | 雷克斯爱帝斯照明股份有限公司 | 具有置于薄膜上的发光二极管芯片的发光二极管平台 |
CN103441198A (zh) * | 2013-09-09 | 2013-12-11 | 聚灿光电科技(苏州)有限公司 | 一种led高亮度倒装芯片以及制作方法 |
CN103855280A (zh) * | 2014-01-26 | 2014-06-11 | 上海瑞丰光电子有限公司 | 一种led晶片级封装方法 |
CN103855282A (zh) * | 2014-01-26 | 2014-06-11 | 上海瑞丰光电子有限公司 | 一种led |
CN203746897U (zh) * | 2014-01-26 | 2014-07-30 | 上海瑞丰光电子有限公司 | 一种led |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107331752A (zh) * | 2017-07-06 | 2017-11-07 | 庞绮琪 | 提高耐压能力的led封装结构 |
CN107507898A (zh) * | 2017-08-16 | 2017-12-22 | 广东聚科照明股份有限公司 | 一种led照明cob封装结构 |
CN107507898B (zh) * | 2017-08-16 | 2023-11-03 | 广东天基光电有限公司 | 一种led照明cob封装结构 |
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