WO2015101255A1 - 像素电路、像素及包括该像素的amoled显示装置及其驱动方法 - Google Patents

像素电路、像素及包括该像素的amoled显示装置及其驱动方法 Download PDF

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Publication number
WO2015101255A1
WO2015101255A1 PCT/CN2014/095331 CN2014095331W WO2015101255A1 WO 2015101255 A1 WO2015101255 A1 WO 2015101255A1 CN 2014095331 W CN2014095331 W CN 2014095331W WO 2015101255 A1 WO2015101255 A1 WO 2015101255A1
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Prior art keywords
transistor
circuit
pixel
oled
power source
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PCT/CN2014/095331
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English (en)
French (fr)
Inventor
朱晖
胡思明
黄秀颀
Original Assignee
昆山工研院新型平板显示技术中心有限公司
昆山国显光电有限公司
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Application filed by 昆山工研院新型平板显示技术中心有限公司, 昆山国显光电有限公司 filed Critical 昆山工研院新型平板显示技术中心有限公司
Priority to EP14877391.4A priority Critical patent/EP3059728A4/en
Priority to US15/109,420 priority patent/US10607538B2/en
Priority to JP2016558254A priority patent/JP6261757B2/ja
Priority to KR1020167016355A priority patent/KR101862494B1/ko
Publication of WO2015101255A1 publication Critical patent/WO2015101255A1/zh
Priority to US16/134,737 priority patent/US10607542B2/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/043—Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0814—Several active elements per pixel in active matrix panels used for selection purposes, e.g. logical AND for partial update
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G09G2300/0866—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes by means of changes in the pixel supply voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements

Definitions

  • Pixel circuit, pixel and AMOLED display device including the same and driving method thereof
  • the present invention relates to a flat panel display technology, and more particularly to a pixel circuit, a pixel, and an active matrix organic light emitting diode (AMOLED) display device including the same, and a driving method thereof.
  • AMOLED active matrix organic light emitting diode
  • an active matrix organic light emitting diode (AMOLED) display device uses a self-luminous organic light emitting diode (OLED) to display an image, it generally has a short response time, and uses low power consumption. Driving, and relatively better brightness and color purity characteristics, organic light-emitting display devices have become the focus of next-generation display technology.
  • AMOLED active matrix organic light emitting diode
  • OLED organic light emitting diode
  • Each pixel includes an OLED and a pixel circuit for driving the OLED.
  • the pixel circuit typically includes a turn-off transistor, a drive transistor, and a storage capacitor.
  • the quality uniformity and uniformity of the image displayed by such a plurality of pixels is inferior.
  • FIG. 1 is a schematic diagram of a pixel of an active matrix organic light emitting diode (AMOLED) display device of the prior art.
  • the transistor in the pixel circuit 112 is a PMOS (n-type substrate, p-channel, MOS transistor carrying current by the flow of holes) transistor.
  • the pixel 110 of the AMOLED display device includes: an OLED, a connection to the data line Dm, and a scan control line Sn
  • the anode of the OLED is connected to the pixel circuit 112, and the cathode of the OLED is connected to the second power source ELV
  • the OLED emits light having a brightness corresponding to the intensity of the current supplied by the pixel circuit 112.
  • the pixel circuit 112 includes a second transistor T2 (ie, a driving transistor) connected between the first power source EL VDD and the anode of the organic light emitting diode OLED, and is connected between the gate of the second transistor T2 and the data line Dm.
  • a transistor T1 ie, a bypass transistor
  • a first capacitor C1 connected between the gate of the second transistor T2 and the first power source ELVDD, wherein the gate of the first transistor T1 is connected to the scan control line Sn1.
  • the gate of the first transistor T1 is connected to the scan control line Sn1, and the source (or drain) of the first transistor T1 is connected to the data line Dm.
  • the drain (or source) of the first transistor T1 is connected to one end of the first capacitor C1 (the other end is connected to the first power source ELVDD).
  • the gate of the second transistor T2 is connected to one end of the first capacitor C1 (the other end is connected to the first power source ELVDD), and the source of the second transistor T2 is connected to the first power source ELVDD.
  • the drain of the second transistor T2 is connected to the anode of the OLED.
  • the second transistor T2 controls a current flowing from the first power source ELVDD through the OLED to the second power source ELVSS, the magnitude of the current corresponding to the voltage stored in the first capacitor C1.
  • One end of the first capacitor C1 is connected to the gate of the second transistor T2, the other end of the first capacitor C1 is connected to the first power source ELVDD, and the voltage corresponding to the data signal is charged to the first capacitor C1. in.
  • the pixel 110 controls the brightness of the OLED by adjusting the current supplied to the OLED corresponding to the voltage charged in the first capacitor C1, thereby displaying an image having a predetermined brightness.
  • the current flowing through the OLED is inconsistent when the same gate driving voltage is added, causing the brightness of the OLED to be inconsistent, and each pixel responds. With the same data signal, the generated light has different brightnesses, thus making it difficult for the displayed image to have uniform brightness.
  • a main object of the present invention is to provide a pixel, an active matrix organic light emitting diode (AM0LED) display device using the same, and a driving method thereof, by compensating for a difference between a threshold voltage of a transistor and a power supply voltage
  • the AM0LED's response characteristics are improved to produce light having the same brightness, thereby satisfying the image uniformity and consistency required by the AM0LED display device.
  • a pixel circuit 112 includes a basic circuit 1122, the pixel circuit 112 further includes a power supply circuit 1121 and a compensation circuit 1123; the power supply circuit 1121, the base circuit 1122 and the compensation circuit 1123 are sequentially connected; the power supply circuit 1121 is connected
  • the first power source ELVDD supplies power to the base circuit 1122;
  • the compensation circuit 1123 is connected to the second power source ELVSS1 and the third power source ELVSS2, respectively, for providing a difference between the voltage and current of the compensation organic light emitting diode OLED.
  • the power supply circuit 1121 is a second transistor T2; the gate of the second transistor T2 is connected to the scan control signal line Scan1, the source is connected to the first power source ELVDD, and the drain and the base circuit 1122 Connected.
  • the base circuit 1122 is connected to the compensation circuit 1123 via a parallel OLED and a parasitic capacitance Coled.
  • the basic circuit 1122 includes a first transistor T1, a fifth transistor T5, and a first capacitor C1; a gate of the first transistor T1 is connected to a second scan control line Scan2, a source of the first transistor T1 The pole is connected to the data line Dm, and the drain thereof is connected to the gate of the fifth transistor T5; the first capacitor C1 is connected in parallel between the gate and the source of the fifth transistor T5.
  • the compensation circuit 1123 includes: a parasitic capacitance Coled, a third transistor T3, and a fourth transistor T4 connected in parallel with the OLED; the OLED and the parasitic capacitance Coled are connected in parallel and connected in series to the drain of the fifth transistor T5 of the basic circuit 1122.
  • the gates of the third transistor T3 and the fourth transistor T4 are connected to the emission control line Eml and the emission control line Em2, respectively; Then, the second power source ELVSS1 and the third power source ELVSS2 are connected, respectively.
  • the present invention also provides pixels of any of the foregoing pixel circuits.
  • the present invention also provides an AMOLED display device of the pixel.
  • a pixel driving method includes the following steps:
  • the first power source ELVDD is connected to the power supply circuit 1121 and the base circuit 1122, and the base circuit 11 22 is connected to the compensation circuit 1123 through the OLED; the compensation circuit 1123 is connected to the second power source ELVSS1, the third power source ELVSS2;
  • the second transistor T2 of the power supply circuit 1121 is powered by the base circuit 1122;
  • the second power source ELVSS1 and the third power source ELVSS2 supply power to the compensation circuit 1123;
  • the gate of the second transistor T2 of the power supply circuit 1121 inputs a scan control signal Scan1; and the gate input scan control of the first transistor T1 of the base circuit 1122 a signal Scan2, a source input data signal Dm;
  • a gate of the third transistor T3 and the fourth transistor T4 of the compensation circuit 1 123 respectively input an emission control signal Eml and an emission control signal Em2, the source of which is respectively connected to the cathode of the OLED Docking
  • D during the period t2 of supplying the scan control signal Scan2 to the first transistor T1, storing a voltage corresponding to the data signal Vdata supplied through the first transistor T1 in the first capacitor C1;
  • the transistor T1 is turned on in response to the low level scan control signal Scan2, and the data signal Vdata supplied to the data line Dm is supplied to the gate of the fifth transistor T5 via the first transistor T1;
  • the drain of the second transistor T2 is correspondingly The voltage is supplied to the anode of the OLED, and the second power voltage ELVSS1 that supplies the cathode of the OLED charges the first capacitor C1 through the parasitic capacitance Coled of the OLED and the drain of the fifth transistor T5;
  • the emission control signal Em2 transitions to a low level, so that the fourth transistor T4 is turned on by the response emission control signal Em2; the charge of the drain of the second transistor T2 passes through The fifth transistor T5, the path of the anode of the OLED flows to the third power source ELVSS2; when the drain voltage of the second transistor T2 is higher than the voltage of the gate of the fifth transistor T5 by a threshold voltage ⁇ , the fifth transistor T5 is turned off, the second transistor The charge at the drain of T2 stops flowing;
  • the scan control signal Scan1 transitions to a low level; the second transistor T2 is turned on by responding to the scan control signal Scan1, the drive current is along the first power source ELVDD via the second transistor T2
  • the paths of the fifth transistor T5, the OLED, and the fourth transistor T4 flow to the third power source ELVSS2.
  • the voltage of the second power source ELVSS1 can also be supplied as a reset voltage to the source of the third transistor T3 through the third transistor T3, so that the source of the third transistor T3 in each frame The pole is constantly reset.
  • Cox, ⁇ , W, and L are channel capacitance per unit area, channel mobility, channel width, and length of the fifth transistor T5, respectively;
  • Vdata is a data voltage.
  • Vdata is a data voltage
  • MOLED MOLED
  • the pixel of the present invention and the AMOLED display device including the pixel can improve the response characteristic of the AMOL ED by compensating for the difference between the threshold voltage of the second transistor T2 and the first power supply voltage ELVDD. Light having the same brightness is generated, so that the AM OLED display device using the pixel circuit can exhibit uniformity and uniformity in image quality.
  • AMOLED active matrix organic light emitting diode
  • FIG. 2 is a functional block diagram of an active matrix organic light emitting diode (AMOLED) display device including the pixel of the present invention
  • FIG. 3 is a schematic structural diagram of a pixel shown in FIG. 2;
  • FIG. 4 is a waveform diagram of driving signals for driving the pixel shown in FIG. 3.
  • the pixel circuit, the pixel, and the active matrix organic light emitting diode (AMOLED) display device including the pixel and the driving method thereof will be further described in detail below with reference to the accompanying drawings and embodiments of the present invention.
  • AMOLED active matrix organic light emitting diode
  • FIG. 2 is a functional block diagram of an active matrix organic light emitting diode (AMOLED) display device including the pixel of the present invention.
  • AMOLED active matrix organic light emitting diode
  • the AMOLED display device mainly includes a display unit 100, a scan driver 200, and a data driver 300. among them:
  • the display unit 100 includes a plurality of pixels 110 (shown in FIG. 3), and the plurality of pixels 110 are arranged in a matrix on the scan control line Scania scan control line Sc an 2n, the emission control line Emln, The control line Em2n and the intersection of the data line D1 and the data line Dm are transmitted. Where n is the line number where the pixel is located.
  • Each pixel 110 is connected to a scan control line (eg, Scanln. Scan2n), a transmission control line (eg, Em ln, Em2n), and a data line, respectively.
  • the data lines are connected in columns to pixels 110 in each column of pixels.
  • the pixels 110 located in the i-th row and the j-th column are connected to the i-th scanning control line Scanli, Scan2i, the i-th row emission control lines Emli and Em2i, and the j-th column data line Dj.
  • the display unit 100 accepts an external power source such as a power supply of the first power source ELVDD, the second power source ELVSS1, and the third power source ELVSS2.
  • the first power source ELVDD and the third power source ELVSS2 function as a high level voltage source and a low level voltage source, respectively.
  • the first power source ELVDD and the third power source ELVSS2 are used as driving power sources for the pixels 110.
  • the second power source ELVSS1 is used to compensate for variations in the driving current of the organic light emitting diode caused by the threshold voltage fluctuation of the fifth transistor T5 (refer to FIG. 3).
  • the scan driver 200 generates a scan control signal and a transmission control signal for the pixel 110.
  • the scan control signals generated by the scan controller 200 are supplied to the pixels 110 through the scan control line Scanli to the scan control line Scanln, respectively; and the emission control signals generated by the scan controller 200 are respectively passed through the emission control line Emli to the emission control line Emln The order is provided to the pixel 110.
  • the data driver 300 generates data signals for the pixels 110 corresponding to the data control signals.
  • the data signal generated by the data driver 300 is supplied to the pixel 110 through the data line D1 to the data line Dm in synchronization with the scan signal.
  • FIG. 3 is a schematic structural view of the pixel shown in FIG. 2.
  • the pixel shown in Figure 3 can be applied to A shown in Figure 2.
  • the pixel 110 located in the nth row and the mth column is taken as an example in Fig. 3, and further includes a data line Dm.
  • the pixel 110 includes a pixel circuit 112 and an OLED.
  • the pixel circuit 112 is connected between the first power source ELVDD and the third power source ELVSS2 for supplying a driving current to the organic light emitting diode (OLED).
  • the pixel circuit 112 mainly includes three parts: a power supply circuit 1121, a base circuit 1122, and a compensation circuit 1123 which are sequentially connected. among them:
  • the power supply circuit 1121 includes a second transistor T2.
  • the gate of the second transistor T2 is connected to the first scan control line Scan1, the source (or drain) thereof is connected to the first power source ELVDD, and the drain (or source) thereof is the fifth in the base circuit 1122.
  • the source (or drain) of transistor T5 is connected.
  • the basic circuit 1122 that is, the 2T1C circuit, belongs to a conventional pixel circuit.
  • the base circuit 1122 includes a first transistor T1, a fifth transistor ⁇ 5, and a first capacitor Cl.
  • the gate of the first transistor T1 is connected to the second scan control line Scan2, and the source (or drain) of the first transistor T1 is connected to the data line Dm, and the drain (or source) thereof is The gate of the fifth transistor T5 is connected.
  • the first capacitor C 1 is connected in parallel between the gate of the fifth transistor T5 and the source (or drain) connected to the power supply circuit 1121.
  • the base circuit 1122 passes through the source of the fifth transistor T5. (or drain) is connected to the drain (or gate) of the second transistor T2 of the power supply circuit 1121.
  • the base circuit 1122 is connected to the anode of the OLED in the pixel 110 through the drain (or source) of the fifth transistor T5, the cathode of the OLED and the third transistor T3 and the fourth transistor ⁇ 4 of the compensation circuit 1123.
  • the source (or drain) is connected.
  • the parasitic capacitance Coled is connected in parallel across the anode cathode of the OLED, and constitutes the compensation circuit 1123 with the third transistor T3 and the fourth transistor ⁇ 4.
  • the drains (or sources) of the third transistor ⁇ 3 and the fourth transistor ⁇ 4 are respectively connected to the second power source ELVSS1 and the third power source ELVSS2.
  • the gate of the third transistor T3 is connected to the emission control line Em1
  • the gate of the fourth transistor T4 is connected to the emission control line Em2.
  • the source (or drain) potential of the third transistor T3 and the fourth transistor ⁇ 4 are the same.
  • the first, second, third, fourth, and fifth transistors described above are all field effect transistors having the same source and drain.
  • the pixel circuit 112 of the present invention is in operation:
  • the first transistor T1 supplies the data voltage Vdata to the gate of the fifth transistor during the scan control signal supplied to the scan control line Scan2 segment t2.
  • the second transistor T2 is connected between the first power source ELVDD and the source (or drain) of the fifth transistor T5, and the gate of the second transistor T2 is connected to the scan control line Scan1, and is scanned during the period t2
  • the control signal is supplied to the scan control line Scan1, and the second transistor T2 in the turn-on power supply circuit 1121 is turned on, thereby
  • the first power source ELVDD is turned on with the pixel 110.
  • the third transistor T3 is connected between the cathode of the OLED and the second power source ELVSS1, and the gate of the third transistor T3 is connected to the emission control line Eml.
  • the third transistor T3 is turned on, thereby turning on the OLED and the second power source voltage ELVSS1, thereby controlling the data of the pixel 110 during the initialization period t1.
  • the amplitude of the cathode driving voltage of the OLED during the voltage writing period t2 is the voltage of the second power source ELVSS1.
  • the fourth transistor T4 is connected between the cathode of the OLED and the third power source ELVSS2, and the gate of the fourth transistor T4 is connected to the emission control line Em2.
  • the fourth transistor T4 is turned on, thereby turning on the OLED and the third power source voltage ELVSS2, and controlling the pixel 110 during the threshold voltage compensation period t3,
  • the amplitude of the cathode driving voltage of the OLED during the light-emitting period t4 is the third power source ELVSS2 voltage.
  • the fifth transistor T5 is connected in series between the second transistor T2 and the anode of the OLED, and the gate of the fifth transistor T5 is connected to the drain (or source) of the first transistor T1.
  • the scan control signal Scan2 supplied from the scan control line transitions to the low level
  • the first transistor T1 is turned on, and the data signal is sent through the first transistor T1 to the gate of the fifth transistor T5.
  • the first capacitor C1 is connected between the drain (or source) of the second transistor T2 and the gate of the fifth transistor T5.
  • the first capacitor Cl is initialized by the second transistor T2 providing the first supply voltage ELVDD.
  • the voltage corresponding to the data signal supplied through the first transistor T1 is stored in the first capacitor C1.
  • the OLED is connected in series between the drain (or source) of the fifth transistor T5 and the source (or drain) of the third transistor T3. In the illumination stage of pixel 110
  • the OLED will emit light of a magnitude corresponding to the magnitude of the drive current supplied through the first power source ELVDD, the fifth transistor T5, the second transistor ⁇ 2, and the fourth transistor ⁇ 4.
  • the current flowing through the OLED is also inconsistent, which may cause the uniformity of the brightness of the pixel 110 to be deteriorated, eventually resulting in image unevenness.
  • the threshold voltage of the driving transistor (such as the fifth transistor T5) is compensated during the initialization period t1 of each frame, and the above can be avoided.
  • a product defect in which the brightness of the pixel 110 is deteriorated causes image unevenness.
  • FIG. 4 is a waveform diagram of driving signals for driving the pixel shown in FIG. 3.
  • a waveform of a driving signal supplied during a frame signal of the pixel shown in Fig. 3 is shown in Fig. 4, and the driving process of the pixel will be described with reference to Fig. 3. among them:
  • the scan control signal Scan1 is used to control the second transistor T2 to control its conduction with the first power source ELVDD.
  • the scan control signal Scan2 is used to control the first transistor T1 to write the data level.
  • the emission control line Eml is used to control the third transistor T3 to control its conduction with the second power source ELVSS1.
  • the emission control line Em2 is used to control the fourth transistor T4 to control its conduction with the third power source ELVSS2.
  • the low-level scan control signal Scan1 is first supplied to the pixel 110. Therefore, the second transistor T2 is turned on by the scan control signal Scan1 of the low level. Further, the voltage of the first power source ELVDD is supplied to the source (or drain) of the fifth transistor T5. A low level emission control signal Eml is supplied to the pixel 110. Therefore, the third transistor T3 is turned on by the low-level emission control signal Eml. Thereby, the voltage of the second power source ELVSS1 is supplied to the source (or drain) of the third transistor T3.
  • the voltage of the second power source ELVSS1 may also be supplied as a reset voltage to the source (or drain) of the third transistor T3 through the third transistor T3, thereby The source (or drain) of the third transistor T3 can be constantly reset.
  • the scan control signal Scan2 of the low level is supplied to the pixel 110 during the period of setting the data voltage writing period t2 (i.e., writing the data voltage phase).
  • the first transistor T1 is turned on in response to the low level scan control signal Scan2. Therefore, the data signal Vda ta supplied to the data line Dm is supplied to the gate of the fifth transistor T5 via the first transistor T1.
  • a corresponding voltage of the drain (or source) of the second transistor T2 is supplied to the anode of the OLED.
  • the second power supply voltage ELVSS1 supplied to the cathode end of the OLED charges the first capacitor C1 through the parasitic capacitance Coled of the OLED and the drain (or source) of the fifth transistor T5.
  • the emission control signal Em is transmitted. 2 transition to low level.
  • the fourth transistor T4 is turned on by responding to the emission control signal Em2. Therefore, the charge of the drain (or source) of the second transistor T2 flows to the third power source ELVSS2 through the path of the fifth transistor T5, the anode of the OLED, and the voltage of the drain (or source) of the second transistor ⁇ 2 is higher than the first
  • the voltage of the five transistor ⁇ 5 gate is one threshold voltage (ie, the threshold voltage of the fifth transistor ⁇ 5) ⁇ , the fifth transistor ⁇ 5 is turned off, and the charge of the drain (or source) of the second transistor ⁇ 2 stops flowing.
  • the fifth transistor ⁇ 5 is stored in the first capacitor C1 in response to the voltage corresponding to the threshold voltage supplied to the fifth transistor ⁇ 5, so that the threshold voltage of the fifth transistor ⁇ 5 is compensated during the period t3.
  • the scan control signal Scan1 transitions to a low level.
  • the second transistor T2 is then turned on by responding to the scan control signal Scan1. Therefore, the driving current flows along the path of the second transistor T2, the fifth transistor T5, the OLED, and the fourth transistor ⁇ 4 along the first power source ELVDD to the third power source ELVSS2.
  • the current flowing through the organic light emitting diode (OLED) Ioled is:
  • Cox, ⁇ , W, and L are the channel capacitance per unit area of the fifth transistor ⁇ 5, respectively, channel mobility
  • Vdata is the data voltage
  • the current flowing through the OLED can be approximated as:
  • K is Cox* *W*L, which is a constant; Vsg is the voltage difference between the source and the gate; Vth is the threshold voltage; Vdd is the first supply voltage ELVDD; Vcl is the storage voltage of the first capacitor C1 ; Vdata is the data voltage; N is a natural number greater than 1.

Abstract

一种像素电路、像素及包括该像素的有源矩阵有机发光二极管（AMOLED）显示装置及其驱动方法，该像素电路（112）包括依次相连的供电电路（1121）、基础电路（1122）和补偿电路（1123）。供电电路（1121）连接第一电源（ELVDD），为基础电路（1122）提供电源。补偿电路（1123）分别与第二电源（ELVSS1）和第三电源（ELVSS2）相连，用于提供补偿有机发光二极管（OLED）的电压和电流的差值。像素包含OLED和该像素电路。AMOLED显示装置包括该像素电路。该方案能够补偿晶体管的阈值电压和电源电压的差值，改善AMOLED的响应特性，使其产生具有相同亮度的光，从而满足AMOLED的图像均匀性、一致性要求。

Description

像素电路、 像素及包括该像素的 AMOLED显示装置及其驱动方法
技术领域
[0001] 本发明涉及平板显示技术， 尤其涉及一种像素电路、 像素及包括该像素的有源 矩阵有机发光二极管 （AMOLED) 显示装置及其驱动方法。
背景技术
[0002] 近年来， 已经幵发出相比阴极射线管重量轻且体积小的各种类型的平板显示装 置。
[0003] 在各种类型的平板显示装置中， 由于有源矩阵有机发光二极管 （AMOLED) 显示装置使用自发光的有机发光二极管 （OLED) 来显示图像， 通常具有响应吋 间短， 使用低功耗进行驱动， 以及相对更好的亮度和颜色纯度的特性， 因此有 机发光显示装置已成为下一代显示技术的焦点。
[0004] 对于大型 AMOLED显示装置， 包括位于扫描线和数据线交叉区域的多个像素
。 每个像素包括 OLED和用于驱动所述 OLED的像素电路。 所述像素电路通常包 括幵关晶体管、 驱动晶体管和存储电容。
[0005] 由于 AMOLED的像素特性受驱动晶体管之间的差异和幵关晶体管的漏电流的 不利因素影响， 因此通过这样的多个像素显示的图像的质量均匀性和一致性较 差。
[0006] 图 1为现有技术中有源矩阵有机发光二极管 （AMOLED) 显示装置的像素示意 图。 如图 1所示， 其像素电路 112中的晶体管为 PMOS (n型衬底、 p沟道， 靠空穴 的流动运送电流的 MOS管） 晶体管。
[0007] AMOLED显示装置的像素 110包括： OLED、 连接至数据线 Dm和扫描控制线 Sn
1以控制所述 OLED的像素电路 112。 其中，
[0008] 所述 OLED的阳极连接至像素电路 112， 并且 OLED的阴极连接至第二电源 ELV
SS。 该 OLED发出具有与像素电路 112所提供的电流强弱相对应亮度的光。
[0009] 当向扫描控制线 Snl提供扫描信号吋， 像素电路 112对应于供给数据线 Dm的数 据信号来控制供给 OLED的电流量。 为此， 像素电路 112包括连接在第一电源 EL VDD和有机发光二极管 OLED阳极之间的第二晶体管 T2 (即驱动晶体管） 、 连接 在第二晶体管 T2的栅极和数据线 Dm之间的第一晶体管 T1 (即幵关晶体管） 以及 连接在第二晶体管 T2的栅极与第一电源 ELVDD之间的第一电容 Cl， 其中第一晶 体管 T1的栅极与所述扫描控制线 Snl相连。
[0010] 第一晶体管 T1的栅极连接至扫描控制线 Snl， 并且第一晶体管 T1的源极 （或漏 极） 连接至数据线 Dm。 第一晶体管 T1的漏极 （或源极） 连接至第一电容 C1的一 端 （另一端与第一电源 ELVDD相连） 。 当从扫描控制线 Snl向第一晶体管 T1提 供扫描控制信号吋， 第一晶体管 T1导通， 并且从数据线 Dm供应的数据信号被供 给第一电容 Cl。 此吋， 与数据信号对应的电压被存储到第一电容 C1中。
[0011] 第二晶体管 T2的栅极连接至第一电容 C1的一端 （另一端与第一电源 ELVDD相 连） ， 并且第二晶体管 T2的源极与第一电源 ELVDD相连。 第二晶体管 T2的漏极 与 OLED的阳极相连。 第二晶体管 T2对从第一电源 ELVDD经所述 OLED流到第二 电源 ELVSS的电流进行控制， 该电流的大小对应存储在第一电容 C1中的电压。
[0012] 第一电容 C1的一端与第二晶体管 T2的栅极相连， 该第一电容 C1的另一端与第 一电源 ELVDD相连， 并将与数据信号对应的电压被充入到第一电容 C1中。
[0013] 像素 110通过对应于第一电容 C1中所充入的电压通过调节向 OLED供应的电流 来控制 OLED的亮度， 从而显示具有预定亮度的图像。 然而， 在这种传统的 AM OLED显示装置中， 由于受第二晶体管 T2的阈值电压变化和第一晶体管 T1的漏电 流的影响， 很难显示亮度均匀的图像。 如， 在不同像素中由于第二晶体管 T2的 阈值电压的差异和第一电源 ELVDD的差异， 使得在加入相同的栅极驱动电压吋 流过 OLED的电流不一致， 造成 OLED的亮度不一致， 各个像素响应同一数据信 号， 产生的光具有不同亮度， 因而导致显示出的图像很难具有均匀的亮度。 技术问题
[0014] 有鉴于此， 本发明的主要目的在于提供一种像素、 使用该像素的有源矩阵有机 发光二极管 （AM0LED) 显示装置及其驱动方法， 通过补偿晶体管的阈值电压 和电源电压的差值， 改善 AM0LED的响应特性， 使其产生具有相同亮度的光， 从而满足 AM0LED显示装置所显示的图像均匀性、 一致性的要求。 问题的解决方案
技术解决方案
[0015] 为达到上述目的， 本发明的技术方案是这样实现的：
[0016] 一种像素电路 112， 包括基础电路 1122， 该像素电路 112还包括供电电路 1121和 补偿电路 1123; 所述供电电路 1121、 基础电路 1122及补偿电路 1123依次相连； 所述供电电路 1121连接第一电源 ELVDD, 为所述基础电路 1122提供电源； 所述 补偿电路 1123分别与第二电源 ELVSS1和第三电源 ELVSS2相连， 用于提供补偿 有机发光二极管 OLED的电压和电流的差值。
[0017] 其中， 所述供电电路 1121为第二晶体管 T2; 所述第二晶体管 T2的栅极与扫描控 制信号线 Scanl相连， 源极与第一电源 ELVDD相连， 漏极与所述基础电路 1122相 连。
[0018] 所述基础电路 1122经并联的 OLED和寄生电容 Coled与所述补偿电路 1123相连。
[0019] 所述基础电路 1122包括第一晶体管 Tl、 第五晶体管 Τ5和第一电容 C1 ; 所述第 一晶体管 T1的栅极与第二扫描控制线 Scan2相连， 所述第一晶体管 T1的源极与数 据线 Dm相连， 其漏极则与所述第五晶体管 T5的栅极相连； 第一电容 C1并联在所 述第五晶体管 T5的栅极和源极之间。
[0020] 所述补偿电路 1123包括： 与 OLED并联的寄生电容 Coled、 第三晶体管 T3和第四 晶体管 T4; 所述 OLED和寄生电容 Coled并联后串联在基础电路 1122的第五晶体 管 T5的漏极与补偿电路 1123的第三晶体管 T3和第四晶体管 T4的源极之间； 所述 第三晶体管 T3、 第四晶体管 Τ4的栅极分别与发射控制线 Eml、 发射控制线 Em2 相连； 其漏极则分别连接第二电源 ELVSS1、 第三电源 ELVSS2。
[0021] 本发明还提供了任一前述像素电路的像素。
[0022] 本发明还提供了所述像素的 AMOLED显示装置。
[0023] 一种像素的驱动方法， 包括如下步骤：
[0024] A、 通过第一电源 ELVDD连接供电电路 1121和基础电路 1122， 并使基础电路 11 22通过 OLED与补偿电路 1123相连； 所述补偿电路 1123与第二电源 ELVSS1、 第 三电源 ELVSS2相连；
[0025] B、 禾 所述供电电路 1121的第二晶体管 T2为基础电路 1122供电； 并分别利用 第二电源 ELVSS1、 第三电源 ELVSS2为补偿电路 1123供电； 所述供电电路 1121 的第二晶体管 T2的栅极输入扫描控制信号 Scanl ; 所述基础电路 1122的第一晶体 管 T1的栅极输入扫描控制信号 Scan2， 其源极输入数据信号 Dm; 所述补偿电路 1 123的第三晶体管 T3和第四晶体管 T4的栅极分别输入发射控制信号 Eml和发射控 制信号 Em2， 其源极均与 OLED的阴极相接；
[0026] C、 在像素工作周期 T的吋段 tl期间， 提供扫描控制信号， 通过第二晶体管 T2提 供第一电源电压 ELVDD初始化第一电容 C1；
[0027] D、 在向第一晶体管 Tl提供扫描控制信号 Scan2的吋段 t2期间， 将与通过第一晶 体管 T1提供的数据信号 Vdata相应的电压存储在第一电容 C1中； 同吋， 第一晶体 管 T1响应低电平的扫描控制信号 Scan2而导通， 经第一晶体管 T1将提供给数据线 Dm的数据信号 Vdata提供给第五晶体管 T5的栅极； 将第二晶体管 T2的漏极相应 的电压提供给 OLED的阳极， 而给 OLED的阴极供电的第二电源电压 ELVSS1则通 过 OLED的寄生电容 Coled、 第五晶体管 T5的漏极对第一电容 C1充电；
[0028] E、 在阈值电压补偿的吋段 t3期间， 发射控制信号 Em2跃迁到低电平， 使第四 晶体管 T4通过响应发射控制信号 Em2导通； 第二晶体管 T2的漏极的电荷经第五 晶体管 T5、 OLED的阳极的路径流向第三电源 ELVSS2; 当第二晶体管 T2的漏极 电压高于第五晶体管 T5栅极的电压一个阈值电压吋， 第五晶体管 T5截止， 所述 第二晶体管 T2漏极的电荷停止流动；
[0029] F、 在 OLED发光的吋段 t4期间， 扫描控制信号 Scanl跃迁到低电平； 第二晶体 管 T2通过响应扫描控制信号 Scanl而导通， 驱动电流沿第一电源 ELVDD经第二晶 体管 T2、 第五晶体管 T5、 OLED和第四晶体管 Τ4的路径流到第三电源 ELVSS2。
[0030] 其中， 在吋段 tl期间， 还能够通过第三晶体管 T3将第二电源 ELVSS1的电压作 为复位电压提供给第三晶体管 T3的源极， 使在每一帧中第三晶体管 T3的源极被 恒定地复位。
[0031] 在 OLED发光的吋段 t4期间， 流经所述 OLED的电流 Ioled为：
[0032] Ioled= l/2Cox ( W/L) (Vdata ) Λ2；
[0033] 其中： 所述 Cox、 μ、 W和 L分别为第五晶体管 Τ5的单位面积沟道电容， 沟道迁 移率， 沟道宽度和长度； Vdata为数据电压。 [0034] 所述流经 OLED的电流 Ioled近似表示为：
[0035] Ioled=l/2*K*[Vdata]A2;
[0036] 其中， K为常数； Vdata为数据电压。
发明的有益效果
有益效果
[0037] 本发明所提供的像素电路、 像素及包括该像素的有源矩阵有机发光二极管 （A
MOLED) 显示装置及其驱动方法， 具有以下优点：
[0038] 应用本发明的像素及包含所述像素的 AMOLED显示装置， 能够通过采用可补 偿第二晶体管 T2的阈值电压和第一电源电压 ELVDD的差异的方式， 改善 AMOL ED的响应特性， 使其产生具有相同亮度的光， 从而能够使采用该像素电路的 AM OLED显示装置， 显示出的图像质量具有均匀性和一致性。
对附图的简要说明
附图说明
[0039] 图 1为现有技术的有源矩阵有机发光二极管 （AMOLED) 显示装置的像素电路 示意图；
[0040] 图 2为包含本发明像素的有源矩阵有机发光二极管 （AMOLED) 显示装置的功 能框图；
[0041] 图 3为图 2所示的像素的架构示意图；
[0042] 图 4为驱动图 3所示像素的驱动信号波形图。
本发明的实施方式
[0043] 下面结合附图及本发明的实施例对本发明的像素电路、 像素及包括该像素的有 源矩阵有机发光二极管 （AMOLED) 显示装置及其驱动方法作进一步详细的说 明。
[0044] 这里， 当将第一元件描述为连接到第二元件吋， 第一元件可以直接连接至第二 元件， 或经过一个或多个附加元件间接连接至第二元件。 进一步的， 为了清楚 起见， 简明省略了对于充分理解本发明而言不是必须的某些元件。 [0045] 图 2为包含本发明像素的有源矩阵有机发光二极管 （AMOLED) 显示装置的功 能框图。 如图 2所示， 所述 AMOLED显示装置主要包括显示单元 100、 扫描驱动 器 200和数据驱动器 300。 其中：
[0046] 所述显示单元 100， 包括多个像素 110 (如图 3所示） ， 所述多个像素 110以矩阵 形式排布在扫描控制线 Scania 扫描控制线 Scan2n、 发射控制线 Emln、 发射控 制线 Em2n及数据线 D1至数据线 Dm的交叉区域。 其中， n为像素所在的行号。
[0047] 将每个像素 110与扫描控制线 （如， Scanln. Scan2n) 、 发射控制线 （如， Em ln、 Em2n) 及数据线分别相连。 所述数据线按列分别与每列像素中的像素 110相 连。 例如， 将位于第 i行和第 j列的像素 110连接到第 i行扫描控制线 Scanli、 Scan2i 、 第 i行发射控制线 Emli和 Em2i， 以及第 j列数据线 Dj。
[0048] 显示单元 100接受外部电源， 如第一电源 ELVDD、 第二电源 ELVSS1和第三电 源 ELVSS2的供电。 所述第一电源 ELVDD和第三电源 ELVSS2分别用作高电平电 压源和低电平电压源。 第一电源 ELVDD和第三电源 ELVSS2用作像素 110的驱动 电源。 第二电源 ELVSS1用于补偿第五晶体管 T5 (参考图 3) 阈值电压波动所造 成的有机发光二极管驱动电流的变化。
[0049] 扫描驱动器 200产生用于像素 110的扫描控制信号和发射控制信号。 由扫描控制 器 200产生的扫描控制信号分别通过扫描控制线 Scanli至扫描控制线 Scanln的次 序提供给像素 110; 以及将由扫描控制器 200产生的发射控制信号分别通过发射 控制线 Emli至发射控制线 Emln的顺序提供给像素 110。
[0050] 数据驱动器 300产生用于像素 110的数据和数据控制信号相对应的数据信号。 将 由数据驱动器 300产生的数据信号通过数据线 D1至数据线 Dm与扫描信号同步地 提供给像素 110。
[0051] 图 3为图 2所示的像素的架构示意图。 如图 3所示的像素， 可应用到图 2所示的 A
MOLED显示装置中。 为了便于说明， 图 3中以位于第 n行和第 m列的像素 110为例 进行描述， 还包括数据线 Dm。
[0052] 如图 3所示， 所述像素 110， 包括像素电路 112和 OLED。 所述像素电路 112连接 在第一电源 ELVDD和第三电源 ELVSS2之间， 用于向有机发光二极管 （OLED) 提供驱动电流。 [0053] 所述像素电路 112主要包括依次相连的供电电路 1121、 基础电路 1122和补偿电 路 1123三部分。 其中：
[0054] 供电电路 1121， 包括第二晶体管 T2。 所述第二晶体管 Τ2的栅极与第一扫描控制 线 Scanl相连， 其源极 （或漏极） 连接第一电源 ELVDD, 其漏极 （或源极） 则与 所述基础电路 1122中第五晶体管 T5的源极 （或漏极） 相连。
[0055] 基础电路 1122， 即 2T1C电路， 属于现有常用的像素电路。 该基础电路 1122， 包括第一晶体管 Tl、 第五晶体管 Τ5和第一电容 Cl。 其中， 第一晶体管 T1的栅极 与第二扫描控制线 Scan2相连， 所述第一晶体管 T1的源极 （或漏极） 与数据线 D m相连， 其漏极 （或源极） 则与所述第五晶体管 T5的栅极相连。 所述第一电容 C 1并联在所述第五晶体管 T5的栅极和与供电电路 1121相连的源极 （或漏极） 之间 ， 换言之， 所述基础电路 1122通过第五晶体管 T5的源极 （或漏极） 与所述供电 电路 1121的第二晶体管 T2的漏极 （或栅极） 相连。
[0056] 所述基础电路 1122通过第五晶体管 T5的漏极 （或源极） 与像素 110中 OLED的 阳极相连， 所述 OLED的阴极与补偿电路 1123的第三晶体管 T3、 第四晶体管 Τ4的 源极 （或漏极） 相连。 寄生电容 Coled并联在所述 OLED的阳极阴极两端， 与所 述第三晶体管 T3、 第四晶体管 Τ4构成所述的补偿电路 1123。
[0057] 所述补偿电路 1123中， 第三晶体管 Τ3、 第四晶体管 Τ4的漏极 （或源极） 分别连 接第二电源 ELVSS 1和第三电源 ELVSS2。 第三晶体管 T3的栅极与发射控制线 Em 1相连， 第四晶体管 T4的栅极与发射控制线 Em2相连。 所述第三晶体管 T3、 第四 晶体管 Τ4的源极 （或漏极） 电位相同。
[0058] 上述的第一、 第二、 第三、 第四和第五晶体管， 均为场效应管， 其源极和漏极 相同。
[0059] 本发明的像素电路 112在工作吋：
[0060] 第一晶体管 T1在扫描控制信号提供给扫描控制线 Scan2吋段 t2期间， 所述第一 晶体管 T1将数据电压 Vdata提供给第五晶体管的栅极。
[0061] 第二晶体管 T2连接在第一电源 ELVDD与第五晶体管 T5的源极 （或漏极） 之间 ， 第二晶体管 T2的栅极通过连接扫描控制线 Scanl , 在吋段 t2期间将扫描控制信 号提供给扫描控制线 Scanl , 此吋供电电路 1121中的第二晶体管 T2导通， 从而将 第一电源 ELVDD与像素 110导通。
[0062] 第三晶体管 T3连接在 OLED的阴极与第二电源 ELVSS1之间， 所述第三晶体管 T 3的栅极与发射控制线 Eml相连。 在将扫描控制信号提供给发射控制线 Eml的吋 段 t3期间， 第三晶体管 T3导通， 从而使所述 OLED与第二电源电压 ELVSS1导通 ， 从而控制像素 110在初始化吋段 tl期间、 数据电压写入吋段 t2期间 OLED的阴极 驱动电压的幅度为第二电源 ELVSS 1电压。
[0063] 第四晶体管 T4连接在 OLED的阴极与第三电源 ELVSS2之间， 所述第四晶体管 T 4的栅极与发射控制线 Em2相连。 在将扫描控制信号提供给发射控制线 Em2的吋 段 t4期间， 第四晶体管 T4导通， 从而使所述 OLED与第三电源电压 ELVSS2导通 ， 控制像素 110在阈值电压补偿吋段 t3期间、 发光吋段 t4期间所述 OLED的阴极驱 动电压的幅度为第三电源 ELVSS2电压。
[0064] 第五晶体管 T5串联在第二晶体管 T2及 OLED的阳极之间， 所述第五晶体管 T5的 栅极与第一晶体管 T1的漏极 （或源极） 相连。 当从扫描控制线提供的扫描控制 信号 Scan2跃迁到低电平吋， 第一晶体管 T1导通， 则数据信号通过第一晶体管 T1 发送到第五晶体管 T5的栅极。
[0065] 第一电容 C1连接在第二晶体管 T2的漏极 （或源极） 和第五晶体管 T5的栅极之 间。 在将扫描控制信号提供给扫描控制线 Scanl吋段 tl期间， 通过第二晶体管 T2 提供第一电源电压 ELVDD来初始化第一电容 Cl。 其后， 在将扫描控制信号提供 给扫描控制线 Scan2吋段 t2期间， 将与通过第一晶体管 T1提供的数据信号相应的 电压存储在第一电容 C1中。
[0066] 所述 OLED串联在第五晶体管 T5的漏极 （或源极） 、 第三晶体管 T3的源极 （或 漏极） 之间。 在像素 110的发光吋段
t4期间， OLED将发射与经过第一电源 ELVDD、 第五晶体管 T5、 第二晶体管 Τ2 和第四晶体管 Τ4提供的驱动电流大小相对应强度的光。
[0067] 在像素 110中， 由于驱动晶体管 （如， 第五晶体管 Τ5) 阈值电压的不一致， 导 致流过 OLED的电流也不一致， 会造成像素 110亮度的一致性会变差， 最终导致 图像不均匀。 而经过设置第四晶体管 T4和第三晶体管 T3后， 在每一帧的初始化 吋段 tl期间补偿驱动晶体管 （如第五晶体管 T5) 的阈值电压的变化， 能够避免上 述因像素 110的亮度一致性变差而造成图像不均匀的产品缺陷。
[0068] 图 4为驱动图 3所示像素的驱动信号波形图。 为了便于描述， 图 4中示出了一段 图 3所示像素在一帧信号期间提供的驱动信号的波形， 结合图 3对该像素的驱动 过程进行说明。 其中：
[0069] 扫描控制信号 Scanl , 用于控制第二晶体管 T2， 以控制其与第一电源 ELVDD的 导通。
[0070] 扫描控制信号 Scan2， 用于控制第一晶体管 Tl， 以写入数据电平。
[0071] 发射控制线 Eml， 用于控制第三晶体管 T3， 以控制其与第二电源 ELVSS1的导 通。
[0072] 发射控制线 Em2， 用于控制第四晶体管 T4， 以控制其与第三电源 ELVSS2的导 通。
[0073] 如图 4所示， 在设置为初始化阶段即吋段 tl期间， 首先将低电平的扫描控制信 号 Scanl提供给像素 110。 因此第二晶体管 T2通过低电平的扫描控制信号 Scanl而 导通。 进而第一电源 ELVDD的电压被提供给第五晶体管 T5的源极 （或漏极） 。 将低电平的发射控制信号 Eml提供给像素 110。 因此第三晶体管 T3通过低电平的 发射控制信号 Eml而导通。 从而将第二电源 ELVSS1的电压提供给第三晶体管 T3 的源极 （或漏极） 。
[0074] 参考图 3， 在吋段 tl期间， 还可通过第三晶体管 T3将第二电源 ELVSS1的电压作 为复位电压提供给第三晶体管 T3的源极 （或漏极） ， 从而在每一帧中第三晶体 管 T3的源极 （或漏极） 可被恒定地复位。
[0075] 其后， 在设置为数据电压写入吋段 t2期间 （即写入数据电压阶段） ， 将低电平 的扫描控制信号 Scan2提供给像素 110。 然后， 第一晶体管 T1响应低电平的扫描 控制信号 Scan2而导通。 因此经第一晶体管 T1将提供给数据线 Dm的数据信号 Vda ta提供给第五晶体管 T5的栅极。 此吋， 由于第五晶体管 T5处于导通状态， 将第二 晶体管 T2的漏极 （或源极） 相应的电压提供给 OLED的阳极。 而提供给 OLED的 阴极端的第二电源电压 ELVSS1 , 则通过 OLED的寄生电容 Coled、 第五晶体管 T5 的漏极 （或源极） 对第一电容 C1充电。
[0076] 再后， 在设置为阈值电压补偿的吋段 t3期间 （即闺值补偿） ， 发射控制信号 Em 2跃迁到低电平。 然后， 第四晶体管 T4通过响应发射控制信号 Em2而导通。 因此 ， 第二晶体管 T2的漏极 （或源极） 的电荷经第五晶体管 T5、 OLED的阳极的路径 流向第三电源 ELVSS2, 当第二晶体管 Τ2的漏极 （或源极） 电压高于第五晶体管 Τ5栅极的电压一个阈值电压 （即第五晶体管 Τ5的阈值电压） 吋， 第五晶体管 Τ5 截止， 所述第二晶体管 Τ2漏极 （或源极） 的电荷停止流动。
[0077] 这里， 所述第五晶体管 Τ5响应于提供给第五晶体管 Τ5的阈值电压相应的电压存 储在第一电容 C1中， 所以在吋段 t3期间对于第五晶体管 Τ5的阈值电压进行补偿
[0078] 最后， 在设置为发光的吋段 t4期间 （即发光阶段） ， 扫描控制信号 Scanl跃迁到 低电平。 然后第二晶体管 T2通过响应扫描控制信号 Scanl而导通。 因此， 驱动电 流沿第一电源 ELVDD经第二晶体管 T2、 第五晶体管 T5、 OLED和第四晶体管 Τ4 的路径流到第三电源 ELVSS2。 流经有机发光二极管 （OLED) 的电流 Ioled为：
[0079] Ioled= l/2Cox ( W/L) (Vdata ) Λ2
[0080] 其中： Cox、 μ、 W和 L分别为第五晶体管 Τ5的单位面积沟道电容， 沟道迁移率
， 沟道宽度和长度； Vdata为数据电压。
[0081] 上述流经 OLED的电流， 可以近似的表示为：
[0082] Ioled= l/2*K*[Vsg - IVthl]A2
[0083] =l/2*K*[Vdd - (Vdd - Vcl) - IVthl]A2
[0084] =l/2*K*[IVthl +(1 - N)/N* Vdata - IVthl]A 2
[0085] =1/2*K*[(1 - N)/N* Vdata] Λ2
[0086] =l/2*K*[Vdata]A2。
[0087] 其中： K为 Cox* *W*L， 为一常数； Vsg为源极和栅极的电压差； Vth为阈值 电压； Vdd为第一电源电压 ELVDD; Vcl为第一电容 C1存储电压； Vdata为数据 电压； N为大于 1的自然数。
[0088] 以上所述， 仅为本发明的较佳实施例而已， 并非用于限定本发明的保护范围。

Claims

权利要求书
一种像素电路 （112) ， 包括基础电路 （1122) ， 其特征在于， 所 述像素电路 （112) 还包括供电电路 （1121) 和补偿电路 （1123) ； 所述供电电路 （1121) 、 基础电路 （1122) 及补偿电路 （1123 ) 依次相连； 所述供电电路 （1121) 连接第一电源 ELVDD, 为所 述基础电路 （1122) 提供电源； 所述补偿电路 （1123) 分别与第 二电源 ELVSS1和第三电源 ELVSS2相连， 用于提供补偿有机发光 二极管 OLED的电压和电流的差值。
根据权利要求 1所述的像素电路， 其特征在于， 所述供电电路 （11
21) 为第二晶体管 T2; 所述第二晶体管 T2的栅极与扫描控制信号 线 Scanl相连， 源极与第一电源 ELVDD相连， 漏极与所述基础电 路 （1122) 相连。
根据权利要求 1所述的像素电路， 其特征在于， 所述基础电路 （11
22) 经并联的 OLED和寄生电容 Coled与所述补偿电路 （1123) 相 连。
根据权利要求 1所述的像素电路， 其特征在于， 所述基础电路 （11
22) 包括第一晶体管 Tl、 第五晶体管 Τ5和第一电容 C1 ; 所述第一 晶体管 T1的栅极与第二扫描控制线 Scan2相连， 所述第一晶体管 T1 的源极与数据线 Dm相连， 其漏极则与所述第五晶体管 T5的栅极相 连； 所述第一电容 C 1并联在所述第五晶体管 T5的栅极和源极之间 根据权利要求 1所述的像素电路， 其特征在于， 所述补偿电路 （11
23) 包括： 与 OLED并联的寄生电容 Coled、 第三晶体管 T3和第四 晶体管 T4; 所述 OLED和寄生电容 Coled并联后串联在基础电路 （1 122) 的第五晶体管 T5的漏极与补偿电路 （1123) 的第三晶体管 T3 和第四晶体管 T4的源极之间； 所述第三晶体管 T3、 第四晶体管 Τ4 的栅极分别与发射控制线 Eml、 发射控制线 Em2相连； 其漏极则分 别连接第二电源 ELVSS 1、 第三电源 ELVSS2。 [权利要求 6] 一种包含权利要求 1〜5任一项所述像素电路的像素。
[权利要求 7] 一种包含权利要求 6所述像素的 AM0LED显示装置。
[权利要求 8] 一种像素的驱动方法， 其特征在于， 包括如下步骤：
A、 通过第一电源 ELVDD连接供电电路 （1121) 和基础电路 （112 2) ， 并使基础电路 （1122) 通过 OLED与补偿电路 （1123) 相连
； 所述补偿电路 （1123) 与第二电源 ELVSS1、 第三电源 ELVSS2 相连；
B、 利用所述供电电路 （1121) 的第二晶体管 T2为基础电路 （1122 ) 供电； 并分别利用第二电源 ELVSS1、 第三电源 ELVSS2为补偿 电路 （1123) 供电； 所述供电电路 （1121) 的第二晶体管 T2的栅 极输入扫描控制信号 Scanl ; 所述基础电路 （1122) 的第一晶体管 T1的栅极输入扫描控制信号 Scan2， 其源极输入数据信号 Dm; 所 述补偿电路 （1123) 的第三晶体管 T3和第四晶体管 T4的栅极分别 输入发射控制信号 Eml和发射控制信号 Em2， 其源极均与 OLED的 阴极相接；
C、 在像素工作周期 T的吋段 tl期间， 提供扫描控制信号， 通过第 二晶体管 T2提供第一电源电压 ELVDD初始化第一电容 C 1；
D、 在向第一晶体管 Tl提供扫描控制信号 Scan2的吋段 t2期间， 将 与通过第一晶体管 T1提供的数据信号 Vdata相应的电压存储在第一 电容 C1中； 同吋， 第一晶体管 T1响应低电平的扫描控制信号 Scan2 而导通， 经第一晶体管 T1将提供给数据线 Dm的数据信号 Vdata提 供给第五晶体管 T5的栅极； 将第二晶体管 T2的漏极相应的电压提 供给 OLED的阳极， 而给 OLED的阴极供电的第二电源电压 ELVSS 1则通过 OLED的寄生电容 Coled、 第五晶体管 T5的漏极对第一电容 C1充电；
E、 在阈值电压补偿的吋段 t3期间， 发射控制信号 Em2跃迁到低电 平， 使第四晶体管 T4通过响应发射控制信号 Em2导通； 第二晶体 管 T2的漏极的电荷经第五晶体管 T5、 OLED的阳极的路径流向第 三电源 ELVSS2; 当第二晶体管 T2的漏极电压高于第五晶体管 T5栅 极的电压一个阈值电压吋， 第五晶体管 Τ5截止， 所述第二晶体管 Τ 2漏极的电荷停止流动；
F、 在 OLED发光的吋段 t4期间， 扫描控制信号 Scanl跃迁到低电平 ； 第二晶体管 T2通过响应扫描控制信号 Scanl而导通， 驱动电流沿 第一电源 ELVDD经第二晶体管 T2、 第五晶体管 T5、 OLED和第四 晶体管 T4的路径流到第三电源 ELVSS2。
根据权利要求 8所述像素的驱动方法， 其特征在于， 在吋段 tl期间 ， 还能够通过第三晶体管 T3将第二电源 ELVSS 1的电压作为复位电 压提供给第三晶体管 T3的源极， 使在每一帧中第三晶体管 T3的源 极被恒定地复位。
根据权利要求 8所述像素的驱动方法， 其特征在于， 在 OLED发光 的吋段 t4期间， 流经所述 OLED的电流 Ioled为：
Ioled=l/2Cox (μ Υ/L) (Vdata ) Λ2;
其中： 所述 Cox、 μ、 W和 L分别为第五晶体管 Τ5的单位面积沟道 电容， 沟道迁移率， 沟道宽度和长度； Vdata为数据电压。
根据权利要求 10所述像素的驱动方法， 其特征在于， 所述流经 OL
ED的电流 Ioled近似表示为：
Ioled=l/2*K* [Vdata] Λ2;
其中， Κ为常数； Vdata为数据电压。
PCT/CN2014/095331 2013-12-31 2014-12-29 像素电路、像素及包括该像素的amoled显示装置及其驱动方法 WO2015101255A1 (zh)

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US15/109,420 US10607538B2 (en) 2013-12-31 2014-12-29 Pixel circuit, pixel, AMOLED display device comprising same and driving method thereof
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KR1020167016355A KR101862494B1 (ko) 2013-12-31 2014-12-29 화소회로, 화소 및 해당 화소를 포함하는 amoled 디스플레이 장치 및 그 구동방법
US16/134,737 US10607542B2 (en) 2013-12-31 2018-09-18 Pixel circuit, pixel, and AMOLED display device comprising pixel and driving method thereof

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