WO2015100893A1 - 阵列基板及显示装置 - Google Patents

阵列基板及显示装置 Download PDF

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Publication number
WO2015100893A1
WO2015100893A1 PCT/CN2014/076460 CN2014076460W WO2015100893A1 WO 2015100893 A1 WO2015100893 A1 WO 2015100893A1 CN 2014076460 W CN2014076460 W CN 2014076460W WO 2015100893 A1 WO2015100893 A1 WO 2015100893A1
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Prior art keywords
electrode
array substrate
layer
light blocking
light
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PCT/CN2014/076460
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English (en)
French (fr)
Inventor
金起满
柳在健
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京东方科技集团股份有限公司
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Priority to US14/420,764 priority Critical patent/US9559126B2/en
Publication of WO2015100893A1 publication Critical patent/WO2015100893A1/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133528—Polarisers
    • G02F1/133548—Wire-grid polarisers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned

Definitions

  • Embodiments of the invention relate to an array substrate and a display device. Background technique
  • FIG. 1 shows an array substrate of an advanced super-dimensional field switching (ADS) mode.
  • the array substrate includes: a base substrate 1, a pixel structure layer (only the lowermost common electrode 3 is shown), and a lower polarizer 5 located under the base substrate.
  • the underlying polarizer 5 is deformed due to stress generated in the base substrate 1, thereby causing a phase difference and causing light leakage.
  • an array substrate including: a substrate substrate; a pixel structure layer formed on the substrate substrate; and a line between the substrate substrate and the pixel structure layer
  • the gate layer, the wire grid layer comprises a plurality of light blocking strips arranged in parallel.
  • all of the light barriers of the wire grid layer are rectangular in cross section and are unequal in size.
  • the distance between adjacent light bars is equal.
  • the light blocking strip is made of a reflective material.
  • the pixel structure layer includes: a first electrode and a second electrode, the first electrode is located between the second electrode and the base substrate, and the wire grid layer is formed in the first Between an electrode and a substrate.
  • the first electrode is formed on a surface of the wire grid layer facing away from the base substrate.
  • the first electrode is a pixel electrode
  • the second electrode is a common electrode
  • the first electrode is a common electrode
  • the second electrode is a pixel electrode
  • the thickness of the common electrode layer is 117-143 nm
  • the thickness of the light-blocking strip is 81-99 nm
  • the width of the light-blocking strip is 67.5-82.5 nm, adjacent to two light-blocking strips. between The distance is 67.5 ⁇ 82.5 ⁇ .
  • the common electrode layer has a thickness of 130 nm
  • the light blocking strip has a thickness of 90 nm
  • the light blocking strip has a width of 75 nm
  • a distance between adjacent two light blocking strips is 75 nm.
  • a display device comprising any of the array substrates described.
  • FIG. 1 is a schematic structural view of an array substrate of a conventional technology
  • FIG. 2 is a schematic structural view of an array substrate according to an embodiment of the present invention.
  • Figure 3 is a partial enlarged view of the array substrate of Figure 2;
  • FIG. 4 is a simulation diagram of transmissivity of each polarized light passing through the array substrate of FIG. 2;
  • Figure 5 is a schematic illustration of light passing through the array substrate of Figure 2.
  • an array substrate includes: a base substrate 1 and a pixel structure layer formed on the base substrate 1.
  • the base substrate in this embodiment further includes: a wire grid layer 6 formed by a plurality of light blocking strips 4 arranged in parallel between the base substrate 1 and the pixel structure layer. Such a design can avoid light leakage due to stress generated by the substrate.
  • all of the light blocking strips 4 of the wire grid layer are rectangular in cross section and of equal size.
  • the distance between adjacent light bars 4 is equal.
  • the present invention is not limited thereto, and for example, the light blocking strip 4 may have a semicircular cross section or the like.
  • the light blocking strip 4 is made of a reflective material such as metal A1 or aluminum alloy. This allows untransmitted light to be reflected to the backlight and reflected by the backlight into the array substrate.
  • the reflective material may also be other materials such as a resin material doped with glass beads or the like.
  • the pixel structure layer comprises: a first electrode and a second electrode.
  • the first electrode is located between the second electrode and the base substrate, and the wire grid layer is formed between the first electrode and the base substrate.
  • the first electrode may form a surface of the wire grid layer facing away from the substrate substrate.
  • the first electrode is a pixel electrode, the second electrode is a common electrode; or the first electrode is a common electrode, and the second electrode is a pixel electrode.
  • the wire grid layer may be formed together with the source and drain electrodes, and then a first electrode (such as a pixel electrode) connected to the drain is formed, so that the first electrode covers the wire grid.
  • a first electrode such as a pixel electrode
  • the wire grid layer may be formed together with the gate electrode and the common electrode line, and the common electrode may be formed on the surface of the wire gate layer.
  • embodiments of the invention are not limited to the ADS mode.
  • the common electrode layer 3 is located at the bottom of the pixel structure layer.
  • the wire grid layer 6 is formed on the surface of the base substrate 1, and the common electrode layer 3 forms a surface of the wire gate layer 6 facing away from the substrate substrate 1.
  • the common electrode layer can also be located at other suitable locations.
  • the thickness (H+D) of the common electrode layer is 117 to 143 nm, for example, 130 nm, and the thickness H of the light blocking strip is 81 to 99 nm, for example, 90 nm.
  • the width of the light strip W is 67.5-82.5 nm, for example, 75 nm, and the distance G between two adjacent light blocking strips is 67.5-82.5 nm, and the mouth is 75 nm.
  • FIG. 4 shows the Rigorous Coupled Wave Analysis
  • CWA CWA
  • the X-axis in the figure represents the wavelength ⁇
  • the ⁇ -axis represents the transmittance ⁇ or the reflectance 1.
  • 4 is a view in which the arrangement period of the light blocking strip 4 in FIG. 3 is set to 150 nm, the width of the light blocking strip 4 is set to 75 nm, the thickness is set to 90 nm, and the thickness of the ITO layer on the light blocking strip 4 is set to 40 nm. Simulation results. As shown in Fig. 5, the P-polarized component is left. However, due to the residual stress of the base substrate 1, the portion becomes elliptically polarized.
  • the wire grid layer 6 is characterized by allowing P-polarization in one direction, and other polarization reflections, for example, as shown in FIG. 4, the metal or dielectric substance is located between the common electrode 3 and the substrate 1 .
  • the S-polarized component is not transmitted, and only the P-polarized component is passed, thereby preventing light leakage.
  • S-T represents the transmittance of S-polarized light
  • S-R represents the reflectance of S-polarized light
  • P-T represents the transmittance of P-polarized light
  • P-R represents the reflectance of P-polarized light.
  • a display device comprising the array substrate described above.
  • the display device can be: a liquid crystal panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigation device, and the like, or any display product or component.

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  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Chemical & Material Sciences (AREA)
  • Mathematical Physics (AREA)
  • Geometry (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Polarising Elements (AREA)

Abstract

一种阵列基板和包括该阵列基板的显示装置，其中阵列基板包括衬底基板（1），像素结构层形成在衬底基板（1）上，衬底基板（1）和像素结构层之间具有由若干平行排列的挡光条（4）形成的线栅层（6）。由于具有由挡光条（4）形成的线栅层（6），该阵列基板能够防止衬底基板（1）在产生应力时所造成的漏光现象。

Description

阵列基板及显示装置 技术领域 本发明的实施例涉及一种阵列基板及显示装置。 背景技术
图 1示出一种高级超维场转换技术 ( ADvanced Super Dimension Switch, ADS )模式的阵列基板。 该阵列基板包括： 衬底基板 1、 像素结构层（只示 出了最下方的公共电极 3 )及位于衬底基板下方的下偏光片 5。
在使用过程中， 由于衬底基板 1会产生应力，使得下偏光片 5发生形变， 从而产生相位差， 引起漏光现象。 发明内容
根据本发明的至少一个实施例， 提供一种阵列基板， 包括： 衬底基板； 像素结构层， 形成在所述衬底基板上的； 以及位于所述衬底基板和像素结构 层之间的线栅层， 线栅层包括若干平行排列的挡光条。
在一个示例中， 所述线栅层的所有挡光条的横截面均为矩形， 且大小相 等。
在一个示例中， 相邻所述挡光条间的距离相等。
在一个示例中， 所述挡光条为反光材料制成。
在一个示例中， 所述像素结构层包括： 第一电极和第二电极， 所述第一 电极位于所述第二电极和所述衬底基板之间， 所述线栅层形成在所述第一电 极和衬底基板之间。
在一个示例中， 所述第一电极形成在所述线栅层背离所述衬底基板的表 面。
在一个示例中， 所述第一电极为像素电极， 所述第二电极为公共电极； 或所述第一电极为公共电极， 所述第二电极为像素电极。
在一个示例中， 所述公共电极层的厚度为 117~143nm， 所述挡光条的厚 度为 81~99nm， 所述挡光条的宽度为 67.5~82.5nm， 相邻两个挡光条的之间的 距离为 67.5~82.5匪。
在一个示例中， 所述公共电极层的厚度为 130nm， 所述挡光条的厚度为 90nm， 所述挡光条的宽度为 75nm， 相邻两个挡光条的之间的距离为 75nm。
根据本发明的至少一个实施例， 还提供一种显示装置， 包括所述的任一 种阵列基板。 附图说明
以下将结合附图对本发明的实施例进行更详细的说明， 以使本领域普通 技术人员更加清楚地理解本发明， 其中：
图 1是常规技术的一种阵列基板结构示意图；
图 2是本发明的实施例的一种阵列基板结构示意图；
图 3是图 2中阵列基板的局部放大图；
图 4是通过图 2中阵列基板的各偏光的透射反射率的模拟图；
图 5是光通过图 2中阵列基板的示意图。 具体实施方式
为使本发明的实施例的目的、 技术方案和优点更加清楚， 下面将结合本 发明实施例的附图对本发明的实施例的技术方案进行清楚、 完整的描述。 显 然， 所描述的实施例仅是本发明的一部分示例性实施例， 而不是全部的实施 例。 基于所描述的本发明的示例性实施例， 本领域普通技术人员在无需创造 性劳动的前提下所获得的所有其它实施例都属于本发明的保护范围。
除非另作定义， 此处使用的技术术语或者科学术语应当为本发明所属领 域内具有一般技能的人士所理解的通常意义。 本发明专利申请说明书以及权 利要求书中使用的 "第一"、 "第二" 以及类似的词语并不表示任何顺序、 数 量或者重要性， 而只是用来区分不同的组成部分。 同样， "一个"、 "一" 或者 "该" 等类似词语也不表示数量限制， 而是表示存在至少一个。 "包括" 或者 "包含" 等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后 面列举的元件或者物件及其等同，而不排除其他元件或者物件。 "上"、 "下"、 等仅用于表示相对位置关系， 当被描述对象的绝对位置改变后， 则该相对位 置关系也可能相应地改变。
下面对本发明的具体实施方式作进一步详细描述， 其中为了使描述更清 楚， 文中省略了一些特征、 结构， 但这种描述方式并不表示在本发明的实施 例中， 只包含所描述的特征、 结构， 因此， 还可以包括其他需要的特征结构。 本发明一实施例的阵列基板如图 2所示， 包括： 衬底基板 1及形成在衬底基板 1 上的像素结构层。 该实施例中的衬底基板还包括： 位于衬底基板 1和像素结构 层之间的由若干挡光条 4平行排列形成的线栅层 6。 这样的设计可以避免由于 衬底基板产生应力而导致的漏光现象。
在本发明的一实施例中， 线栅层的所有挡光条 4的横截面均为矩形， 且 大小相等。 相邻挡光条 4间的距离相等。 但本发明不限于此， 例如， 挡光条 4 的横截面可以为半圓形等。
为了提高亮度， 挡光条 4由反光材料制成， 如金属 A1或者铝合金。 这样 可以使未透过的光反射到背光源， 再由背光源反射入阵列基板。 反光材料还 可以是其它材料， 例如， 掺有玻璃微珠的树脂材料等。
根据本发明实施例中的阵列基板， 其中的像素结构层包括： 第一电极和 第二电极。 第一电极位于第二电极和衬底基板之间， 线栅层形成在所述第一 电极和衬底基板之间。 为了方便制作， 第一电极可以形成在线栅层背离衬底 基板的表面。 第一电极为像素电极， 第二电极为公共电极； 或第一电极为公 共电极， 第二电极为像素电极。
例如， 对于 ADS模式中像素电极在公共电极下方的情况， 线栅层可以和 源、 漏电极一起形成， 再形成与漏极连接的第一电极（如像素电极）， 使第一 电极覆盖在线栅层的表面。 再例如， 对于 ADS模式中公共电极在像素电极下 方的情况， 线栅层可以和栅极及公共电极线一起形成， 再在线栅层表面形成 公共电极。 但是本发明的实施例不限于 ADS模式。
如图 2所示， 公共电极层 3位于像素结构层的最下方。 线栅层 6形成在 衬底基板 1的表面， 公共电极层 3形成在线栅层 6背离所述衬底基板 1的表 面。 公共电极层也可以位于其它合适位置。
如图 3所示， 本实施例中， 公共电极层的厚度 ( H+D )为 117~143nm， 例如为 130nm， 所述挡光条的厚度 H为 81~99nm， 例如为 90nm， 所述挡光 条 W的宽度为 67.5~82.5nm， 例如为 75nm， 相邻两个挡光条的之间的距离 G 为 67.5~82.5nm， 例 口为 75nm。
图 4所示为通过严格耦合波分析 （ Rigorous Coupled Wave Analysis
( CWA ) )方法， 对新结构中的各偏光的透射反射率进行模拟得到的结果。 图中的 X轴表示波长 λ， Υ轴表示透射率 Τ或反射率1。 图 4是在图 3中的挡光条 4 的排列周期设置为 150nm，挡光条 4的宽度设置为 75nm，厚度设置为 90nm，位 于挡光条 4上的 ITO层厚度设置为 40nm时获得的模拟结果。 结合图 5所示， 由 剩下 P偏光成分。 但因衬底基板 1的残余应力作用， 部分变为椭圓偏光。 在部 分变为椭圓偏光的光中， P偏光成分的一部分变为 S偏光成分。 而由于线栅层 6 的特点是允许通过一个方向的 P偏光， 对其他的偏光反射， 例如， 参见图 4所 示， 在通过位于公共电极 3和衬底基板 1之间的由金属或电介质物质形成的线 栅结构时， 不会透射 S偏光成分， 而仅通过 P偏光成分， 从而可以防止漏光现 象。 图 4中的 S—T表示 S偏光的透射率， S— R表示 S偏光的反射率， P— T表示 P偏 光的透射率， P— R表示 P偏光的反射率。
本发明实施例的阵列基板， 由于在衬底基板和像素结构层之间形成有线 栅层， 因此， 可以防止由于衬底基板产生应力而可能导致的漏光现象。 而且， 制作工艺非常简单。
在本发明的实施例中， 还提供一种显示装置， 包括上面所述的阵列基板。 该显示装置可以为： 液晶面板、 手机、 平板电脑、 电视机、 显示器、 笔记本 电脑、 数码相框、 导航仪等任何具有显示功能的产品或部件。
以上实施方式仅用于说明本发明， 而并非对本发明的限制， 本技术领域 的普通技术人员， 在不脱离本发明的精神和范围的情况下， 还可以做出各种 变化和变型， 这些变化、 变型和以及所有等同的技术方案也应属于本发明的 范畴， 本发明的保护范围由权利要求限定。
本申请要求于 2013年 12月 31 日提交的名称为 "阵列基板及显示装置" 的中国专利申请 No. 201310752975.5的优先权， 该申请全文以引用方式合并 于本文。

Claims

权利要求书
1、 一种阵列基板， 包括：
衬底基板；
像素结构层， 形成在所述衬底基板上； 以及
线栅层， 位于所述衬底基板和像素结构层之间， 包括若干平行排列的挡 光条。
2、 如权利要求 1所述的阵列基板， 其中所述线栅层的所有挡光条的横截 面均为矩形， 且大小相等。
3、 如权利要求 1-2任一项所述的阵列基板， 其中相邻所述挡光条间的距 离相等。
4、 如权利要求 1-3任一项所述的阵列基板， 其中所述挡光条为反光材料 制成。
5、如权利要求 1-4中任一项所述的阵列基板，其中所述像素结构层包括： 第一电极和第二电极， 所述第一电极位于所述第二电极和所述衬底基板之间， 所述线栅层形成在所述第一电极和所述衬底基板之间。
6、 如权利要求 5所述的阵列基板， 其中所述第一电极形成在所述线栅层 背离所述衬底基板的表面。
7、 如权利要求 5所述的阵列基板， 其中所述第一电极为像素电极， 所述 第二电极为公共电极； 或所述第一电极为公共电极， 所述第二电极为像素电 极。
8、 如权利要求 5 所述的阵列基板， 其中所述公共电极层的厚度为 117~143nm , 所述挡光条的厚度为 81~99nm， 所述挡光条的宽度为 67.5~82.5nm, 相邻两个挡光条的之间的距离为 67.5~82.5nm。
9、如权利要求 8所述的阵列基板，其中所述公共电极层的厚度为 130nm， 所述挡光条的厚度为 90nm， 所述挡光条的宽度为 75nm， 相邻两个挡光条的 之间的 巨离为 75nm。
10、 一种显示装置， 包括： 如权利要求 1-9中任一项所述的阵列基板。
PCT/CN2014/076460 2013-12-31 2014-04-29 阵列基板及显示装置 WO2015100893A1 (zh)

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