WO2015081564A1 - 基于锁相环频率快速锁定的频率合成方法及其电路 - Google Patents

基于锁相环频率快速锁定的频率合成方法及其电路 Download PDF

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WO2015081564A1
WO2015081564A1 PCT/CN2013/088791 CN2013088791W WO2015081564A1 WO 2015081564 A1 WO2015081564 A1 WO 2015081564A1 CN 2013088791 W CN2013088791 W CN 2013088791W WO 2015081564 A1 WO2015081564 A1 WO 2015081564A1
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phase
frequency
locked loop
unit
loop filter
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French (fr)
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崔建伟
陈杰
唐伟群
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Hytera Communications Corp Ltd
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Hytera Communications Corp Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H03L7/107—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
    • H03L7/1075—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth by changing characteristics of the loop filter, e.g. changing the gain, changing the bandwidth

Definitions

  • the channel used by the wireless transceiver to communicate will be switched in real time according to channel occupancy and channel quality.
  • the switching of the channel is achieved by changing the output frequency of the frequency synthesizer.
  • the frequency synthesizer provides a programmable local carrier signal to the frequency conversion circuit in the transceiver circuit and is the core of the wireless communication device.
  • the frequency synthesis method currently used is mainly realized by a phase-locked loop pressure-controlled oscillator.
  • the time required for the oscillation frequency of the frequency source to switch between the two frequency points is related to the frequency interval between the two frequency points: the larger the interval between the two frequency points, the larger the difference between the voltage control voltages of the corresponding filter outputs is needed.
  • the switching time of the voltage control voltage between two different frequency points of the frequency source frequency is shortened (ie, the voltage controlled oscillator is improved) to improve the phase locking speed of the frequency source. But this will increase the phase noise of the voltage controlled oscillator itself.
  • the frequency synthesizer locking process of the phase-locked loop mode is shown in Figure 1.
  • the frequency locking process is divided into three phases:
  • T1 Capture phase: The frequency changes from stable to unstable, the phase difference between the output frequency and the reference clock phase-detection frequency is very large, and the phase-locked loop is in an unlocked state;
  • T2 tilting phase
  • the phase difference between the output frequency and the reference clock phase-detection frequency is small, and the phase-locked loop tracks the output frequency, which belongs to the stage of loop self-adjustment;
  • T3 stable phase: The phase difference between the output frequency and the reference clock phase-detection frequency is very small, and the phase-locked loop is locked.
  • T1 phase In the three phases of the locking process, it is mainly determined by the T1 phase and the T2 phase that the target frequency is locked. And T2 The time of the phase is mainly determined by the parameters of the loop itself. The phase difference is small in the T2 phase, and the T3 phase can be quickly entered by the adjustment of the phase-locked loop itself.
  • T1 The time consumed by the phase capture phase has a critical impact on the overall lock time, generally by reducing the time in the TI phase to increase the phase-locked speed of the frequency source.
  • the phase-locked loop locking method in the related art is to pre-configure the estimated charging time for the phase-locked loop, and open the phase-locked loop to charge the loop filter in the phase-locked loop circuit in advance, so that the voltage in the loop is close to the locking voltage. Reduce the charging pump's time to charge the phase-locked loop, thus speeding up the locking speed.
  • the scheme needs to pre-measure the charging time statistical characteristics of the single-point voltage in the locked frequency band of the voltage-controlled oscillator, and store, and then read the charging time when the phase-locked loop circuit is turned on, so that the control center can issue the continuous charging time; the charging time and the frequency change Relationship 2; Because the voltages of different voltage-controlled oscillators corresponding to the same frequency point are not completely the same due to factors such as consistency and temperature, the preset voltage is not accurate enough, so that the locking time becomes longer.
  • the phase locked loop locking circuit is shown in Figure 3.
  • the voltage of the lock frequency is preset for the phase detector.
  • the digital-to-analog converter connected to the control center charges the low-pass filter through the operational amplifier, and detects the low-pass filter through the analog-to-digital converter through the reading switch.
  • the charging voltage when the preset locking voltage value is reached, the digital-to-analog converter sends a signal to the control center, and the control center sends a control signal to stop charging the loop filter, so that the voltage approaches the locking voltage of the set frequency point, thereby Achieve the purpose of reducing the lock time.
  • the scheme needs to pre-measure the statistical characteristics of the single-point voltage in the locked frequency band of the voltage-controlled oscillator, and store it in the memory; read the pre-stored voltage when configuring the data for the phase-locked loop, pre-charge through the digital-to-analog converter, and charge time
  • the digital converter detects feedback to the controller to form a closed-loop control; the scheme requires high circuit consistency and temperature stability, software response delay, and complicated circuit and high cost.
  • the phase locked loop unit compares in real time whether the output frequency of the voltage controlled oscillator reaches a range of its configuration data:
  • the DC power supply is disconnected according to the lock indication: the control unit receives the lock indication sent by the phase-locked loop unit, and sends a control signal to the DC The power supply causes it to stop charging the loop filter.
  • the phase-locked loop unit configures data through the central processing unit at the beginning of each lock slot.
  • phase-locked loop unit that compares the input frequency with the configuration data and outputs a lock indication when the input frequency reaches the range of the configuration data
  • a voltage controlled oscillator connected to the phase locked loop unit and outputting a frequency to the phase locked loop unit
  • a DC power source connected to the loop filter to provide a DC voltage for the loop filter and the voltage controlled oscillator
  • a charge pump located inside the phase locked loop unit, connected to the loop filter, and controlled by the phase locked loop unit to provide a pulsating alternating current power supply for the loop filter;
  • the DC power source charges the loop filter, the voltage rise of the loop filter pushes the frequency of the voltage controlled oscillator connected thereto from low to high; the voltage controlled oscillator will continuously change the output frequency Sending to the phase-locked loop unit, the phase-locked loop unit compares the new output frequency to its configuration data range in real time; if the output frequency reaches the range of the configuration data, the phase-locked loop unit outputs a lock indication, The DC power source is turned on, and the loop filter continues to be charged by the charge pump until the phase locked loop is locked.
  • the loop filter is further connected with a second switch for discharging to reduce an output frequency of the voltage controlled oscillator, the loop filter Grounded through the second switch.
  • the phase-locked loop unit is further connected with a control unit, and the control unit receives the lock indication of the phase-locked loop unit and outputs a control signal to be connected to the The first switch of the DC power source is turned off, stopping charging the loop filter.
  • FIG. 1 is a schematic diagram of a frequency synthesizer locking process of a phase locked loop method.
  • Fig. 2 is a diagram showing the relationship between charging time and frequency in a phase locked loop circuit in the prior art.
  • FIG. 3 is a schematic diagram of a phase locked loop locking circuit in the prior art.
  • FIG. 5 is a waveform diagram of an oscilloscope for capturing each signal in a frequency synthesis method based on phase-locked loop frequency fast lock in an embodiment of the present invention
  • FIG. 6 is a lock time test diagram of a frequency synthesizing method based on phase-locked loop frequency fast lock according to the present invention
  • FIG. 7 is a circuit block diagram of a frequency synthesizing circuit based on phase locked loop frequency fast locking in an embodiment of the present invention.
  • FIG. 4 illustrates a preferred embodiment of the invention
  • a frequency synthesis method based on phase-locked loop frequency fast lock is applicable to all phase-locked loop frequency synthesis communication systems with lock indication.
  • the frequency synthesizing method based on the phase locked loop frequency fast locking of the invention comprises the following steps:
  • the configuration data includes control information for each register configuration data of the phase locked loop unit, a frequency division ratio for the phase locked loop, and the like, so that the phase locked loop unit can work normally.
  • the loop filter is charged by the DC power supply, and the voltage rise of the loop filter pushes the frequency of the voltage controlled oscillator connected thereto from low to high.
  • the first switch connecting the loop filter and the DC power source is closed to charge the capacitor in the loop filter.
  • the DC power supply can directly charge the loop filter, so that the output frequency of the voltage controlled oscillator can quickly reach the configuration data range of the phase locked loop.
  • the phase locked loop chip calculates the value of the configuration data of its internal register to obtain a desired frequency. Then, the output frequency of the voltage controlled oscillator is compared with the desired frequency. It can be understood that the voltage value of the DC power source is greater than the locking voltage of the phase locked loop.
  • the phase-locked loop unit compares in real time whether the output frequency of the voltage-controlled oscillator reaches the range of its configuration data:
  • the phase locked loop unit If the output frequency is lower than the lower limit of the configuration data range, continue to charge the loop filter to increase the output frequency of the voltage controlled oscillator, and the phase locked loop unit reads the output frequency of the new output of the voltage controlled oscillator for real-time comparison.
  • the phase-locked loop unit sends a lock indication when it is repeated until the output frequency reaches the range of the configuration data.
  • the loop filter Before charging, since the loop filter is not charged, the voltage is low, and the frequency of the voltage controlled oscillator is at the low end of the output frequency of the entire frequency synthesizer; after the DC filter is used to charge the loop filter, the loop filtering
  • the voltage rise of the device drives the output frequency of the voltage controlled oscillator to change rapidly from the low end; until the output frequency reaches the desired frequency value of the configuration data, the phase locked loop unit sends a lock indication, that is, a high level.
  • the time of the capture phase of the phase locked loop frequency lock can be reduced.
  • the charging pump outputs a pulsating AC power supply, and the frequency of the voltage controlled oscillator enters a slow rising process. At this time, the phase locked loop frequency locks into the tracking phase.
  • the method prior to charging the loop filter, further includes discharging the loop filter to reduce an output frequency of the voltage controlled oscillator.
  • the phase locked loop reduces the output frequency of the voltage controlled oscillator by increasing the interval duration of the locked time slots.
  • the loop filter may be at a high level, and the lock frequency of the phase-locked loop unit is low, the loop filter needs to be discharged first, so that the voltage is low, and the voltage-controlled oscillation is performed. The frequency of the device is at the low end of the output frequency of the entire frequency synthesizer; the loop filter is then charged.
  • control unit is an FPGA. Through actual measurement, the response time of the phase-locked loop circuit through the FPGA control switch is less than 25 ⁇ S .
  • control unit can also be a latch of a flip flop or digital circuit. It will be appreciated that the control unit can be any logic unit that can react quickly to input signals.
  • the phase locked loop unit configures the data through the central processor.
  • the central processor is OMAP (Open Multimedia Application Platform, an open multimedia platform) processor.
  • the central processing unit is OMAP 5912 .
  • the phase locked loop unit is coupled to the host via its SPI bus for configuration data.
  • FIG. 5 is a waveform diagram of capturing various signals using an oscilloscope, wherein waveform 1 is a configuration data signal, waveform 2 is a charging time signal, waveform 3 is a lock indication signal, and waveform 4 is a phase locked loop circuit voltage signal.
  • the lock indication signal is a series of sharp pulse signals, wherein the phase of the first phase of the first sharp pulse is closest to the final lock voltage, that is, the DC power supply is interrupted at this time, the phase locked loop
  • the first lock indication spike is captured and the sample data is saved so that the subsequent spike signal is no longer responsive to triggering the DC power switch.
  • the lock time test chart of the frequency synthesis method based on the fast lock of the phase-locked loop frequency is shown in Fig. 6.
  • the lock time of the frequency synthesis circuit based on the fast lock of the phase-locked loop frequency from 0-483.35 MHz is shown.
  • the time of the T1 phase that is, the frequency lock tends to lock at the target frequency of 100 Hz
  • the time of the T1 phase is 1.733 ms, which reduces the lock time of the phase-locked loop circuit and reduces the power consumption of the circuit. .
  • a frequency synthesizing circuit based on phase-locked loop frequency fast locking as shown in FIG. 7, the frequency synthesizing circuit based on phase-locked loop frequency fast locking comprises:
  • the phase-locked loop unit compares the input frequency with the configuration data and outputs a lock indication when the input frequency reaches the range of the configuration data.
  • the voltage controlled oscillator is connected to the phase locked loop unit and outputs the frequency to the phase locked loop unit.
  • a loop filter connected to the voltage controlled oscillator.
  • a DC power supply connected to the loop filter, provides DC voltage to the loop filter and the voltage controlled oscillator.
  • the charge pump located inside the phase-locked loop unit, is connected to the loop filter and is controlled by the phase-locked loop unit to provide pulsating AC power to the loop filter.
  • the charge pump provides charge and discharge power to the loop filter.
  • the DC power supply charges the loop filter, and the voltage rise of the loop filter pushes the frequency of the voltage controlled oscillator connected thereto from low to high; the voltage controlled oscillator sends the changing output frequency to the phase locked loop unit, and the lock
  • the phase loop unit compares the new output frequency to its configuration data range in real time; if the output frequency reaches the range of the configuration data, the phase-locked loop unit outputs a lock indication, disconnects the DC power supply, and the loop filter continues to charge through the charge pump until the phase lock Ring locked.
  • the locking time is effectively shortened, and the circuit is simple, the cost is low, and the reliability is high.
  • the phase-locked loop unit is further connected with a control unit.
  • the control unit receives the lock indication of the phase-locked loop unit and outputs a control signal to disconnect the first switch connected to the DC power supply, and stops charging the loop filter.
  • the lock detection of the phase locked loop unit is realized by a phase detector inside the phase locked loop unit.

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Abstract

一种基于锁相环频率快速锁定的频率合成方法及其电路，该方法包括以下步骤：锁定时隙开始时为锁相环单元配置数据；对环路滤波器充电；锁相环单元在压控振荡器的输出频率达到其配置数据的范围时输出锁定指示；根据锁定指示断开电源。本发明在锁定时隙开始时提前为环路滤波器充电，通过锁定指示信号断开电源，缩短锁相环的锁定时间。

Description

基于锁相环频率快速锁定的频率合成方法及其电路 技术领域
本发明涉及无线通信电路，更具体地说，涉及一种基于锁相环频率快速锁定的频率合成方法及其电路。
背景技术
为了提高频谱效率，现代无线通信系统大都利用频分 / 时分复用技术，无线收发机进行通信时所用信道，会根据信道占用情况、信道质量进行实时切换。信道的切换，是通过改变频率合成器的输出频率来实现的。频率合成器给收发电路中的变频电路提供可编程的本地载波信号，是无线通信设备的核心。目前使用的频率合成方式主要是采用锁相环加压控振荡器方式实现的。
在锁相环频合方式中，在目前窄带通信系统中需要带内噪声尽量低，即需要环路滤波器带宽不能过宽，由于锁相环滤波器带宽的限制，频率源的相位噪声与锁相速度之间的互相制约：环路带宽窄时，锁定时间变长，但带内噪声比较低；环路带宽大时，可降低锁相环路的锁定时间，但带内相位噪声较差。频率源的振荡频率在两个频点之间切换所需要的时间与两个频点间的频率间隔有关：两个频点间隔越大，对应的滤波器输出的压控电压相差越大，需要的切换时间就越长。相关技术中大多采用缩短频率源频率两个不同频点间压控电压的切换时间（即提高压控振荡器），以提高频率源的锁相速度。但这会增加压控振荡器本身的相位噪声。
锁相环方式的频率合成器锁定过程示意如图 1 所示，其频率锁定过程分为三个阶段：
T1 （捕获阶段）：频率从稳定到不稳定的急剧变化，输出频率与参考时钟鉴相频率相位差非常大，锁相环处于失锁状态；
T2 ( 跟踪阶段 ) ：输出频率与参考时钟鉴相频率相位差较小，锁相环对输出频率进行跟踪，属于环路自身调节的阶段；
T3 ( 稳定阶段 ) ：输出频率与参考时钟鉴相频率相位差非常小，锁相环处于锁定的状态。
锁定过程的三个阶段中，主要是由 T1 阶段和 T2 阶段决定目标频率的锁定时间。而 T2 阶段的时间主要是由于环路自身的参数决定， T2 阶段时相位差较小，靠锁相环自身的调节可很快进入 T3 阶段。然而 T1 阶段捕获阶段所消耗的时间，对整体锁定时间起关键的影响，一般通过减小 TI 阶段的时间来提高频率源的锁相速度。
相关技术中的锁相环锁定方法是通过为锁相环提前配置预估充电时间，打开锁相环为锁相环电路中的环路滤波器提前充电，使环路中的电压接近锁定电压，减少充电泵为锁相环充电的时间，从而加快锁定速度。该方案需要预先测量压控振荡器锁定频段内单点电压的充电时间统计特性，并存储，在开启锁相环电路时再读取充电时间，便于控制中心发出持续充电时间；充电时间与频率变化关系如图 2 所示；由于不同的压控振荡器对应同一频点的电压由于一致性、温度等因素不完全相同，导致预置电压不够精确从而使得锁定时间变长。
目前， 锁相环锁定电路如图3 所示，首先为鉴相器预置锁定频点的电压，连接于控制中心的数模转换器通过运算放大器为低通滤波器充电，同时通过模数转换器通过阅读交换机检测低通滤波器的充电电压，当达到预置的锁定电压值时，数模转换器发送信号至控制中心，控制中心发送控制信号停止为环路滤波器充电，使电压趋近于所设置频点的锁定电压，从而达到减少锁定时间的目的。该方案需要预先测量压控振荡器锁定频段内单点电压的统计特性，并存储至储存器；为锁相环配置数据时再读预存的电压，通过数模转换器预先充电，充电时间由模数转换器检测反馈给控制器，形成闭环控制；该方案对电路一致性及温度稳定性要求较高，软件反应有延迟并且电路比较复杂、成本较高。
发明内容
本发明要解决的技术问题在于，提供一种改进的 基于锁相环频率快速锁定的频率合成方法及其电路 。
本发明解决其技术问题所采用的技术方案是：构造 一种基于锁相环频率快速锁定的频率合成方法，包括以下步骤：
在每个锁定时隙开始时，为锁相环单元配置数据；
通过直流电源对环路滤波器进行充电，所述环路滤波器的电压上升推动与其连接的压控振荡器的频率由低变高；
所述锁相环单元实时比较所述压控振荡器的输出频率是否达到其配置数据的范围：
在所述输出频率达到所述配置数据的范围时，所述锁相环单元送出锁定指示；
根据所述锁定指示断开所述直流电源，并连通充电泵继续为所述环路滤波器充电，直至所述锁相环锁定。
优选地，上述基于锁相环频率快速锁定的频率合成方法中，在对所述环路滤波器进行充电之前，还包括：对所述环路滤波器进行放电以降低所述压控振荡器的输出频率。
优选地，上述基于锁相环频率快速锁定的频率合成方法中，根据所述锁定指示断开所述直流电源为：控制单元接收锁相环单元发送的锁定指示，并发送控制信号至所述直流电源，使其停止为所述环路滤波器充电。
优选地，上述基于锁相环频率快速锁定的频率合成方法中，在每个锁定时隙开始时，所述锁相环单元通过中央处理器配置数据。
一种基于锁相环频率快速锁定的频率合成电路，包括：
锁相环单元，将输入频率与配置数据进行比较，并在输入频率达到配置数据的范围内时输出锁定指示；
压控振荡器，连接于所述锁相环单元，并输出频率至所述锁相环单元；
环路滤波器，连接于所述压控振荡器；
直流电源，连接于所述环路滤波器，为环路滤波器与压控振荡器提供直流电压；
充电泵，位于所述锁相环单元内部，连接于所述环路滤波器，由所述锁相环单元控制为所述环路滤波器提供脉动交流电源；
所述直流电源对所述环路滤波器进行充电，所述环路滤波器的电压上升推动与其连接的压控振荡器的频率由低变高；所述压控振荡器将不断变化的输出频率发送至所述锁相环单元，所述锁相环单元实时比较新输出频率是否达到其配置数据范围；若输出频率达到所述配置数据的范围，则所述锁相环单元输出锁定指示，断开所述直流电源，所述环路滤波器通过所述充电泵继续充电直至所述锁相环锁定。
优选地，上述基于锁相环频率快速锁定的频率合成电路中，所述环路滤波器还连接有用于放电以降低所述压控振荡器的输出频率的第二开关，所述环路滤波器通过所述第二开关接地。
优选地，上述基于锁相环频率快速锁定的频率合成电路中，所述锁相环单元还连接有控制单元，所述控制单元接收锁相环单元的锁定指示并输出控制信号使连接于所述直流电源的第一开关断开，停止为所述环路滤波器充电。
优选地，上述基于锁相环频率快速锁定的频率合成电路中，所述锁相环单元还连接有为其配置数据的中央处理器。
附图说明
下面将结合附图及实施例对本发明作进一步说明，附图中：
图1是锁相环方式的频率合成器锁定过程示意图。
图2是现有技术中锁相环电路中 充电时间与频率变化关系图。
图3是现有技术中锁相环锁定电路原理图。
图4是本发明一个实施例中基于锁相环频率快速锁定的频率合成方法的流程示意图；
图5是本发明一个实施例中基于锁相环频率快速锁定的频率合成方法中使用示波器抓捕各个信号的波形图；
图6是本发明基于锁相环频率快速锁定的频率合成方法的锁定时间测试图；
图7是本发明一个实施例中基于锁相环频率快速锁定的频率合成电路的电路原理框图。
具体实施方式
为了对本发明的技术特征、目的和效果有更加清楚的理解，现对照附图详细说明本发明的具体实施方式。
图 4 示出了本发明一个优选实施例中的 基于锁相环频率快速锁定的频率合成方法，适用于所有带锁定指示的锁相环路频率合成通信系统。本发明基于锁相环频率快速锁定的频率合成方法包括以下步骤：
在每个锁定时隙开始时，为锁相环单元配置数据。在配置数据时包括为锁相环单元的各寄存器配置数据、为锁相环配置分频比等使锁相环单元正常工作所需要的控制信息。
通过直流电源对环路滤波器进行充电，环路滤波器的电压上升推动与其连接的压控振荡器的频率由低变高。在配置数据完成后，将连通环路滤波器和直流电源的第一开关闭合，为环路滤波器中的电容进行充电。直流电源可直接为环路滤波器进行充电，使压控振荡器的输出频率快速达到锁相环的配置数据范围，锁相环芯片通过计算其内部寄存器的配置数据的值，得到一个期望达到频率，再将压控振荡器的输出频率与该期望达到的频率进行比较。可以理解地，直流电源的电压值大于锁相环的锁定电压。
锁相环单元实时比较压控振荡器的输出频率是否达到其配置数据的范围：
若输出频率低于配置数据范围的下限，则继续对环路滤波器进行充电以增加压控振荡器的输出频率，锁相环单元读取压控振荡器新输出的输出频率进行实时比较，如此反复直至输出频率达到配置数据的范围时，锁相环单元送出锁定指示。
在充电前，由于环路滤波器未充电，电压表现为低电平，压控振荡器的频率在整个频率合成器输出频率的低端；使用直流电源为环路滤波器充电后，环路滤波器的电压快速上升推动压控振荡器的输出频率从低端快速向上变化；直到输出频率达到配置数据期望达到的频率值，锁相环单元送出锁定指示，即高电平。可减小锁相环频率锁定的捕获阶段的时间。
根据锁定指示断开直流电源，并连通充电泵继续为环路滤波器充电，直至锁相环锁定。充电泵输出脉动交流电源，压控振荡器的频率进入缓慢上升过程，此时锁相环频率锁定进入跟踪阶段。
在一些实施例中，在对环路滤波器进行充电之前，还包括：对环路滤波器进行放电以降低压控振荡器的输出频率。可以理解地，在另一些实施例中，锁相环通过增加锁定时隙的间隔时长以降低所述压控振荡器的输出频率。在充电前，环路滤波器可能处于高电平，而锁相环单元的锁定频率为低端，则需要先对环路滤波器进行放电，使其电压表现为低电平，使压控振荡器的频率处于整个频率合成器输出频率的低端；再对环路滤波器进行充电。
根据锁定指示断开直流电源为：控制单元接收锁相环单元发送的锁定指示，并发送控制信号至直流电源，使其停止为环路滤波器充电。控制单元接收到控制信号后，断开与直流电源连接的第一开关，使直流电源停止为环路滤波器的电容充电。
在一些实施例中，控制单元为FPGA。通过实际测量，锁相环电路通过FPGA控制开关开闭的响应时间小于25 μ S 。在另一些实施例中，控制单元还可以为触发器或数字电路的锁存器。可以理解地，控制单元可为任何能对输入信号快速反应的逻辑单元。
在每个锁定时隙开始时，锁相环单元通过中央处理器配置数据。中央处理器为 OMAP （ Open Multimedia Application Platform ，开放式多媒体平台 ）系列的处理器。优选地，中央处理器为 OMAP 5912 。在另一些实施例中， 锁相环单元通过SPI总线连接于主机为其配置数据。
图5为使用示波器抓捕各个信号的波形图，其中波形1为配置数据信号，波形2为充电时间信号，波形3为锁定指示信号，波形4为锁相环电路电压信号。由图可看出锁定指示信号为一系列的尖脉冲信号，其中第一个尖脉冲的起始时刻锁相环电路电压最接近于最终的锁定电压，即在此时中断直流电源，锁相环捕捉第一个锁定指示尖脉冲并保存采样数据使得后面的尖脉冲信号不再响应触发直流电源开关。
基于锁相环频率快速锁定的频率合成方法的锁定时间测试图如图6所示，图中为基于锁相环频率快速锁定的频率合成电路从0-483.35MHz的锁定时间。由图可知，T1阶段（即频率锁定趋于目标频率100Hz完成锁定）的时间为1.733ms，减少锁相环电路的锁定时间，可降低电路所需功耗 。
一种基于锁相环频率快速锁定的频率合成电路，如图7所示，该基于锁相环频率快速锁定的频率合成电路包括： 锁相环单元，将输入频率与配置数据进行比较，并在输入频率达到配置数据的范围内时输出锁定指示。 压控振荡器，连接于锁相环单元，并输出频率至锁相环单元。 环路滤波器，连接于压控振荡器。直流电源，连接于环路滤波器，为环路滤波器与压控振荡器提供直流电压。 充电泵，位于锁相环单元内部，连接于环路滤波器，由锁相环单元控制为环路滤波器提供脉动交流电源。
充电泵可为环路滤波器提供充放电电源。 直流电源对环路滤波器进行充电，环路滤波器的电压上升推动与其连接的压控振荡器的频率由低变高；压控振荡器将不断变化的输出频率发送至锁相环单元，锁相环单元实时比较新输出频率是否达到其配置数据范围；若输出频率达到配置数据的范围，则锁相环单元输出锁定指示，断开直流电源，环路滤波器通过充电泵继续充电直至锁相环锁定。有效缩短了锁定时间，并且电路简单、成本较低，且可靠性高。
在一些实施例中，环路滤波器还连接有用于放电以降低所述压控振荡器的输出频率的第二开关，环路滤波器通过所述第二开关接地。在锁定时隙开始时，若锁相环电路中的电压大于锁定电压，即压控振荡器的输出频率处于高端，而锁相环的锁定频率处于低端时，通过第二开关闭合将环路滤波器放电，使压控振荡器表现为低电平，再重新进行充电以达到锁定电压。在另一些实施例中，锁相环电路通过增加锁定时隙的间隔时长以降低所述压控振荡器的输出频率。
锁相环单元还连接有控制单元，控制单元接收锁相环单元的锁定指示并输出控制信号使连接于直流电源的第一开关断开，停止为环路滤波器充电。锁相环单元的锁定检测通过锁相环单元内部的鉴相器实现。
在一些实施例中，锁相环单元还连接有为其配置数据的中央处理器。优选地，中央处理器为OMAP 5912。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的权利要求范围之内。

Claims (8)

  1. 一种基于锁相环频率快速锁定的频率合成方法，其特征在于，包括以下步骤：
    在每个锁定时隙开始时，为锁相环单元配置数据；
    通过直流电源对环路滤波器进行充电，所述环路滤波器的电压上升推动与其连接的压控振荡器的频率由低变高；
    所述锁相环单元实时比较所述压控振荡器的输出频率是否达到其配置数据的范围：
    在所述输出频率达到所述配置数据的范围时，所述锁相环单元送出锁定指示；
    根据所述锁定指示断开所述直流电源，并连通充电泵继续为所述环路滤波器充电，直至所述锁相环锁定。
  2. 根据权利要求 1 所述的基于锁相环频率快速锁定的频率合成方法，其特征在于，在对所述环路滤波器进行充电之前，还包括：对所述环路滤波器进行放电以降低所述压控振荡器的输出频率。
  3. 根据权利要求1所述的基于锁相环频率快速锁定的频率合成方法，其特征在于，根据所述锁定指示断开所述直流电源为：控制单元接收锁相环单元发送的锁定指示，并发送控制信号至所述直流电源，使其停止为所述环路滤波器充电。
  4. 根据权利要求1所述的基于锁相环频率快速锁定的频率合成方法，其特征在于，在每个锁定时隙开始时，所述锁相环单元通过中央处理器配置数据。
  5. 一种基于锁相环频率快速锁定的频率合成电路，其特征在于，包括：
    锁相环单元，将输入频率与配置数据进行比较，并在输入频率达到配置数据的范围内时输出锁定指示；
    压控振荡器，连接于所述锁相环单元，并输出频率至所述锁相环单元；
    环路滤波器，连接于所述压控振荡器；
    直流电源，连接于所述环路滤波器，为环路滤波器与压控振荡器提供直流电压；
    充电泵，位于所述锁相环单元内部，连接于所述环路滤波器，由所述锁相环单元控制为所述环路滤波器提供脉动交流电源；
    所述直流电源对所述环路滤波器进行充电，所述环路滤波器的电压上升推动与其连接的压控振荡器的频率由低变高；所述压控振荡器将不断变化的输出频率发送至所述锁相环单元，所述锁相环单元实时比较新输出频率是否达到其配置数据范围；若输出频率达到所述配置数据的范围，则所述锁相环单元输出锁定指示，断开所述直流电源，所述环路滤波器通过所述充电泵继续充电直至所述锁相环锁定。
  6. 根据权利要求5所述的基于锁相环频率快速锁定的频率合成电路，其特征在于，所述环路滤波器还连接有用于放电以降低所述压控振荡器的输出频率的第二开关，所述环路滤波器通过所述第二开关接地。
  7. 据权利要求5所述的基于锁相环频率快速锁定的频率合成电路，其特征在于，所述锁相环单元还连接有控制单元，所述控制单元接收锁相环单元的锁定指示并输出控制信号使连接于所述直流电源的第一开关断开，停止为所述环路滤波器充电。
  8. 据权利要求5所述的基于锁相环频率快速锁定的频率合成电路，其特征在于，所述锁相环单元还连接有为其配置数据的中央处理器。
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