WO2015070715A1 - 金属氧化物薄膜晶体管及其制备方法 - Google Patents

金属氧化物薄膜晶体管及其制备方法 Download PDF

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WO2015070715A1
WO2015070715A1 PCT/CN2014/090193 CN2014090193W WO2015070715A1 WO 2015070715 A1 WO2015070715 A1 WO 2015070715A1 CN 2014090193 W CN2014090193 W CN 2014090193W WO 2015070715 A1 WO2015070715 A1 WO 2015070715A1
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layer
metal
film
metal oxide
thin film
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PCT/CN2014/090193
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English (en)
French (fr)
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徐苗
彭俊彪
罗东向
王磊
邹建华
陶洪
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广州新视界光电科技有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Definitions

  • the present invention relates to the field of semiconductor technology, and in particular, to a metal oxide thin film transistor and a method of fabricating the same.
  • This application is based on the Chinese invention patent application with the application number 2013105642043 and the application date being November 14, 2013.
  • TFT thin film transistor
  • MOTFT metal oxide TFT
  • the main structures used in MOTFT are a back channel etch structure and an etch barrier structure.
  • the back channel etch structure is to deposit a metal layer on the active layer after the active layer is formed, and is patterned as a source and drain electrode.
  • the etch barrier structure is formed by forming an etch barrier layer after the active layer is formed, and then depositing a metal layer thereon and patterning as a source and drain electrode.
  • the stability of the MOTFT of the etch barrier structure is relatively good, and the thin film transistor of the structure has been commercialized.
  • the process is complicated and the fabrication cost is high.
  • the fabrication process of the back channel etch structure is relatively simple, and is the same as the conventional amorphous silicon fabrication process, and the equipment investment and production cost are relatively low.
  • This structure is considered to be an inevitable development direction in which mass production of metal oxide thin film transistors is possible and can be widely used.
  • the problem of back channel damage occurs in either dry etching or wet etching: when dry etching is used, the metal oxide is susceptible to ion damage.
  • an organic conductive film is considered as a back channel etch protection layer.
  • an electrode structure such as a metal/etch barrier layer/metal oxide semiconductor, it is necessary to realize electrical conduction between the metal and the metal oxide semiconductor by conductivity of the organic conductive film. Ohmic contact, therefore, it is necessary to select a material having a certain conductivity in the material selection as a back channel etch protection layer.
  • the preparation method of the organic conductive film is vacuum hot steaming, spin coating or screen printing, which does not match the equipment of the existing manufacturers. In the preparation process, the manufacturer needs to additionally introduce relevant equipment, resulting in high preparation cost. . In addition, the portion of the organic conductive film that overlaps the back channel must be etched away, otherwise carriers will flow directly between the source and drain electrodes through the conductive film, causing the back channel to lose its effect, which means an additional need Etching process.
  • One of the objects of the present invention is to provide a method for preparing a metal oxide thin film transistor, which has the characteristics of simple manufacturing process, low cost, and high stability of the prepared metal oxide thin film transistor.
  • the present invention also provides a metal oxide thin film transistor prepared by the method.
  • a method for preparing a metal oxide thin film transistor includes the following steps in sequence:
  • PVD physical vapor deposition
  • a non-metal thin film is deposited by a physical vapor deposition method, and a carbon film or a silicon film is deposited by using a physical vapor deposition method.
  • the thickness of the back channel etch protection layer is set to be 0.1 to 30 nm.
  • the thickness of the back channel etch protection layer is set to be 0.5-20 nm.
  • the thickness of the back channel etch protection layer is set to 0.5 to 1 nm.
  • the thickness of the back channel etch protection layer is set to be 0.6 to 0.8 nm.
  • the substrate is provided as a glass substrate having a buffer layer or a flexible substrate having a water-oxygen barrier layer;
  • the flexible substrate is specifically provided as polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyimide (PI) or metal. Foil flexible substrate.
  • PEN polyethylene naphthalate
  • PET polyethylene terephthalate
  • PI polyimide
  • Foil flexible substrate is specifically provided as polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyimide (PI) or metal.
  • the metal used in the above step a for preparing and patterning the metal conductive layer on the substrate is aluminum, copper, molybdenum, titanium, silver, gold, tantalum, tungsten, chromium or aluminum alloy;
  • the metal conductive layer is a single-layer aluminum film, a copper film, a molybdenum film, a titanium film, a silver film, a gold film, a tantalum film, a tungsten film, a chromium film or an aluminum alloy film; or two of the above single-layer metal films. a film above the layer;
  • the thickness of the metal conductive layer is set to be 100 nm to 2000 nm;
  • the metal conductive layer acts as a metal oxide thin film transistor gate.
  • the thickness of the first insulating film in the above step b is 50 nm to 500 nm;
  • the first insulating film is a single layer film of silicon oxide, silicon nitride, aluminum oxide, tantalum pentoxide or yttria insulating film, or two or more films composed of any combination of the above materials;
  • the thickness of the active layer in the step c is 20 nm to 200 nm;
  • the metal used for depositing the metal layer in the above step e is aluminum, copper, molybdenum, titanium, or an alloy material mainly composed of the above metal element;
  • the metal layer is a single-layer aluminum film, a copper film, a molybdenum film, a titanium film or an alloy material film mainly composed of the above metal element, or a film of two or more layers composed of the above single-layer metal film;
  • the metal layer has a thickness of 100 nm to 2000 nm.
  • the passivation layer has a thickness of 50 nm to 2000 nm;
  • the passivation layer is a single-layer film of silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, polyimide, photoresist, styrene-butadiene or polymethyl methacrylate, or any of the above materials. Two or more layers of the film are combined.
  • the method for preparing a metal oxide thin film transistor of the present invention comprises the steps of: a. preparing and patterning a metal conductive layer as a gate on a substrate; b. depositing a first insulating film on the metal conductive layer as a gate a very insulating layer; c. depositing a metal oxide film on the gate insulating layer and patterning as an active layer; d. depositing a non-metal film on the active layer using a PVD method as a back channel etch protection a layer; a metal layer is deposited on the back channel etch protection layer and then only the metal layer is patterned as a source and drain electrode pattern; f. a second insulating film is deposited on the source and drain electrodes as passivation Floor.
  • the present invention is based on a back channel etch type metal oxide thin film transistor structure, and a non-metal film is deposited as a back channel etch protection layer using a PVD method.
  • a back channel etch protection layer of a non-metal film structure can greatly reduce damage to the back channel of the metal oxide thin film transistor during etching of the source drain electrode.
  • the PVD preparation method used is compatible with the existing thin film transistor production line, and only the metal layer needs to be patterned in the process of patterning the source and drain electrodes. Therefore, the method of the invention has simple preparation process and good compatibility, and the prepared metal oxide thin film transistor has high stability, simple process and low cost.
  • the metal oxide thin film transistor provided by the present invention is prepared by the above method.
  • the stability of the prepared metal oxide thin film transistor is greatly improved, meets the requirements for the commercialization of the metal oxide thin film transistor, and the preparation process is simple and the cost is low.
  • FIG. 1 is a schematic view of a deposited and patterned metal conductive layer as a gate electrode in accordance with an embodiment of the present invention
  • FIG. 2 is a schematic view showing deposition of a first insulating film on a metal conductive layer as a gate insulating layer according to an embodiment of the present invention
  • FIG. 3 is a schematic view of a deposited active layer in accordance with an embodiment of the present invention.
  • FIG. 4 is a schematic view showing a deposited non-metal film as a back channel etch protection layer according to an embodiment of the present invention
  • FIG. 5 is a schematic view showing deposition of a metal layer on a back channel etch protection layer according to an embodiment of the present invention
  • FIG. 6 is a schematic diagram of a patterned source and a drain electrode according to an embodiment of the present invention.
  • FIG. 7 is a schematic view of fabricating a passivation layer according to an embodiment of the present invention.
  • FIG. 8 is a schematic diagram of an imaged source and a drain electrode when a non-metal film is used as a back channel etch protection layer;
  • Figure 9 is a schematic illustration of a passivation layer made for the structure of Figure 8.
  • the metal layer is patterned into a non-metal film 08 which remains after the source and drain electrodes.
  • a method for preparing a metal oxide thin film transistor includes the following steps in sequence.
  • a metal conductive layer is prepared and patterned on the substrate as a gate.
  • the substrate in step a is provided as a glass substrate having a buffer layer or a flexible substrate having a water oxygen barrier layer.
  • the flexible substrate is specifically provided as polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyimide (PI) or metal. Foil flexible substrate.
  • PEN polyethylene naphthalate
  • PET polyethylene terephthalate
  • PI polyimide
  • Foil flexible substrate is specifically provided as polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyimide (PI) or metal.
  • the metal used in the step a to prepare and pattern the metal conductive layer on the substrate is aluminum, copper, molybdenum, titanium, silver, gold, tantalum, tungsten, chromium or aluminum.
  • the thickness of the metal conductive layer is set to be 100 nm to 2000 nm.
  • Metal conductive layer as metal oxide The gate of the thin film transistor may specifically be a single-layer aluminum film, a copper film, a molybdenum film, a titanium film, a silver film, a gold film, a tantalum film, a tungsten film, a chromium film or an aluminum alloy film; or may be composed of the above single-layer metal film. Two or more layers of film.
  • step b After the metal conductive layer is completed, the process proceeds to step b.
  • the thickness of the first insulating film in the step b is 50 nm to 500 nm.
  • the first insulating film is a single layer film of silicon oxide, silicon nitride, aluminum oxide, tantalum pentoxide or yttria insulating film, or a film of two or more layers composed of any combination of the above materials.
  • the active layer in step c has a thickness of 20 nm to 200 nm.
  • the non-metal film is specifically a silicon film or a carbon film.
  • the thickness of the back channel etch protection layer is set to 0.1 to 30 nm, preferably 0.5 to 20 nm, or 0.5 to 1 nm or 0.6 to 0.8 nm.
  • the non-metallic elemental film having extremely low conductivity and even no conductivity is used in the technical solution, it is difficult to conduct between the active layer and the source and drain electrodes in a normal state, so in the process of preparing the source and drain electrodes, As long as the metal layer as the source and drain electrodes is etched, it is not necessary to re-pair the non-metal elemental film. Etching is performed. This is in contrast to the use of an organic conductive film as an etch protection layer. When an organic conductive film is used as an etch protection layer, a portion of the organic conductive film is etched after the preparation of the organic conductive film. Remove the portion that overlaps the channel. If partial removal is not performed, electrons will pass directly from the source to the drain through the conductive film, causing channel failure, resulting in the entire oxide thin film transistor being discarded.
  • the metal used for depositing the metal layer in the step e is aluminum, copper, molybdenum, titanium, or an alloy material mainly composed of the above metal element.
  • the metal layer is a single-layer aluminum film, a copper film, a molybdenum film, a titanium film, an alloy material film mainly composed of the above metal element, or a film of two or more layers composed of the above single-layer metal film.
  • the thickness of the metal layer is from 100 nm to 2,000 nm.
  • the passivation layer has a thickness of 50 nm to 2000 nm.
  • the passivation layer is a single layer film of silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, polyimide, photoresist, styrene-butadiene or polymethyl methacrylate, or any combination of the above materials. Two or more layers of the film are formed.
  • the non-metal film is used as the back channel etching protection layer, and the film itself is more stable than the organic conductive film, and the non-metal film has better adhesion, and the prepared film is less prone to protrusion and splitting. It has a good improvement effect on the performance of the overall metal oxide thin film transistor.
  • the present invention is based on a back channel etch type metal oxide thin film transistor structure, and a non-metal film deposited by a physical vapor deposition method is introduced as a back channel etch protection layer.
  • the back channel etch protection layer not only greatly reduces damage to the back channel of the metal oxide thin film transistor during etching of the source and drain electrodes, but also is compatible with existing fabrication processes and can reduce the fabrication process steps. Therefore, the metal oxide thin film transistor prepared by the method of the invention has high stability, and the method of the invention is simple in process and low in cost.
  • the prepared metal oxide thin film transistor also has the characteristics of high stability, simple preparation process and low cost.
  • a method for preparing a metal oxide thin film transistor includes the following steps.
  • a three-layer metal film of Mo/Al/Mo is sequentially deposited as a metal conductive layer by a PVD (Physical Vapor Deposition) method on an alkali-free glass substrate 01 having a SiO 2 buffer layer of 200 nm thick. 25 nm / 100 nm / 25 nm, respectively.
  • the metal conductive layer is patterned as the gate 02 using a photolithography process.
  • the thickness of the metal conductive layer ranges from 100 nm to 2000 nm, and the specific size thereof can be flexibly set according to actual needs, and is not limited to the size of the embodiment.
  • the constituent material of the metal conductive layer is not limited to the case of the present embodiment.
  • a first insulating film 03 is deposited on the patterned metal conductive layer by a PECVD method, the first insulating film 03 is made of 300 nm of SiN x and 30 nm of SiO 2 . Laminated to form a gate insulating layer. It should be noted that the thickness of the first insulating film is in the range of 50 nm to 500 nm, and the specific size thereof can be flexibly set according to actual needs, and is not limited to the size of the embodiment, and the constituent material of the first insulating film is not limited to the embodiment. Case.
  • a 50 nm metal oxide IZO thin film (In, Zn atomic ratio of 1:1) was deposited as the active layer 04 by a PVD method, as shown in FIG.
  • the thickness of the active layer ranges from 20 nm to 200 nm, and the specific size thereof can be flexibly set according to actual needs, and is not limited to the size of the embodiment.
  • the constituent material of the active layer is not limited to the case of the present embodiment.
  • a 0.5 nm amorphous carbon elementary film back channel etch protection layer 05 was formed by physical vapor deposition.
  • a back channel etch protection layer 05 is formed, which can reduce damage to the back channel of the metal oxide thin film transistor during etching of the source and drain electrodes.
  • the thickness of the back channel etch protection layer is in the range of 0.1 nm to 30 nm, and the specific size thereof can be flexibly set according to actual needs, and is not limited to the size of the embodiment, and may be set to 0.5 to 20 nm, The range of 0.5 to 1 nm is preferable, and may be set to 0.6 to 0.8 nm as needed.
  • the non-metal film can effectively prevent damage to the back channel of the metal oxide thin film transistor during the etching source and the drain electrode, and improve the stability of the prepared device.
  • the present application breaks the conventional use of a non-metal film as an etch protection layer.
  • the principle is to use the tunneling effect of a non-metallic film.
  • quantum mechanics theory when the film is thin enough, there will be a certain amount. The phenomenon that electrons pass directly through the film from one side of the film to the other.
  • the metal oxide thin film transistor is applied with a certain voltage, so that the electrons can effectively flow to form a current.
  • the non-metal film does not conduct between the active layer and the source and drain electrodes, and is only turned on when in operation.
  • a Mo/Al/Mo laminated metal layer was prepared on the back channel etching protective layer by a PVD method, and the thickness was 25 nm/100 nm/25 nm, respectively.
  • 30% H 2 O 2 and 1% KOH as the wet etching solution only the metal layer is etched, and Mo/Al/Mo is patterned by this method to form the metal layer of the source and drain electrodes. ,As shown in Figure 6.
  • the non-metallic elemental film having extremely low conductivity and even no conductivity is used in the technical solution, it is difficult to conduct between the active layer and the source and drain electrodes in a normal state, so in the process of preparing the source and drain electrodes, As long as the metal layer as the source and drain electrodes is etched, it is not necessary to etch the non-metal elemental film. This is in contrast to the use of an organic conductive film as an etch protection layer.
  • an organic conductive film is used as an etch protection layer, a portion of the organic conductive film is etched after the preparation of the organic conductive film. The portion overlapping the channel is removed, as shown in Figs. If partial removal is not performed, electrons will pass directly from the source to the drain through the conductive film, causing channel failure, resulting in the entire oxide thin film transistor being discarded.
  • the preparation process using the amorphous carbon elemental film as the back channel etching protection layer can simplify the process.
  • the fabrication of the metal oxide thin film transistor is completed by depositing SiO 2 having a thickness of 300 nm as the passivation layer 07 by PECVD.
  • the structure of the metal oxide thin film transistor is a bottom gate and a back channel etch structure.
  • a back channel etching protection layer structure is formed.
  • the back channel etching protection layer can not only reduce the damage caused by the etching process of the etching source and the drain electrode on the back channel of the metal oxide thin film transistor, but also adopts the non-metal film as the back channel etching protection layer.
  • it can simplify the preparation process and has the characteristics of low cost. It has been proved by a large number of practices that the metal oxide thin film transistor prepared by the preparation method of the invention has high stability, simple preparation process and low cost, and can realize high-definition and low cost of the metal oxide thin film transistor driving back plate. Production.
  • the non-metal film is used as the back channel etching protection layer, and the film itself is more stable than the organic conductive film, and the non-metal film has better adhesion, and the prepared film is less prone to protrusion and splitting. It has a good improvement effect on the performance of the overall metal oxide thin film transistor.
  • the metal oxide thin film transistor produced by the process can be used in the field of liquid crystal display (LCD) and active matrix/Organic Light Emitting Diode (AMOLED).
  • LCD liquid crystal display
  • AMOLED active matrix/Organic Light Emitting Diode
  • the size and the ratio of the ratios involved in the present embodiment do not limit the preparation process of the metal oxide thin film transistor of the present invention. In the actual preparation process, the user can flexibly adjust according to specific needs.
  • a method for preparing a metal oxide thin film transistor includes the following steps.
  • a Cu film having a thickness of 500 nm was deposited as a metal conductive layer on a substrate 01 of a flexible PET film having a 50 nm Al 2 O 3 water-oxygen barrier layer using a PVD (Physical Vapor Deposition) method.
  • the metal conductive layer is patterned as the gate 02 using a photolithography process.
  • the thickness of the metal conductive layer ranges from 100 nm to 2000 nm, and the specific size thereof can be flexibly set according to actual needs, and is not limited to the size of the embodiment.
  • the constituent material of the metal conductive layer is not limited to the case of the present embodiment.
  • a first insulating film 03 is deposited on the patterned metal conductive layer by a PECVD method, which is composed of 200 nm of aluminum oxide and 100 nm of cerium oxide. Laminated to form a gate insulating layer. It should be noted that the thickness of the first insulating film is in the range of 50 nm to 500 nm, and the specific size thereof can be flexibly set according to actual needs, and is not limited to the size of the embodiment, and the constituent material of the first insulating film is not limited to the embodiment. Case.
  • a 50 nm metal oxide IGZO thin film (In, Ga, and Zn atomic ratio of 1:1:1) was deposited as the active layer 04 by a PVD method, as shown in FIG.
  • the thickness of the active layer ranges from 20 nm to 200 nm, and the specific size thereof can be flexibly set according to actual needs, and is not limited to the size of the embodiment.
  • the constituent material of the active layer is not limited to the case of the present embodiment.
  • a 30 nm amorphous silicon elemental film was deposited as a back channel etch protection layer 05 using a physical vapor deposition method.
  • a back channel etch protection layer 05 is formed, which can reduce damage to the back channel of the metal oxide thin film transistor by etching source and drain electrodes.
  • the thickness of the back channel etch protection layer ranges from 0.1 nm to 30 nm, and the specific size thereof can be flexibly set according to actual needs, and is not limited to the size of the embodiment.
  • the constituent material of the back channel etching protective layer is not limited to the case of the present embodiment.
  • a Cu metal layer was formed on the back channel etching protective layer by a PVD method to a thickness of 500 nm.
  • a mixed solution of H 2 O 2 and H 2 SO 4 as a wet etching solution the Cu metal layer is etched, and the Cu film is patterned by this method to form a metal layer 06 of source and drain electrodes, as shown in FIG. 6 . Shown.
  • a polyimide having a thickness of 800 nm was deposited as a passivation layer 07 by PECVD to complete fabrication of a metal oxide thin film transistor.
  • the non-metal film can effectively prevent the damage caused by the etching source and the drain electrode on the back channel of the metal oxide thin film transistor, and improve the stability of the prepared device.
  • the present application breaks the conventional use of a non-metal film as an etch protection layer.
  • the principle is to utilize the tunneling effect of a non-metallic film.
  • quantum mechanics theory when the film is sufficiently thin, there is a certain amount of electrons directly passing through the film from one side of the film to the other side.
  • the metal oxide thin film transistor is applied with a certain voltage, so that the effective flow of electrons can be realized to form a current.
  • the non-metal film does not conduct between the active layer and the source and drain electrodes, and is only turned on when in operation.
  • the technical solution adopts a non-metallic elemental film which is extremely weak in conductivity and does not even have conductivity, In the normal state, it is difficult to conduct between the active layer and the source and drain electrodes. Therefore, in the process of preparing the source and drain electrodes, the metal layer as the source and drain electrodes may be etched, and no re-pairing is required.
  • the metal elemental film is etched. This is in contrast to the use of an organic conductive film as an etch protection layer.
  • an organic conductive film is used as an etch protection layer, a portion of the organic conductive film is etched after the preparation of the organic conductive film. The portion overlapping the channel is removed, as shown in Figs. If partial removal is not performed, electrons will pass directly from the source to the drain through the conductive film, causing channel failure, resulting in the entire oxide thin film transistor being discarded.
  • the preparation process using the amorphous silicon elemental film as the back channel etching protection layer can simplify the process.
  • the non-metal film is used as the back channel etching protection layer, and the film itself is more stable than the organic conductive film, and the non-metal film has better adhesion, and the prepared film is less prone to protrusion and splitting. It has a good improvement effect on the performance of the overall metal oxide thin film transistor.
  • the structure of the metal oxide thin film transistor is a bottom gate and a back channel etch structure.
  • a back channel etching protection layer structure is formed.
  • the back channel etching protection layer can not only reduce the damage caused by the etching process of the etching source and the drain electrode on the back channel of the metal oxide thin film transistor, but also adopts the non-metal film as the back channel etching protection layer.
  • it can simplify the preparation process and has the characteristics of low cost. It has been proved by a large number of practices that the metal oxide thin film transistor prepared by the preparation method of the invention has high stability, simple preparation process and low cost, and can realize high-definition and low cost of the metal oxide thin film transistor driving back plate. Production.
  • the metal oxide thin film transistor produced by the process can be used in the field of liquid crystal display (LCD) and active matrix/Organic Light Emitting Diode (AMOLED).
  • LCD liquid crystal display
  • AMOLED active matrix/Organic Light Emitting Diode
  • the size and the ratio of the ratios involved in the present embodiment do not limit the preparation process of the metal oxide thin film transistor of the present invention. In the actual preparation process, the user can flexibly adjust according to specific needs.
  • a method for preparing a metal oxide thin film transistor includes the following steps.
  • a 200 nm thick ITO film was deposited as a metal conductive layer using a PVD (Physical Vapor Deposition) method.
  • the metal conductive layer is patterned as the gate 02 using a photolithography process.
  • the thickness of the metal conductive layer ranges from 100 nm to 2000 nm, and the specific size thereof can be flexibly set according to actual needs, and is not limited to the size of the embodiment.
  • the constituent material of the metal conductive layer is not limited to the case of the present embodiment.
  • a first insulating film 03 is deposited on the patterned metal conductive layer by a PECVD method (Plasma Enhanced Chemical Vapor Deposition), and the first insulating film 03 is made of 100 nm of silicon nitride and 90 nm of five. Bismuth oxide and 20 nm of silicon oxide are laminated to form a gate insulating layer. It should be noted that the thickness of the first insulating film is in the range of 50 nm to 500 nm, and the specific size thereof can be flexibly set according to actual needs, and is not limited to the size of the embodiment, and the constituent material of the first insulating film is not limited to the embodiment. Case.
  • a 50 nm metal oxide IZO thin film (In, Zn atomic ratio of 1:1) was deposited as the active layer 04 by a PVD method, as shown in FIG.
  • the thickness of the active layer ranges from 20 nm to 200 nm, and the specific size thereof can be flexibly set according to actual needs, and is not limited to the size of the embodiment.
  • the constituent material of the active layer is not limited to the case of the present embodiment.
  • a back channel etch protection layer 05 is formed, which can reduce the damage caused by the etching source and drain electrodes on the back channel of the metal oxide thin film transistor.
  • the thickness of the back channel etch protection layer is in the range of 0.1 nm to 30 nm, particularly preferably 0.5 nm to 1.0 nm, and the specific size thereof can be flexibly set according to actual needs, and is not limited to the size of the embodiment. .
  • the constituent material of the back channel etching protective layer is not limited to the case of the present embodiment.
  • a Mo single-layer metal layer was formed on the back channel etching protective layer using a PVD method to a thickness of 200 nm.
  • Mo was dry-etched using a reactive ion etching apparatus using SF 6 /O 2 having a flow ratio of 50 sccm:10 sccm as a reaction gas to etch Mo in the metal layer.
  • Mo is patterned to form metal layers 06 of source and drain electrodes, as shown in FIG.
  • the fabrication of the metal oxide thin film transistor is completed by depositing SiO 2 having a thickness of 300 nm as the passivation layer 07 by PECVD.
  • the structure of the metal oxide thin film transistor is a bottom gate and a back channel etch structure.
  • a back channel etching protection layer structure is formed.
  • the back channel etching protection layer can not only reduce the damage caused by the etching process of the etching source and the drain electrode on the back channel of the metal oxide thin film transistor, but also adopts the non-metal film as the back channel etching protection layer.
  • it can simplify the preparation process and has the characteristics of low cost. It has been proved by a large number of practices that the metal oxide thin film transistor prepared by the preparation method of the invention has high stability, simple preparation process and low cost, and can realize high-definition and low cost of the metal oxide thin film transistor driving back plate. Production.
  • the metal oxide thin film transistor produced by the process can be used in the field of liquid crystal display (LCD) and active matrix/Organic Light Emitting Diode (AMOLED).
  • LCD liquid crystal display
  • AMOLED active matrix/Organic Light Emitting Diode
  • the size and the ratio of the ratios involved in the present embodiment do not limit the preparation process of the metal oxide thin film transistor of the present invention. In the actual preparation process, the user can flexibly adjust according to specific needs.
  • the other processes are the same as those of any of the first to fourth embodiments, except that in the present embodiment, the thickness of the non-metal thin film as the etching protection layer is 1 nm.
  • the thickness of the non-metal film is not limited to the thickness of the embodiment, and can be flexibly selected in the range of 0.1-30 nm, such as 0.5 nm, 0.6 nm, 0.8 nm, 5 nm, 8 nm, 10 nm, 11 nm, 20 nm. , 23nm, 26nm, etc., only need to adjust the working voltage.
  • a metal oxide thin film transistor is prepared by any one of the above embodiments 1 to 5.
  • the metal oxide thin film transistor of the invention has high stability, simple preparation process and low cost, and can realize high-definition and low-cost fabrication of the metal oxide thin film transistor driving back plate.
  • the metal oxide thin film transistor produced by the process can be used in the field of liquid crystal display (LCD) and active matrix/Organic Light Emitting Diode (AMOLED).
  • LCD liquid crystal display
  • AMOLED active matrix/Organic Light Emitting Diode

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Abstract

一种金属氧化物薄膜晶体管及其制备方法，制备方法依次包括：a.在衬底上制备并图形化金属导电层作为栅极；b.在所述金属导电层上沉积第一绝缘薄膜作为栅极绝缘层；c.在所述栅极绝缘层上沉积金属氧化物薄膜并图形化作为有源层；d.在所述有源层上使用物理气相沉积方法沉积非金属薄膜作为背沟道刻蚀保护层；e.在所述背沟道刻蚀保护层上沉积金属层然后对金属层图形化作为源、漏电极图形；f.在所述源、漏电极上沉积第二绝缘薄膜作为钝化层。制备工艺简单，所制备的金属氧化物薄膜晶体管稳定性好、尺寸小，可实现金属氧化物薄膜晶体管驱动背板高精细化、低成本制作。

Description

金属氧化物薄膜晶体管及其制备方法 技术领域
本发明涉及半导体技术领域，尤其涉及一种金属氧化物薄膜晶体管及其制备方法。本申请是以申请号2013105642043、申请日为2013年11月14日的中国发明专利申请为基础的。
背景技术
近年来，新型平板显示(FPD)产业发展日新月异。消费者对于大尺寸、高分辨率平板显示的高需求量刺激着整个产业不断进行显示技术提升。而作为FPD产业核心技术的薄膜晶体管(TFT)背板技术，也在经历着深刻的变革。金属氧化物TFT(MOTFT)不仅具有较高的迁移率(在5～50cm2/(V·s)左右)，而且制作工艺简单，制造成本较低，还具有优异的大面积均匀性。因此MOTFT技术自诞生以来便备受业界瞩目。
目前MOTFT主要使用的结构有背沟道刻蚀结构和刻蚀阻挡层结构。背沟道刻蚀结构是在生成有源层之后，在有源层上沉积金属层，并且图形化作为源、漏电极。而刻蚀阻挡层结构是在有源层生成之后，先制作一层刻蚀阻挡层，再在之上沉积金属层并且图形化作为源、漏电极。
刻蚀阻挡层结构的MOTFT的稳定性比较好，目前该结构薄膜晶体管已商业化。但是因为其需要增加额外的光刻掩膜版制作刻蚀阻挡层，导致工艺复杂，制作成本高。
背沟道刻蚀结构制作工艺较为简单，并且与传统非晶硅制作工艺相同，设备投资和生产成本都较低廉。该结构被认为是，金属氧化物薄膜晶体管实现大规模量产和能够广泛使用的必然发展方向。但是在有源层上刻蚀源、漏电极时，无论是采用干法刻蚀还是湿法刻蚀都会出现背沟道损伤的问题：采用干法刻蚀时，金属氧化物容易受到离子损伤，导致暴露的沟道表面有载流子陷阱生成以 及氧空位浓度增加，使得器件稳定性较差；采用湿法刻蚀时，因为有源层对大部分酸性刻蚀液都比较敏感，很容易在刻蚀过程中被腐蚀，从而也将极大地影响器件性能。该结构的MOTFT目前还无法实现产品化。
现有技术中，针对背沟道刻蚀结构的稳定性问题，有采用通过在有源层上增加背沟道刻蚀保护层以防止对有源层进行保护的先例。通常考虑以有机导电薄膜作为背沟道刻蚀保护层，在金属/刻蚀阻挡层/金属氧化物半导体这样的电极结构中，需要通过有机导电薄膜的导电性实现金属与金属氧化物半导体之间的欧姆接触，因此在作为背沟道刻蚀保护层的材料选择中需要选择具有一定导电性能的材料。
但是有机导电薄膜的制备方法为真空热蒸法、旋涂法或者丝网印刷法，其于现有的厂家的设备不相配，在制备过程中，厂家需要额外引入相关设备，导致制备成本较高。此外，有机导电薄膜与背沟道重叠的部分必须被刻蚀掉，否则载流子将直接通过导电薄膜在源漏电极之间流动，从而使得背沟道失去作用，这意味着需要额外的一次刻蚀工艺。
因此，针对现有技术不足，提供一种稳定性好、制备工艺简单、成本低廉的金属氧化物薄膜晶体管及其制备工艺以克服现有技术不足甚为必要。
发明内容
本发明的目的之一是提供了一种金属氧化物薄膜晶体管的制备方法，该制备方法具有制造工艺简单、成本低廉且所制备的金属氧化物薄膜晶体管稳定性高的特点。本发明同时提供一种通过该方法制备的金属氧化物薄膜晶体管。
本发明的上述目的通过如下技术手段实现。
一种金属氧化物薄膜晶体管的制备方法，依次包括如下步骤：
a.在衬底上制备并图形化金属导电层作为栅极；
b.在所述金属导电层上沉积第一绝缘薄膜作为栅极绝缘层；
c.在所述栅极绝缘层上沉积金属氧化物薄膜并图形化作为有源层；
d.在所述有源层上使用物理气相沉积(Physical Vapor Deposition，PVD)方法沉积非金属薄膜作为背沟道刻蚀保护层；
e.在所述背沟道刻蚀保护层上沉积金属层然后对所述金属层进行图形化作为源、漏电极图形；
f.在所述源、漏电极上沉积第二绝缘薄膜作为钝化层。
上述步骤d中使用物理气相沉积方法沉积非金属薄膜，具体使用物理气相沉积方法沉积碳膜或者硅膜。
上述背沟道刻蚀保护层的厚度设置为0.1～30nm。
优选的，上述背沟道刻蚀保护层的厚度设置为0.5～20nm。
优选的，上述背沟道刻蚀保护层的厚度设置为0.5～1nm。
优选的，上述背沟道刻蚀保护层的厚度设置为0.6～0.8nm。
优选的，上述步骤a中衬底设置为具有缓冲层的玻璃衬底或者具有水氧阻隔层的柔性衬底；
当所述衬底为柔性衬底时，柔性衬底具体设置为聚萘二甲酸乙二醇酯(PEN)、聚对苯二甲酸乙二酯(PET)、聚酰亚胺(PI)或者金属箔柔性衬底。
优选的，上述步骤a中在衬底上制备并图形化金属导电层所使用的金属为铝、铜、钼、钛、银、金、钽、钨、铬单质或铝合金；
所述金属导电层为单层铝薄膜、铜薄膜、钼薄膜、钛薄膜、银薄膜、金薄膜、钽薄膜、钨薄膜、铬薄膜或铝合金薄膜；或者是由以上单层金属薄膜构成的两层以上的薄膜；
所述金属导电层的厚度设置为100nm至2000nm；
所述金属导电层作为金属氧化物薄膜晶体管栅极。
优选的，上述步骤b中的所述第一绝缘薄膜的厚度为50nm至500nm；
所述第一绝缘薄膜为氧化硅、氮化硅、氧化铝、五氧化二钽或氧化镱绝缘薄膜的单层薄膜，或是由以上材料的任意组合构成的两层以上的薄膜；
所述步骤c中的所述有源层厚度为20nm至200nm；
构成所述有源层的半导体材料是金属氧化物(In2O3)x(MO)y(ZnO)z，其中0≤x≤1，0≤y≤1，0≤z≤1，且x+y+z＝1，M为镓、锡、硅、铝、镁、钽、铪、镱、镍、锆或镧系稀土元素中的一种或两种以上的任意组合。
优选的，上述步骤e中沉积所述金属层所使用的金属为铝、铜、钼、钛单质，或由以上金属单质作为主体的合金材料；
所述金属层为单层铝薄膜、铜薄膜、钼薄膜、钛薄膜或由以上金属单质作为主体的合金材料膜，或者由以上单层金属薄膜构成的两层以上的薄膜；
所述金属层的厚度为100nm～2000nm。
优选的，上述钝化层的厚度为50nm～2000nm；
上述钝化层为氧化硅、氮化硅、氧化铝、氧化镱、聚酰亚胺、光刻胶、苯丙环丁烯或聚甲基丙烯酸甲酯单层薄膜，或者是由以上材料的任意组合构成的两层以上的薄膜。
本发明的金属氧化物薄膜晶体管的制备方法，依次包括如下步骤：a.在衬底上制备并图形化金属导电层作为栅极；b.在所述金属导电层上沉积第一绝缘薄膜作为栅极绝缘层；c.在所述栅极绝缘层上沉积金属氧化物薄膜并图形化作为有源层；d.在所述有源层上使用PVD方法沉积非金属薄膜作为背沟道刻蚀保护层；e.在所述背沟道刻蚀保护层上沉积金属层然后仅对金属层图形化作为源、漏电极图形；f.在所述源、漏电极上沉积第二绝缘薄膜作为钝化层。本发明基于背沟道刻蚀型金属氧化物薄膜晶体管结构，使用PVD方法沉积非金属薄膜作为背沟道刻蚀保护层。使用非金属薄膜结构的背沟道刻蚀保护层能够大大减少在刻蚀源漏电极的过程中对金属氧化物薄膜晶体管背沟道的损伤。并且所使用的PVD制备方法与现有薄膜晶体管生产线相兼容，且在图形化形成源、漏电极的过程中仅需对金属层进行图形化。故，本发明的方法制备工艺简单、兼容性好，所制备的金属氧化物薄膜晶体管的稳定性高，而且工艺简单，成本低廉。
本发明提供的金属氧化物薄膜晶体管，采用上述的方法制备而成。所制备的金属氧化物薄膜晶体管的稳定性大大提高，满足了金属氧化物薄膜晶体管产品化的要求，而且制备工艺简单、成本低廉。
附图说明
利用附图对本发明作进一步的说明，但附图中的内容不构成对本发明的任何限制。
图1是本发明实施例的沉积并图形化金属导电层作为栅极的示意图
图2是本发明实施例的在金属导电层上沉积第一绝缘膜作为栅极绝缘层的示意图；
图3是本发明实施例的沉积有源层的示意图；
图4是本发明实施例的沉积非金属薄膜作为背沟道刻蚀保护层的示意图；
图5是本发明实施例的在背沟道刻蚀保护层上沉积金属层的示意图；
图6是本发明实施例的图形化源、漏电极的示意图；
图7是本发明实施例的制作钝化层的示意图；
图8是采用非金属薄膜作为背沟道刻蚀保护层时图像化源、漏电极的示意图；
图9是针对图8的结构制作了钝化层的示意图。
在图1至图9中，包括：
衬底01、栅极02、第一绝缘薄膜03、有源层04、背沟道刻蚀保护层05、
图形化成源、漏电极的金属层06、钝化层07、
对金属层图形化成源、漏电极后仍然保留的非金属薄膜08。
具体实施方式
结合以下实施例对本发明作进一步描述。
实施例1。
一种金属氧化物薄膜晶体管的制备方法，依次包括如下步骤。
a.在衬底上制备并图形化金属导电层作为栅极。
具体的，步骤a中衬底设置为具有缓冲层的玻璃衬底或者具有水氧阻隔层的柔性衬底。
当所述衬底为柔性衬底时，柔性衬底具体设置为聚萘二甲酸乙二醇酯(PEN)、聚对苯二甲酸乙二酯(PET)、聚酰亚胺(PI)或者金属箔柔性衬底。
步骤a中在衬底上制备并图形化金属导电层所使用的金属为铝、铜、钼、钛、银、金、钽、钨、铬单质或铝合金。
金属导电层的厚度设置为100nm至2000nm。金属导电层作为金属氧化物 薄膜晶体管栅极，具体可为单层铝薄膜、铜薄膜、钼薄膜、钛薄膜、银薄膜、金薄膜、钽薄膜、钨薄膜、铬薄膜或铝合金薄膜；或者是由以上单层金属薄膜构成的两层以上的薄膜。
完成金属导电层制作后，进入步骤b。
b.在金属导电层上沉积第一绝缘薄膜作为栅极绝缘层。
具体的，步骤b中的第一绝缘薄膜的厚度为50nm至500nm。
第一绝缘薄膜为氧化硅、氮化硅、氧化铝、五氧化二钽或氧化镱绝缘薄膜的单层薄膜，或是由以上材料的任意组合构成的两层以上的薄膜。
c.在栅极绝缘层上沉积金属氧化物薄膜并图形化作为有源层。
具体的，步骤c中的有源层厚度为20nm至200nm。构成有源层的半导体材料是金属氧化物(In2O3)x(MO)y(ZnO)z，其中0≤x≤1，0≤y≤1，0≤z≤1，且x+y+z＝1，M为镓、锡、硅、铝、镁、钽、铪、镱、镍、锆或镧系稀土元素中的一种或两种以上的任意组合。
d.在有源层上使用物理气相沉积方法沉积非金属薄膜作为刻蚀保护层。
非金属薄膜具体是硅薄膜、碳薄膜。背沟道刻蚀保护层的厚度设置为0.1～30nm，优选设置为0.5～20nm，也可设置为0.5～1nm或者设置为0.6～0.8nm。
作为本领域公知常识，通常需要采用具有导电功能的薄膜使得有源层与源、漏电极之间进行欧姆接触，由于有机薄膜的导电性，故可被作为背沟道刻蚀保护层。然而，使用物理气相沉积方法沉积非金属薄膜通常导电性不良。本申请打破常规，尝试采用物理气相沉积方法制备的非金属薄膜作为刻蚀保护层。利用非金属薄膜的隧穿效应，实现在工作条件下有源层与源、漏电极之间的导通，而非工作状态下有源层与源、漏电极之间呈非导通状态。
e.在背沟道刻蚀保护层上沉积金属层然后对金属层图形化作为源、漏电极图形。
由于本技术方案中采用导电性极弱，甚至不具备导电性的非金属单质薄膜，在常态下有源层与源、漏电极之间难以导通，因此在制备源、漏电极的过程中，只要对作为源、漏电极的金属层进行刻蚀即可，不需要对再对非金属单质薄膜 进行刻蚀。这与采用有机导电薄膜作为刻蚀保护层的方式截然不同，由于采用有机导电薄膜作为刻蚀保护层时，有机导电薄膜制备完成后还需再设置一道工序对部分有机导电薄膜进行刻蚀，以去除和沟道重叠的部分。如果不进行部分去除，电子将直接通过导电薄膜从源极到达漏极，从而导致沟道失效，导致整个氧化物薄膜晶体管作废。
因此，采用非金属薄膜作为背沟道刻蚀保护层具有制备工序简单的特点。
具体的，步骤e中沉积金属层所使用的金属为铝、铜、钼、钛单质，或由以上金属单质作为主体的合金材料。金属层为单层铝薄膜、铜薄膜、钼薄膜、钛薄膜或由以上金属单质作为主体的合金材料膜，或者由以上单层金属薄膜构成的两层以上的薄膜。金属层的厚度为100nm～2000nm。最后，进入步骤f。
f.在源、漏电极上沉积第二绝缘薄膜作为钝化层。
钝化层的厚度为50nm～2000nm。钝化层为氧化硅、氮化硅、氧化铝、氧化镱、聚酰亚胺、光刻胶、苯丙环丁烯或聚甲基丙烯酸甲酯单层薄膜，或者是由以上材料的任意组合构成的两层以上的薄膜。
实践发现，采用非金属薄膜作为背沟道刻蚀保护层，其薄膜本身较有机导电薄膜稳定，而且非金属薄膜的粘附性更好，所制备的薄膜不易出现凸起、分裂的等状况，对于整体金属氧化物薄膜晶体管的性能有良好的改善作用。
本发明基于背沟道刻蚀型金属氧化物薄膜晶体管结构，引入了使用物理气相沉积方法沉积的非金属薄膜作为背沟道刻蚀保护层。背沟道刻蚀保护层不仅能够大大减少在刻蚀源、漏电极的过程中对金属氧化物薄膜晶体管背沟道的损伤，而且与现有制备工艺相容，且能够减少制备工艺步骤。故，本发明的方法所制备的金属氧化物薄膜晶体管的稳定性高，而且本发明的方法工艺简单、成本低廉。所制备的金属氧化物薄膜晶体管也具有稳定性高，制备工艺简单、成本低廉的特点。
实施例2。
一种金属氧化物薄膜晶体管的制备方法，包括如下工序。
如图1所示，在带有200nm厚的SiO2缓冲层的无碱玻璃衬底01上，使用PVD(Physical Vapor Deposition)法依次沉积Mo/Al/Mo三层金属薄膜作为金属导电层，厚度分别为25nm/100nm/25nm。使用光刻工艺将金属导电层图形化作为栅极02。
需要说明的是，金属导电层的厚度范围在100nm至2000nm范围内,其具体尺寸可以根据实际需要灵活设置，不限于本实施例的尺寸。金属导电层的构成材料也不限于本实施例的情况。
接着，如图2所示，在已图形化的金属导电层上，使用PECVD法(Plasma Enhanced Chemical Vapor Deposition)沉积第一绝缘膜03，第一绝缘膜03由300nm的SiNx和30nm的SiO2叠层而成作为栅极绝缘层。需要说明的是,第一绝缘膜的厚度范围在50nm至500nm范围内,其具体尺寸可以根据实际需要灵活设置,不限于本实施例的尺寸，第一绝缘膜的构成材料也不限于本实施例的情况。
接着，使用PVD法沉积50nm金属氧化物IZO薄膜(In、Zn原子比为1:1)作为有源层04，如图3所示。
需要说明的是，有源层的厚度范围在20nm至200nm范围内，其具体尺寸可以根据实际需要灵活设置，不限于本实施例的尺寸。有源层的构成材料也不限于本实施例的情况。
如图4所示，使用物理气相沉积法制作0.5nm的无定型碳单质薄膜背沟道刻蚀保护层05。此处，制作背沟道刻蚀保护层05，该背沟道刻蚀保护层05能够降低刻蚀源、漏电极过程中对金属氧化物薄膜晶体管背沟道造成的损伤。
需要说明的是,背沟道刻蚀保护层的厚度范围在0.1nm至30nm范围内，其具体尺寸可以根据实际需要灵活设置，不限于本实施例的尺寸，如可以设置为0.5～20nm，以0.5～1nm范围较佳，也可根据需要设置为0.6～0.8nm。
非金属薄膜作为背沟道刻蚀保护层，可以有效防止刻蚀源、漏电极过程中对金属氧化物薄膜晶体管背沟道造成的损伤，提高所制备的器件的稳定性。
本申请打破常规采用非金属薄膜作为刻蚀保护层。其原理是利用非金属薄膜的隧穿效应，根据量子力学理论，当薄膜足够薄的时候，会存在一定数量的 电子直接穿过薄膜从薄膜的一侧达到另一侧的现象。为了有效实现电子从“源极→有源层沟道→漏极”方向的流动，在工作状态下，金属氧化物薄膜晶体管会被施加一定的电压，这样，就可以使电子有效流动形成电流。在非工作状态下，非金属薄膜使得有源层与源、漏电极之间并不导通，而只有工作状态下时才导通。
如图5所示，使用PVD法在背沟道刻蚀保护层上制备Mo/Al/Mo叠层金属层，厚度分别为25nm/100nm/25nm。使用30％的H2O2和1％的KOH作为湿法刻蚀药液，仅仅对此金属层进行刻蚀，使用该方法将Mo/Al/Mo图形化形成源、漏电极的金属层06，如图6所示。
由于本技术方案中采用导电性极弱，甚至不具备导电性的非金属单质薄膜，在常态下有源层与源、漏电极之间难以导通，因此在制备源、漏电极的过程中，只要对作为源、漏电极的金属层进行刻蚀即可，不需要对再对非金属单质薄膜进行刻蚀。这与采用有机导电薄膜作为刻蚀保护层的方式截然不同，由于采用有机导电薄膜作为刻蚀保护层时，有机导电薄膜制备完成后还需再设置一道工序对部分有机导电薄膜进行刻蚀，以去除和沟道重叠的部分，如图8、9所示。如果不进行部分去除，电子将直接通过导电薄膜从源极到达漏极，从而导致沟道失效，导致整个氧化物薄膜晶体管作废。
因此，采用无定型碳单质薄膜作为背沟道刻蚀保护层的制备工艺能够简化工序。
最后，如图7所示，使用PECVD沉积厚度为300nm的SiO2作为钝化层07，完成金属氧化物薄膜晶体管的制作。
本发明的制备方法，金属氧化物薄膜晶体管的结构为底栅、背沟道刻蚀结构。在背沟道刻蚀制作源、漏电极的过程中，设置了制作背沟道刻蚀保护层结构。该背沟道刻蚀保护层不仅能够降低刻蚀源、漏电极刻蚀的过程对金属氧化物薄膜晶体管背沟道造成的损伤，而且采用非金属薄膜作为背沟道刻蚀保护层其制备工艺与现有中的设备相容，能够简化制备工序，具有成本低廉的特点。 通过大量实践证明，本发明的制备方法所制备的金属氧化物薄膜晶体管的稳定性高，而且具有制备工艺简单，成本低廉等特点，可实现金属氧化物薄膜晶体管驱动背板高精细化、低成本制作。
实践发现，采用非金属薄膜作为背沟道刻蚀保护层，其薄膜本身较有机导电薄膜稳定，而且非金属薄膜的粘附性更好，所制备的薄膜不易出现凸起、分裂的等状况，对于整体金属氧化物薄膜晶体管的性能有良好的改善作用。
该工艺制作的金属氧化物薄膜晶体管，可以用于液晶显示器LCD(Liquid Crystal Display)以及主动矩阵有机发光二极体面板AMOLED(Active Matrix/Organic Light Emitting Diode)领域。
需要说明的是，本实施例中涉及的尺寸、配比比例并不限制本发明金属氧化物薄膜晶体管的制备工艺，在实际制备过程中，使用者可以根据具体需要灵活调整。
实施例3。
一种金属氧化物薄膜晶体管的制备方法，包括如下工序。
如图1所示，在带有50nm的Al2O3水氧阻隔层的柔性PET薄膜的衬底01上，使用PVD(Physical Vapor Deposition)法沉积厚度为500nm的Cu膜作为金属导电层。使用光刻工艺将金属导电层图形化作为栅极02。
需要说明的是，金属导电层的厚度范围在100nm至2000nm范围内,其具体尺寸可以根据实际需要灵活设置，不限于本实施例的尺寸。金属导电层的构成材料也不限于本实施例的情况。
接着，如图2所示，在已图形化的金属导电层上，使用PECVD法(Plasma Enhanced Chemical Vapor Deposition)沉积第一绝缘膜03，第一绝缘膜03由200nm的氧化铝和100nm的氧化镱叠层而成作为栅极绝缘层。需要说明的是,第一绝缘膜的厚度范围在50nm至500nm范围内，其具体尺寸可以根据实际需要灵活设置,不限于本实施例的尺寸，第一绝缘膜的构成材料也不限于本实施例的情况。
接着，使用PVD法沉积50nm金属氧化物IGZO薄膜(In、Ga、Zn原子比为1:1:1)作为有源层04，如图3所示。
需要说明的是，有源层的厚度范围在20nm至200nm范围内，其具体尺寸可以根据实际需要灵活设置，不限于本实施例的尺寸。有源层的构成材料也不限于本实施例的情况。
如图4所示，使用物理气相沉积方法沉积30nm的无定型硅单质薄膜作为背沟道刻蚀保护层05。此处，制作背沟道刻蚀保护层05，该防护层能够减少刻蚀源、漏电极过程对金属氧化物薄膜晶体管背沟道造成的损伤。
需要说明的是,背沟道刻蚀保护层的厚度范围在0.1nm至30nm范围内，其具体尺寸可以根据实际需要灵活设置,不限于本实施例的尺寸。背沟道刻蚀保护层的构成材料也不限于本实施例的情况。
如图5所示，使用PVD法在背沟道刻蚀保护层上制备Cu金属层，厚度分别为500nm。使用H2O2和H2SO4的混合溶液作为湿法刻蚀药液，对Cu金属层进行刻蚀，使用该方法将Cu膜图形化形成源、漏电极的金属层06，如图6所示。
最后，如图7所示，使用PECVD沉积厚度为800nm的聚酰亚胺作为钝化层07，完成金属氧化物薄膜晶体管的制作。
非金属薄膜作为背沟道刻蚀保护层，可以有效防止刻蚀源、漏电极过程对金属氧化物薄膜晶体管背沟道造成的损伤，提高所制备的器件的稳定性。
本申请打破常规采用非金属薄膜作为刻蚀保护层。其原理是利用非金属薄膜的隧穿效应，根据量子力学理论，当薄膜足够薄的时候，会存在一定数量的电子直接穿过薄膜从薄膜的一侧达到另一侧。为了有效实现电子从“源极→有源层沟道→漏极”方向的流动，在工作状态下，金属氧化物薄膜晶体管会被施加一定的电压，这样，就可以实现电子的有效流动形成电流。在非工作状态下，非金属薄膜使得有源层与源、漏电极之间并不导通，而只有工作状态下时才导通。
由于本技术方案中采用导电性极弱，甚至不具备导电性的非金属单质薄膜， 在常态下有源层与源、漏电极之间难以导通，因此在制备源、漏电极的过程中，只要对作为源、漏电极的金属层进行刻蚀即可，不需要对再对非金属单质薄膜进行刻蚀。这与采用有机导电薄膜作为刻蚀保护层的方式截然不同，由于采用有机导电薄膜作为刻蚀保护层时，有机导电薄膜制备完成后还需再设置一道工序对部分有机导电薄膜进行刻蚀，以去除和沟道重叠的部分，如图8、9所示。如果不进行部分去除，电子将直接通过导电薄膜从源极到达漏极，从而导致沟道失效，导致整个氧化物薄膜晶体管作废。
因此，采用无定型硅单质薄膜作为背沟道刻蚀保护层的制备工艺能够简化工序。
实践发现，采用非金属薄膜作为背沟道刻蚀保护层，其薄膜本身较有机导电薄膜稳定，而且非金属薄膜的粘附性更好，所制备的薄膜不易出现凸起、分裂的等状况，对于整体金属氧化物薄膜晶体管的性能有良好的改善作用。
本发明的制备方法，金属氧化物薄膜晶体管的结构为底栅、背沟道刻蚀结构。在背沟道刻蚀制作源、漏电极的过程中，设置了制作背沟道刻蚀保护层结构。该背沟道刻蚀保护层不仅能够降低刻蚀源、漏电极刻蚀的过程对金属氧化物薄膜晶体管背沟道造成的损伤，而且采用非金属薄膜作为背沟道刻蚀保护层其制备工艺与现有中的设备相容，能够简化制备工序，具有成本低廉的特点。通过大量实践证明，本发明的制备方法所制备的金属氧化物薄膜晶体管的稳定性高，而且具有制备工艺简单，成本低廉等特点，可实现金属氧化物薄膜晶体管驱动背板高精细化、低成本制作。
该工艺制作的金属氧化物薄膜晶体管，可以用于液晶显示器LCD(Liquid Crystal Display)以及主动矩阵有机发光二极体面板AMOLED(Active Matrix/Organic Light Emitting Diode)领域。
需要说明的是，本实施例中涉及的尺寸、配比比例并不限制本发明金属氧化物薄膜晶体管的制备工艺，在实际制备过程中，使用者可以根据具体需要灵活调整。
实施例4。
一种金属氧化物薄膜晶体管的制备方法，包括如下工序。
如图1所示，在带有200nm的Si3N4水氧阻隔层的柔性PET薄膜的衬底01上，使用PVD(Physical Vapor Deposition)法沉积厚度为200nm ITO薄膜作为金属导电层。使用光刻工艺将金属导电层图形化作为栅极02。
需要说明的是，金属导电层的厚度范围在100nm至2000nm范围内,其具体尺寸可以根据实际需要灵活设置，不限于本实施例的尺寸。金属导电层的构成材料也不限于本实施例的情况。
接着，如图2所示，在已图形化的金属导电层上，使用PECVD法(Plasma Enhanced Chemical Vapor Deposition)沉积第一绝缘膜03，第一绝缘膜03由100nm的氮化硅、90nm的五氧化二钽和20nm的二氧化硅叠层而成作为栅极绝缘层。需要说明的是，第一绝缘膜的厚度范围在50nm至500nm范围内,其具体尺寸可以根据实际需要灵活设置，不限于本实施例的尺寸，第一绝缘膜的构成材料也不限于本实施例的情况。
接着，使用PVD法沉积50nm金属氧化物IZO薄膜(In、Zn原子比为1:1)作为有源层04，如图3所示。
需要说明的是，有源层的厚度范围在20nm至200nm范围内，其具体尺寸可以根据实际需要灵活设置，不限于本实施例的尺寸。有源层的构成材料也不限于本实施例的情况。
如图4所示，使用物理气相沉积方法，采用反应气体Ar/N2＝50:10sccm,在5mTorr的压力下，制备15nm的氮化碳薄膜，并使用250℃对氮化碳薄膜进行热处理30分钟，作为背沟道刻蚀保护层05。此处，制作背沟道刻蚀保护层05，该保护层能够减少刻蚀源、漏电极过程对金属氧化物薄膜晶体管背沟道造成的损伤。
需要说明的是,背沟道刻蚀保护层的厚度范围在0.1nm至30nm范围内，尤以0.5nm至1.0nm较佳，其具体尺寸可以根据实际需要灵活设置，不限于本实施例的尺寸。背沟道刻蚀保护层的构成材料也不限于本实施例的情况。
如图5所示，使用PVD法在背沟道刻蚀保护层上制备Mo单层金属层，厚度为200nm。使用反应离子刻蚀设备对Mo进行干法刻蚀，所使用流量比为50sccm:10sccm的SF6/O2作为反应气体，刻蚀金属层中的Mo。使用该方法将Mo图形化形成源、漏电极的金属层06，如图6所示。
最后，如图7所示，使用PECVD沉积厚度为300nm的SiO2作为钝化层07，完成金属氧化物薄膜晶体管的制作。
本发明的制备方法，金属氧化物薄膜晶体管的结构为底栅、背沟道刻蚀结构。在背沟道刻蚀制作源、漏电极的过程中，设置了制作背沟道刻蚀保护层结构。该背沟道刻蚀保护层不仅能够降低刻蚀源、漏电极刻蚀的过程对金属氧化物薄膜晶体管背沟道造成的损伤，而且采用非金属薄膜作为背沟道刻蚀保护层其制备工艺与现有中的设备相容，能够简化制备工序，具有成本低廉的特点。通过大量实践证明，本发明的制备方法所制备的金属氧化物薄膜晶体管的稳定性高，而且具有制备工艺简单，成本低廉等特点，可实现金属氧化物薄膜晶体管驱动背板高精细化、低成本制作。
该工艺制作的金属氧化物薄膜晶体管，可以用于液晶显示器LCD(Liquid Crystal Display)以及主动矩阵有机发光二极体面板AMOLED(Active Matrix/Organic Light Emitting Diode)领域。
需要说明的是，本实施例中涉及的尺寸、配比比例并不限制本发明金属氧化物薄膜晶体管的制备工艺，在实际制备过程中，使用者可以根据具体需要灵活调整。
实施例5。
一种金属氧化物薄膜晶体管的制备方法，其他工序与实施例1至4中任意一种相同，不同之处在于：本实施例中，作为刻蚀保护层的非金属薄膜的厚度为1nm。需要说明的是，非金属薄膜的厚度不仅仅局限于本实施例的厚度，可在0.1-30nm范围灵活选择，如设置为0.5nm、0.6nm、0.8nm、5nm、8nm、10nm、11nm、20nm、23nm、26nm等，只需对应调整工作电压即可。
实施例6。
一种金属氧化物薄膜晶体管，采用如上述实施例1至5任意一种方法制备而成。本发明的金属氧化物薄膜晶体管的稳定性高，而且具有制备工艺简单，成本低廉等特点，可实现金属氧化物薄膜晶体管驱动背板高精细化、低成本制作。
该工艺制作的金属氧化物薄膜晶体管，可以用于液晶显示器LCD(Liquid Crystal Display)以及主动矩阵有机发光二极体面板AMOLED(Active Matrix/Organic Light Emitting Diode)领域。
最后应当说明的是，以上实施例仅用以说明本发明的技术方案而非对本发明保护范围的限制，尽管参照较佳实施例对本发明作了详细说明，本领域的普通技术人员应当理解，可以对本发明的技术方案进行修改或者等同替换，而不脱离本发明技术方案的实质和范围。

Claims (10)

  1. 一种金属氧化物薄膜晶体管的制备方法，其特征在于，依次包括如下步骤：
    a.在衬底上制备并图形化金属导电层作为栅极；
    b.在所述金属导电层上沉积第一绝缘薄膜作为栅极绝缘层；
    c.在所述栅极绝缘层上沉积金属氧化物薄膜并图形化作为有源层；
    d.在所述有源层上使用物理气相沉积方法沉积非金属薄膜作为背沟道刻蚀保护层；
    e.在所述背沟道刻蚀保护层上沉积金属层然后对所述金属层进行图形化作为源、漏电极图形；
    f.在所述源、漏电极上沉积第二绝缘薄膜作为钝化层。
  2. 根据权利要求1所述的金属氧化物薄膜晶体管的制备方法，其特征在于：
    所述步骤d中使用物理气相沉积方法沉积非金属薄膜，具体使用物理气相沉积方法沉积碳膜或者硅膜。
  3. 根据权利要求2所述的薄膜晶体管的制备方法，其特征在于：所述背沟道刻蚀保护层的厚度设置为0.1～30nm。
  4. 根据权利要求3所述的金属氧化物薄膜晶体管的制备方法，其特征在于：所述背沟道刻蚀保护层的厚度设置为0.5～20nm。
  5. 根据权利要求4所述的金属氧化物薄膜晶体管的制备方法，其特征在于：所述背沟道刻蚀保护层的厚度设置为0.5～1nm。
  6. 根据权利要求5所述的金属氧化物薄膜晶体管的制备方法，其特征在于：所述背沟道刻蚀保护层的厚度设置为0.6～0.8nm。
  7. 根据权利要求6所述的金属氧化物薄膜晶体管的制备方法，其特征在于：
    所述步骤a中衬底设置为具有缓冲层的玻璃衬底或者具有水氧阻隔层的柔性衬底；
    当所述衬底为柔性衬底时，柔性衬底具体设置为聚萘二甲酸乙二醇酯、聚 对苯二甲酸乙二酯、聚酰亚胺或者金属箔柔性衬底。
  8. 根据权利要求6所述的金属氧化物薄膜晶体管的制备方法，其特征在于：
    所述步骤a中在衬底上制备并图形化金属导电层所使用的金属为铝、铜、钼、钛、银、金、钽、钨、铬单质或铝合金；
    所述金属导电层为单层铝薄膜、铜薄膜、钼薄膜、钛薄膜、银薄膜、金薄膜、钽薄膜、钨薄膜、铬薄膜或铝合金薄膜；或者是由以上单层金属薄膜构成的两层以上的薄膜；
    所述金属导电层的厚度设置为100nm至2000nm；
    所述金属导电层作为金属氧化物薄膜晶体管栅极；
    所述步骤b中的所述第一绝缘薄膜的厚度为50nm至500nm；
    所述第一绝缘薄膜为氧化硅、氮化硅、氧化铝、五氧化二钽或氧化镱绝缘薄膜的单层薄膜，或者是由以上材料的任意组合构成的两层以上的薄膜；
    所述步骤c中的所述有源层厚度为20nm至200nm；
    构成所述有源层的半导体材料是金属氧化物(In2O3)x(MO)y(ZnO)z，其中0≤x≤1，0≤y≤1，0≤z≤1，且x+y+z＝1，M为镓、锡、硅、铝、镁、钽、铪、镱、镍、锆或镧系稀土元素中的一种或两种以上的任意组合。
  9. 根据权利要求6所述的金属氧化物薄膜晶体管的制备方法，其特征在于：
    所述步骤e中沉积所述金属层所使用的金属为铝、铜、钼、钛单质，或由以上金属单质作为主体的合金材料；
    所述金属层为单层铝薄膜、铜薄膜、钼薄膜、钛薄膜或由以上金属单质作为主体的合金材料膜，或者由以上单层金属薄膜构成的两层以上的薄膜；
    所述金属层的厚度为100nm～2000nm；
    所述钝化层的厚度为50nm～2000nm；
    所述钝化层为氧化硅、氮化硅、氧化铝、氧化镱、聚酰亚胺、光刻胶、苯丙环丁烯或聚甲基丙烯酸甲酯单层薄膜，或者是由以上材料的任意组合构成的两层以上的薄膜。
  10. 一种金属氧化物薄膜晶体管，其特征在于：采用如权利要求1至9任意一项所述的方法制备而成。
PCT/CN2014/090193 2013-11-14 2014-11-03 金属氧化物薄膜晶体管及其制备方法 WO2015070715A1 (zh)

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CN103545221B (zh) * 2013-11-14 2018-10-09 广州新视界光电科技有限公司 金属氧化物薄膜晶体管及其制备方法
CN103915509B (zh) 2014-03-25 2017-07-18 京东方科技集团股份有限公司 一种薄膜晶体管、阵列基板及显示装置
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CN107946189B (zh) * 2017-11-22 2020-07-31 深圳市华星光电半导体显示技术有限公司 一种薄膜晶体管及其制备方法
CN109545675B (zh) * 2018-10-26 2020-10-13 深圳市华星光电半导体显示技术有限公司 一种薄膜晶体管阵列基板的制备方法
CN110047851A (zh) * 2019-04-22 2019-07-23 深圳市华星光电半导体显示技术有限公司 Tft阵列基板及其制作方法
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0883169A2 (de) * 1997-06-04 1998-12-09 Robert Bosch Gmbh Verfahren zur Herstellung von einem Dünnschichttransistor
CN102842619A (zh) * 2012-09-03 2012-12-26 南京中电熊猫液晶显示科技有限公司 一种半导体装置及其制造方法
CN103236443A (zh) * 2013-05-14 2013-08-07 广州新视界光电科技有限公司 一种金属氧化物薄膜晶体管及其制备方法
CN103545221A (zh) * 2013-11-14 2014-01-29 广州新视界光电科技有限公司 金属氧化物薄膜晶体管及其制备方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102723279A (zh) * 2012-06-12 2012-10-10 华南理工大学 一种金属氧化物薄膜晶体管的制作方法
CN102790096A (zh) * 2012-07-20 2012-11-21 京东方科技集团股份有限公司 薄膜晶体管及其制作方法、阵列基板、显示装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0883169A2 (de) * 1997-06-04 1998-12-09 Robert Bosch Gmbh Verfahren zur Herstellung von einem Dünnschichttransistor
CN102842619A (zh) * 2012-09-03 2012-12-26 南京中电熊猫液晶显示科技有限公司 一种半导体装置及其制造方法
CN103236443A (zh) * 2013-05-14 2013-08-07 广州新视界光电科技有限公司 一种金属氧化物薄膜晶体管及其制备方法
CN103545221A (zh) * 2013-11-14 2014-01-29 广州新视界光电科技有限公司 金属氧化物薄膜晶体管及其制备方法

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