WO2015069263A1 - Procédé et appareil permettant d'améliorer la précision de mesure du courant continu ("cc") différentiel - Google Patents

Procédé et appareil permettant d'améliorer la précision de mesure du courant continu ("cc") différentiel Download PDF

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WO2015069263A1
WO2015069263A1 PCT/US2013/068961 US2013068961W WO2015069263A1 WO 2015069263 A1 WO2015069263 A1 WO 2015069263A1 US 2013068961 W US2013068961 W US 2013068961W WO 2015069263 A1 WO2015069263 A1 WO 2015069263A1
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channel
channels
ate
voltage
series
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PCT/US2013/068961
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English (en)
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Thien NGO
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Advantest Corporation
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Priority to PCT/US2013/068961 priority Critical patent/WO2015069263A1/fr
Publication of WO2015069263A1 publication Critical patent/WO2015069263A1/fr

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/10—Measuring sum, difference or ratio
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R35/00—Testing or calibrating of apparatus covered by the other groups of this subclass
    • G01R35/005—Calibrating; Standards or reference devices, e.g. voltage or resistance standards, "golden" references
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
    • G01R31/2834—Automated test systems [ATE]; using microprocessors or computers

Definitions

  • Embodiments of the present invention relate generally to automated device testing and more specifically to improving measurement accuracy for equipment used for automated device testing.
  • Automated test equipment can be any testing assembly that performs a test on a device, semiconductor wafer or die, etc. ATE assemblies may be used to execute automated tests that quickly perform measurements and generate test results that can then be analyzed.
  • An ATE assembly may be anything from a computer system coupled to a meter, to a complicated automated test assembly that may include a custom, dedicated computer control system and many different test instruments that are capable of automatically testing electronics parts and/or semiconductor.
  • Automatic Test Equipment ATE is commonly used within the field of electrical chip manufacturing. ATE systems both reduce the amount of time spent on testing devices to ensure that the device functions as designed and serve as a diagnostic tool to determine the presence of faulty components within a given device before it reaches the consumer.
  • a plurality of tests is performed in order to ensure the correct function of a device or product, commonly referred to as a device under test ("DUT") in testing parlance.
  • the plurality of tests is typically part of a test plan that is loaded into the ATE system by the user.
  • the test plan acts as a blueprint for running the tests on the DUTs.
  • the plurality of tests may be compiled in a test flow wherein the test flow may be separated into different test groups which contain one or more tests for testing the device or product.
  • a semiconductor device may be tested with a test flow comprising contact tests, current-voltage tests, logic tests, speed tests, stress tests and functional tests.
  • thermal EMF thermal electromotive force
  • the calibration process can measure the respective thermal EMFs of each individual signal path using a statistical process.
  • the calculated thermal EMFs of each path can be used to characterize each of the signal paths separately.
  • the characterization can then be applied to the measurement values to yield more accurate measurement results.
  • the present invention provides a method and apparatus for measuring and removing thermal EMFs in each signal path of a high accuracy DC voltage measurement application.
  • a calibration mechanism is first employed to characterize the test apparatus prior to performing any measurements.
  • the calibration mechanism will employ a statistical process to characterize thermal EMF values for each individual signal path in the test apparatus separately. After performing DC voltage measurements, the characterized thermal EMF values can then be used to offset the measured values to determine a more accurate measurement result.
  • a method of error correction in automated test equipment comprises calibrating the ATE using a calibration board, wherein the calibration board comprises a reference voltage.
  • the calibrating comprises: (a) measuring the reference voltage using a reference channel and each of a plurality of channels in the ATE; (b) recording a series of differential voltage measurement values obtained from the measuring in a calibration module; and (c) calculating a respective correction factor for each of the plurality of channels utilizing the series of differential voltage measurement values.
  • the method further comprises obtaining a measured voltage value for a DUT connected to a first channel in the ATE, wherein the first channel is one of the plurality of channels.
  • the method comprises correcting the measured voltage value using a respective correction factor for said first channel.
  • a computer-readable storage medium having stored thereon, computer executable instructions that, if executed by a computer system cause the computer system to perform a method of error correction in automated test equipment (ATE)
  • the method comprises calibrating the ATE using a calibration board, wherein the calibration board comprises a reference voltage and wherein the calibrating comprises: (a) measuring the reference voltage using a reference channel and each of a plurality of channels in the ATE; (b) recording a series of differential voltage measurement values obtained from the measuring; and (c) calculating a respective correction factor for each of the plurality of channels utilizing the series of differential voltage measurement values; and (d) storing a plurality of correction factors corresponding to the plurality of channels in a memory module.
  • a system for performing error correction in automated test equipment comprises a memory comprising a test application stored therein; a test interface to connect to a plurality of DUTs; and a calibration board for calibrating the ATE, wherein the calibration board comprises a reference voltage, and wherein the calibration board is configured to plug into the test interface.
  • the system further comprises a processor coupled to the memory and the test interface, wherein the processor is configured to: (a) measure the reference voltage using a reference channel and each of a plurality of channels in the ATE; (b) record a series of differential voltage measurement values obtained from the measuring in a calibration memory module; (c) calculate a respective correction factor for each of the plurality of channels utilizing the series of differential voltage measurement values; and (d) store a plurality of correction factors corresponding to the plurality of channels in a memory module.
  • the processor is configured to: (a) measure the reference voltage using a reference channel and each of a plurality of channels in the ATE; (b) record a series of differential voltage measurement values obtained from the measuring in a calibration memory module; (c) calculate a respective correction factor for each of the plurality of channels utilizing the series of differential voltage measurement values; and (d) store a plurality of correction factors corresponding to the plurality of channels in a memory module.
  • Figure 1 is a computer system on which embodiments of the System on a Chip (SOC) automated test system (ATE) of the present invention used for testing devices under test (DUTs) can be implemented in accordance with one embodiment of the present invention.
  • SOC System on a Chip
  • ATE automated test system
  • FIG. 2 is a schematic block diagram for an automated test equipment (ATE) apparatus for testing DUTs on which embodiments of the present invention can be implemented in accordance with one embodiment of the present invention.
  • ATE automated test equipment
  • Figure 3 is a block diagram illustrating the manner in which the test apparatus is calibrated in accordance with one embodiment of the present invention.
  • Figure 4 is an exemplary circuit diagram illustrating the manner in which the signal paths are characterized in a test apparatus where a digital multi-meter is being used to perform differential measurement between channels in accordance with one embodiment of the present invention.
  • Figure 5 is an exemplary circuit diagram illustrating the manner in which the offset voltage calculated using the circuit in Figure 4 is used to perform a high accuracy single ended voltage measurement in accordance with one embodiment of the present invention.
  • Figure 6 depicts a flowchart of an exemplary computer controlled process for employing a statistical process to characterize and correct for thermal EMF values for each individual signal path in a test apparatus separately in accordance with one embodiment of the present invention.
  • Figure 7 depicts a flowchart of an exemplary computer controlled process for calculating the offset voltage of each channel in a test apparatus in accordance with one embodiment of the present invention.
  • calculating e.g., flowchart 700 of Figure 7 of a computer system or similar electronic computing device or processor (e.g., system 110 of Figure 1).
  • the computer system or similar electronic computing device manipulates and transforms data represented as physical (electronic) quantities within the computer system memories, registers or other such information storage, transmission or display devices.
  • Embodiments described herein may be discussed in the general context of computer- executable instructions residing on some form of computer-readable storage medium, such as program modules, executed by one or more computers or other devices.
  • computer-readable storage media may comprise non-transitory computer-readable storage media and communication media; non-transitory computer-readable media include all computer-readable media except for a transitory, propagating signal.
  • program modules include routines, programs, objects, components, data structures, etc., that perform particular tasks or implement particular abstract data types. The functionality of the program modules may be combined or distributed as desired in various embodiments.
  • Computer storage media includes volatile and nonvolatile, removable and nonremovable media implemented in any method or technology for storage of information such as computer-readable instructions, data structures, program modules or other data.
  • Computer storage media includes, but is not limited to, random access memory (RAM), read only memory (ROM), electrically erasable programmable ROM (EEPROM), flash memory or other memory technology, compact disk ROM (CD-ROM), digital versatile disks (DVDs) or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and that can accessed to retrieve that information.
  • Communication media can embody computer-executable instructions, data structures, and program modules, and includes any information delivery media.
  • communication media includes wired media such as a wired network or direct- wired connection, and wireless media such as acoustic, radio frequency (RF), infrared, and other wireless media. Combinations of any of the above can also be included within the scope of computer-readable media.
  • Figure 1 is a computer system on which embodiments of the System on a Chip (SOC) automated test system (ATE) of the present invention used for testing devices under test (DUTs) can be implemented in accordance with one embodiment of the present invention.
  • computing system 110 in one embodiment, could implement the site controller of the tester system, wherein the site controller connects to and controls the ATE of the present invention used for testing memory DUTs.
  • Computing system 110 broadly represents any single or multiprocessor computing device or system capable of executing computer-readable instructions. Examples of computing system 110 include, without limitation, workstations, laptops, client-side terminals, servers, distributed computing systems, or any other computing system or device.
  • computing system 110 may include at least one processor 114 and a system memory 116.
  • Processor 114 generally represents any type or form of processing unit capable of processing data or interpreting and executing instructions.
  • processor 114 may receive instructions from a software application or module. These instructions may cause processor 114 to perform the functions of one or more of the example embodiments described and/or illustrated herein.
  • System memory 116 generally represents any type or form of volatile or non- volatile storage device or medium capable of storing data and/or other computer-readable instructions. Examples of system memory 116 include, without limitation, RAM, ROM, flash memory, or any other suitable memory device. Although not required, in certain embodiments computing system 110 may include both a volatile memory unit (such as, for example, system memory 116) and a non- volatile storage device (such as, for example, primary storage device 132).
  • volatile memory unit such as, for example, system memory 116
  • non- volatile storage device such as, for example, primary storage device 132).
  • Computing system 110 may also include one or more components or elements in addition to processor 114 and system memory 116.
  • computing system 110 includes a memory controller 118, an input/output (I/O) controller 120, and a communication interface 122, each of which may be interconnected via a communication infrastructure 112.
  • Communication infrastructure 112 generally represents any type or form of infrastructure capable of facilitating communication between one or more components of a computing device. Examples of communication infrastructure 112 include, without limitation, a communication bus (such as an Industry Standard Architecture (ISA), Peripheral Component Interconnect (PCI), PCI Express (PCIe), or similar bus) and a network.
  • ISA Industry Standard Architecture
  • PCI Peripheral Component Interconnect
  • PCIe PCI Express
  • Memory controller 118 generally represents any type or form of device capable of handling memory or data or controlling communication between one or more components of computing system 110.
  • memory controller 118 may control communication between processor 114, system memory 116, and I/O controller 120 via communication infrastructure 112.
  • I/O controller 120 generally represents any type or form of module capable of coordinating and/or controlling the input and output functions of a computing device.
  • I/O controller 120 may control or facilitate transfer of data between one or more elements of computing system 110, such as processor 114, system memory 116, communication interface 122, display adapter 126, input interface 130, and storage interface 134.
  • Communication interface 122 broadly represents any type or form of communication device or adapter capable of facilitating communication between example computing system 110 and one or more additional devices.
  • communication interface 122 may facilitate communication between computing system 110 and a private or public network including additional computing systems.
  • Examples of communication interface 122 include, without limitation, a wired network interface (such as a network interface card), a wireless network interface (such as a wireless network interface card), a modem, and any other suitable interface.
  • communication interface 122 provides a direct connection to a remote server via a direct link to a network, such as the Internet.
  • Communication interface 122 may also indirectly provide such a connection through any other suitable connection.
  • Communication interface 122 may also represent a host adapter configured to facilitate communication between computing system 110 and one or more additional network or storage devices via an external bus or communications channel.
  • host adapters include, without limitation, Small Computer System Interface (SCSI) host adapters, Universal Serial Bus (USB) host adapters, IEEE (Institute of Electrical and Electronics Engineers) 1394 host adapters, Serial Advanced Technology Attachment (SAT A) and External SATA (eSATA) host adapters, Advanced Technology Attachment (ATA) and Parallel ATA (PATA) host adapters, Fibre Channel interface adapters, Ethernet adapters, or the like.
  • Communication interface 122 may also allow computing system 110 to engage in distributed or remote computing. For example, communication interface 122 may receive instructions from a remote device or send instructions to a remote device for execution.
  • computing system 110 may also include at least one display device 124 coupled to communication infrastructure 112 via a display adapter 126.
  • Display device 124 generally represents any type or form of device capable of visually displaying information forwarded by display adapter 126.
  • display adapter 126 generally represents any type or form of device configured to forward graphics, text, and other data for display on display device 124.
  • computing system 110 may also include at least one input device 128 coupled to communication infrastructure 112 via an input interface 130.
  • Input device 128 generally represents any type or form of input device capable of providing input, either computer- or human-generated, to computing system 110. Examples of input device 128 include, without limitation, a keyboard, a pointing device, a speech recognition device, or any other input device.
  • computing system 110 may also include a primary storage device 132 and a backup storage device 133 coupled to communication infrastructure 112 via a storage interface 134.
  • Storage devices 132 and 133 generally represent any type or form of storage device or medium capable of storing data and/or other computer-readable instructions.
  • storage devices 132 and 133 may be a magnetic disk drive (e.g., a so-called hard drive), a floppy disk drive, a magnetic tape drive, an optical disk drive, a flash drive, or the like.
  • Storage interface 134 generally represents any type or form of interface or device for transferring data between storage devices 132 and 133 and other components of computing system 110.
  • databases 140 may be stored in primary storage device 132.
  • Databases 140 may represent portions of a single database or computing device or it may represent multiple databases or computing devices.
  • databases 140 may represent (be stored on) a portion of computing system 110 and/or portions of example network architecture 200 in Figure 2 (below).
  • databases 140 may represent (be stored on) one or more physically separate devices capable of being accessed by a computing device, such as computing system 110 and/or portions of network architecture 200.
  • storage devices 132 and 133 may be configured to read from and/or write to a removable storage unit configured to store computer software, data, or other computer-readable information.
  • suitable removable storage units include, without limitation, a floppy disk, a magnetic tape, an optical disk, a flash memory device, or the like.
  • Storage devices 132 and 133 may also include other similar structures or devices for allowing computer software, data, or other computer-readable instructions to be loaded into computing system 110.
  • storage devices 132 and 133 may be configured to read and write software, data, or other computer-readable information.
  • Storage devices 132 and 133 may also be a part of computing system 110 or may be separate devices accessed through other interface systems.
  • computing system 110 may be connected to many other devices or subsystems. Conversely, all of the components and devices illustrated in Figure 1 need not be present to practice the embodiments described herein. The devices and subsystems referenced above may also be interconnected in different ways from that shown in Figure 1. Computing system 110 may also employ any number of software, firmware, and/or hardware configurations. For example, the example embodiments disclosed herein may be encoded as a computer program (also referred to as computer software, software applications, computer-readable instructions, or computer control logic) on a computer-readable medium.
  • a computer program also referred to as computer software, software applications, computer-readable instructions, or computer control logic
  • the computer-readable medium containing the computer program may be loaded into computing system 110. All or a portion of the computer program stored on the computer- readable medium may then be stored in system memory 116 and/or various portions of storage devices 132 and 133. When executed by processor 114, a computer program loaded into computing system 110 may cause processor 114 to perform and/or be a means for performing the functions of the example embodiments described and/or illustrated herein. Additionally or alternatively, the example embodiments described and/or illustrated herein may be implemented in firmware and/or hardware.
  • a computer program for running test plans may be stored on the computer-readable medium and then stored in system memory 116 and/or various portions of storage devices 132 and 133.
  • the computer program may cause the processor 114 to perform and/or be a means for performing the functions required for sharing resources between multiple test cores in a concurrent test environment.
  • the present invention provides a method and system that accounts for differences in unwanted thermal EMF in all the different pairs of test signal paths of an ATE system, thereby, facilitating accurate low current and voltage measurements.
  • SOC System on a Chip
  • the problem with conventional System on a Chip (SOC) test systems that can perform low current and voltage measurement, e.g., on the order of pico-amps and micro-volts, is that while they may perform a default correction for distortions in measurement resulting from thermal EMF, they do not account for the fact that the thermal EMF of each signal path varies due to many factors and, therefore, a different correction needs to be applied to each signal path to obtain more accurate measurement results.
  • the problem with conventional ATE apparatuses is that they used a static thermal EMF value to correct for EMF related error.
  • each signal path is different and, as a result, each path has a different thermal EMF.
  • the calibration process can allow the respective thermal EMFs of each individual test signal path to be measured using a statistical process.
  • the calculated thermal EMFs of each path can be used to characterize each of the signal paths separately. The characterization can then be applied to the measurement values to yield more accurate measurement results.
  • the present invention provides a method and apparatus for measuring and removing thermal EMFs in each signal path of a high accuracy DC voltage measurement application.
  • the invention provides a method and apparatus to measure and remove thermal EMF in the connection paths of a test apparatus being used in a high accuracy differential DC voltage measurement application.
  • the present invention can improve differential DC voltage measurement to the limit of the measurement instrument instead of being limited by the thermal EMF of the connection paths.
  • a calibration mechanism is first employed to characterize the test apparatus prior to performing any measurements. As part of characterization, the calibration mechanism will employ a statistical process to characterize thermal EMF values for each individual signal path in the test apparatus separately. After performing DC voltage measurements, the characterized thermal EMF values can then be used to offset the measured values to determine a more accurate measurement result.
  • FIG. 2 is a schematic block diagram for an automated test equipment (ATE) apparatus for testing DUTs on which embodiments of the present invention can be implemented in accordance with one embodiment of the present invention.
  • the system controller 201 comprises one or more linked computers. In other embodiments, the system controller often comprises only a single computer.
  • the system controller 201 is the overall system control unit, and runs the software for the ATE that is responsible for accomplishing all the user-level testing tasks, including running the user's main test plan.
  • the communicator bus 215 provides a high-speed electronic communication channel between the system controller and the tester hardware.
  • the communicator bus can also be referred to as a backplane, a module connection enabler, or system bus. Physically,
  • communicator bus 215 is a fast, high-bandwidth duplex connection bus that can be electrical, optical, etc.
  • communicator bus 215 can use the TCP/IP protocol.
  • System controller 201 sets up the conditions for testing the DUTs 211-214 by programming the tester hardware through commands sent over the communicator bus 215.
  • Tester hardware 202 comprises the complex set of electronic and electrical parts and connectors necessary to provide the test stimulus to the devices under test (DUTs) 211-214 and measure the response of the DUTs to the stimulus, and compare it against the expected response.
  • tester hardware 202 can comprise multiple site controllers, wherein each site controller is connected to multiple DUTs.
  • Each site controller is a computer used in a device test and, in one embodiment, can perform substantially the same function as computing system 110.
  • a test plan program can be executed on a site controller. The site controllers are connected to the system controller and test operations performed by a user are processed on the system controller, which controls the site controllers over communicator bus 215.
  • FIG. 3 is a block diagram illustrating the manner in which the test apparatus is calibrated in accordance with one embodiment of the present invention.
  • the test apparatus needs to be calibrated before performing measurements in order to ensure the accuracy of the measurements. Measurement accuracy is especially important in test apparatuses capable of performing low current, e.g., on the order of pico-amps and low voltage e.g., on the order of micro-volts. Some of the factors that contribute to measurement errors are repeatable and predictable over time and temperature and can be removed.
  • test apparatus needs to be calibrated to account for the various errors.
  • Calibration is typically performed each time the test apparatus is used to perform a new measurement by a user.
  • the purpose of calibration is to characterize the path error, including thermal EMF related error, for each signal path precisely.
  • the signal path error can be characterized to a micro-volt level.
  • Calibration is performed by first plugging a calibration board 302 into the test apparatus.
  • the calibration board in one embodiment, is plugged into the same interface that the DUTs will subsequently be plugged into for device testing.
  • An interface board 312 (also known as a Wafer Probe Interface board), in one embodiment, is used to route all the internal signals in the test head 306 of the test apparatus to pins on an external interface so that the calibration board or connected DUT can easily interface with the test system.
  • the interface board 312 allows the user to interface with the tester functionality and tester instruments within test head 306. In one embodiment, once calibration is performed, the user can plug the DUTs to be tested into the test apparatus, wherein the interface board 312 is used to provide an interface between the DUTs and the tester functionality within test head 306.
  • the calibration board provides a DC voltage reference that can be used for calibration purposes.
  • calibration board 302 in Figure 3 uses voltage references 350, a 4.096 Volt and a 1.25 Volt reference.
  • different voltage references can be used to accommodate the range of measurements in the test head 306.
  • a high voltage reference, 4.096V, and a low voltage reference, 1.25V is used.
  • divider modules 352 may also be used so that different branches of measurement can be serviced.
  • a 1/125 divider module can be used to derive a 10 mV (1.25V / 125) voltage reference from the 1.25 V reference.
  • Each of the signal paths or channels 354 within test head 306 connect to the calibration board through a series of associated external pins 308, e.g. P730, P729, etc.
  • Each signal path can typically have a trace between 0 to 6 meters long between the origin point of the signal within the test apparatus and the external signal pin that connects to the calibration board or the DUT. Further, each trace may comprise multiple metal connections en route to the external interface signal pin. This results in thermal EMF and an undesirable voltage change along the signal path represented in Figure 3 as offset voltage (Voffset) 316.
  • the digital multimeter (DMM) 370 will measure a differential voltage between two channels, e.g., CHI and CH3 in Figure 3 that may be inaccurate as a result of the thermal EMF related offset voltages in each channel.
  • a differential voltage between two channels e.g., CHI and CH3 in Figure 3
  • This offset voltage varies for each signal path, as explained above, and must be accounted or calibrated for when conducting high accuracy differential DC voltage measurement. In certain test apparatuses, there may be hundreds of signal paths. Embodiments of the present invention allow for the varying thermal EMFs of each path to be accounted for individually.
  • the thermal EMF value of a given path may then be used to offset a measurement reading taken for that path using a DMM to obtain a more precise measurement value.
  • the measurement reading may also be corrected for the voltage error added from the measurement instrumentation, e.g., DMM 370.
  • the offset voltages calculated to compensate for thermal EMF or the measuring instrument may be memory stored in a calibration file 324 located within test-head 306.
  • Other calibration files besides DC voltage measurement, e.g. capacitance measurement, inductance measurement may also be stored in the same calibration file as well.
  • Figure 4 is an exemplary circuit diagram illustrating the manner in which the signal paths are characterized in a test apparatus where a digital multi-meter is being used to perform differential measurement between channels in accordance with one embodiment of the present invention.
  • DMM 370 is first used to determine a series of differential voltages between a reference channel and all the other channels in the test apparatus.
  • a reference voltage is used for measuring the differential voltage between the reference and other channels.
  • a 10 mV voltage reference is used.
  • the voltage reference, Vref 402 typically needs to be precisely known and is typically floating with respect to the system ground or the ground reference of the circuit under test.
  • the system may have "n" signal paths, PI to Pn.
  • the system in Figure 4 for example, has 100 channels or signal paths. If channel 1, 412, is used as a reference channel, a differential voltage would first be measured between all the other channels, 406, and channel 1, 412. In the apparatus of Figure 4, for example, with 100 channels, 99 different measurements would be taken by Digital Voltmeter (DVM) (or DMM) 424.
  • DVM Digital Voltmeter
  • any channel in the system can be used as a reference channel.
  • Each measured pair is multiplexed into the DVM for measurement.
  • the interface board 312 is configured with multiplexers 358 that allow the measurements between the reference channel and the other channels to be taken easily without needing to physically switch the DVM connections.
  • multiplexer 359 allows the test apparatus to switch between different measurement instruments, e.g., DMM 370 and LCR meter 371.
  • the differential voltage measurement for each of the (n-1) pairs as recorded by DVM 424 will have some thermal EMF related error built into it, wherein both channels contribute to the error. Accordingly, embodiments of the present invention must be used so that a respective error can be attributed to each channel separately.
  • the calibration process of the present invention characterizes all the channel paths and provides correction factors for the differential measurements as will be explained further below.
  • the DVM 424 is used to measure Vref for all 99 pairs of channels for the test apparatus illustrated in Figure 4.
  • the voltage measured for a given pair comprises the reference voltage and the difference in offset voltages between the reference channel, e.g. Channel 1 and the channel being measured (Channel M).
  • the vector of measured voltages, ⁇ VM k ⁇ of all 99 pairs can accordingly be represented by the following equation:
  • Vref is fixed at 10 mV.
  • ⁇ VM k ⁇ is the vector of measured voltages for all 99 pairs as stated above.
  • V 0fs (CH k ) is the offset voltage for the k-th channel while V ofs (CHi) is the offset voltage of Channel 1.
  • the thermal EMF of each signal path will be random.
  • each path will typically comprise a random number and combination of connections.
  • the thermal EMF of each signal path can be positive, or negative, small or large.
  • the average of all the thermal EMFs in the system should either be 0 or approximate to 0. The more the signal paths in a test apparatus, the closer the average thermal EMF of all the paths will be to 0. For the purposes of this illustration, therefore, the average of V 0fs (CH k ) will be approximated to 0.
  • the average of the measured voltage vector can be represented as the following:
  • V ofs (CH 1 ) V ref - V avg (3)
  • V aVg is the simply the measured average of all the (n-1) pairs and V ref will be 10 mV in the example illustrated in Figure 4. Thus, the offset voltage of Channel 1 can be calculated.
  • the offset voltage of Channel 3 can be determined using equation 1.
  • the offset voltage of Channel 3 would be given by the following:
  • V ofs (CH 3 ) VM 3 - V ref + V ofs (CHi) (4), where VM 3 is the measured differential voltage between channel 3 and channel 1.
  • V 0fs (CH 3 ) can also be represented as the following:
  • V ofs (CH 3 ) VM 3 - V avg (5)
  • the offset voltage of any channel M can be represented by the following:
  • V ofs (CH M ) VM M [0074]
  • V, VM jk + V 0fs (CH j ) - V ofs (CH k ) (5), where V, is the true voltage after it has been adjusted for thermal EMF and where VM jk is the measured voltage between paths j and k.
  • Figure 5 is an exemplary circuit diagram illustrating the manner in which the offset voltage calculated using the circuit in Figure 4 is used to perform a high accuracy single ended voltage measurement in accordance with one embodiment of the present invention.
  • the determined values can be used to correct other types of measurements taken by the test apparatus.
  • the derived channel offsets can be used to correct single- ended measurements taken by VI measures within the test apparatus.
  • each channel within test head 306 comprises a VI measure, e.g., VI measure 358 that can be used to take single-ended voltage or current measurements of DUTs connected to any of the channels 308, e.g., P401, P402, etc.
  • VI measure 358 e.g., VI measure 358 that can be used to take single-ended voltage or current measurements of DUTs connected to any of the channels 308, e.g., P401, P402, etc.
  • Multiplexers 362 can be used to connect the VI measures to each respective channel.
  • VI measure 524 measuring a IV voltage reference (or DUT) through channel 1, 512. It should be noted that the DUT could be at any voltage e.g., 4V, 10 V etc.
  • the measurement, V n , taken by VI measure 524 can be characterized by the following equation:
  • V n Vofs (CH n ) + VV IR - V GFS (7)
  • the measured voltage, V n equals the channel offset V 0fs (CH n ), as measured earlier, plus the DUT voltage (or reference voltage) V VIR minus the ground offset error VG F S- Ground offset error occurs because the ground reference uses by the VI, e.g., VI 524 in the test apparatus will not be the same as the ground reference used by the DUT or voltage reference it is connected to, e.g. DUT or reference 551. Thus, it is necessary to calibrate for ground offset error.
  • ground offset error can be represented as the following:
  • VGFS VGNDVIII - VGNDDUT (8), where the ground offset error is the difference between the ground at the VI measure (VGN D V III ) and the ground at the DUT (VGN DD U T )-
  • the ground offset error can be determined using equation (7).
  • the channel offset can be calculated using the technique illustrated in Figure 4, V VIR is the DUT or voltage reference voltage 551, and V n is the voltage measured by the VI measure, e.g. VI measure 524.
  • the value of VG F S SO determined can be used to determine the corrected voltage at the DUT or voltage reference, Vn corrected, wherein Vn corrected is determined using the following equation:
  • Vn corrected V n - V ofs (CH n ) + V GF S (9)
  • Figure 6 depicts a flowchart of an exemplary computer controlled process for employing a statistical process to characterize and correct for thermal EMF values for each individual signal path in a test apparatus separately in accordance with one embodiment of the present invention.
  • the invention is not limited to the description provided by flowchart 600. Rather, it will be apparent to persons skilled in the relevant art(s) from the teachings provided herein that other functional flows are within the scope and spirit of the present invention.
  • Flowchart 600 will be described with continued reference to exemplary embodiments described above though the method is not limited to those embodiments.
  • a calibration board 302 is connected to the test apparatus in order to calibrate the tester.
  • ⁇ PI the number of signal paths: ⁇ PI, P2 ⁇ , ⁇ PI, P3 ⁇ , ⁇ PI, Pn
  • ⁇ VM k the number of channels, ⁇ PI, P3 ⁇ , ⁇ PI, Pn
  • the offset voltage, V 0fs (CH n ), is calculated for each of the signal paths, e.g., PI to PI 00 in Figure 4, using the differential measurements from the prior step.
  • Figure 7 provides further details on how the offset voltage for each channel is calculated.
  • the calibration board 302 is replaced with a DUT that is connected to the tester apparatus.
  • a voltage measurement is obtained for the DUT using any channel to obtain a single-ended measurement or any pair of channels to obtain a differential measurement.
  • the voltage measurement obtained is offset by the correction factor or offset voltage calculated for each of the channels to obtain a more accurate voltage measurement.
  • Figure 7 depicts a flowchart of an exemplary computer controlled process for calculating the offset voltage of each channel in a test apparatus in accordance with one embodiment of the present invention.
  • the invention is not limited to the description provided by flowchart 700. Rather, it will be apparent to persons skilled in the relevant art(s) from the teachings provided herein that other functional flows are within the scope and spirit of the present invention.
  • Flowchart 700 will be described with continued reference to exemplary embodiments described above though the method is not limited to those embodiments.
  • step 702 an average of all the differential voltages for all pairs of signal paths: ⁇ PI, P2 ⁇ , ⁇ PI, P3 ⁇ , ⁇ PI, Pn) calculated at step 604 in Figure 7 is obtained.
  • step 704 the average of all the channel offset errors of all the paths in the system are approximated as zero. As explained above, if all paths are drawn randomly, statistically the positive and negative values of offset errors for all the paths would average out to zero and the higher the number of paths in a test system, the closer this approximation is to zero. [0096] At step 706, a channel offset value is determined for the reference channel using the average of all the differential voltages from step 702 and the static reference voltage value.
  • step 708 using the channel offset of the reference channel calculated at step 708, a channel offset for each of the remainder of the channels is calculated.
  • cloud-based services e.g., software as a service, platform as a service, infrastructure as a service, etc.
  • Various functions described herein may be provided through a remote desktop environment or any other cloud-based computing environment.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

L'invention concerne un procédé de correction d'erreurs dans un équipement d'essai automatique (EEA). Le procédé comporte l'étalonnage de l'EEA au moyen d'une carte d'étalonnage, la carte d'étalonnage comportant une tension de référence. L'étalonnage comporte les étapes consistant à : (a) mesurer la tension de référence en utilisant un canal de référence et chacun d'une pluralité de canaux dans l'EEA; (b) enregistrer une série de valeurs de mesure de tension différentielle obtenues par la mesure dans un module d'étalonnage; et (c) calculer un facteur de correction respectif pour chacun de la pluralité de canaux en utilisant la série de valeurs de mesure de tension différentielle. Le procédé comporte par ailleurs l'étape consistant à obtenir une valeur de tension mesurée pour un dispositif à l'essai connecté à un premier canal dans l'EEA, le premier canal étant l'un de la pluralité de canaux. Enfin, le procédé comporte l'étape consistant à corriger la valeur de tension mesurée au moyen d'un facteur de correction respectif pour ledit premier canal.
PCT/US2013/068961 2013-11-07 2013-11-07 Procédé et appareil permettant d'améliorer la précision de mesure du courant continu ("cc") différentiel WO2015069263A1 (fr)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018112452A1 (fr) 2016-12-16 2018-06-21 Abb Schweiz Ag Compensation de différences de retour à la masse
CN110749848A (zh) * 2019-09-25 2020-02-04 西安航天计量测试研究所 一种基于电流通道切换仪的电流参数校准系统与方法
CN110998478A (zh) * 2017-08-07 2020-04-10 凌力尔特科技控股有限责任公司 应力受损信号校正电路
IT202100015431A1 (it) * 2021-06-14 2022-12-14 Belvedere S R L Dispositivo di connessione elettro-meccanica per apparecchiature da testare

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4724378A (en) * 1986-07-22 1988-02-09 Tektronix, Inc. Calibrated automatic test system
US20040186675A1 (en) * 2003-03-21 2004-09-23 Advantest Corporation Calibration method for system performance validation of automatic test equipment
US20060111861A1 (en) * 2004-11-23 2006-05-25 Horne Stephen J System and method for calibrating signal paths connecting a device under test to a test system
US20060236157A1 (en) * 2005-03-31 2006-10-19 Li Huang Calibrating automatic test equipment
US20080024159A1 (en) * 2006-07-31 2008-01-31 Eran Tilbor Compensation for voltage drop in automatic test equi0pment

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4724378A (en) * 1986-07-22 1988-02-09 Tektronix, Inc. Calibrated automatic test system
US20040186675A1 (en) * 2003-03-21 2004-09-23 Advantest Corporation Calibration method for system performance validation of automatic test equipment
US20060111861A1 (en) * 2004-11-23 2006-05-25 Horne Stephen J System and method for calibrating signal paths connecting a device under test to a test system
US20060236157A1 (en) * 2005-03-31 2006-10-19 Li Huang Calibrating automatic test equipment
US20080024159A1 (en) * 2006-07-31 2008-01-31 Eran Tilbor Compensation for voltage drop in automatic test equi0pment

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018112452A1 (fr) 2016-12-16 2018-06-21 Abb Schweiz Ag Compensation de différences de retour à la masse
CN110383088A (zh) * 2016-12-16 2019-10-25 Abb瑞士股份有限公司 对接地返回差异的补偿
EP3555646A4 (fr) * 2016-12-16 2021-01-13 ABB Schweiz AG Compensation de différences de retour à la masse
CN110998478A (zh) * 2017-08-07 2020-04-10 凌力尔特科技控股有限责任公司 应力受损信号校正电路
CN110749848A (zh) * 2019-09-25 2020-02-04 西安航天计量测试研究所 一种基于电流通道切换仪的电流参数校准系统与方法
IT202100015431A1 (it) * 2021-06-14 2022-12-14 Belvedere S R L Dispositivo di connessione elettro-meccanica per apparecchiature da testare

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