WO2015068341A1 - 太陽電池 - Google Patents

太陽電池 Download PDF

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Publication number
WO2015068341A1
WO2015068341A1 PCT/JP2014/005294 JP2014005294W WO2015068341A1 WO 2015068341 A1 WO2015068341 A1 WO 2015068341A1 JP 2014005294 W JP2014005294 W JP 2014005294W WO 2015068341 A1 WO2015068341 A1 WO 2015068341A1
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semiconductor layer
crystal substrate
type semiconductor
thickness
type
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PCT/JP2014/005294
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English (en)
French (fr)
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浩一 廣瀬
義宏 松原
訓裕 川本
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パナソニックＩｐマネジメント株式会社
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Priority to JP2015546284A priority Critical patent/JPWO2015068341A1/ja
Priority to EP14859500.2A priority patent/EP3067936A4/en
Publication of WO2015068341A1 publication Critical patent/WO2015068341A1/ja
Priority to US15/142,967 priority patent/US20160322522A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
    • H01L31/035272—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions characterised by at least one potential jump barrier or surface barrier
    • H01L31/03529—Shape of the potential jump barrier or surface barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0236—Special surface textures
    • H01L31/02363—Special surface textures of the semiconductor body itself, e.g. textured active layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
    • H01L31/035272—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions characterised by at least one potential jump barrier or surface barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
    • H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
    • H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/20—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials
    • H01L31/202—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials including only elements of Group IV of the Periodic Table
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • This disclosure relates to solar cells.
  • Patent Document 1 in order to reduce the deterioration of characteristics due to the semiconductor layers on the front and back surfaces of the photovoltaic element wrapping around the end surface, the semiconductor layer on the front surface side is formed on the substantially entire surface of the substrate, and the semiconductor layer on the back surface side is A structure formed in a smaller area than the substrate is disclosed.
  • Patent Document 2 in a photovoltaic device, for example, when an n-type semiconductor layer is formed on a first main surface of an n substrate and a p-type semiconductor layer is formed on a second main surface, semiconductor layers having different conductivity types are formed. Depending on the order of formation, an n substrate-n layer-p layer rectifying junction or an n substrate-p layer-n layer reverse junction is formed on the side surface and peripheral edge of the n substrate. According to the former, it is stated that a rectifying junction is provided on the entire surface of the substrate, and there is no adverse effect such as suppression of carrier movement due to reverse bonding.
  • JP 2001-044461 A Japanese Patent Laid-Open No. 11-251609
  • the side surface of the substrate is exposed and there is no protective film. If the semiconductor layer on the light-receiving surface side or the semiconductor layer on the back surface wraps around the side surface of the substrate, the side surface of the substrate is covered. However, as described in Patent Documents 1 and 2, there is a possibility that the characteristics of the solar cell may deteriorate. .
  • a solar cell which is one embodiment of the present disclosure includes a crystal substrate having one conductivity type, a first semiconductor layer having one conductivity type formed on one main surface of the crystal substrate, and on the other main surface of the crystal substrate.
  • the thickness in the normal direction is less than the thickness in the normal direction of the first semiconductor layer on one main surface, and the thickness in the normal direction of the second semiconductor layer on the side surface is the second semiconductor layer on the other main surface. It is thinner than the thickness in the normal direction.
  • the protective film can be formed on the side surface of the crystal substrate without causing deterioration of the characteristics of the solar cell.
  • FIG. 1 is a diagram showing a solar cell 10.
  • an n-type amorphous semiconductor layer wraps around the side surface of the crystal substrate from one main surface side
  • a p-type amorphous semiconductor layer wraps around the side surface of the crystal substrate from the other main surface side. It is based on the knowledge that experimentally confirmed that leaks hardly occur if only repeated. As described above, if no leakage occurs even if the n-type amorphous semiconductor layer on one main surface and the p-type amorphous semiconductor layer on the other main surface are overlapped on the side surface of the crystal substrate, this is used to protect the side surface. We thought it could be used for membranes. The following configuration is based on this finding.
  • FIG. 1A is a cross-sectional view.
  • the upper side is the light receiving surface side
  • the lower side is the back side.
  • (B) is a plan view showing the light receiving surface side
  • (c) is a plan view showing the back surface side
  • (d) is a cross-sectional view taken along the line DD in (b). Note that (d) shows the arrangement direction opposite to (a), the upper side being the back side, and the lower side being the light receiving side.
  • the vertical direction of the arrangement is defined as the Y direction
  • the upper side of the page is defined as the + Y direction in (b), and the -Y direction in (c), and is distinguished by a sign. .
  • the sectional view changes depending on where to cut, (a) corresponds to the sectional view taken along line AA in (b).
  • the “light receiving surface” means a surface in the solar cell 10 on which light mainly enters from the outside. For example, more than 50% to 100% of the light incident on the solar cell 10 enters from the light receiving surface side.
  • the “back surface” means a surface opposite to the light receiving surface.
  • Solar cell 10 receives light such as sunlight, generates carriers and electrons and holes, collects the generated carriers, collects the collected carriers, and takes them out.
  • a portion that generates carriers is called a photoelectric conversion portion, and is composed of an n-type single crystal silicon substrate 11, an n-type semiconductor layer 12, and a p-type semiconductor layer 13.
  • the carriers are collected by the transparent conductive film 14 on the light receiving surface side and the transparent conductive film 15 on the back surface side. It is the current collecting electrode 16 on the light receiving surface side and the current collecting electrode 17 on the back surface side that collects the collected carriers.
  • the n-type single crystal silicon substrate 11 is simply referred to as a crystal substrate 11.
  • the current collecting electrode 16 on the light receiving surface side is a carrier current collecting electrode provided on the transparent conductive film 14 on the light receiving surface side.
  • the back-side collecting electrode 17 is a carrier collecting electrode provided on the back-side transparent conductive film 15.
  • These are, for example, fine wire electrode portions formed by screen printing a conductive paste in which conductive particles such as silver (Ag) are dispersed in a binder resin in a desired pattern on the transparent conductive films 14 and 15. It is.
  • the collecting electrodes 16 and 17 may be formed by using various sputtering methods, various vapor deposition methods, various plating methods, or the like instead of screen printing. As shown in FIGS. 1A and 1D, a plurality of current collecting electrodes 16 and 17 may be provided.
  • the present disclosure relates to the configuration of the photoelectric conversion unit and the transparent conductive films 14 and 15, the current collecting electrodes 16 and 17 are limited to the above description, and those illustrations are illustrated in FIGS. Only shown in d). Hereinafter, each configuration will be described in detail.
  • the crystal substrate 11 constituting the photoelectric conversion part is a single crystal semiconductor substrate having one conductivity type.
  • one conductivity type is n-type
  • a single crystal semiconductor is single crystal silicon.
  • the planar shape of the crystal substrate 11 has an octagonal shape in which the four corners 18, 19, 20, and 21 of the outer edge of the rectangular shape are cut out.
  • one side is about 100 mm to about 200 mm, and the four corners are cut out with a length of about 5 mm to about 16 mm along the side direction.
  • the thickness is, for example, about 75 ⁇ m to about 200 ⁇ m. These dimensions are merely examples, and other values may be used.
  • the surface of the crystal substrate 11, that is, the light receiving surface, the back surface, and the side surfaces each have a texture structure. 1 and 2, the texture structure is not shown, but will be described in detail later with reference to FIG. 3.
  • the “texture structure” is an uneven structure that suppresses surface reflection and increases the light absorption amount of the photoelectric conversion unit.
  • the thickness of the crystal substrate 11 along the direction in which the various films are stacked is several tens to several hundreds ⁇ m, and the unevenness height of the texture structure is several ⁇ m.
  • the n-type semiconductor layer 12 is a one-conductivity-type semiconductor layer provided on one main surface of the crystal substrate 11. Assuming that one main surface is a light receiving surface, one conductivity type is the conductivity type of the crystal substrate 11, and thus here is an n-type semiconductor layer provided on the light receiving surface.
  • the n-type semiconductor layer 12 includes an i-type amorphous silicon layer 22 and an n-type amorphous silicon layer 23 stacked thereon.
  • the p-type semiconductor layer 13 is a semiconductor layer of another conductivity type provided on the other main surface of the crystal substrate 11.
  • the other main surface is a main surface facing one main surface of the crystal substrate 11, and is the back surface of the crystal substrate 11 in this embodiment.
  • the one conductivity type is a conductivity type of the crystal substrate 11 and the other conductivity type is a conductivity type other than the one conductivity type, and thus is a p-type semiconductor layer.
  • the p-type semiconductor layer 13 includes an i-type amorphous silicon layer 24 and a p-type amorphous silicon layer 25 stacked thereon. When the n-type semiconductor layer 12 and the p-type semiconductor layer 13 are distinguished, the former is called a first semiconductor layer and the latter is called a second semiconductor layer.
  • the amorphous silicon layers 25 are stacked in this order.
  • the former is called a first i-type amorphous silicon layer and the latter is called a second i-type amorphous silicon layer.
  • the thickness of these laminated amorphous semiconductor thin layers is several nm to several tens of nm. For example, it can be about 5 to 20 nm.
  • the i-type amorphous silicon layers 22 and 24 are intrinsic amorphous silicon thin layers having a lower concentration of dopant that generates carriers than the n-type amorphous silicon layer 23 and the p-type amorphous silicon layer 25.
  • the first i-type amorphous silicon layer 22 and the second i-type amorphous silicon layer 24 can have the same composition.
  • the n-type amorphous silicon layer 23 is an amorphous silicon thin layer containing a group V metal atom at a predetermined concentration. P (phosphorus) is used as the group V metal atom.
  • the p-type amorphous silicon layer 25 is an amorphous silicon thin layer containing a group III metal atom at a predetermined concentration. B (boron) is used as the group III metal atom.
  • the photoelectric conversion part which has the n-type semiconductor layer 12 in the light-receiving surface side of the crystal substrate 11, and has the p-type semiconductor layer 13 in the back surface side can be manufactured with the following method as an example.
  • the crystal substrate 11 is placed in a vacuum chamber, and the i-type amorphous silicon layer 22 is laminated on the light receiving surface of the crystal substrate 11 by, for example, plasma CVD (chemical vapor deposition). Subsequently, an n-type amorphous silicon layer 23 is stacked on the i-type amorphous silicon layer 22. In this way, the n-type semiconductor layer 12 is formed on the light receiving surface.
  • plasma CVD chemical vapor deposition
  • the i-type amorphous silicon layer 24 and the p-type amorphous silicon layer 25 are sequentially laminated on the back surface of the crystal substrate 11 by, for example, a plasma CVD method.
  • a plasma CVD method instead of the plasma CVD method, another low pressure CVD method may be used.
  • a catalytic CVD method can be used.
  • silane gas SiH 4
  • hydrogen H 2
  • phosphine PH 3
  • diborane B 2 H 6
  • the n-type semiconductor layer 12 is formed on the entire light receiving surface of the crystal substrate 11 except for portions corresponding to the four corners 18, 19, 20, and 21 of the outer edge of the crystal substrate 11.
  • the crystal substrate 11 is held at a predetermined position of the plasma CVD apparatus.
  • the four light receiving surface sides of the four corners 18, 19, 20, and 21 of the crystal substrate 11 are separated from each other.
  • the holders 26, 27, 28, and 29 are pressed and held.
  • Four holders 26, 27, 28, and 29 may be used as one holder.
  • the locations corresponding to the four corners 18, 19, 20, and 21 of the crystal substrate 11 are shaded by the holders 26, 27, 28, and 29, and the non-film-formation regions 30, 31, 32, where the n-type semiconductor layer 12 is not formed. 33.
  • one of the four holders 29 is provided with an identification hole, and the n-type semiconductor layer 12 is formed at a location corresponding to the identification hole to form the identification mark 34.
  • the identification mark 34 can be omitted.
  • FIG. 1B shows the wraparound n-type semiconductor layers 35, 36, 37 and 38 formed on the side surface of the crystal substrate 11.
  • the p-type semiconductor layer 13 is formed on the entire back surface of the crystal substrate 11 except for portions corresponding to the four corners 18, 19, 20, and 21 of the outer edge of the crystal substrate 11.
  • the crystal substrate 11 is held at a predetermined position of the plasma CVD apparatus for forming the p-type semiconductor layer 13.
  • four holders 26, 27, 28, used for forming the n-type semiconductor layer 12 are used. 29 is used as it is, and the back side of the four corners 18, 19, 20, 21 of the crystal substrate 11 is pressed.
  • the locations corresponding to the four corners 18, 19, 20, and 21 of the crystal substrate 11 are shaded by the holders 26, 27, 28, and 29, and the non-deposited regions 39, 40, 41, where the p-type semiconductor layer 13 is not formed. 42.
  • An identification mark 43 is formed by the p-type semiconductor layer 13 corresponding to the identification hole provided in the holder 29. The identification mark 43 can be omitted.
  • FIG. 1C shows the wraparound p-type semiconductor layers 44, 45, 46 and 47 formed on the side surface of the crystal substrate 11.
  • the latter When distinguishing the non-deposition regions 39, 40, 41, and 42 of the p-type semiconductor layer 13 from the non-deposition regions 30, 31, 32, and 33 of the n-type semiconductor layer 12, the latter is designated as the first non-deposition region, and the former This is called a second non-film formation region.
  • the non-deposited regions 30, 31, 32, 33 of the n-type semiconductor layer 12 and the non-deposited regions 39, 40, 41, 42 of the p-type semiconductor layer 13 are When the manufacturing error is eliminated with respect to the crystal substrate 11, the positional relationship is reversed.
  • the n-type semiconductor layers 35, 36, 37, and 38 are formed on the side surface of the crystal substrate 11 from the light receiving surface side, and the p-type semiconductor layers 44, 45, 46, and 47 are formed from the back surface side. . Therefore, on the side surface of the crystal substrate 11, the overlap layer in which the wraparound n-type semiconductor layer 35 and the wraparound p-type semiconductor layer 44 overlap, the overlap layer in which the wraparound n-type semiconductor layer 36 and the wraparound p-type semiconductor layer 45 overlap, An overlapping layer in which the wraparound n-type semiconductor layer 38 and the wraparound p-type semiconductor layer 47 are overlapped is formed.
  • 1A illustrates a superposition layer 48 in which the wraparound n-type semiconductor layer 36 and the wraparound p-type semiconductor layer 45 overlap, and a superposition layer 49 in which the wraparound n-type semiconductor layer 38 and the wraparound p-type semiconductor layer 47 overlap.
  • the transparent conductive film 14 on the light receiving surface side is laminated on the first semiconductor layer on one main surface of the crystal substrate 11.
  • the transparent conductive film 14 on the light receiving surface side is formed on the light receiving surface of the crystal substrate 11.
  • the n-type semiconductor layer 12 is laminated on the n-type amorphous silicon layer 23 in detail.
  • the transparent conductive film 15 on the back surface side is stacked on the second semiconductor layer on the other main surface of the crystal substrate 11, and here, on the p-type semiconductor layer 13 on the back surface of the crystal substrate 11, in detail, p It is laminated on the type amorphous silicon layer 25.
  • the former is referred to as a first transparent conductive film
  • the latter is referred to as a second conductive film.
  • the transparent conductive film 14 on the light-receiving surface side is disposed on the inner side by an appropriate dimension from the outer edge of the crystal substrate 11. This dimension is set to a minimum value as long as it does not coincide with the outer shape of the crystal substrate 11 even if all manufacturing errors are included. That is, the transparent conductive film 14 is arranged regardless of the non-deposition regions 30, 31, 32, 33 of the n-type semiconductor layer 12. Therefore, when the undeposited regions 30, 31, 32, 33 are wide, the transparent conductive film 14 is provided on the undeposited regions 30, 31, 32, 33. In the example of FIG. 1B, the transparent conductive film 14 is provided on the non-film formation regions 32 and 33.
  • the transparent conductive film 15 on the back side is the same as the planar shape of the crystal substrate 11. That is, the transparent conductive film 15 is formed over the entire back surface of the crystal substrate 11.
  • the transparent conductive films 14 and 15 are made of, for example, metal oxides such as indium oxide (In 2 O 3 ), zinc oxide (ZnO), tin oxide (SnO 2 ), and titanium oxide (TiO 2 ) having a polycrystalline structure. Is a thin layer (TCO layer) configured to include at least one of them, and functions as a light-transmissive electrode unit. These metal oxides contain dopants such as tin (Sn), zinc (Zn), tungsten (W), antimony (Sb), titanium (Ti), aluminum (Al), cerium (Ce), and gallium (Ga). It may be doped. The concentration of the dopant can be 0 to 20% by mass.
  • the thickness of the transparent conductive films 14 and 15 is, for example, about 50 nm to 200 nm.
  • the transparent conductive films 14 and 15 can be formed using a sputtering apparatus.
  • FIG. 2 is a diagram in which the crystal substrate 11, the n-type semiconductor layer 12, and the p-type semiconductor layer 13 are extracted from the structure of the solar cell 10.
  • 2A is an enlarged sectional view of the side surface of the crystal substrate 11
  • FIG. 2B is an enlarged sectional view of the overlapping layer 49
  • FIG. 2C is an n-type semiconductor layer 12 and a p-type semiconductor on the side surface of the crystal substrate 11.
  • FIG. 6 is a diagram showing a thickness distribution of a layer 13.
  • the illustration of the texture structure on the surface of the crystal substrate 11 is omitted. Since the influence of the texture structure on the thickness distribution of the n-type semiconductor layer 12 and the p-type semiconductor layer 13 will be described with reference to FIG. 3, the influence of the texture structure on the thickness distribution is not considered here.
  • the n-type semiconductor layer 12 is formed from the direction of the light receiving surface side of the crystal substrate 11, the n-type semiconductor layer 12 is formed so as to go around the side surface of the crystal substrate 11. That is the wraparound n-type semiconductor layer 38.
  • the thickness t n is the thickest on the light receiving surface side of the side surface of the crystal substrate 11 and gradually decreases toward the back surface side. Assuming that the thickness of the n-type semiconductor layer 12 formed on the light-receiving surface is t n0 , the thickness t n of the wrap-around n-type semiconductor layer 38 on the side of the light-receiving surface on the side surface of the crystal substrate 11 is as shown in FIG. As shown in FIG. 2, the light receiving surface end is substantially t n0 and the back surface end is substantially zero (0).
  • the p-type semiconductor layer 13 is formed by film formation from the direction of the back surface side of the crystal substrate 11, the p-type semiconductor layer 13 is also formed so as to wrap around the side surface of the crystal substrate 11. That is the wraparound p-type semiconductor layer 47.
  • the thickness t p is thickest on the back surface side of the side surface of the crystal substrate 11 and gradually decreases toward the light receiving surface side. Assuming that the thickness of the p-type semiconductor layer 13 formed on the light receiving surface is t p0 , the thickness t p of the wraparound p-type semiconductor layer 47 on the back surface side of the side surface of the crystal substrate 11 is shown in FIG. As shown, it is approximately t p0 at the back surface end and approximately zero (0) at the light receiving surface end.
  • FIG. 2C shows the distribution of (t n + t p ) along the side surface of the crystal substrate 11.
  • the thickness t n of the n-type semiconductor layer 38 wraparound at the side surface is slightly thinner than t n0 at the light receiving surface end, wraparound thickness t p of the p-type semiconductor layer 47 is slightly thinner than t p0 at the back side end. Therefore, the thickness t n of the n-type semiconductor layer 38 wraparound at the side surface is thinner than t n0, the thickness t p of the wraparound p-type semiconductor layer 47 is thinner than t p0. Further, the total thickness (t n + t p ) of the semiconductor layer that has been wrapped is thicker than both t n0 and t p0 , but is thinner than (t n0 + t p0 ). Thus, the side surface of the crystal substrate 11 is covered with the wraparound semiconductor layer, and the crystal substrate 11 is not exposed.
  • the side surface of the crystal substrate 11 is covered with a semiconductor layer having a thickness in the range of about 20 to 40 nm. From the viewpoint of protecting the side surface of the crystal substrate 11, this thickness is not too thin and not too thick, and is an appropriate thickness. That is, the wraparound semiconductor layer can be used as it is as a protective film on the side surface of the crystal substrate 11.
  • FIG. 3 corresponds to FIG. 2 and is a view when the texture structure 50 formed on the surface of the crystal substrate 11 is taken into consideration.
  • 3A is an enlarged cross-sectional view of the side surface of the crystal substrate 11
  • FIG. 3B is a diagram illustrating the texture structure 50
  • FIG. 3C is an n-type semiconductor layer 12 and a p-type semiconductor layer on the side surface of the crystal substrate 11.
  • 13 is a diagram showing a thickness distribution of 13.
  • the n-type semiconductor layer 12 has a laminated structure of an i-type amorphous layer silicon layer 22 and an n-type amorphous layer silicon layer 23, and the p-type semiconductor layer 13 includes an i-type amorphous layer silicon layer 24 and a p-type layer.
  • the laminated amorphous silicon layer 25 has a laminated structure, the laminated structure is not shown in FIG.
  • the texture structure 50 is minute irregularities formed on the surface of the crystal substrate 11 by treating the crystal substrate 11 with an anisotropic etching solution such as KOH.
  • the convex portion has a quadrangular pyramid shape as shown in FIG. The extending direction of one side of the bottom surface of the quadrangular pyramid is parallel to the Y direction of the crystal substrate 11 or parallel to the direction perpendicular thereto. The same applies to the side surface of the crystal substrate 11.
  • the length of one side of the base of the quadrangular pyramid is about 2 to 5 ⁇ m
  • the angle between the base of the quadrangular pyramid and the slope is 60 degrees
  • the vertical height of the apex with the base of the quadrangular pyramid as the reference plane The length is (3 0.5 ) times the length of one side of the bottom surface.
  • the texture structure 50 has a slope inclined at a constant angle with respect to the surface of the crystal substrate 11, the n-type semiconductor layer 12 and the p-type semiconductor layer 13 are formed on the slope. Therefore, the film thicknesses t n and t p are values measured along the normal direction of the slope of the texture structure 50.
  • the n-type semiconductor layer 12 is formed from the direction of the light receiving surface side of the crystal substrate 11, the n-type semiconductor layer 12 is also formed so as to go around the side surface of the crystal substrate 11. Since the texture structure 50 has a quadrangular pyramid shape, the n-type semiconductor layer 12 is formed so as to cover the entire surface of the quadrangular pyramid shape on the light receiving surface of the crystal substrate 11. On the side surface of the crystal substrate 11, one of the four slopes of the quadrangular pyramid shape of the texture structure 50 faces the light receiving surface side, the other one faces the back surface side, and the remaining two face the intermediate direction. Therefore, the n-type semiconductor layer 12 is formed on the surface facing the light receiving surface side of the texture structure 50 and is not formed on the surface facing the back surface side.
  • the p-type semiconductor layer 13 is formed from the direction of the back side of the crystal substrate 11, the p-type semiconductor layer 13 is also formed around the side surface of the crystal substrate 11. Since the texture structure 50 has a quadrangular pyramid shape, the p-type semiconductor layer 13 is formed on the back surface of the crystal substrate 11 so as to cover the entire surface of the quadrangular pyramid shape. On the side surface of the crystal substrate 11, one of the four slopes of the quadrangular pyramid shape of the texture structure 50 faces the back surface side, the other one faces the light receiving surface side, and the other two face the intermediate direction. Therefore, the p-type semiconductor layer 13 is formed on the surface facing the back surface side of the texture structure 50 and is not formed on the surface facing the back surface side.
  • FIG. 3B shows a region 51 where the n-type semiconductor layer 12 is formed and a region 52 where the p-type semiconductor layer 13 is formed in the texture structure 50 on the side surface of the crystal substrate 11.
  • the texture structure 50 is divided into two regions: a region 51 where the n-type semiconductor layer 12 is formed and a region 52 where the p-type semiconductor layer 13 is formed.
  • the two regions are distinguished, and the region 51 is referred to as a first region 51 and the region 52 is referred to as a second region 52.
  • the thickness t n in the normal direction of the wraparound n-type semiconductor layer 38 that wraps around the side surface of the crystal substrate 11 is the thickest on the light receiving surface side of the side surface of the crystal substrate 11 and gradually increases toward the back surface side. getting thin. If the thickness in the normal direction of the n-type semiconductor layer 12 formed on the light receiving surface is t n0 , the thickness t n in the normal direction of the wrap-around n-type semiconductor layer 38 on the side surface of the crystal substrate 11 is As shown in FIG. 3C, it is substantially t n0 at the light receiving surface end face and substantially zero (0) at the back face end face.
  • the thickness t p in the normal direction of the wraparound p-type semiconductor layer 47 that wraps around the side surface of the crystal substrate 11 is thickest on the back surface side of the side surface of the crystal substrate 11 and gradually decreases toward the light receiving surface side. Assuming that the thickness in the normal direction of the p-type semiconductor layer 13 formed on the light receiving surface is t p0 , the thickness t p of the wraparound p-type semiconductor layer 47 from the back surface side on the side surface of the crystal substrate 11 is As shown in FIG. 3 (c), it is substantially t p0 at the back surface end and substantially zero (0) at the light receiving surface end.
  • FIG. 3C shows the thickness distribution of the wraparound semiconductor layer along the side surface of the crystal substrate 11.
  • the first region 51 where the n-type semiconductor layer 12 is formed and the p-type semiconductor layer 13 where the p-type semiconductor layer 13 is formed are formed from the light receiving surface end toward the back surface end. Two regions 52 are alternately repeated.
  • the thickness t n in the normal direction of the wraparound n-type semiconductor layer 38 on the side surface is slightly thinner than t n0 at the end of the light receiving surface, and the thickness t p in the normal direction of the wraparound p-type semiconductor layer 47 is t at the end of the back surface. Slightly thinner than p0 . Therefore, the thickness t n in the normal direction of the wrap-around n-type semiconductor layer 38 on the side surface is smaller than t n0 , and the thickness t p in the normal direction of the wrap-around p-type semiconductor layer 47 is smaller than t p0 .
  • the total value (t n + t p ) of the thicknesses in the normal direction of the semiconductor layers formed around one texture structure 50 is thicker than t n0 and thicker than t p0 , but (t n0 + T p0 ).
  • the side surface of the crystal substrate 11 is covered with the wraparound semiconductor layer, and the crystal substrate 11 is not exposed.
  • the total value of the thicknesses in the normal direction of the semiconductor layers formed around one texture structure 50 on the side surface of the crystal substrate 11 is about 20 It is covered with a semiconductor layer having a thickness in the range of ⁇ 40 nm. From the viewpoint of protecting the side surface of the crystal substrate 11, this thickness is not too thin and not too thick, and is an appropriate thickness. That is, the wraparound semiconductor layer can be used as it is as a protective film on the side surface of the crystal substrate 11.
  • the photoelectric conversion part having a structure in which the amorphous silicon thin layers are laminated on both surfaces of the crystal substrate 11 is illustrated, but the structure of the photoelectric conversion part is not limited thereto.
  • the photoelectric conversion unit has, for example, a structure having no i-type amorphous silicon layer, n-type amorphous silicon layer, or p-type amorphous silicon layer, or a structure using a semiconductor other than silicon (for example, gallium arsenide). It can also be.
  • the amorphous silicon in this embodiment includes amorphous silicon including crystal grains.
  • the one conductivity type is n-type and the other conductivity type is p-type.
  • the one conductivity type may be p-type and the other conductivity type may be n-type.
  • one main surface is the light receiving surface and the other main surface is the back surface, this may be reversed so that one main surface is the back surface and the other main surface is the light receiving surface.
  • the crystal substrate is an octagon with four corners cut off, it may have a rectangular shape with four corners not cut, a polygon other than an octagon, a round shape other than a rectangular shape, or an elliptical shape. Good.
  • the crystal substrate 11 may be configured to hold at least one location. It is good also as a structure which hold

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Abstract

　太陽電池１０は、一導電型としてｎ型の導電型を有する結晶基板１１と、結晶基板１１の一主面としての受光面上に形成されるｎ型半導体層１２と、結晶基板１１の一主面としての裏面上に形成されるｐ型半導体層１３と、を有し、ｎ型半導体層１２とｐ型半導体層１３は、結晶基板１１の主面と交差する側面の一部を覆い、側面におけるｎ型半導体層の法線方向の厚さは受光面上のｎ型半導体層１２の法線方向の厚さよりも薄く、側面におけるｐ型半導体層１３の法線方向の厚さは裏面上のｐ型半導体層１３の法線方向の厚さよりも薄い。

Description

太陽電池
　本開示は、太陽電池に関する。
　特許文献１には、光起電力素子において表裏面の半導体層が端面に回り込むことによる特性低下を低減するために、表面側の半導体層は基板の略全面に形成され、裏面側の半導体層は基板より小面積に形成される構造を開示している。
　特許文献２には、光起電力素子において、例えばｎ基板の第一主面にｎ型半導体層を形成し、第二主面にｐ型半導体層を形成するとき、導電型の異なる半導体層の形成順序によって、ｎ基板の側面及び周端部には、ｎ基板－ｎ層－ｐ層の整流接合か、ｎ基板－ｐ層－ｎ層の逆接合かが形成される。前者のように形成することで、基板の全面に整流接合が備えられることになり、逆接合によるキャリア移動の抑制等の悪影響が生じないと述べている。
特開２００１－０４４４６１号公報 特開平１１－２５１６０９号公報
　太陽電池において、受光面や裏面と異なり、基板の側面は露出していて、保護膜がない状態である。基板の側面に受光面側の半導体層や裏面側の半導体層が回り込めば基板の側面が覆われるが、特許文献１，２に記載されるように、太陽電池の特性低下が生じる恐れがある。
　即ち、太陽電池の特性低下を生じさせないで、結晶基板の側面に保護膜を形成することが求められる。
　本開示の一態様である太陽電池は、一導電型を有する結晶基板と、結晶基板の一主面上に形成された一導電型を有する第１半導体層と、結晶基板の他主面上に形成された他導電型を有する第２半導体層と、を有し、第１半導体層と第２半導体層は、結晶基板の主面と交差する側面の一部を覆い、側面における第１半導体層の法線方向の厚さは一主面上の第１半導体層の法線方向の厚さよりも薄く、側面における第２半導体層の法線方向の厚さは他主面上の第２半導体層の法線方向の厚さよりも薄い。
　本開示の一態様によれば、太陽電池の特性低下を生じさせないで、結晶基板の側面に保護膜を形成することができる。
実施の形態における太陽電池を示す図で、（ａ）は断面図、（ｂ）は受光面側を示す平面図、（ｃ）は裏面側を示す平面図、（ｄ）は（ｂ）のＤ－Ｄ線における断面図である。（ｂ），（ｃ）では集電電極の図示を省略した。 実施の形態の太陽電池における側面の拡大図である。（ａ）は断面図、（ｂ）は（ａ）の一部拡大図、（ｃ）は（ａ）における半導体層の膜厚分布を示す図である。 実施の形態の太陽電池において、結晶基板にテクスチャ構造を有するときの図２に対応する図である。（ａ）は断面図、（ｂ）はテクスチャ構造の拡大図、（ｃ）は（ａ）における半導体層の膜厚分布を示す図である。
　以下に図面を用いて、実施形態の一例について詳細に説明する。以下で述べる形状、寸法、材質等は、説明のための例示であって、これらに限定するものではない。以下の図面は、説明のための模式図であり、縦横高さに関する縮尺は、実際の太陽電池等の縦横高さと異なる場合がある。具体的な縦横高さに関する縮尺は、以下の説明を参酌して判断される。
　図１は、太陽電池１０を示す図である。この太陽電池１０は、一主面側からｎ型非晶質半導体層を結晶基板の側面に回り込ませ、その上に他主面側からｐ型非晶質半導体層を結晶基板の側面に回り込ませて重ねただけでは、リークがほとんど発生しないことを実験的に確かめた知見に基づくものである。このように、結晶基板の側面において、一主面のｎ型非晶質半導体層と他主面のｐ型非晶質半導体層を重ねてもリークが発生しないのであれば、これを側面の保護膜に用いることができると考えた。以下の構成は、この知見に基づくものである。
　図１（ａ）は断面図である。（ａ）において上方側が受光面側、下方側が裏面側である。（ｂ）は受光面側を示す平面図、（ｃ）は裏面側を示す平面図、（ｄ）は（ｂ）のＤ－Ｄ線における断面図である。なお（ｄ）は、（ａ）と配列方向を逆とし、上方側を裏面側、下方側を受光面側として示した。また、（ｂ）と（ｃ）も表裏反転となるので、配列の上下方向をＹ方向とし、紙面の上方側を（ｂ）では＋Ｙ方向、（ｃ）では－Ｙ方向として、符号で区別した。
　このように、断面図はどこで切断するかで変わるが、（ａ）は（ｂ）のＡ－Ａ線における断面図に相当する。ここで、「受光面」とは、太陽電池１０において外部から光が主に入射する面を意味する。例えば、太陽電池１０に入射する光のうち５０％超過～１００％が受光面側から入射する。また、「裏面」とは、受光面とは反対側の面を意味する。
　太陽電池１０は、太陽光等の光を受光してキャリアである電子および正孔を生成し、生成されたキャリアを収集し、収集したキャリアを集電して外部へ取り出す。キャリアを生成する部分は光電変換部と呼ばれ、ｎ型単結晶シリコン基板１１と、ｎ型半導体層１２と、ｐ型半導体層１３で構成される。キャリアを収集するのは、受光面側の透明導電膜１４と裏面側の透明導電膜１５である。収集したキャリアを集電するのは、受光面側の集電電極１６と裏面側の集電電極１７である。以下では、ｎ型単結晶シリコン基板１１を、単に結晶基板１１と呼ぶ。
　受光面側の集電電極１６は受光面側の透明導電膜１４上に設けられるキャリアの集電電極である。裏面側の集電電極１７は裏面側の透明導電膜１５上に設けられるキャリアの集電電極である。これらは、例えば、バインダー樹脂中に銀（Ａｇ）等の導電性粒子を分散させた導電性ペーストを透明導電膜１４，１５上に所望のパターンでスクリーン印刷して形成される細線状の電極部である。または、スクリーン印刷の代わりに、各種スパッタ法、各種蒸着法、各種メッキ法等を用いて集電電極１６，１７を形成してもよい。図１（ａ），（ｄ）に示すように集電電極１６，１７をそれぞれ、複数設けてもよい。
　本開示は、光電変換部と透明導電膜１４，１５の構成に関するものであるので、集電電極１６，１７については、上記の説明に止め、またそれらの図示は、図１（ａ），（ｄ）に示すのみとした。以下に、各構成について詳細に説明を行う。
　光電変換部を構成する結晶基板１１は、一導電型を有する単結晶半導体基板である。ここでは、一導電型をｎ型とし、単結晶半導体を単結晶シリコンとする。結晶基板１１の平面形状は、図１（ｂ），（ｃ）に示すように、矩形形状の外縁の４隅部１８，１９，２０，２１を切り欠いた８角形状を有する。寸法の一例を述べると、一辺が約１００ｍｍから約２００ｍｍで、各４隅において辺方向に沿って約５ｍｍから約１６ｍｍ程度の長さで切り欠かれる。薄型の太陽電池１０の場合、厚さは、例えば、約７５μｍから約２００μｍ程度である。これらの寸法は一例であって、これ以外の値であってもよい。
　結晶基板１１の表面、すなわち、受光面、裏面、側面は、それぞれテクスチャ構造を有する。図１、図２では、テクスチャ構造の図示を省略するが、後述する図３において詳述する。ここで、「テクスチャ構造」とは、表面反射を抑制し、光電変換部の光吸収量を増大させる凹凸構造である。各種の膜が積層される方向に沿った結晶基板１１の厚さは、数十～数百μｍであり、テクスチャ構造の凹凸高さは、数μｍである。
　ｎ型半導体層１２は、結晶基板１１の一主面に設けられる一導電型の半導体層である。一主面を受光面とすると、一導電型は、結晶基板１１の導電型であるので、ここでは、受光面に設けられるｎ型の半導体層である。ｎ型半導体層１２は、ｉ型非晶質シリコン層２２と、その上に積層されたｎ型非晶質シリコン層２３で構成される。
　ｐ型半導体層１３は、結晶基板１１の他主面に設けられる他導電型の半導体層である。他主面は結晶基板１１の一主面と対向する主面であり、本実施形態の場合、結晶基板１１の裏面である。また、一導電型は、結晶基板１１の導電型であり、他導電型は一導電型でない導電型であるため、ｐ型の半導体層である。ｐ型半導体層１３は、ｉ型非晶質シリコン層２４と、その上に積層されたｐ型非晶質シリコン層２５で構成される。ｎ型半導体層１２とｐ型半導体層１３を区別するときは、前者を第１半導体層、後者を第２半導体層と呼ぶ。
　図１（ａ）では、受光面側から裏面側に向かって、ｎ型非晶質シリコン層２３、ｉ型非晶質シリコン層２２、結晶基板１１、ｉ型非晶質シリコン層２４、ｐ型非晶質シリコン層２５の順に積層される。ｉ型非晶質シリコン層２２，２４を区別するときは、前者を第一ｉ型非晶質シリコン層、後者を第二ｉ型非晶質シリコン層と呼ぶ。これらの積層された非晶質半導体薄層の厚さは、数ｎｍ～数十ｎｍである。例えば、約５～２０ｎｍとすることができる。
　ｉ型非晶質シリコン層２２，２４は、ｎ型非晶質シリコン層２３およびｐ型非晶質シリコン層２５よりもキャリアを発生させるドーパントの濃度が低い真性非晶質シリコン薄層である。第一ｉ型非晶質シリコン層２２と第二ｉ型非晶質シリコン層２４は、同一の組成を有するものとできる。ｎ型非晶質シリコン層２３は、Ｖ族の金属原子を所定の濃度で含む非晶質シリコン薄層である。Ｖ族の金属原子としては、Ｐ（リン）が用いられる。ｐ型非晶質シリコン層２５は、ＩＩＩ族の金属原子を所定の濃度で含む非晶質シリコン薄層である。ＩＩＩ族の金属原子としては、Ｂ（ボロン）が用いられる。
　結晶基板１１の受光面側にｎ型半導体層１２を有し、裏面側にｐ型半導体層１３を有する光電変換部は、一例として、以下の方法で製造できる。
　まず、結晶基板１１を真空チャンバ内に設置し、例えば、プラズマＣＶＤ（化学気相成長法）法により、結晶基板１１の受光面上にｉ型非晶質シリコン層２２を積層する。続いて、ｉ型非晶質シリコン層２２上にｎ型非晶質シリコン層２３を積層する。このようにしてｎ型半導体層１２が受光面上に形成される。
　一方、結晶基板１１の裏面上にも、例えば、プラズマＣＶＤ法でｉ型非晶質シリコン層２４およびｐ型非晶質シリコン層２５を順に積層する。このようにして、ｐ型半導体層１３が裏面状に形成される。プラズマＣＶＤ法に代えて、他の減圧ＣＶＤ法を用いてもよい。例えば、触媒ＣＶＤ法を用いることができる。
　ｉ型非晶質シリコン層２２，２４の積層工程では、例えば、シランガス（ＳｉＨ4）を原料ガスとして使用する。ｎ型非晶質シリコン層２３の積層工程では、シラン（ＳｉＨ4）、水素（Ｈ2）、およびホスフィン（ＰＨ3）を原料ガスとする。ｐ型非晶質シリコン層２５の積層工程では、ジボラン（Ｂ2Ｈ6）を原料ガスとする。
　ｎ型半導体層１２は、結晶基板１１の外縁の４隅部１８，１９，２０，２１に対応する箇所を除き、結晶基板１１の受光面の全面に形成される。ｎ型半導体層１２の形成のためにプラズマＣＶＤ装置の所定の位置に結晶基板１１を保持するが、ここでは、結晶基板１１の４隅部１８，１９，２０，２１の受光面側を４つの保持具２６，２７，２８，２９（図２参照）で押えて保持するものとした。４つの保持具２６，２７，２８，２９を１つの保持具としてもよい。
　結晶基板１１の４隅部１８，１９，２０，２１に対応する箇所は、保持具２６，２７，２８，２９の陰となり、ｎ型半導体層１２が形成されない未成膜領域３０，３１，３２，３３となる。なお、４つの内の１つの保持具２９に識別穴が設けられ、その識別穴に対応する箇所にはｎ型半導体層１２が形成され、識別マーク３４となる。識別マーク３４は省略することができる。
　それ以外は保持具２６，２７，２８，２９の陰にならないので、ｎ型半導体層１２は、結晶基板１１の受光面から連続して側面にも回り込んで形成される。図１（ｂ）に、結晶基板１１の側面に形成された回り込みｎ型半導体層３５，３６，３７，３８を示した。
　ｐ型半導体層１３は、結晶基板１１の外縁の４隅部１８，１９，２０，２１に対応する箇所を除き、結晶基板１１の裏面の全面に形成される。ｐ型半導体層１３の形成のためにプラズマＣＶＤ装置の所定の位置に結晶基板１１を保持するが、ここでは、ｎ型半導体層１２形成の際に用いられる４つの保持具２６，２７，２８，２９をそのまま用いて、結晶基板１１の４隅部１８，１９，２０，２１の裏面側を押えるものとした。結晶基板１１の４隅部１８，１９，２０，２１に対応する箇所は、保持具２６，２７，２８，２９の陰となり、ｐ型半導体層１３が形成されない未成膜領域３９，４０，４１，４２となる。なお、保持具２９に設けられる識別穴に対応して、識別マーク４３がｐ型半導体層１３によって形成される。識別マーク４３は省略することができる。
　それ以外は保持具の陰にならないので、ｐ型半導体層１３は、結晶基板１１の受光面から連続して側面にも回り込んで形成される。図１（ｃ）に、結晶基板１１の側面に形成された回り込みｐ型半導体層４４，４５，４６，４７を示した。
　ｐ型半導体層１３の未成膜領域３９，４０，４１，４２と、ｎ型半導体層１２の未成膜領域３０，３１，３２，３３を区別するときは、後者を第１未成膜領域、前者を第２未成膜領域と呼ぶ。
　図１（ｂ），（ｃ）に示されるように、ｎ型半導体層１２の未成膜領域３０，３１，３２，３３と、ｐ型半導体層１３の未成膜領域３９，４０，４１，４２は、結晶基板１１に対し、製造誤差をなくした場合、表裏反転の位置関係を有することになる。
　一方で、結晶基板１１の側面には、受光面側から回り込みｎ型半導体層３５，３６，３７，３８が形成され、裏面側から回り込みｐ型半導体層４４，４５，４６，４７が形成される。したがって、結晶基板１１の側面には、回り込みｎ型半導体層３５と回り込みｐ型半導体層４４が重なった重畳層、回り込みｎ型半導体層３６と回り込みｐ型半導体層４５が重なった重畳層、回り込みｎ型半導体層３７と回り込みｐ型半導体層４６が重なった重畳層、回り込みｎ型半導体層３８と回り込みｐ型半導体層４７が重なった重畳層が形成される。図１（ａ）には、回り込みｎ型半導体層３６と回り込みｐ型半導体層４５が重なった重畳層４８と回り込みｎ型半導体層３８と回り込みｐ型半導体層４７が重なった重畳層４９を図示した。実験結果によれば、これらの重畳層が形成されても、リークには影響を及ぼさないことが確認された。
　受光面側の透明導電膜１４は、結晶基板１１の一主面上において第一半導体層に積層されるもので、ここでは、受光面側の透明導電膜１４は、結晶基板１１の受光面において、ｎ型半導体層１２上、詳しくは、ｎ型非晶質シリコン層２３上に積層される。裏面側の透明導電膜１５は、結晶基板１１の他主面上において第二半導体層に積層されるもので、ここでは、結晶基板１１の裏面において、ｐ型半導体層１３上、詳しくは、ｐ型非晶質シリコン層２５上に積層される。受光面側の透明導電膜１４と裏面側の透明導電膜１５を区別するときは、前者を第１透明導電膜、後者を第２導電膜と呼ぶ。
　受光面側の透明導電膜１４は、図１（ｃ）に示すように、結晶基板１１の外縁から適当な寸法だけ内側に配置される。この寸法は、製造上の誤差を全部含めても結晶基板１１の外形と一致しない限度で最小の値に設定される。すなわち、ｎ型半導体層１２の未成膜領域３０，３１，３２，３３とは無関係に透明導電膜１４の配置が行われる。したがって、未成膜領域３０，３１，３２，３３が広い場合には、透明導電膜１４は、未成膜領域３０，３１，３２，３３上に設けられる。図１（ｂ）の例では、未成膜領域３２，３３上に透明導電膜１４が設けられる。一方、裏面側の透明導電膜１５は、結晶基板１１の平面形状と同じである。つまり、結晶基板１１の裏面全面に渡って、透明導電膜１５が形成される。
　かかる透明導電膜１４，１５は、例えば、多結晶構造を有する酸化インジウム（Ｉｎ2Ｏ3）、酸化亜鉛（ＺｎＯ）、酸化錫（ＳｎＯ2）、および酸化チタン（ＴｉＯ2）等の金属酸化物のうちの少なくとも１つを含んで構成される薄層（ＴＣＯ層）であって、光透過性の電極部として機能する。これらの金属酸化物に、錫（Ｓｎ）、亜鉛（Ｚｎ）、タングステン（Ｗ）、アンチモン（Ｓｂ）、チタン（Ｔｉ）、アルミニウム（Ａｌ）、セリウム（Ｃｅ）、ガリウム（Ｇａ）などのドーパントがドープされていてもよい。ドーパントの濃度は、０～２０質量％とすることができる。透明導電膜１４，１５の厚さは、例えば、５０ｎｍ～２００ｎｍ程度である。透明導電膜１４，１５は、スパッタ装置を用いて形成できる。
　図２は、太陽電池１０の構造のなかで、結晶基板１１とｎ型半導体層１２とｐ型半導体層１３を抜き出した図である。図２（ａ）は、結晶基板１１の側面の拡大断面図、（ｂ）は、重畳層４９の拡大断面図、（ｃ）は、結晶基板１１の側面におけるｎ型半導体層１２とｐ型半導体層１３の厚さ分布を示す図である。なお、ここでは、結晶基板１１の表面におけるテクスチャ構造の図示を省略した。テクスチャ構造によるｎ型半導体層１２とｐ型半導体層１３の厚さ分布への影響は、次の図３で説明するので、ここでは、テクスチャ構造による厚さ分布への影響を考慮していない。
　ｎ型半導体層１２は、結晶基板１１の受光面側の方向から成膜されるので、結晶基板１１の側面にも回り込んで成膜される。それが回り込みｎ型半導体層３８である。その厚さｔnは、結晶基板１１の側面の受光面側が最も厚く、裏面側に向かうにつれて次第に薄くなる。受光面上に成膜されるｎ型半導体層１２の厚さをｔn0とすると、結晶基板１１の側面における受光面側の回り込みｎ型半導体層３８の厚さｔnは、図２（ｃ）に示すように、受光面端においてほぼｔn0で、裏面端においてほぼ零（０）である。
　ｐ型半導体層１３は、結晶基板１１の裏面側の方向からの成膜によって形成されるので、結晶基板１１の側面にも回り込んで形成される。それが回り込みｐ型半導体層４７である。その厚さｔpは、結晶基板１１の側面の裏面側が最も厚く、受光面側に向かうにつれて次第に薄くなる。受光面上に成膜されるｐ型半導体層１３の厚さをｔp0とすると、結晶基板１１の側面における裏面側の回り込みｐ型半導体層４７の厚さｔpは、図２（ｃ）に示すように、裏面端においてほぼｔp0で、受光面端においてほぼ零（０）である。
　結晶基板１１の側面には、ｎ型半導体層１２もｐ型半導体層１３も回り込むので、回り込んだ半導体層の全体の厚さは、（回り込みｎ型半導体層３８の厚さｔn＋回り込みｐ型半導体層４７の厚さｔp）である。図２（ｃ）に結晶基板１１の側面に沿った（ｔn＋ｔp）の分布を示した。
　側面における回り込みｎ型半導体層３８の厚さｔnは、受光面端においてｔn0よりやや薄く、回り込みｐ型半導体層４７の厚さｔpは、裏面端においてｔp0よりやや薄い。したがって、側面における回り込みｎ型半導体層３８の厚さｔnは、ｔn0より薄く、回り込みｐ型半導体層４７の厚さｔpは、ｔp0より薄い。また、回り込んだ半導体層の全体の厚さ（ｔn＋ｔp）は、ｔn0およびｔp0のいずれよりも厚いが、（ｔn0＋ｔp0）よりは薄い。このように、結晶基板１１の側面は、回り込み半導体層で覆われ、結晶基板１１が露出しない。
　例えば、ｔn0とｔp0を、それぞれ約２０ｎｍとすると、結晶基板１１の側面は、約２０～４０ｎｍの範囲の厚さの半導体層で覆われることになる。この厚さは、結晶基板１１の側面の保護の観点から見て、薄すぎず、厚すぎず、適切な厚さである。すなわち、回り込み半導体層を、結晶基板１１の側面の保護膜としてそのまま用いることができる。
　図３は、図２に対応し、結晶基板１１の表面に形成されるテクスチャ構造５０を考慮したときの図である。図３（ａ）は、結晶基板１１の側面の拡大断面図、（ｂ）は、テクスチャ構造５０を示す図、（ｃ）は、結晶基板１１の側面におけるｎ型半導体層１２とｐ型半導体層１３の厚さ分布を示す図である。なお、ｎ型半導体層１２は、ｉ型非晶層シリコン層２２とｎ型非晶層シリコン層２３の積層構造を有し、ｐ型半導体層１３は、ｉ型非晶層シリコン層２４とｐ型非晶層シリコン層２５の積層構造を有するが、図３では、これらの積層構造の図示を省略した。
　テクスチャ構造５０は、結晶基板１１を、例えばＫＯＨのような異方性エッチング液で処理することで結晶基板１１の表面に形成される微小凹凸である。凸部は、図３（ｂ）に示すように四角錐の形状を有する。四角錐の底面の一辺の延びる方向は、結晶基板１１のＹ方向に平行、またはこれに直交する方向に平行である。結晶基板１１の側面においても同様である。四角錐の寸法の一例を挙げると、四角錐の底面の一辺の長さが約２～５μｍ、四角錐の底面と斜面のなす角度は６０度、四角錐の底面を基準面として頂点の垂直高さは、底面の一辺の長さの（３0.5）倍である。
　テクスチャ構造５０は、結晶基板１１の表面に対し一定角度で傾斜する斜面を有するので、ｎ型半導体層１２、ｐ型半導体層１３は、その斜面上に形成される。そこで、その膜厚ｔn，ｔpは、テクスチャ構造５０の斜面の法線方向に沿って測った値とする。
　ｎ型半導体層１２は、結晶基板１１の受光面側の方向から成膜されるので、結晶基板１１の側面にも回り込んで成膜される。テクスチャ構造５０は四角錐形状であるので、結晶基板１１の受光面上では、ｎ型半導体層１２は四角錐形状の全面を覆って形成される。結晶基板１１の側面では、テクスチャ構造５０の四角錐形状の４つの斜面のうち１つは受光面側を向くが、他の１つは裏面側を向き、残る２つはその中間方向を向く。したがって、ｎ型半導体層１２は、テクスチャ構造５０の受光面側を向く面に形成され、その裏面側を向く面には形成されない。
　同様に、ｐ型半導体層１３は、結晶基板１１の裏面側の方向から成膜されるので、結晶基板１１の側面にも回り込んで成膜される。テクスチャ構造５０は四角錐形状であるので、結晶基板１１の裏面上では、ｐ型半導体層１３は四角錐形状の全面を覆って形成される。結晶基板１１の側面では、テクスチャ構造５０の四角錐形状の４つの斜面のうち１つは裏面側を向くが、他の１つは受光面側を向き、残る２つはその中間方向を向く。したがって、ｐ型半導体層１３は、テクスチャ構造５０の裏面側を向く面に形成され、その裏面側を向く面には形成されない。
　図３（ｂ）に、結晶基板１１の側面におけるテクスチャ構造５０において、ｎ型半導体層１２が形成される領域５１と、ｐ型半導体層１３が形成される領域５２を示した。このように、結晶基板１１の側面において、テクスチャ構造５０は、ｎ型半導体層１２が形成される領域５１と、ｐ型半導体層１３が形成される領域５２の２つの領域に分けられる。２つの領域を区別して、以下では、領域５１を第１領域５１、領域５２を第２領域５２と呼ぶ。
　図２の説明と同様に、結晶基板１１の側面に回り込む回り込みｎ型半導体層３８の法線方向の厚さｔnは、結晶基板１１の側面の受光面側が最も厚く、裏面側に向かうにつれて次第に薄くなる。受光面上に成膜されるｎ型半導体層１２の法線方向の厚さをｔn0とすると、結晶基板１１の側面における回り込みｎ型半導体層３８の法線方向の厚さｔnは、図３（ｃ）に示すように、受光面端面においてほぼｔn0で、裏面端面においてほぼ零（０）である。
　また、結晶基板１１の側面に回り込む回り込みｐ型半導体層４７の法線方向の厚さｔpは、結晶基板１１の側面の裏面側が最も厚く、受光面側に向かうにつれて次第に薄くなる。受光面上に成膜されるｐ型半導体層１３の法線方向の厚さをｔp0とすると、結晶基板１１の側面における裏面側からの回り込みｐ型半導体層４７の厚さｔpは、図３（ｃ）に示すように、裏面端においてほぼｔp0で、受光面端においてほぼ零（０）である。
　結晶基板１１の側面には、ｎ型半導体層１２もｐ型半導体層１３も回り込むが、回り込みｎ型半導体層３８はテクスチャ構造５０の領域２には形成されず、回り込みｐ型半導体層３８はテクスチャ構造５０の領域１には形成されない。図３（ｃ）に結晶基板１１の側面に沿った回り込み半導体層の厚さ分布を示す。この図に示されるように、結晶基板１１の側面において、受光面端から裏面端に向かって、ｎ型半導体層１２が形成される第１領域５１と、ｐ型半導体層１３が形成される第２領域５２が交互に繰り返される。
　側面における回り込みｎ型半導体層３８の法線方向の厚さｔnは、受光面端においてｔn0よりやや薄く、回り込みｐ型半導体層４７の法線方向の厚さｔpは、裏面端においてｔp0よりやや薄い。したがって、側面における回り込みｎ型半導体層３８の法線方向の厚さｔnは、ｔn0より薄く、回り込みｐ型半導体層４７の法線方向の厚さｔpは、ｔp0より薄い。また、１つのテクスチャ構造５０に回り込んで形成される半導体層の法線方向の厚さの合計値（ｔn＋ｔp）は、ｔn0よりも厚く、ｔp0よりも厚いが、（ｔn0＋ｔp0）よりは薄い。このように、結晶基板１１の側面は、回り込み半導体層で覆われ、結晶基板１１が露出しない。
　例えば、ｔn0とｔp0を、それぞれ約２０ｎｍとすると、結晶基板１１の側面において、１つのテクスチャ構造５０に回り込んで形成される半導体層の法線方向の厚さの合計値は、約２０～４０ｎｍの範囲の厚さの半導体層で覆われることになる。この厚さは、結晶基板１１の側面の保護の観点から見て、薄すぎず、厚すぎず、適切な厚さである。すなわち、回り込み半導体層を、結晶基板１１の側面の保護膜としてそのまま用いることができる。
　上記では、結晶基板１１の両面に非晶質シリコン薄層が積層された構造の光電変換部を例示したが、光電変換部の構造はこれに限定されない。光電変換部は、例えば、ｉ型非晶質シリコン層やｎ型非晶質シリコン層、ｐ型非晶質シリコン層を有さない構造、シリコン以外の半導体（例えば、ガリウムヒ素）を用いた構造とすることもできる。なお、本実施形態における非晶質シリコンとは、結晶粒を含んだ非晶質シリコンをも含む。
　また、上記では、一導電型をｎ型、他導電型をｐ型としたが、これを逆にして、一導電型をｐ型、他導電型をｎ型としてもよい。また、一主面を受光面、他主面を裏面としたが、これを逆にして、一主面を裏面、他主面を受光面としてもよい。
　また、結晶基板を４隅が切り欠かれた８角形としたが、４隅が切り欠かれない矩形形状、８角形以外の多角形形状、矩形形状以外の丸形形状や楕円形状であってもよい。
　加えて上記実施形態では、結晶基板１１の４隅部１８，１９，２０，２１を保持する構成としたが、結晶基板１１の少なくとも１箇所を保持する構成とすればよく、例えば、結晶基板１１の隅部１８，１９の２箇所を保持する構成としてもよい。
　１０　太陽電池、１１　結晶基板、１２　ｎ型半導体層、１３　ｐ型半導体層、１４，１５　透明導電膜、１６，１７　集電電極、１８，１９，２０，２１　隅部、２２，２４　ｉ型非晶質シリコン層、２３　ｎ型非晶質シリコン層、２５　ｐ型非晶質シリコン層、２６，２７，２８，２９　保持具、３０，３１，３２，３３，３９，４０，４１，４２　未成膜領域、３４，４３　識別マーク、３５，３６，３７，３８　回り込みｎ型半導体層、４４，４５，４６，４７　回り込みｐ型半導体層、４８，４９　重畳層、５０　テクスチャ構造、５１　（第１）領域、５２　（第２）領域。

Claims (8)

  1. 　一導電型を有する結晶基板と、
    　前記結晶基板の一主面上に形成された前記一導電型を有する第１半導体層と、
    　前記結晶基板の他主面上に形成された他導電型を有する第２半導体層と、
    　を有し、
    　前記第１半導体層と前記第２半導体層は、前記結晶基板の主面と交差する側面の一部を覆い、前記側面における前記第１半導体層の法線方向の厚さは前記一主面上の前記第１半導体層の法線方向の厚さよりも薄く、前記側面における前記第２半導体層の法線方向の厚さは前記他主面上の前記第２半導体層の法線方向の厚さよりも薄い、太陽電池。
  2. 　前記第１半導体層または前記第２半導体層の少なくとも一方が非晶質半導体層である、請求項１に記載の太陽電池。
  3. 　前記第１半導体層と前記結晶基板との間、または前記第２半導体層と前記結晶基板との間の少なくとも一方にｉ型非晶質半導体層が形成された、請求項１または２に記載の太陽電池。
  4. 　前記一導電型はｎ型、前記他導電型はｐ型である、請求項１から３のいずれか１項に記載の太陽電池。
  5. 　前記側面に、前記一導電型の第１領域と前記他導電型の第２領域を有する、請求項１から４のいずれか１項に記載の太陽電池。
  6. 　前記結晶基板は、前記一主面と前記他主面と前記側面に複数の凹凸を有するテクスチャ構造を含み、
    　前記側面上に、前記テクスチャ構造の凹凸形状に応じて区画された前記第１領域と前記第２領域を形成した、請求項５に記載の太陽電池。
  7. 　前記側面において、前記第１半導体層と前記第２半導体層が重畳し、前記結晶基板が露出しない、請求項１から６のいずれか１に記載の太陽電池。
  8. 　前記側面において、前記第１半導体層と前記第２半導体層が重畳して形成された層の法線方向の厚さは、前記一主面上の前記第１半導体層の法線方向の厚さと前記他主面上の前記第２半導体層の法線方向の厚さのそれぞれよりも厚く、前記一主面上の前記第１半導体層の法線方向の厚さと前記他主面上の前記第２半導体層の法線方向の厚さを加算した値よりも薄い、太陽電池。
PCT/JP2014/005294 2013-11-08 2014-10-20 太陽電池 WO2015068341A1 (ja)

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