WO2015062323A1 - 阵列基板及其制造方法和显示装置 - Google Patents

阵列基板及其制造方法和显示装置 Download PDF

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Publication number
WO2015062323A1
WO2015062323A1 PCT/CN2014/083353 CN2014083353W WO2015062323A1 WO 2015062323 A1 WO2015062323 A1 WO 2015062323A1 CN 2014083353 W CN2014083353 W CN 2014083353W WO 2015062323 A1 WO2015062323 A1 WO 2015062323A1
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Prior art keywords
gate
conductive strip
scan line
array substrate
scanning line
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PCT/CN2014/083353
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English (en)
French (fr)
Inventor
吴洪江
袁剑峰
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US14/427,770 priority Critical patent/US9647002B2/en
Publication of WO2015062323A1 publication Critical patent/WO2015062323A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3659—Control of matrices with row and column drivers using an active matrix the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1237—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a different composition, shape, layout or thickness of the gate insulator in different devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods

Definitions

  • Embodiments of the present invention relate to an array substrate, a method of fabricating the same, and a display device. Background technique
  • Fig. 1 shows a top view of an array substrate structure
  • Fig. 2 shows a cross-sectional view taken along line A-A of Fig. 1.
  • a gate scanning line 12 is formed on the glass substrate 11, and an insulating layer 13 is covered on the gate scanning line 12, and the insulating layer 13 is usually made of silicon nitride.
  • An active layer 14 is formed on the insulating layer 13, and a data scan line 15 is formed on the active layer 14, and the data scan line 15 is etched to form a source and a drain of the TFT transistor.
  • a protective layer 16 is formed on the data scan line 15, and the protective layer 16 is etched to form via holes in the drain of the TFT transistor. Then, a pixel electrode 17 is formed on the protective layer, and the pixel electrode 17 is connected to the drain of the TFT transistor through a via hole on the protective layer 16.
  • Embodiments of the present invention provide an array substrate having excellent picture quality.
  • An aspect of the invention provides an array substrate, comprising: a substrate; a first gate scan line formed on the substrate; a first gate insulating layer formed on the first gate scan line; An active layer on the first gate insulating layer; a data scan line formed on the active layer and perpendicular to the first gate scan line; a gate formed on the data scan line a pixel electrode in a pixel unit defined by the first gate scan line and the data scan line; a second gate scan line formed above or below the first gate scan line, wherein the second gate The pole scan lines are respectively insulated from the first gate scan line, the active layer, the data scan line, and the pixel electrode.
  • the second gate scan line is located on the first gate insulating layer and the The source layers are insulated from the active layer by a second gate insulating layer.
  • the second gate scan line and the first gate scan line at least partially coincide in a stacking direction of the array substrate.
  • the first gate scan line is composed of a first conductive strip and a plurality of first protrusions extending from one side of the first conductive strip, the first protrusion along the first An extending direction of a conductive strip is disposed at equal intervals on one side of the first conductive strip.
  • the second gate scan line is composed of a second conductive strip and a plurality of second protrusions extending from one side of the second conductive strip, the second conductive strip and the first a conductive strip is overlapped in the stacking direction, and the second convex portion is disposed at equal intervals along an extending direction of the second conductive strip on a side of the second conductive strip opposite to the first convex portion And interlaced with the first convex portion.
  • the second gate scan line is composed of a second conductive strip and a plurality of second protrusions extending from one side of the second conductive strip, the second conductive strip and the first a conductive strip is overlapped in the stacking direction, and the second convex portion is disposed at equal intervals along an extending direction of the second conductive strip on a side of the second conductive strip opposite to the first convex portion And flush with the first convex portion.
  • the data scan line is composed of a third conductive strip and a plurality of third protrusions extending from the third conductive strip, the third conductive strip being perpendicular to the first conductive strip and the The second conductive strip is located between the adjacent first convex portion and the second convex portion, and the third convex portion is formed above each of the first convex portion and the second convex portion.
  • the material of the first insulating layer and/or the second insulating layer is an organic dielectric film.
  • the organic dielectric film comprises at least one of polyethylene, polycarbonate, polystyrene, polyimide, and acrylate.
  • Another aspect of the present invention also provides a method of fabricating an array substrate, comprising: forming a first gate scan line on a substrate; forming a first gate insulating layer on the first gate scan line; Forming an active layer on the first gate insulating layer; forming a data scan line on the active layer, the data scan line being perpendicular to the first gate scan line; a pixel electrode is formed in the pixel unit defined by the first gate scan line and the data scan line; a second gate scan line is formed above or below the first gate scan line, wherein the second gate The pole scan lines are respectively insulated from the first gate scan line, the active layer, the data scan line, and the pixel electrode.
  • the second gate scan line is formed between the first gate insulating layer and the active layer, and the second gate scan line and the active layer pass through Two Gate Insulation Layer
  • a further aspect of the invention also provides a display device having the array substrate as described above.
  • Figure 1 shows a top view of an array substrate structure
  • Figure 2 shows a cross-sectional view taken along line A-A of Figure 1;
  • FIG. 3 is a top plan view showing an array substrate structure according to an embodiment of the present invention.
  • Figure 4 shows a cross-sectional view taken along line B-B of Figure 3;
  • Figure 5 shows a cross-sectional view taken along line C-C of Figure 3;
  • 6-10 are respectively top plan views showing the completion of each step of the manufacturing method of the array substrate structure according to an embodiment of the present invention.
  • Figure 11 is a top plan view showing the structure of an array substrate according to another embodiment of the present invention.
  • Figures 12A and -12B are schematic views showing the resolution of an array substrate;
  • FIGS. 1A and 13B are schematic diagrams showing a black matrix of a color filter corresponding to an array substrate; A schematic diagram of a black matrix of a color filter corresponding to the array substrate of the embodiment of the invention;
  • 14A and 14B are schematic diagrams showing pixel driving of an array substrate in a row-by-row driving manner when the gate scans to the nth row and the n+1th row;
  • FIG. 15A and FIG. 15B are respectively schematic diagrams showing pixel driving when the array substrate is gate-scanned to the first gate scan line and the second gate scan line of the nth row in the progressive drive mode according to an embodiment of the invention.
  • 16A and 16B are schematic diagrams showing pixel driving of an array substrate in which an array substrate is driven by an Mth frame first gate scan line and a second gate scan line, respectively, in an interlaced driving manner, according to an embodiment of the present invention.
  • the array substrate shown in FIG. 1 and FIG. 1 has the following disadvantages:
  • the black matrix shading area corresponding to the grid structure composed of the data scanning line and the gate scanning line is large, and the aperture ratio and transmittance of the display panel are biased. Low; the resolution of the display panel is limited by the data scan line and the gate scan line, which is not conducive to the design and preparation of high PP I (P i xe ls per inch, pixels per inch); Flip mode, the picture quality is not ideal.
  • Embodiments of the present invention provide an array substrate having excellent picture quality.
  • FIG. 3 to 5 are schematic views showing the structure of an array substrate according to an embodiment of the present invention, wherein FIG. 3 shows a top view of an array substrate structure according to an embodiment of the present invention, and FIG. 4 shows a line BB along FIG. Cutaway cross-sectional view, FIG. 5 shows a cross-sectional view taken along line CC of FIG.
  • the array substrate structure according to the embodiment of the present invention has two gate scan lines stacked on top of each other, which are a first gate scan line 2 and a second gate scan line 8, respectively.
  • the gate scan lines are separated by a first gate insulating layer 3, and a second gate insulating layer 9 is formed on the second gate scan line 8, and then sequentially formed on the second gate insulating layer 9.
  • a method of fabricating an array substrate structure includes the following steps: Step S1, forming a first gate scan line 2 on the substrate 1.
  • the substrate is, for example, a glass substrate, a plastic substrate or a quartz substrate.
  • Figure 6 shows a top view of the structure after the first gate scan line process is completed.
  • the first convex portion is formed by a plurality of first convex portions 2.2 extending from one side of the first conductive strip 2.1. 2 ⁇ On the first side of the first conductive strip 2.1 on one side of the first conductive strip 2.1. ⁇ For example, the first conductive strip 2.1 and the first convex portion 2. 2 - body Formed.
  • Step S2 forming a first gate insulating layer 3 on the first gate scan line 2.
  • Fig. 7 is a top plan view showing the structure after the second gate scan line process is completed.
  • the second gate scanning line 8 is composed of a second conductive strip 8.1 and a plurality of second convex portions 8.2 extending from one side of the second conductive strip 8.1.
  • the second conductive strip 8.1 and the first conductive strip 2.1 overlap in the stacking direction.
  • the second convex portion 8.2 is disposed on the side opposite to the first convex portion 2.2, and the first convex portion, at an interval of the second conductive strip 8.1. 2. 2 staggered settings.
  • the second conductive strips 8.1 and the second convex portions 8.2 are integrally formed.
  • Step S4 forming a second gate insulating layer 9 on the second gate scan line 8.
  • step S5 the active layer 4 is formed on the second gate insulating layer 9.
  • a data scan line 5 is formed on the active layer 4.
  • Figure 8 shows a top view of the structure after the active layer and data scan line patterning process is completed.
  • the data scanning line 5 is composed of a third conductive strip 5.1 and a plurality of third convex portions 5.2 extending from the third conductive strip 5.1.
  • the third conductive strip 5.1 is perpendicular to the first conductive strip 2.1 and the second conductive strip 8.1, and is located between the adjacent first convex portion 2. 2 and the second convex portion 8.2.
  • the second convex portion 5. 2 is formed over each of the first convex portion 2.2 and the second convex portion 8. 2 as a source of the thin film transistor on the array substrate. For example, opposite to the plurality of protruding third projections 5. 2, the drains 5. 3 of the thin film transistors on the array substrate are formed.
  • step S7 a protective layer 6 is formed on the data scanning line 5.
  • Figure 9 shows a top view of the structure after the protective layer process is completed.
  • the protective layer 6 is etched to form a via 10 in the protective layer 6 above the drain 5.3.
  • step S8 the pixel electrode 7 is formed on the protective layer 6.
  • Fig. 10 shows a top view of the structure after the pixel electrode process is completed.
  • the pixel electrode 7 is electrically connected to the drain 5.3 through the via 10 in the protective layer 6.
  • Figure 11 shows a top view of an array substrate structure in accordance with another embodiment of the present invention.
  • the first gate scan line is composed of a first conductive strip and a plurality of first convex portions extending from one side of the first conductive strip, and the first convex portion is along the extending direction of the first conductive strip. They are disposed at intervals on one side of the first conductive strip.
  • the second gate scan line is composed of a second conductive strip and a plurality of second protrusions extending from one side of the second conductive strip, the second conductive strip and the first conductive strip are overlapped in the stacking direction, and the second convex portion
  • the second conductive strip is disposed on the side opposite to the first convex portion at equal intervals along the extending direction of the second conductive strip, and is flush with the first convex portion.
  • the data scan line is composed of a third conductive strip and a plurality of third protrusions extending from the third conductive strip, the third conductive strip is perpendicular to the first conductive strip and the second conductive strip, and is disposed on the flush first convex One side of the second convex portion.
  • a third convex portion is formed over each of the first convex portion and the second convex portion as a source of the thin film transistor on the array substrate, and a pair of the plurality of protruding third protrusions The face forms a drain of the thin film transistor on the array substrate.
  • the second gate scan line may be located above or below the first gate scan line and not in the same layer as the first gate scan line, and the second gate scan line may be as in the above embodiment.
  • the first gate insulating layer and the active layer or between the active layer and the data scan line layer, or between the data scan line layer and the pixel electrode layer, or on the pixel electrode layer.
  • the second gate scan line layer is disposed in a different layer from the first gate scan line layer, and the second gate scan line is insulated from the adjacent conductive member (
  • the conductive member includes a first gate scan line, a rim layer, a data scan line, or a pixel electrode layer) to achieve a normal TFT function.
  • various scanning lines are fabricated using a low-resistance material such as copper to make the line width thinner.
  • a method of increasing the thickness of the insulating layer material may also be used as the insulating layer material, such as silicon nitride, oxidized ytterbium, yttria, zirconia, lead zirconate titanate (PZT), barium titanate (BST), or the like.
  • PZT lead zirconate titanate
  • BST barium titanate
  • It is also possible to use an organic dielectric film which is excellent in flexibility, light weight, low cost and easy processability as an insulating layer material such as polyethylene, polycarbonate, polystyrene, polyimide, acrylate. Wait.
  • FIG. 12A is a schematic diagram showing the resolution of an array substrate of a single-gate scan line structure
  • FIG. 12A is a schematic diagram showing the resolution of an array substrate of a double-gate scan line structure disposed in the same layer
  • FIG. 12C shows A schematic diagram of the resolution of an array substrate according to an embodiment of the present invention. Since the gate scan line structure of the upper and lower layers is formed in the array substrate according to the embodiment of the present invention, it can be formed in the pixel unit defined by the gate scan line in the lateral direction and the data scan line in the longitudinal direction. Two pixel electrodes, that is, a pixel area. The two pixel regions are driven by the upper and lower gate scan lines, respectively.
  • the pixel area on the array substrate according to the embodiment of the present invention may be four times that of the pixel area on the array substrate of the single-gate scan line structure, thereby effectively improving the resolution of the display panel;
  • the array substrate ratio of the double-gate scan line structure disposed in the same layer is smaller because the area occupied by the coincident gate scan lines of the embodiment of the present invention is also increased.
  • FIG. 13B is a schematic diagram showing a black matrix of a color filter corresponding to an array substrate of a single-gate scanning line structure
  • FIG. 13B is a view showing a color corresponding to an array substrate of a double-gate scanning line structure disposed in the same layer.
  • Schematic diagram of a black matrix of filters as a comparison
  • FIG. 13C shows an embodiment of the present invention.
  • the gate scan line structure of the upper and lower layers is formed in the array substrate according to the embodiment of the present invention, in the pixel unit defined by the gate scan line in the lateral direction and the data scan line in the longitudinal direction Two pixel regions can be formed, and the two pixel regions are driven by the upper and lower gate scan lines.
  • the shape of the light-shielding region on the color filter corresponding to the array substrate according to the embodiment of the present invention corresponds to a shape composed of a gate scanning line in the lateral direction and a data scanning line in the longitudinal direction.
  • the light-shielding area corresponding to the gate scan line can be reduced by half compared with the array substrate of the single-gate scan line structure, and is significantly lower than the array substrate of the double-gate scan line structure disposed in the same layer, thereby improving The aperture ratio and pass rate of the display panel.
  • FIG. 14A is a schematic diagram showing pixel driving of a single-gate scanning line structure of an array substrate in a row-by-row driving manner when a gate is scanned to an nth row
  • FIG. 14B is a diagram showing a single-gate scanning line structure of an array substrate in a row-by-row manner. Schematic diagram of pixel driving when the gate scans to the n+1th row in the driving mode. Since such a display device usually uses a row flip mode, as shown in FIGS.
  • FIG. 15A is a schematic diagram showing pixel driving when an array substrate is gate-scanned to a first gate scan line of an nth row in a row-by-row driving manner according to an embodiment of the present invention
  • FIG. 15B illustrates a pixel driving according to an embodiment of the present invention.
  • a schematic diagram of pixel driving when the array substrate scans to the second gate scan line of the nth row in the progressive driving mode.
  • FIGS. 15A-B when scanning to the nth row gate, the pixel corresponding to the first gate scan line of the nth row is driven to +; then, the second gate scan with the nth row The entire row of pixels corresponding to the line is driven to -. Thereby, the pixels are driven at intervals, and dot inversion is realized.
  • the difference in the picture is small, and the experience of viewing the picture by the human eye is better.
  • FIG. 16A is a schematic diagram showing pixel driving of an array substrate driven by a first gate scan line of an Mth frame in an interlaced driving manner according to an embodiment of the present invention
  • FIG. 16B is a diagram showing an interlaced driving of an array substrate according to an embodiment of the present invention.
  • the pixels corresponding to the first gate scan lines of the entire array substrate are driven to +; then, the second gate scan lines of the entire array substrate are correspondingly integrated.
  • the row pixels are driven to -.
  • a point flip is achieved, which improves the picture quality.
  • the resolution of the display panel can be improved by using the array substrate provided by the embodiment of the invention. Reduce the shading area at the same resolution, and increase the aperture ratio and transmittance of the display panel. Can In order to achieve point flip, the picture quality is significantly improved.

Abstract

一种阵列基板及其制造方法和显示装置，所述阵列基板包括：基板（1）；形成在所述基板（1）上的第一栅极扫描线（2）；形成在所述第一栅极扫描线（2）上的第一栅极绝缘层（3）；形成在所述第一栅极绝缘层（3）上的有源层（4）；形成在所述有源层（4）上且垂直于所述第一栅极扫描线（2）的数据扫描线（5）；形成在所述数据扫描线（5）上的由所述第一栅极扫描线（2）和所述数据扫描线（5）所定义的像素单元中的像素电极（7）；以及形成在所述第一栅极扫描线（2）上方或下方的第二栅极扫描线（8），所述第二栅极扫描线（8）与所述第一栅极扫描线（2）在所述阵列基板的堆叠方向上大体重合，并且所述第二栅极扫描线（8）与所述第一栅极扫描线（2）、所述有源层（4）、所述数据扫描线（5）及所述像素电极（7）绝缘设置。

Description

阵列基板及其制造方法和显示装置 技术领域
本发明的实施例涉及一种阵列基板及其制造方法和显示装置。 背景技术
随着显示技术的发展， 高透过率、 大尺寸、 低功耗和低成本的显示面板 成为了未来的发展方向。
TFT-LCD阵列基板的栅极扫描线多为单线结构， 图 1示出了一种阵列基 板结构的顶视图， 图 2示出了沿图 1的 A-A线截取的截面图。 如图 1和 2所 示，在玻璃基板 11上形成栅极扫描线 12，在栅极扫描线 12上覆盖绝缘层 1 3 , 绝缘层 13通常由氮化硅构成。在绝缘层 1 3上形成有源层 14，并在有源层 14 上形成数据扫描线 15， 对数据扫描线 15进行蝕刻， 以形成 TFT晶体管的源 极和漏极。 在数据扫描线 15上形成保护层 16， 并对保护层 16进行蝕刻， 以 在 TFT晶体管的漏极上形成过孔。 然后在保护层上形成像素电极 17， 像素电 极 17通过保护层 1 6上的过孔与 TFT晶体管的漏极连接。
为了减少使用数据驱动器的数量以降低成本， 还存在有一种双栅极扫描 线的结构来减少数据驱动器的使用数量。 在这种双栅极扫描线结构中， 两条 栅极扫描线平行设置在同一层上， 虽然扫描线的数量加倍， 但由于数据线的 数目减半， 因此减少了整体所需的数据驱动器数量。 发明内容
本发明的实施例提供一种画面品质优良的阵列基板。
本发明的一个方面提出了一种阵列基板， 包括： 基板； 形成在所述基板 上的第一栅极扫描线； 形成在所述第一栅极扫描线上的第一栅极绝缘层； 形 成在所述第一栅极绝缘层上的有源层； 形成在所述有源层上且垂直于所述第 一栅极扫描线的数据扫描线； 形成在所述数据扫描线上的由所述第一栅极扫 描线和所述数据扫描线所定义的像素单元中的像素电极； 形成在所述第一栅 极扫描线上方或下方的第二栅极扫描线， 其中所述第二栅极扫描线分别与所 述第一栅极扫描线、 所述有源层、 所述数据扫描线及所述像素电极绝缘设置。
在一个示例中， 所述第二栅极扫描线位于所述第一栅极绝缘层与所述有 源层之间， 且通过第二栅极绝缘层与所述有源层绝缘。
在一个示例中， 所述第二栅极扫描线与所述第一栅极扫描线在所述阵列 基板的堆叠方向上至少部分重合。
在一个示例中， 所述第一栅极扫描线由第一导电条和从所述第一导电条 的一侧延伸出的多个第一凸部构成， 所述第一凸部沿所述第一导电条的延伸 方向等间隔地设置在所述第一导电条的一侧上。
在一个示例中， 所述第二栅极扫描线由第二导电条和从所述第二导电条 的一侧延伸出的多个第二凸部构成， 所述第二导电条与所述第一导电条在所 述堆叠方向上重合， 所述第二凸部沿所述第二导电条的延伸方向等间隔地设 置在所述第二导电条的与所述第一凸部相对的侧上， 且与所述第一凸部交错 设置。
在一个示例中， 所述第二栅极扫描线由第二导电条和从所述第二导电条 的一侧延伸出的多个第二凸部构成， 所述第二导电条与所述第一导电条在所 述堆叠方向上重合， 所述第二凸部沿所述第二导电条的延伸方向等间隔地设 置在所述第二导电条的与所述第一凸部相对的侧上， 且与所述第一凸部齐平。
在一个示例中， 所述数据扫描线由第三导电条和从所述第三导电条延伸 出的多个第三凸部构成， 所述第三导电条垂直于所述第一导电条和所述第二 导电条， 且位于相邻的所述第一凸部与所述第二凸部之间， 所述第三凸部形 成在每个第一凸部和第二凸部上方。
在一个示例中， 所述第一绝缘层和 /或第二绝缘层的材料为有机介电膜。 在一个示例中， 所述有机介电膜包括聚乙烯、 聚碳酸脂、 聚苯乙烯、 聚 酰亚胺、 丙烯酸酯中的至少一种。
在一个示例中， 在每个所述像素单元中具有两个所述像素电极。
本发明的另一方面还提出了一种阵列基板的制造方法， 包括： 在基板上 形成第一栅极扫描线； 在所述第一栅极扫描线上形成第一栅极绝缘层； 在所 述第一栅极绝缘层上形成有源层； 在所述有源层上形成数据扫描线， 所述数 据扫描线垂直于所述第一栅极扫描线； 在所述数据扫描线上的由所述第一栅 极扫描线与所述数据扫描线所定义的像素单元中形成像素电极； 在所述第一 栅极扫描线上方或下方形成第二栅极扫描线， 其中所述第二栅极扫描线分别 与所述第一栅极扫描线、 所述有源层、 所述数据扫描线及所述像素电极绝缘 设置。 在一个示例中， 在所述第一栅极绝缘层与所述有源层之间形成所述第二 栅极扫描线， 所述第二栅极扫描线与所述有源层之间通过第二栅极绝缘层绝 本发明的又一方面还提供了一种显示装置， 具有如上所述的阵列基板。 附图说明
以下将结合附图对本发明的实施例进行更详细的说明， 以使本领域普通 技术人员更加清楚地理解本发明， 其中：
图 1示出了一种阵列基板结构的顶视图；
图 2示出了沿图 1的 A-A线截取的截面图；
图 3示出了根据本发明实施例的阵列基板结构的顶视示意图；
图 4示出了沿图 3的 B-B线截取的截面图；
图 5示出了沿图 3的 C-C线截取的截面图；
图 6-10分别示出了根据本发明实施例的阵列基板结构的制造方法各步工 艺完成后的顶视示意图；
图 11示出了根据本发明另一实施例的阵列基板结构的顶视示意图； 图 12A和 -12B示出了一种阵列基板的分辨率的示意图；
图 12C示出了根据本发明实施例的阵列基板的分辨率的示意图； 图 1 3A、 13B示出了一种阵列基板对应的彩色滤光片的黑矩阵的示意图； 1 3C示出了根据本发明实施例的阵列基板对应的彩色滤光片的黑矩阵的 示意图；
图 14A和图 14B分别示出了一种阵列基板在逐行驱动方式下栅极扫描到第 n行和第 n+1行时像素驱动的示意图；
图 15A和图 15B分别示出了根据本发明实施例的阵列基板在逐行驱动方式 下栅极扫描到第 n行的第一栅极扫描线和第二栅极扫描线时像素驱动的示意 图； 以及
图 16A和图 16B分别示出了根据本发明实施例的阵列基板在隔行驱动方式 下第 M帧第一栅极扫描线和第二栅极扫描线驱动时像素驱动的示意图。 具体实施方式
为使本发明的实施例的目的、 技术方案和优点更加清楚， 下面将结合本 发明实施例的附图对本发明的实施例的技术方案进行清楚、 完整的描述。 显 然， 所描述的实施例仅是本发明的一部分示例性实施例， 而不是全部的实施 例。 基于所描述的本发明的示例性实施例， 本领域普通技术人员在无需创造 性劳动的前提下所获得的所有其它实施例都属于本发明的保护范围。
除非另作定义， 此处使用的技术术语或者科学术语应当为本发明所属领 域内具有一般技能的人士所理解的通常意义。 本发明专利申请说明书以及权 利要求书中使用的 "第一"、 "第二" 以及类似的词语并不表示任何顺序、 数 量或者重要性， 而只是用来区分不同的组成部分。 同样， "一个"、 "一" 或者 "该" 等类似词语也不表示数量限制， 而是表示存在至少一个。 "包括" 或者 "包含" 等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后 面列举的元件或者物件及其等同，而不排除其他元件或者物件。 "上"、 "下"、 等仅用于表示相对位置关系， 当被描述对象的绝对位置改变后， 则该相对位 置关系也可能相应地改变。
发明人注意到图 1和图 1所示的阵列基板存在如下缺点： 数据扫描线与 栅极扫描线组成的网格结构对应的黑矩阵遮光区域较多， 显示面板的开口率 和透过率偏低； 显示面板的分辨率受数据扫描线和栅极扫描线限制偏低， 不 利于高 PP I ( P i xe l s per inch, 每英寸的像素数）产品的设计与制备； 由于 驱动方式是行翻转模式， 画面品质效果不理想。 本发明的实施例提供一种画 面品质优良的阵列基板。
图 3至图 5示出了根据本发明实施例的阵列基板结构的示意图， 其中图 3示 出了根据本发明实施例的阵列基板结构的顶视图， 图 4示出了沿图 3的 B-B线截 取的截面图，图 5示出了沿图 3的 C-C线截取的截面图。从图 3至图 5中可以看出， 根据本发明实施例的阵列基板结构具有上下堆叠的两层栅极扫描线， 分别为 第一栅极扫描线 2和第二栅极扫描线 8， 两层栅极扫描线之间由第一栅极绝缘 层 3隔开， 并且第二栅极扫描线 8上形成有第二栅极绝缘层 9， 然后在第二栅极 绝缘层 9上顺次形成有源层 4、 数据扫描线 5、 保护层 6及像素电极 7。
根据本发明实施例的阵列基板结构的制造方法， 包括如下步骤： 步骤 S l， 在基板 1上形成第一栅极扫描线 2。 基板例如为玻璃基板， 塑料 基板或石英基板。 图 6示出了第一栅极扫描线工艺完成后的结构顶视图。 如图 6所示， 第一栅极扫描线 2由第一导电条 2. 1和从第一导电条 2. 1的一侧延伸出 的多个第一凸部 2. 2构成， 第一凸部 2. 2沿第一导电条 2. 1的延伸方向等间隔地 设置在第一导电条 2. 1的一侧上。 例如， 第一导电条 2. 1和第一凸部 2. 2—体地 形成。
步骤 S 2， 在第一栅极扫描线 2上形成第一栅极绝缘层 3。
步骤 S3， 在第一栅极绝缘层 3上形成第二栅极扫描线 8。 图 7示出了第二栅 极扫描线工艺完成后的结构顶视图。 如图 7所示， 第二栅极扫描线 8由第二导 电条 8. 1和从第二导电条 8. 1的一侧延伸出的多个第二凸部 8. 2构成。 第二导电 条 8. 1与第一导电条 2. 1在堆叠方向上重合。 第二凸部 8. 2沿第二导电条 8. 1的 延伸方向等间隔地设置在第二导电条 8. 1的与第一凸部 2. 2相对的侧上， 且与 第一凸部 2. 2交错设置。 例如， 第二导电条 8. 1和第二凸部 8. 2—体地形成。
步骤 S4， 在第二栅极扫描线 8上形成第二栅极绝缘层 9。
步骤 S5， 在第二栅极绝缘层 9上形成有源层 4。
步骤 S6， 在有源层 4上形成数据扫描线 5。 图 8示出了有源层和数据扫描线 构图工艺完成后的结构顶视图。 如图 8所示， 数据扫描线 5由第三导电条 5. 1、 从第三导电条 5. 1延伸出的多个第三凸部 5. 2构成。 第三导电条 5. 1垂直于第一 导电条 2. 1和第二导电条 8. 1， 且位于相邻的第一凸部 2. 2与第二凸部 8. 2之间。 第二凸部 5. 2形成在每个第一凸部 2. 2和第二凸部 8. 2上方， 作为阵列基板上的 薄膜晶体管的源极。 例如， 在凸出的多个第三凸部 5. 2的对面， 形成阵列基板 上的薄膜晶体管的漏极 5. 3。
步骤 S7， 在数据扫描线 5上形成保护层 6。 图 9示出了保护层工艺完成后的 结构顶视图。 对保护层 6进行蝕刻， 在漏极 5. 3上方的保护层 6中形成过孔 10。
步骤 S8， 在保护层 6上形成像素电极 7。 图 10示出了像素电极工艺完成后 的结构顶视图。 像素电极 7通过保护层 6中的通孔 10与漏极 5. 3电连接。
图 11示出了根据本发明另一实施例的阵列基板结构的顶视图。 如图 11所 示， 第一栅极扫描线由第一导电条和从第一导电条的一侧延伸出的多个第一 凸部构成， 第一凸部沿第一导电条的延伸方向等间隔地设置在第一导电条的 一侧上。 第二栅极扫描线由第二导电条和从第二导电条的一侧延伸出的多个 第二凸部构成， 第二导电条与第一导电条在堆叠方向上重合， 第二凸部沿第 二导电条的延伸方向等间隔地设置在第二导电条的与第一凸部相对的侧上， 且与第一凸部平齐。 数据扫描线由第三导电条和从第三导电条延伸出的多个 第三凸部构成， 第三导电条垂直于第一导电条和第二导电条， 且设置在齐平 的第一凸部与第二凸部的一侧。 第三凸部形成在每个第一凸部和第二凸部上 方， 作为阵列基板上的薄膜晶体管的源极， 并且在凸出的多个第三凸部的对 面形成阵列基板上的薄膜晶体管的漏极。
上述的阵列基板及其制造方法的实施例的描述只是说明性的， 并非用于 限定本发明。 本领域技术人员应当理解， 第二栅极扫描线可以位于第一栅极 扫描线的上方或下方而不与第一栅极扫描线同层设置， 第二栅极扫描线可以 如以上实施例所述位于第一栅极绝缘层与有源层之间， 也可以位于有源层与 数据扫描线层之间， 或者位于数据扫描线层与像素电极层之间， 或者位于像 素电极层之上， 或者位于第一栅极扫描线层与玻璃基板之间， 但是第二栅极 扫描线层与第一栅极扫描线层不同层设置， 并且第二栅极扫描线与相邻的导 电部件绝缘（此处导电部件包括第一栅极扫描线、 有缘层、 数据扫描线或像 素电极层）， 以实现正常的 TFT功能。
为了克服制造过程中电容过高的问题， 釆用例如铜等低电阻材料来制作 各个扫描线， 以将线宽做的较细。 或者釆用增加绝缘层材料的厚度的方法。 也可以釆用介电常数较大的材料来作为绝缘层材料， 诸如氮化硅、 氧化辞、 氧化铪、 氧化锆、 锆钛酸铅（PZT )、 钛酸锶钡 ( BST )等。 还可以釆用具有柔 韧性好、 重量轻、 低成本及易加工性等优点的有机介电膜来作为绝缘层材料， 诸如聚乙烯、 聚碳酸脂、 聚苯乙烯、 聚酰亚胺、 丙烯酸酯等。
下面将结合对应的附图详细介绍釆用本发明实施例的阵列基板相比于常 规的阵列基板的优势。
图 12Α示出了单栅极扫描线结构的阵列基板的分辨率的示意图， 图 12Β示 出了同层设置的双栅极扫描线结构的阵列基板的分辨率的示意图， 作为对比， 图 12C示出了根据本发明实施例的阵列基板的分辨率的示意图。 由于根据本发 明实施例的阵列基板中形成了上下两层的栅极扫描线结构， 因此， 在由横向 方向上的栅极扫描线与纵向方向上的数据扫描线所定义的像素单元中可以形 成两个像素电极， 即像素区。 由上下两层栅极扫描线来分别驱动这两个像素 区。 在相同的单位面积下， 根据本发明实施例的阵列基板上的像素区可以是 单栅极扫描线结构的阵列基板上的像素区的四倍， 从而有效提升了显示面板 的分辨率； 而与同层设置的双栅极扫描线结构的阵列基板比， 因为本发明实 施例的重合的栅极扫描线所占的面积少， 同样提高了像素区的面积。
图 1 3Α示出了单栅极扫描线结构的阵列基板所对应的彩色滤光片的黑矩 阵的示意图， 图 13B示出了同层设置的双栅极扫描线结构的阵列基板所对应的 彩色滤光片的黑矩阵的示意图， 作为对比， 图 1 3C示出了才艮据本发明实施例的 阵列基板所对应的彩色滤光片的黑矩阵的示意图。 由于才艮据本发明实施例的 阵列基板中形成了上下两层的栅极扫描线结构， 因此， 在由横向方向上的栅 极扫描线与纵向方向上的数据扫描线所定义的像素单元中可以形成两个像素 区， 由上下两层栅极扫描线来驱动这两个像素区。 根据本发明实施例的阵列 基板所对应的彩色滤光片上的遮光区域的形状对应于由横向方向上的栅极扫 描线与纵向方向上的数据扫描线构成的形状。 在相同的分辨率下， 可以实现 栅极扫描线对应的遮光区域比单栅极扫描线结构的阵列基板减少一半， 且显 著低于同层设置的双栅极扫描线结构的阵列基板， 从而提升了显示面板的开 口率和通过率。
图 14A示出了单栅极扫描线结构的阵列基板在逐行驱动方式下栅极扫描 到第 n行时像素驱动的示意图， 图 14B示出了单栅极扫描线结构的阵列基板在 逐行驱动方式下栅极扫描到第 n+1行时像素驱动的示意图。 由于这种显示装置 通常釆用行翻转的方式， 如图 14A-B所示， 在扫描到第 n行栅极时， 与第 n行栅 极相对应的整行像素被驱动为 +; 在扫描到第 n+1行栅极时， 与第 n+1行栅极相 对应的整行像素被驱动为-。 由于整行翻转画面差异较大， 所以人眼观看画面 的体验不佳。
图 15A示出了根据本发明实施例的阵列基板在逐行驱动方式下栅极扫描 到第 n行的第一栅极扫描线时像素驱动的示意图， 图 15B示出了根据本发明实 施例的阵列基板在逐行驱动方式下栅极扫描到第 n行的第二栅极扫描线时像 素驱动的示意图。 如图 15A-B所示， 在扫描到第 n行栅极时， 与第 n行的第一栅 极扫描线相对应的像素被驱动为 +; 接着， 与第 n行的第二栅极扫描线相对应 的整行像素被驱动为-。 由此， 像素被相间隔地驱动， 实现了点翻转。 这样， 画面差异较小， 人眼观看画面的体验较佳。
图 16A示出了根据本发明实施例的阵列基板在隔行驱动方式下第 M帧第一 栅极扫描线驱动时像素驱动的示意图； 图 16B示出了根据本发明实施例的阵列 基板在隔行驱动方式下第 M帧第二栅极扫描线驱动时像素驱动的示意图。 如图 16A-B所示， 在第 M帧时， 首先整个阵列基板的第一栅极扫描线相对应的像素 被驱动为 +; 接着， 整个阵列基板的第二栅极扫描线相对应的整行像素被驱动 为-。 实现了点翻转， 提升了画面品质。
通过釆用本发明实施例提供的阵列基板， 可以提升显示面板的分辨率。 在相同分辨率的情况下减少遮光区域， 提升显示面板的开口率和透过率。 可 以实现点翻转， 显著提升画面品质。
虽然结合附图描述了本发明的实施方式， 但是本领域技术人员可以在不 脱离本发明的精神和范围的情况下作出各种修改和变型， 这样的修改和变型 均落入由所附权利要求所限定的范围之内。
本申请要求于 2013年 10月 28日提交的名称为"阵列基板及其制造方法 和显示装置" 的中国专利申请 No. 201310516917.2的优先权， 其全文以引用 方式合并于本文。

Claims

权利要求书
1、 一种阵列基板， 包括：
基板；
形成在所述基板上的第一栅极扫描线；
形成在所述第一栅极扫描线上的第一栅极绝缘层；
形成在所述第一栅极绝缘层上的有源层；
形成在所述有源层上且垂直于所述第一栅极扫描线的数据扫描线； 形成在所述数据扫描线上的由所述第一栅极扫描线和所述数据扫描线所 定义的像素单元中的像素电极；
形成在所述第一栅极扫描线上方或下方的第二栅极扫描线， 其中所述第 二栅极扫描线分别与所述第一栅极扫描线、 所述有源层、 所述数据扫描线及 所述像素电极绝缘设置。
2、 根据权利要求 1所述的阵列基板， 其中， 所述第二栅极扫描线位于所 述第一栅极绝缘层与所述有源层之间， 且通过第二栅极绝缘层与所述有源层 绝缘。
3、 根据权利要求 1或 2所述的阵列基板， 其中， 所述第二栅极扫描线与 所述第一栅极扫描线在所述阵列基板的堆叠方向上至少部分重合。
4、 根据权利要求 1-3任一项所述的阵列基板， 其中， 所述第一栅极扫描 线由第一导电条和从所述第一导电条的一侧延伸出的多个第一凸部构成， 所 述第一凸部沿所述第一导电条的延伸方向等间隔地设置在所述第一导电条的 一侧上。
5、 根据权利要求 4所述的阵列基板， 其中， 所述第二栅极扫描线由第二 导电条和从所述第二导电条的一侧延伸出的多个第二凸部构成， 所述第二导 电条与所述第一导电条在所述堆叠方向上重合， 所述第二凸部沿所述第二导 电条的延伸方向等间隔地设置在所述第二导电条的与所述第一凸部相对的侧 上， 且与所述第一凸部交错设置。
6、 根据权利要求 4或 5所述的阵列基板， 其中， 所述第二栅极扫描线由 第二导电条和从所述第二导电条的一侧延伸出的多个第二凸部构成， 所述第 二导电条与所述第一导电条在所述堆叠方向上重合， 所述第二凸部沿所述第 二导电条的延伸方向等间隔地设置在所述第二导电条的与所述第一凸部相对 的侧上， 且与所述第一凸部齐平。
7、 根据权利要求 4-6任一所述的阵列基板， 其中， 所述数据扫描线由第 三导电条和从所述第三导电条延伸出的多个第三凸部构成， 所述第三导电条 垂直于所述第一导电条和所述第二导电条， 且位于相邻的所述第一凸部与所 述第二凸部之间， 所述第三凸部形成在每个第一凸部和第二凸部上方。
8、 根据权利要求 2-7任一所述的阵列基板， 其中， 所述第一栅极绝缘层 和 /或第二栅极绝缘层的材料为有机介电膜。
9、 根据权利要求 7所述的阵列基板， 其中， 所述有机介电膜包括聚乙烯、 聚碳酸脂、 聚苯乙烯、 聚酰亚胺、 丙烯酸酯中的至少一种。
10、 根据权利要求 1至 9中任一项所述的阵列基板， 其中， 在每个所述 像素单元中具有两个所述像素电极。
11、 一种阵列基板的制造方法， 包括：
在基板上形成第一栅极扫描线；
在所述第一栅极扫描线上形成第一栅极绝缘层；
在所述第一栅极绝缘层上形成有源层；
在所述有源层上形成数据扫描线， 所述数据扫描线垂直于所述第一栅极 扫描线；
在所述数据扫描线上的由所述第一栅极扫描线与所述数据扫描线所定义 的像素单元中形成像素电极； 以及
在所述第一栅极扫描线上方或下方形成第二栅极扫描线；
其中所述第二栅极扫描线分别与所述第一栅极扫描线、 所述有源层、 所 述数据扫描线及所述像素电极绝缘设置。
12、 根据权利要求 11所述的制造方法， 其中， 在所述第一栅极绝缘层与 所述有源层之间形成所述第二栅极扫描线， 所述第二栅极扫描线与所述有源 层之间通过第二栅极绝缘层绝缘。
1 3、 一种显示装置， 包括权利要求 1至 10中任一项所述的阵列基板。
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