WO2015060106A1 - 半導体パッケージの製造方法 - Google Patents

半導体パッケージの製造方法 Download PDF

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Publication number
WO2015060106A1
WO2015060106A1 PCT/JP2014/076575 JP2014076575W WO2015060106A1 WO 2015060106 A1 WO2015060106 A1 WO 2015060106A1 JP 2014076575 W JP2014076575 W JP 2014076575W WO 2015060106 A1 WO2015060106 A1 WO 2015060106A1
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WIPO (PCT)
Prior art keywords
semiconductor
resin sheet
semiconductor wafer
sealing
sealing resin
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PCT/JP2014/076575
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English (en)
French (fr)
Japanese (ja)
Inventor
浩介 盛田
石坂　剛
豊田　英志
豪士 志賀
智絵 飯野
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日東電工株式会社
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Publication of WO2015060106A1 publication Critical patent/WO2015060106A1/ja

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

Definitions

  • the present invention relates to a method for manufacturing a semiconductor package.
  • a semiconductor package is manufactured by sealing an electronic component fixed to a semiconductor wafer with a sealing resin, and dicing the sealed product into a package for each electronic component as necessary. Is adopted.
  • a technique for reducing the thickness by grinding a sealing resin or a semiconductor wafer after resin sealing has been proposed (for example, Patent Documents 1 and 2). Thinning by grinding is also important in the manufacturing process of thin semiconductor packages such as flip chip BGA (Ball Grid Array), flip chip SiP (System in Package), fan-in type wafer level package, and fan out type wafer level package. Become an element.
  • An object of the present invention is to provide a semiconductor package manufacturing method capable of forming a target circuit element on a ground surface of a semiconductor wafer with high yield after grinding of a sealing body using a sealing resin sheet.
  • the present invention provides a preparation step of preparing a semiconductor wafer having one or more semiconductor chips mounted on the first main surface, A sealing step of sealing the semiconductor chip by laminating a sealing resin sheet on the first main surface of the semiconductor wafer so as to embed the semiconductor chip; and a first step opposite to the first main surface of the semiconductor wafer. 2 including a back grinding process to grind the main surface,
  • the difference between the thickness of the thickest thickest part and the thinnest thinnest part of the laminate of the sealing resin sheet and the ground semiconductor wafer is 20 ⁇ m or less.
  • the cause of the trouble in forming the circuit element is the state of the second main surface forming the circuit element of the semiconductor wafer after grinding, particularly the bulge of the surface.
  • a bulge is considered to occur during grinding of the semiconductor wafer. That is, the grinding of the second main surface of the semiconductor wafer is performed by fixing the sealing body to a fixing means such as a back surface grinding tape with the sealing resin sheet side as a fixed surface. At this time, a region where the semiconductor chip is interposed and a region where the semiconductor chip is not interposed are mixed between the second main surface of the semiconductor wafer and the fixing means.
  • the hardness of the sealing resin sheet and the hardness of the semiconductor chip are different from each other. It will not be uniformly loaded. Since the hardness of the semiconductor chip is generally higher than the hardness of the encapsulated resin sheet after curing, the repulsion from the encapsulated resin sheet in the region where the semiconductor chip intervenes between the semiconductor wafer and the fixing means.
  • the semiconductor wafer is deeply (thinly) easily ground due to the increased force, and conversely, the sealing resin in the region where the semiconductor chip is not interposed between the semiconductor wafer and the fixing means (the region where only the sealing resin sheet is interposed)
  • the repulsive force from the sheet is weakened, and the semiconductor wafer becomes shallower (thicker) and more easily ground.
  • the ground surface of the semiconductor wafer rises due to the thickness variation in the semiconductor wafer after grinding.
  • laminated body the difference between the thickness of the thickest thickest part and the thickness of the thinnest thinnest part of the laminated body (hereinafter also simply referred to as “laminated body”) of the encapsulating resin sheet and the ground semiconductor wafer.
  • thickness difference is 20 ⁇ m or less, it is possible to suppress the occurrence of swell of the ground surface of the semiconductor wafer and ensure sufficient flatness. Circuit elements can be formed efficiently. If the thickness difference exceeds 20 ⁇ m, there may be a problem in forming the circuit element described above.
  • the sealing step is preferably performed by flat plate pressing or compression molding on the sealing resin sheet. Thereby, the surface of the sealing resin sheet of a laminated body can be smoothed, and the bulge of the grinding surface of a semiconductor wafer can be measured and controlled accurately.
  • the thickest portion of the laminate is also referred to as a region where the semiconductor wafer and the semiconductor chip do not overlap when the semiconductor wafer is seen through in plan view (hereinafter also referred to as “resin sheet region”.
  • the region where the semiconductor wafer and the semiconductor chip overlap when viewed through is also referred to as a “chip overlapping region”).
  • the region where the semiconductor chip is not interposed between the semiconductor wafer and the fixing means that is, the resin sheet region
  • the semiconductor wafer is thicker and easier to grind.
  • circuit elements can be formed on the ground surface of the semiconductor wafer with a high yield.
  • the Shore D hardness at 25 ° C. of the encapsulating resin sheet after being subjected to thermosetting treatment at 150 ° C. for 1 hour is preferably 60 or more.
  • the storage elastic modulus in 25 degreeC of the said sealing resin sheet after performing a thermosetting process at 150 degreeC for 1 hour is 3 GPa or more.
  • a rewiring forming step for forming a rewiring on the ground second main surface of the semiconductor chip may be further included.
  • a dicing step of dicing the semiconductor wafer together with the sealing resin sheet in units of a target semiconductor chip may be further included after the rewiring formation step.
  • the present invention includes a semiconductor package obtained by the method for manufacturing the semiconductor package.
  • FIGS. 1A to 1G are cross-sectional views schematically showing one process of a method for manufacturing a semiconductor package according to an embodiment of the present invention.
  • a semiconductor chip is manufactured by sealing a semiconductor chip mounted on a semiconductor wafer with a sealing resin sheet.
  • the semiconductor package manufacturing method according to the present embodiment is suitable for a chip-on-wafer (COW) process.
  • COW chip-on-wafer
  • Chip mounting wafer preparation process In the chip mounting wafer preparation step, a semiconductor wafer 12A in which a plurality of semiconductor chips 13 are flip-chip connected to the first main surface is prepared (see FIG. 1A).
  • the semiconductor chip 13 can be formed by dicing a semiconductor wafer on which a predetermined circuit is formed by a known method.
  • a known device such as a flip chip bonder can be used for mounting the semiconductor chip 13 on the semiconductor wafer 12A.
  • flip chip connection is employed in which the active surface A1 on which the protruding electrode 13a of the semiconductor chip 13 is formed faces the semiconductor wafer 12A.
  • the semiconductor chip 13 and the semiconductor wafer 12A are electrically connected to each other through bump electrode electrodes 13a formed on the semiconductor chip 13 and through electrodes 12a provided on the semiconductor wafer 12A.
  • a TSV (Through Silicon Via) type electrode can be preferably used as the through-electrode 12a.
  • an underfill material 14 is filled between the semiconductor chip 13 and the semiconductor wafer 12A in order to reduce the difference in thermal expansion coefficient between the semiconductor chip 13 and the semiconductor wafer 12A, in particular, to prevent the occurrence of cracks or the like at the connection site.
  • a known material may be used as the underfill material 14.
  • the underfill material 14 may be arranged by injecting the liquid underfill material 14 between the semiconductor chips 13 after the semiconductor chip 13 is mounted on the semiconductor wafer 12A.
  • the semiconductor chip with the sheet-like underfill material 14 may be disposed. 13 or the semiconductor wafer 12A may be prepared, and the semiconductor chip 13 and the semiconductor wafer 12A may be connected to each other.
  • the sealing resin sheet 11 is laminated on the semiconductor wafer 12A so as to embed the semiconductor chip 13, and the semiconductor chip 13 is resin-sealed with the sealing resin sheet (see FIG. 1B).
  • the sealing resin sheet 11 functions as a sealing resin for protecting the semiconductor chip 13 and its accompanying elements from the external environment.
  • the method for laminating the sealing resin sheet 11 is not particularly limited, and a melt-kneaded product of the resin composition for forming the sealing resin sheet is extruded, and the extruded product is placed on the semiconductor wafer 12A and pressed.
  • the coating film is dried. Examples include a method of forming the sealing resin sheet 11 and transferring the sealing resin sheet 11 onto the semiconductor wafer 12A.
  • the sealing resin sheet 11 by adopting the sealing resin sheet 11, the semiconductor chip 13 can be embedded simply by sticking the semiconductor chip 13 on the semiconductor wafer 12 ⁇ / b> A, thereby improving the production efficiency of the semiconductor package. Can do.
  • the sealing resin sheet 11 can be laminated on the semiconductor wafer 12A by a known method such as compression using a flat plate press, a laminator, or a mold. It is preferable to perform a sealing process by the flat plate press with respect to the sealing resin sheet 11, or compression molding. Thereby, the surface of the sealing resin sheet 11 of the laminate 16B (see FIG. 1D) of the sealing resin sheet 11 and the ground semiconductor wafer 12B can be smoothed, and the rising of the ground surface of the semiconductor wafer 12B can be accurately performed.
  • a hot press using a flat plate press is preferable.
  • the temperature is, for example, 40 to 120 ° C., preferably 50 to 100 ° C.
  • the pressure is, for example, 50 to 2500 kPa, preferably 100 to 2000 kPa
  • the time is, for example, 0 3 to 10 minutes, preferably 0.5 to 5 minutes.
  • it is preferable to press under reduced pressure conditions for example, 10 to 2000 Pa).
  • the temperature is, for example, 40 to 200 ° C., preferably 60 to 160 ° C.
  • the pressure is, for example, 100 to 6000 kPa, preferably 500 to 5000 kPa
  • the time is, for example, 0.5 to 20 minutes, preferably 1 to 15 minutes.
  • the sealing resin sheet is thermally cured to form the sealing body 15 in which the semiconductor chip 13 is embedded in the sealing resin sheet 11 (see FIG. 1B).
  • the conditions for the thermosetting treatment of the sealing resin sheet are preferably 100 to 200 ° C., more preferably 120 to 180 ° C. as the heating temperature, and preferably 10 to 180 minutes, more preferably 30 to 120 minutes as the heating time. You may pressurize as needed. In the pressurization, preferably 0.1 MPa to 10 MPa, more preferably 0.5 MPa to 5 MPa can be employed. Thereby, since this sealing body formation process is included in a sealing process, a sealing process is completed here.
  • a grinding process may be performed in which the sealing resin sheet 11 of the sealing body 15 is ground so that the surface opposite to the active surface A of the semiconductor chip 13 is exposed to form a grinding body 16A (FIG. 1C).
  • the semiconductor chip 13 may be ground together with the sealing resin sheet 11 as shown in FIG. 1C, or only the sealing resin sheet 11 may be ground. Grinding may be performed using a known grinding apparatus.
  • a procedure for forming the grinding body 16A by grinding the surface of the sealing body while feeding the sealing body 15 while rotating a grinding tool such as a diamond tool can be suitably employed. This step can be omitted depending on the specifications of the target semiconductor package.
  • the back surface grinding step In the back surface grinding step, the surface opposite to the grinding surface G1 of the grinding body 16A (that is, the back surface B1) is ground (see FIG. 1D). Thereby, the exposed 2nd main surface (surface on the opposite side to the surface which laminated
  • Laminated body 16B of encapsulating resin sheet 11 and ground semiconductor wafer 12B (Note that when encapsulating resin sheet 11 is ground and semiconductor chip 13 is exposed as shown in FIG.
  • the difference between the thickness T max of the thickest thickest part of the semiconductor chip 13 and the thickness T min of the thinnest thinnest part is 20 ⁇ m or less, preferably 10 ⁇ m or less, and more preferably 5 ⁇ m or less.
  • the lower limit of the thickness difference is preferably 0 ⁇ m, but may be 1 ⁇ m or more as long as it does not affect circuit element formation.
  • the bulge occurs only in the resin sheet region corresponding to the space between the leftmost semiconductor chip and the central semiconductor chip among the illustrated semiconductor chips. Instead of the region or together with the resin sheet region, the resin sheet region corresponding to another semiconductor chip may be raised. When a plurality of swells occur on the ground surface of the semiconductor wafer, the thickness difference is obtained with reference to a portion where the thickness of the stacked body 16B is maximum.
  • a rewiring forming step of forming the rewiring 19 on the surface B1 on the active surface A1 side of the semiconductor chip 13 of the stacked body 16B (see FIG. 1E).
  • a rewiring 39 connected to the through electrode 12a of the semiconductor wafer 12B is formed on the stacked body 16B.
  • a metal seed layer is formed on the exposed semiconductor wafer 12B using a known method such as a vacuum film forming method, and the rewiring is performed by a known method such as a semi-additive method.
  • the wiring 19 can be formed.
  • an insulating layer such as polyimide or PBO may be formed on the rewiring 19 and the stacked body 16B.
  • bumping processing for forming bumps 17 on the formed rewiring 19 may be performed (see FIG. 1D).
  • the bumping process can be performed by a known method such as a solder ball or solder plating.
  • the material of the bump is not particularly limited.
  • tin-lead metal material tin-silver metal material, tin-silver-copper metal material, tin-zinc metal material, tin-zinc-bismuth metal material, etc.
  • Solders alloys
  • gold-based metal materials copper-based metal materials, and the like.
  • Chip back surface protection process When a surface opposite to the active surface A1 of the semiconductor chip 13 is exposed by performing a grinding process, the ground surface of the grinding body 16A is formed to protect the exposed surface 13S of the semiconductor chip 13 after the bumps 17 are formed. G1 (see FIG. 1C) may be resin-sealed again.
  • the sealing method is not particularly limited, and a known liquid or film-like sealing resin may be applied or bonded to the grinding surface G1, dried, and cured. When the grinding process is performed, this process may be performed at any stage after the grinding process and before the dicing process.
  • the grinding body 16C may be diced through bump formation including elements such as the sealing resin sheet 11, the semiconductor wafer 12B, and the semiconductor chip 13 (see FIG. 1G).
  • the semiconductor package 18 can be obtained in the target semiconductor chip 13 unit.
  • dicing is performed corresponding to one semiconductor chip, but dicing may be performed with two or more semiconductor chips as a unit. Dicing is usually performed after the grinding body 16C is fixed by a conventionally known dicing sheet.
  • the alignment of the cut portion may be performed by image recognition using direct illumination or indirect illumination.
  • a cutting method called full cut that cuts up to a dicing sheet can be adopted. It does not specifically limit as a dicing apparatus used at this process, A conventionally well-known thing can be used.
  • the expanding device when expanding a grinding body following a dicing process, this expansion can be performed using a conventionally well-known expanding apparatus.
  • the expanding device includes a donut-shaped outer ring that can push down the dicing sheet through the dicing ring, and an inner ring that has a smaller diameter than the outer ring and supports the dicing sheet.
  • a substrate mounting step of mounting the semiconductor package 18 obtained above on a separate substrate can be performed.
  • a known device such as a flip chip bonder or a die bonder can be used.
  • FIG. 2 is a cross-sectional view schematically showing a sealing resin sheet according to an embodiment of the present invention.
  • the sealing resin sheet 11 is typically provided in a state of being laminated on a support 11a such as a polyethylene terephthalate (PET) film. Note that a release treatment may be applied to the support 11a in order to easily peel off the sealing resin sheet 11.
  • PET polyethylene terephthalate
  • the Shore D hardness at 25 ° C. of the encapsulating resin sheet 11 after performing the thermosetting treatment at 150 ° C. for 1 hour is preferably 60 or more, and more preferably 70 or more.
  • the upper limit of the Shore D hardness is preferably 92 or less.
  • the storage elastic modulus in 25 degreeC of the sealing resin sheet 11 after performing a thermosetting process at 150 degreeC for 1 hour is 3 GPa or more, and it is more preferable that it is 10 GPa or more.
  • the upper limit of the storage elastic modulus is preferably 30 GPa or less.
  • the Shore D hardness and storage elastic modulus of the encapsulating resin sheet 11 after the thermosetting treatment By setting the Shore D hardness and storage elastic modulus of the encapsulating resin sheet 11 after the thermosetting treatment to the above ranges, the difference between the hardness of the semiconductor chip in the chip overlap region and the hardness of the encapsulating resin sheet in the resin sheet region is reduced. Thus, the thickness difference can be reduced.
  • the resin composition for forming the sealing resin sheet is not particularly limited as long as it has the above-described characteristics and can be used for resin sealing of electronic components such as semiconductor chips.
  • An epoxy resin composition containing an A component to an E component is preferable.
  • the C component may or may not be added as necessary.
  • the epoxy resin (component A) is not particularly limited.
  • Various epoxy resins such as an epoxy resin, a phenol novolac type epoxy resin, and a phenoxy resin can be used. These epoxy resins may be used alone or in combination of two or more.
  • a modified bisphenol A type epoxy resin having a flexible skeleton such as an acetal group or a polyoxyalkylene group is preferable, and a modified bisphenol A type epoxy resin having an acetal group is in a liquid state and is easy to handle. Therefore, it can be particularly preferably used.
  • the content of the epoxy resin (component A) is preferably set in the range of 1 to 10% by weight with respect to the entire epoxy resin composition.
  • the phenol resin (component B) is not particularly limited as long as it causes a curing reaction with the epoxy resin (component A).
  • a phenol novolak resin, a phenol aralkyl resin, a biphenyl aralkyl resin, a dicyclopentadiene type phenol resin, a cresol novolak resin, a resole resin, or the like is used. These phenolic resins may be used alone or in combination of two or more.
  • phenol resin those having a hydroxyl equivalent weight of 70 to 250 and a softening point of 50 to 110 ° C. are preferably used from the viewpoint of reactivity with the epoxy resin (component A), and above all, from the viewpoint of high curing reactivity.
  • a phenol novolac resin can be preferably used. From the viewpoint of reliability, low hygroscopic materials such as phenol aralkyl resins and biphenyl aralkyl resins can also be suitably used.
  • the blending ratio of the epoxy resin (component A) and the phenol resin (component B) is a hydroxyl group in the phenol resin (component B) with respect to 1 equivalent of the epoxy group in the epoxy resin (component A). It is preferable to blend so that the total amount becomes 0.7 to 1.5 equivalents, more preferably 0.9 to 1.2 equivalents.
  • the total content of the epoxy resin and the phenol resin in the sealing resin sheet 11 is preferably 2.5% by weight or more, and more preferably 3.0% by weight or more. Adhesive force with respect to the semiconductor chip 13, the semiconductor wafer 12A, etc. is obtained favorably as it is 2.5 wt% or more.
  • the total content of the epoxy resin and the phenol resin in the sealing resin sheet 11 is preferably 20% by weight or less, and more preferably 10% by weight or less. Hygroscopicity can be reduced as it is 20 weight% or less.
  • the elastomer (component C) used together with the epoxy resin (component A) and the phenol resin (component B) provides the epoxy resin composition with the flexibility necessary for sealing electronic components with a sealing resin sheet.
  • the structure is not particularly limited as long as such an effect is exhibited.
  • various acrylic copolymers such as polyacrylates, styrene acrylate copolymers, butadiene rubber, styrene-butadiene rubber (SBR), ethylene-vinyl acetate copolymer (EVA), isoprene rubber, acrylonitrile rubber, etc. Polymers can be used.
  • the heat resistance and strength of the resulting sealing resin sheet can be improved. It is preferable to use an acrylic copolymer. These may be used alone or in combination of two or more.
  • the acrylic copolymer can be synthesized, for example, by radical polymerization of an acrylic monomer mixture having a predetermined mixing ratio by a conventional method.
  • a method for radical polymerization a solution polymerization method in which an organic solvent is used as a solvent or a suspension polymerization method in which polymerization is performed while dispersing raw material monomers in water are used.
  • polymerization initiator used in this case examples include 2,2′-azobisisobutyronitrile, 2,2′-azobis- (2,4-dimethylvaleronitrile), and 2,2′-azobis-4- Methoxy-2,4-dimethylvaleronitrile, other azo or diazo polymerization initiators, peroxide polymerization initiators such as benzoyl peroxide and methyl ethyl ketone peroxide are used.
  • a dispersing agent such as polyacrylamide or polyvinyl alcohol.
  • the content of the elastomer (component C) is 15 to 30% by weight of the entire epoxy resin composition.
  • the content of the elastomer (component C) is less than 15% by weight, it becomes difficult to obtain the flexibility and flexibility of the sealing resin sheet 11, and it is also difficult to perform resin sealing while suppressing warping of the sealing resin sheet. It becomes.
  • the content exceeds 30% by weight, the melt viscosity of the sealing resin sheet 11 is increased, the embedding property of the semiconductor chip 13 is lowered, and the strength and heat resistance of the cured body of the sealing resin sheet 11 are reduced. There is a tendency to decrease.
  • the weight ratio of the elastomer (component C) to the epoxy resin (component A) is preferably set in the range of 3 to 4.7.
  • weight ratio is less than 3, it is difficult to control the fluidity of the sealing resin sheet 11, and when it exceeds 4.7, the adhesion of the sealing resin sheet 11 to the semiconductor chip 13 tends to be inferior. Because it is.
  • the inorganic filler (component D) is not particularly limited, and various conventionally known fillers can be used.
  • silica powder is used in that the internal stress is reduced by reducing the coefficient of thermal expansion of the cured product of the epoxy resin composition, and as a result, warpage of the sealing resin sheet 11 after sealing of the electronic component can be suppressed.
  • a fused silica powder among the silica powders examples include spherical fused silica powder and crushed fused silica powder. From the viewpoint of fluidity, it is particularly preferable to use a spherical fused silica powder. Among them, those having an average particle diameter in the range of 0.1 to 30 ⁇ m are preferably used, and those in the range of 1 to 20 ⁇ m are more preferable.
  • the average particle diameter can be derived by using a sample arbitrarily extracted from the population and measuring it using a laser diffraction / scattering particle size distribution measuring apparatus.
  • the content of the inorganic filler (component D) is preferably 70 to 95% by weight of the entire epoxy resin composition, more preferably 75 to 92% by weight, and still more preferably 80 to 90% by weight.
  • the content of the inorganic filler (component D) is less than 50% by weight, the linear expansion coefficient of the cured product of the epoxy resin composition increases, and thus the warpage of the sealing resin sheet 11 tends to increase.
  • liquidity of the sealing resin sheet 11 will worsen when the said content exceeds 90 weight%, the tendency for adhesiveness with a semiconductor chip to fall is seen.
  • the curing accelerator (component E) is not particularly limited as long as it allows curing of the epoxy resin and the phenol resin, but from the viewpoint of curability and storage stability, triphenylphosphine or tetraphenylphosphonium tetraphenyl. Organic phosphorus compounds such as borates and imidazole compounds are preferably used. These curing accelerators may be used alone or in combination with other curing accelerators.
  • the content of the curing accelerator (component E) is preferably 0.1 to 5 parts by weight with respect to a total of 100 parts by weight of the epoxy resin (component A) and the phenol resin (component B).
  • a flame retardant component may be added to the epoxy resin composition.
  • various metal hydroxides such as aluminum hydroxide, magnesium hydroxide, iron hydroxide, calcium hydroxide, tin hydroxide, and complex metal hydroxide can be used.
  • the average particle diameter of the metal hydroxide is preferably 1 to 10 ⁇ m, more preferably 2 to 5 ⁇ m, from the viewpoint of ensuring appropriate fluidity when the epoxy resin composition is heated. It is.
  • the average particle size of the metal hydroxide is less than 1 ⁇ m, it becomes difficult to uniformly disperse in the epoxy resin composition, and the fluidity during heating of the epoxy resin composition tends to be insufficient.
  • the surface area per addition amount of a metal hydroxide (E component) will become small when an average particle diameter exceeds 10 micrometers, the tendency for a flame-retardant effect to fall is seen.
  • a phosphazene compound can be used in addition to the above metal hydroxide.
  • phosphazene compounds for example, SPR-100, SA-100, SP-100 (above, Otsuka Chemical Co., Ltd.), FP-100, FP-110 (above, Fushimi Pharmaceutical Co., Ltd.) and the like are commercially available. is there.
  • the phosphazene compound represented by the formula (1) or the formula (2) is preferable from the viewpoint of exhibiting a flame retardant effect even in a small amount, and the content of phosphorus element contained in these phosphanzene compounds is 12% by weight or more. Is preferred.
  • n is an integer of 3 to 25
  • R 1 and R 2 are the same or different and are selected from the group consisting of an alkoxy group, a phenoxy group, an amino group, a hydroxyl group and an allyl group.
  • a monovalent organic group having (In the formula (2), n and m are each independently an integer of 3 to 25.
  • R 3 and R 5 are the same or different and are composed of an alkoxy group, a phenoxy group, an amino group, a hydroxyl group and an allyl group.
  • R 4 is a divalent organic group having a functional group selected from the group consisting of an alkoxy group, a phenoxy group, an amino group, a hydroxyl group and an allyl group. .
  • n is an integer of 3 to 25
  • R 6 and R 7 are the same or different and are hydrogen, a hydroxyl group, an alkyl group, an alkoxy group, or a glycidyl group.
  • the cyclic phosphazene oligomer represented by the above formula (3) is commercially available, for example, FP-100, FP-110 (above, Fushimi Pharmaceutical Co., Ltd.) and the like.
  • the content of the phosphazene compound includes the epoxy resin (component A), phenol resin (component B), elastomer (component D), curing accelerator (component E) and phosphazene compound (other components) contained in the epoxy resin composition. It is preferably 10 to 30% by weight of the total organic component containing. That is, when the content of the phosphazene compound is less than 10% by weight of the total organic component, the flame retardancy of the sealing resin sheet 11 is reduced and the unevenness followability to an adherend (semiconductor wafer on which a semiconductor chip is mounted) or the like. Tends to decrease, and voids tend to occur. When the content exceeds 30% by weight of the whole organic component, tackiness is likely to occur on the surface of the sealing resin sheet 11, and the workability tends to be lowered, such as difficulty in alignment with the adherend.
  • the sealing resin sheet 11 having excellent flame retardancy while ensuring the flexibility necessary for sealing the sheet.
  • sufficient flame retardancy when only the metal hydroxide is used and sufficient flexibility can be obtained when only the phosphazene compound is used.
  • organic flame retardants are used from the viewpoint of the deformability of the sealing resin sheet at the time of molding the resin seal, the conformity to the unevenness of the adherend, and the adhesion to the semiconductor chip or the semiconductor wafer.
  • phosphazene flame retardants are preferably used.
  • the epoxy resin composition can be appropriately mixed with other additives such as pigments including carbon black as necessary.
  • an epoxy resin composition is prepared by mixing the above-described components.
  • the mixing method is not particularly limited as long as each component is uniformly dispersed and mixed.
  • a varnish in which each component is dissolved or dispersed in an organic solvent or the like is applied to form a sheet.
  • a kneaded material may be prepared by directly kneading each compounding component with a kneader or the like, and the kneaded material thus obtained may be extruded to form a sheet.
  • the above components A to E and other additives as necessary are mixed as appropriate according to a conventional method, and uniformly dissolved or dispersed in an organic solvent to prepare a varnish.
  • the sealing resin sheet 11 can be obtained by applying the varnish on a support such as polyester and drying it. If necessary, a release sheet such as a polyester film may be bonded to protect the surface of the sealing resin sheet. The release sheet peels at the time of sealing.
  • the organic solvent is not particularly limited, and various conventionally known organic solvents such as methyl ethyl ketone, acetone, cyclohexanone, dioxane, diethyl ketone, toluene, and ethyl acetate can be used. These may be used alone or in combination of two or more. Usually, it is preferable to use an organic solvent so that the solid content concentration of the varnish is in the range of 30 to 60% by weight.
  • the thickness of the sheet after drying the organic solvent is not particularly limited, but is usually preferably set to 5 to 100 ⁇ m, more preferably 20 to 70 ⁇ m, from the viewpoint of thickness uniformity and the amount of residual solvent. is there.
  • the above components A to E and, if necessary, each component of other additives are mixed using a known method such as a mixer, and then kneaded to prepare a kneaded product.
  • the method of melt kneading is not particularly limited, and examples thereof include a method of melt kneading with a known kneader such as a mixing roll, a pressure kneader, or an extruder.
  • the kneading conditions are not particularly limited as long as the temperature is equal to or higher than the softening point of each component described above.
  • thermosetting property of the epoxy resin it is preferably 40 to 140 ° C., more preferably The temperature is 60 to 120 ° C., and the time is, for example, 1 to 30 minutes, preferably 5 to 15 minutes. Thereby, a kneaded material can be prepared.
  • the sealing resin sheet 11 can be obtained by molding the obtained kneaded material by extrusion molding. Specifically, the encapsulating resin sheet 11 can be formed by extrusion molding without cooling the kneaded product after melt-kneading while maintaining a high temperature state.
  • Such an extrusion method is not particularly limited, and examples thereof include a T-die extrusion method, a roll rolling method, a roll kneading method, a co-extrusion method, and a calendar molding method.
  • the extrusion temperature is not particularly limited as long as it is equal to or higher than the softening point of each component described above. However, considering the thermosetting property and moldability of the epoxy resin, for example, 40 to 150 ° C., preferably 50 to 140 ° C. Preferably, it is 70 to 120 ° C.
  • the sealing resin sheet 11 can be formed.
  • the encapsulating resin sheet obtained in this way may be used by being laminated so as to have a desired thickness if necessary. That is, the sealing resin sheet may be used in a single layer structure, or may be used as a laminate formed by laminating two or more multilayer structures.
  • Example 1 (Preparation of sealing resin sheet) The following components were blended with a mixer, melt kneaded at 120 ° C. for 2 minutes with a twin-screw kneader, and then extruded from a T-die to prepare a sealing resin sheet A having a thickness of 500 ⁇ m.
  • Epoxy resin Bisphenol F type epoxy resin (manufactured by Nippon Steel Chemical Co., Ltd., YSLV-80XY (epochine equivalent 200 g / eq. Softening point 80 ° C.)) 286 parts
  • Phenol resin phenol resin having biphenylaralkyl skeleton (Maywa Kasei Co., Ltd.) Manufactured by MEH-7851-SS (hydroxyl equivalent: 203 g / eq., Softening point: 67 ° C.)
  • Curing accelerator imidazole catalyst as a curing catalyst (manufactured by Shikoku Chemicals Co., Ltd., 2PHZ-PW) 6 parts
  • Inorganic Filler Spherical fused silica powder (manufactured by Denki Kagaku Kogyo Co., Ltd., FB-9454, average particle size 20 ⁇ m) 3695 parts
  • Silane coupling agent Epoxy group-containing silane coupling agent
  • Example 2 Preparation of sealing resin sheet
  • the following components were blended with a mixer, melt-kneaded at 120 ° C. for 2 minutes with a twin-screw kneader, and then extruded from a T die to prepare a sealing resin sheet B having a thickness of 500 ⁇ m.
  • Epoxy resin Bisphenol F type epoxy resin (manufactured by Nippon Steel Chemical Co., Ltd., YSLV-80XY (epochine equivalent 200 g / eq. Softening point 80 ° C.)) 169 parts
  • Phenol resin phenol resin having biphenylaralkyl skeleton (Maywa Kasei Co., Ltd.) Manufactured by MEH-7851-SS (hydroxyl equivalent: 203 g / eq., Softening point: 67 ° C.) 179 parts
  • Curing accelerator imidazole catalyst as a curing catalyst (manufactured by Shikoku Kasei Co., Ltd., 2PHZ-PW) 6 parts
  • Elastomer Styrene-isobutylene-styrene triblock copolymer (manufactured by Kaneka Corp., SIBSTAR 072T) 152 parts
  • Inorganic filler spherical fused silica
  • the storage elastic modulus was measured using a solid viscoelasticity measuring apparatus (manufactured by Rheometric Scientific: model: RSA-III). Specifically, each sealing resin sheet is heated and cured at 150 ° C. for 1 hour, and a measurement sample is obtained from the cured product with a sample size of 400 mm long ⁇ 2 mm wide ⁇ 80 ⁇ m thick, and then the measurement sample.
  • a film tension measuring jig was set in a film tension measuring jig, and the storage elastic modulus and loss elastic modulus in the temperature range of ⁇ 50 to 300 ° C. were measured under the conditions of a frequency of 1 Hz and a heating rate of 10 ° C./min. It was obtained by reading the storage modulus (E ′).
  • a chip mounting interposer was prepared in which a semiconductor chip having the following specifications was flip-chip mounted on a silicon interposer, and the space between the chip and the interposer was sealed with a bisphenol A type epoxy thermosetting underfill material.
  • Each of the sealing resin sheets A to C was pasted on the obtained chip mounting interposer by a vacuum flat plate press under the following heating and pressing conditions.
  • the sealing resin sheet was thermally cured in a hot air dryer at 150 ° C. for 1 hour to obtain a sealing body.
  • the thickness of the semiconductor chip is obtained by grinding using a cutting device (manufactured by DISCO Corporation, surface planar “DFS8910”) under the conditions of a peripheral speed of the grinding tool of 1000 m / min, a feed pitch of 100 ⁇ m, and a cutting depth of 10 ⁇ m.
  • the exposed surface of the silicon interposer of the obtained grinding body (the surface opposite to the surface on which the sealing resin sheet was bonded) was removed with a grinding device (“DGP8761” manufactured by DISCO) and the thickness of the silicon interposer was 100 ⁇ m. It grinded until it became, and the laminated body was formed.
  • DISCO grinding device
  • polyamic acid obtained by reacting 3,4 ', 3,4'-biphenyltetracarboxylic dianhydride, 4,4'-diaminodiphenyl ether, paraphenylenediamine
  • polyimide layer having a thickness of 10 ⁇ m.
  • An opening was formed by laser processing at a position corresponding to the through-silicon via to expose the via.
  • a gold film and a nickel film were sequentially formed on the surface of the polyimide layer including the opening by plating.
  • sputtering is performed in the order of chromium and copper to form a seed film (chrome layer thickness 20 nm, copper layer thickness 100 nm), and a rewiring layer having a predetermined wiring pattern is formed by electrolytic copper plating.
  • a semiconductor package was produced.
  • the thickness difference of the laminate of the sealing resin sheet and the silicon interposer is 20 ⁇ m or less, so rewiring as a circuit surface element of the semiconductor package
  • the semiconductor package of Comparative Example 1 has a thickness difference exceeding 20 ⁇ m, resulting in poor rewiring formability.
  • Example 3 In the sealing process of manufacturing a semiconductor package using the sealing resin sheet A of Example 1, instead of the vacuum flat plate press, a compression molding apparatus WCM-300 (manufactured by Apic Yamada) was placed on the obtained chip mounting interposer. Measurement and rewiring of the difference between the thickness of the thickest part and the thickness of the thinnest part in the same manner as in Example 1 except that the sealing resin sheet A was pasted under the following molding conditions. The formability of was evaluated. The results are shown in Table 2.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
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CN110183818A (zh) * 2018-02-22 2019-08-30 味之素株式会社 晶片级封装密封用树脂组合物
CN110246809A (zh) * 2018-03-08 2019-09-17 日东电工株式会社 密封用片

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KR102334181B1 (ko) * 2016-03-25 2021-12-03 쇼와덴코머티리얼즈가부시끼가이샤 유기 인터포저 및 유기 인터포저의 제조 방법
KR102140259B1 (ko) 2018-01-11 2020-07-31 주식회사 엘지화학 반도체 몰딩용 에폭시 수지 조성물, 이를 이용한 몰딩필름 및 반도체 패키지
JP7217865B2 (ja) * 2018-02-22 2023-02-06 味の素株式会社 ウエハーレベルパッケージ封止用樹脂組成物

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JP2001332654A (ja) * 2000-03-17 2001-11-30 Matsushita Electric Ind Co Ltd 電気素子内蔵モジュール及びその製造方法
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CN110246809A (zh) * 2018-03-08 2019-09-17 日东电工株式会社 密封用片

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