WO2015058674A1 - 一种存储单元、存储器及存储单元控制方法 - Google Patents
一种存储单元、存储器及存储单元控制方法 Download PDFInfo
- Publication number
- WO2015058674A1 WO2015058674A1 PCT/CN2014/089044 CN2014089044W WO2015058674A1 WO 2015058674 A1 WO2015058674 A1 WO 2015058674A1 CN 2014089044 W CN2014089044 W CN 2014089044W WO 2015058674 A1 WO2015058674 A1 WO 2015058674A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- port
- memory
- driving
- storage area
- driving circuit
- Prior art date
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/14—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements
- G11C11/15—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements using multiple magnetic layers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/161—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1675—Writing or programming circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/02—Digital stores in which the information is moved stepwise, e.g. shift registers using magnetic elements
- G11C19/08—Digital stores in which the information is moved stepwise, e.g. shift registers using magnetic elements using thin films in plane structure
- G11C19/0808—Digital stores in which the information is moved stepwise, e.g. shift registers using magnetic elements using thin films in plane structure using magnetic domain propagation
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/02—Digital stores in which the information is moved stepwise, e.g. shift registers using magnetic elements
- G11C19/08—Digital stores in which the information is moved stepwise, e.g. shift registers using magnetic elements using thin films in plane structure
- G11C19/0808—Digital stores in which the information is moved stepwise, e.g. shift registers using magnetic elements using thin films in plane structure using magnetic domain propagation
- G11C19/0841—Digital stores in which the information is moved stepwise, e.g. shift registers using magnetic elements using thin films in plane structure using magnetic domain propagation using electric current
Definitions
- the present invention relates to the field of data storage technologies, and in particular, to a storage unit, a memory, and a storage unit control method.
- flash there are two ways to store data: flash and hard disk storage.
- the flash memory has a fast reading speed, a small capacity, and a high price.
- Hard disk storage is slow to read and write, and has a large capacity, but the price is cheap.
- nanotrack Racetrack which has the characteristics of high-performance flash memory and low-cost and high-capacity hard disk.
- the existing nano-scale track is composed of a magnetic material, and includes a plurality of magnetic regions, that is, magnetic domains, adjacent magnetic domains are separated by magnetic domain walls, and the plurality of magnetic regions and magnetic domain walls constitute a U-shaped storage track;
- a high voltage driving circuit is disposed at both ends to generate a current pulse for driving the magnetic domain wall, and the magnetic domain wall moves along the track under the action of the current pulse, thereby moving the magnetic domain.
- a pair of read/write devices are disposed at the bottom of the track to perform read and write control on the U-shaped storage track.
- the U-type nano-scale track contains 2N magnetic domains (N is a positive integer greater than or equal to 1), when the magnetic domain wall moves, the right track needs to accommodate the data information of the left track, so 2N magnetic domains can only
- N is a positive integer greater than or equal to 1
- the magnetic track drives 2N magnetic domain wall motion, the high voltage driving circuit at both ends of the top of the track applies a high voltage, and the memory consumes a large amount of power; and the pair of read/write devices only controls two of the magnetic tracks. Memory sticks, high manufacturing costs.
- Embodiments of the present invention provide a storage unit, a memory, and a storage unit control method for improving storage density, reducing power consumption, and manufacturing cost.
- a first aspect of the present invention provides a storage unit, which may include:
- a comb-type magnetic track a first driving circuit, a second driving circuit, a first driving port connected to the first driving circuit, and a second driving port connected to the second driving circuit;
- the comb-type magnetic track includes a first storage area, a second storage area, and a comb handle connecting the first storage area and the second storage area, in the first storage area and the second storage area At least one storage area includes more than two storage strips;
- the first driving circuit is configured to drive the first storage area
- the second driving circuit is configured to drive the second storage area
- a memory strip Controlling an input voltage of the first port, the second port, and the first driving port and the second driving port, and driving of the first driving circuit, in the first storage area a memory strip generates a current pulse and drives magnetic domain movement of the memory strip that generates the current pulse;
- a memory strip generates a current pulse and drives the magnetic domain movement of the memory strip that produces the current pulse.
- the first driving circuit includes a first gate port
- the second driving circuit includes a second gate port for controlling according to a voltage applied at the first gate port Turning on or off the first driving circuit
- the second gate port is for controlling to turn on or off the second driving circuit according to a voltage applied at the second gate port.
- the first storage area is disposed between the first port and the comb handle, and the second storage area is disposed between the second port and the comb handle.
- the memory unit further includes a write circuit and a read circuit disposed at a bottom of the comb-type magnetic track, the write circuit being configured to be in a memory strip and the second storage area in the first storage area
- the memory strip performs a write operation
- the read circuit is configured to perform a read operation on the memory strips in the first storage area and the memory strips in the second storage area.
- the memory unit further includes a memory module coupled to the read circuit, the memory module configured to store from the comb-type magnetic when a magnetic domain in any one of the comb-type magnetic tracks moves The data removed from the track.
- a second aspect of the present invention provides a memory, wherein at least one memory unit can be included;
- the storage unit may include:
- a comb-type magnetic track a first driving circuit, a second driving circuit, a first driving port connected to the first driving circuit, and a second driving port connected to the second driving circuit;
- the comb-type magnetic track includes a first storage area, a second storage area, and a comb handle connecting the first storage area and the second storage area, in the first storage area and the second storage area At least one storage area includes more than two storage strips;
- the first driving circuit is configured to drive the first storage area
- the second driving circuit is configured to drive the second storage area
- a memory strip Controlling an input voltage of the first port, the second port, and the first driving port and the second driving port, and driving of the first driving circuit, in the first storage area a memory strip generates a current pulse and drives magnetic domain movement of the memory strip that generates the current pulse;
- a memory strip generates a current pulse and drives the magnetic domain movement of the memory strip that produces the current pulse.
- the first driving circuit includes a first gate port
- the second driving circuit includes a second gate port for controlling according to a voltage applied at the first gate port Turning on or off the first driving circuit
- the second gate port is for controlling to turn on or off the second driving circuit according to a voltage applied at the second gate port.
- the first storage area is disposed between the first port and the comb handle, and the second storage area is disposed between the second port and the comb handle.
- the memory unit further includes a write circuit and a read circuit disposed at a bottom of the comb-type magnetic track, the write circuit being configured to be in a memory strip and the second storage area in the first storage area
- the memory strip performs a write operation
- the read circuit is configured to perform a read operation on the memory strips in the first storage area and the memory strips in the second storage area.
- the memory unit further includes a memory module coupled to the read circuit, the memory module configured to store from the comb-type magnetic when a magnetic domain in any one of the comb-type magnetic tracks moves The data removed from the track.
- a third aspect of the present invention provides a storage unit control method, wherein the method is applied to the storage unit as described above, the method may include:
- Controlling the first storage area of the storage unit by controlling the input voltage of the first port, the second port, and the first drive port and the second drive port of the storage unit and the driving of the first driving circuit a memory strip that generates a current pulse and drives the magnetic domain movement of the memory strip that produces the current pulse;
- Controlling a second storage area of the storage unit by controlling an input voltage of the first port, the second port, and the first driving port and the second driving port, and driving of a second driving circuit
- One of the memory strips generates a current pulse and drives a memory strip that generates a current pulse Magnetic domain movement.
- the method further includes:
- the first driving circuit is turned on or the second driving circuit is turned on according to an input voltage level of the first gate port and the second gate port of the memory cell.
- the storage unit includes two or more storage strips for storing data, and the storage density is improved;
- the two or more storage strips are controlled by a pair of read/write devices, and the two storage strips are controlled relative to the existing pair of read/write devices, thereby reducing the manufacturing cost;
- the current pulses provided by the drive circuits in the storage unit are only The magnetic domain wall of a memory strip on one side of the track needs to be driven, thereby reducing the driving voltage and reducing power consumption.
- FIG. 1 is a schematic structural diagram of a storage unit according to an embodiment of the present invention.
- FIG. 2 is another schematic structural diagram of a storage unit according to an embodiment of the present invention.
- FIG. 3 is a schematic structural diagram of a memory according to an embodiment of the present disclosure.
- FIG. 4 is a schematic flowchart diagram of a storage unit control method according to an embodiment of the present invention.
- FIG. 1 is a schematic structural diagram of a storage unit 100 according to an embodiment of the present disclosure, where the storage unit 100 includes:
- a comb-type magnetic track 110 a first driving circuit 20, a second driving circuit 30, a first driving port 40 connected to the first driving circuit 20, and a second driving port 50 connected to the second driving circuit 30 ;
- the comb-type magnetic track 110 includes a first storage area 111, a second storage area 112, and a comb handle 113 connecting the first storage area 111 and the second storage area 112, the first storage area 111 and the At least one of the second storage areas 112 includes more than two storage strips (as shown in the figures a, b, ...);
- the first storage area 111 is disposed between the first port A and the comb handle 113
- the second storage area 112 is disposed between the second port B and the comb handle 113.
- the storage strips in the first storage area 111 and the second storage area 112 may each include N (N is a positive integer greater than or equal to 1) storage blocks, wherein, for example, The diagram a-1 is the first magnetic storage area block of the memory strip a, the illustration b-1 is the first magnetic storage area block of the memory strip b, and the illustration aN is the last magnetic storage area block of the memory strip a, and the illustration bN is The end magnetic storage area block of the strip b. It is also conceivable that the embodiment of the present invention only uses the storage unit shown in FIG. The structure is illustrated for analysis, but does not constitute a limitation of the invention.
- the first port A at the top of the comb-type magnetic track 110 is The first storage area 111 includes a top port of one or more storage strips, and the second port B at the top of the comb-type magnetic track 110 is stored by one or more of the second storage areas 112
- the top port of the bar is composed.
- first driving circuit 20 and the second driving circuit 30 can both be designed as transistors of a metal-oxide-semiconductor (MOS) structure or transistors of a CMOS structure or a driving circuit composed of the same. It is not specifically limited here.
- MOS metal-oxide-semiconductor
- the first driving circuit 20 is used to drive the first storage area 111, and the second driving circuit 30 is used to drive the second storage area 112;
- the control of the input voltage of the first port A, the second port B, and the first driving port 40 and the second driving port 50 and the driving of the first driving circuit 20 A memory strip in a memory region 111 generates a current pulse and drives magnetic domain movement of the memory strip that generates the current pulse;
- the first driving circuit 20 When the first driving circuit 20 is driven, when a current pulse is generated in the first storage region 111, the magnetic domain wall movement in the first storage region 111 is driven, and at the same time, in order to save energy and ensure the first The storage area 111 operates normally, and the second drive circuit 30 is turned off, that is, the second drive circuit 30 does not operate.
- the control of the input voltage of the first port A, the second port B, and the first driving port 40 and the second driving port 50 and the driving of the second driving circuit 30 A memory strip in the two memory regions 112 generates a current pulse and drives the magnetic domain movement of the memory strip that produces the current pulse.
- the first driving circuit 30 When the first driving circuit 30 is driven, when a current pulse is generated in the first storage region 112, the magnetic domain wall movement in the second storage region 112 is driven, and at the same time, in order to save energy and ensure the second The storage area 112 operates normally, and the second driving circuit 20 is turned off, that is, the second driving Circuit 20 does not work.
- the storage unit 100 provided by the embodiment of the present invention includes two or more storage strips for storing data, which improves storage density; and the two or more storage strips are controlled by a pair of read/write devices, The existing pair of reading and writing devices control two storage strips, which reduces the manufacturing cost; in addition, the current pulse provided by the driving circuit in the storage unit 100 only needs to drive the magnetic domain wall of one storage strip on one side of the track, thereby reducing Drive voltage also reduces power consumption.
- the first driving circuit 20 includes a first gate port 201
- the second driving circuit 30 includes a second gate port 301
- the first gate port 201 is used for Controlling the first driving circuit 20 to be turned on or off according to a magnitude of a voltage applied to the first gate port 201
- the second gate port 301 is for applying according to the second gate port 301
- the voltage magnitude controls the second drive circuit 30 to be turned on or off.
- the first storage area 111 if the input voltage is controlled by the first port A, the second port B, and the first driving port 40 and the second driving port 50, So that the voltage difference between the two ends of one of the storage strips 111 (such as the storage strip a) (ie, the top port corresponding to the storage strip and the first drive port 40) is greater than or equal to the criticality of the magnetic domain movement
- the voltage, the voltage difference between the two ends of the other memory strips of the first storage area 111 (ie, the top port corresponding to the memory strip and the first driving port 40) is smaller than the threshold voltage of the magnetic domain movement
- the second storage area 112 is all a voltage difference between the two ends of the memory strip (ie, the memory strip and the first driving port 50) is smaller than a threshold voltage of the magnetic domain movement; and, the voltage of the first gate port 201 is controlled to turn on the first driving
- the circuit 20 controls the voltage of the second gate port 301 to turn off the second driving circuit 30; thereby, under the driving of
- the magnetic domain in the strip a moves to perform a read operation or a write operation on the memory strip a; in addition, it is easily conceivable that the voltage across the memory strip 100 in the memory cell 100 is proportional to the moving distance of the magnetic domain, That is to say, when the moving distance becomes long, if the same magnetic domain speed is maintained, it is necessary to increase the voltage across the corresponding memory strip a.
- the first The storage strips in a storage area 111 and the storage strips in the second storage area 112 do not work simultaneously, that is, only one memory stick is controlled at a time for a read operation or a write operation.
- the other storage strips of the first storage area 111 and the storage strip control operations of the second storage area 112 can refer to the control process of the first storage area 111, and details are not described herein again.
- the memory unit 100 further includes a write circuit 60 and a read circuit 70 disposed at the bottom of the comb-type magnetic track 110, and the write circuit 60 is used to be in the first storage area 111.
- the storage strip and the storage strip in the second storage area 112 perform a write operation, and the read circuit 70 is configured to store the storage strips in the first storage area 111 and the storage strips in the second storage area 112 Read it.
- the principle of storing the strips in the comb-type magnetic track 110 is to use the movement of the magnetic domains to store information; preferably, the first driving circuit 20 and the second driving circuit 30 are disposed in the The bottom of the comb-type magnetic track 110 drives the magnetic domain movement of the memory strip in the first storage area 111 and the memory strip in the second storage area 112, respectively, so M (the M is a positive integer equal to or greater than 2)
- M the M is a positive integer equal to or greater than 2
- the M*N magnetic domains in the memory strips can store M*N-bit data, which improves the storage density.
- the memory unit 100 further includes a memory module connected to the read circuit 70, and the memory module is configured to store when the magnetic domain in any one of the comb-type magnetic tracks 110 moves The data removed by the comb-type magnetic track 110.
- the MOS driving circuit (the first driving circuit 20 or The driving of the second driving circuit 30) may generate a current pulse in the comb-type magnetic track 110 (one memory strip in the first storage area 111 or one of the second storage areas 112) to drive the magnetic domain wall mobile.
- Data is written through the write circuit 60 at the bottom of the track, through The bottom read circuit 70 performs data reading.
- FIG. 2 is a schematic structural diagram of the storage unit 100 provided in the application scenario, and may refer to Table 1 and Table 2 together, where Table 1 is a write operation of the storage unit 100. Port voltage control is shown, and Table 2 shows the port voltage control when the memory unit 100 performs a read operation:
- the first storage area 111 is composed of three storage strips, a storage strip 5 and a storage strip 6, and the second storage area 112 is composed of a storage strip 1, a storage strip 2, and a storage strip.
- 3 three memory bars are composed, as shown in FIG. 2, correspondingly, that is, the first port A is composed of ports 44, 55, 66, and the second port B is composed of ports 11, 22, 33;
- the first storage area 111 and the second storage area 112 may also be composed of two, four or more storage strips, and the number of storage strips may be different, which is not exemplified herein. Limited.
- the MOS transistors in the first driving circuit 20 and the second driving circuit 30 are exemplified by an enhanced N-tube. Please refer to Table 1. If a write operation is performed on the memory stick 1, a voltage of +Vpp is applied to the port 11, in Ports 22-66 are respectively applied with a voltage V-inhibit, a voltage Vss is applied to the first gate port 201, and the second gate port 301, the second driving port 50 and the first driving port 40 are both connected to the ground, wherein the Vss value is greater than The N-tube threshold voltage Vt1, the first gate port 201, and the second gate port 301 are applied with a voltage Vss to enable the MOS transistor in the driving circuit to be turned on; the spin-transfer threshold voltage of the memory strip is defined as Vt2, and the Vpp value is greater than or equal to Vt2. That is, Vpp can generate a current pulse in the memory strip; the voltage V-inhibit is smaller than Vt2, and the value of Vpp-(V-inhibit) is smaller
- the write operation control is performed on the memory strip 1.
- the second gate port 301 is applied with a voltage Vss, and the left MOS transistor is selected (ie, the MOS transistor in the second drive circuit 30 is gated), and the first gate port 201 is connected.
- the port 11 corresponding to the memory strip 1 is applied with a voltage Vpp, and the second driving port 50 is grounded; the voltage across the memory strip 1 is Vpp, which is greater than The threshold voltage Vt2 is rotated by rotation, and under the driving of the second driving circuit 30, a current pulse is generated in the memory strip 1, and the magnetic domain in the memory strip 1 moves, because the direction of the magnetic domain moves is opposite to the current direction. Therefore, the magnetic domain wall in the drive memory stick 1 is moved by the write circuit 60 and the read circuit 70 to the port 11 to implement a write operation.
- Ports 22-66 are applied with voltage V-inhibit, and the voltage across the strips 2-6 is Vpp-(V-inhibit), which is smaller than the spin-transition threshold voltage Vt2, which is insufficient to drive the magnetic domain wall movement; it can be understood that
- Vpp-(V-inhibit) which is smaller than the spin-transition threshold voltage Vt2, which is insufficient to drive the magnetic domain wall movement; it can be understood that
- the magnitude of the voltage applied to the first driving port 40 has no effect on the operation process, because the right MOS transistor (ie, the MOS transistor in the second driving circuit 30) is turned off.
- the voltage of the first driving port 40 is set here.
- the first drive port 50 has the same voltage.
- the memory strip 1 is read and controlled, and the second gate port 301 is applied with a voltage Vss, and the left MOS transistor is selected (ie, the MOS transistor in the second driving circuit 30 is gated), and the first gate port 201 is connected.
- the port 11 corresponding to the memory strip 1 is grounded, the second driving port 50 is applied with a voltage Vpp; the voltage across the memory strip 1 is Vpp, which is greater than The threshold voltage Vt2 is rotated by rotation, and under the driving of the second driving circuit 30, a current pulse is generated in the memory strip 1, and the magnetic domain in the memory strip 1 moves, because the direction of the magnetic domain moves is opposite to the current direction. Therefore, the magnetic domain wall in the drive memory strip 1 is moved from the port 11 to the write circuit 60 and the read circuit 70 to effect a read operation.
- Ports 22-66 are applied with voltage V-inhibit, and the voltage across the strips 2-6 is Vpp-(V-inhibit), which is smaller than the spin-transition threshold voltage Vt2, which is insufficient to drive the magnetic domain wall movement; it can be understood that
- Vpp-(V-inhibit) which is smaller than the spin-transition threshold voltage Vt2, which is insufficient to drive the magnetic domain wall movement; it can be understood that
- the magnitude of the voltage applied to the first driving port 40 has no effect on the operation process, because the right MOS transistor (ie, the MOS transistor in the second driving circuit 30) is turned off.
- the voltage of the first driving port 40 is set here.
- the first drive port 50 has the same voltage.
- the magnitude of the voltage Vpp-(V-inhibit) is insufficient to generate a current pulse to move the magnetic region, and the voltage Vpp is greater than the spin-transfer threshold voltage Vt2, so that the memory strip is controlled by controlling the voltage of each port of the memory unit 100. It doesn't work at the same time, that is, it only controls one memory stick at a time for reading or writing.
- the writing circuit 60 and the reading circuit 70 of the memory unit 100 provided by the embodiment of the present invention have the same working principle as the conventional magnetic track reading and writing device, and are not specifically described herein. It is also conceivable that the embodiment of the present invention only uses the memory cell structure shown in FIG. 2 and its read and write operations. The control process is described analytically, but does not constitute a limitation of the invention.
- the storage unit 100 provided by the embodiment of the present invention includes two or more storage strips for storing data, which improves storage density; and the two or more storage strips are controlled by a pair of read/write devices, and The existing pair of reading and writing devices control the two storage strips, which reduces the manufacturing cost; in addition, the current pulse provided by the driving circuit in the storage unit 100 only needs to drive the magnetic domain wall of one storage strip on one side of the track, so Reduce drive voltage and reduce power consumption.
- the embodiment of the present invention further provides a memory based on the storage unit 100 and a control method of the storage unit 100.
- the meaning of the noun is the same as that in the foregoing storage unit 100.
- FIG. 3 is a schematic structural diagram of a memory 200 according to an embodiment of the present invention.
- the memory 200 includes at least one storage unit 100 as described above.
- the memory 200 provided by the embodiment of the present invention includes the storage unit 100 as described above, and the storage unit 100 includes two or more storage strips for storing data, thereby increasing storage density; and, the two or more storage strips pass through one Controlling the read/write device, controlling two memory sticks relative to the existing pair of read/write devices, reducing manufacturing cost; in addition, the current pulse provided by the drive circuit in the memory unit 100 only needs to drive one memory strip on one side of the track The magnetic domain wall moves, thus reducing the drive voltage and reducing power consumption.
- FIG. 4 is a schematic flowchart of a method for controlling a storage unit 100 according to an embodiment of the present invention.
- the method is applied to the storage unit 100 provided in the foregoing embodiment, and may refer to FIG. 1 or FIG. 2 is a schematic structural diagram of a storage unit 100 shown in FIG. 2; the method includes:
- Step 101 Control the storage by controlling the input voltages of the first port A, the second port B, and the first driving port 40 and the second driving port 50 of the storage unit 100 and the driving of the first driving circuit 20
- One of the first storage areas 111 of the unit 100 generates a current pulse Punching and driving the magnetic domain wall movement of the memory strip that generates the current pulse;
- Step 102 Control the input voltage of the first port A, the second port B, the first driving port 40 and the second driving port 50, and the driving of the second driving circuit 30,
- One of the second storage areas 112 of the memory cell 100 generates a current pulse and drives the magnetic domain wall movement of the memory strip that produces the current pulse.
- the memory unit 100 can include: a comb-type magnetic track 110, a first driving circuit 20, a second driving circuit 30, a first driving port 50 connected to the first driving circuit 20, and a a second driving port 40 connected to the second driving circuit 30;
- the comb-type magnetic track 110 includes a first storage area 111, a second storage area 112, and a connection between the first storage area 111 and the second storage area 112 a comb handle 113, the first storage area 111 is disposed between the first port A and the comb handle 113, and the second storage area 112 is disposed at the second port B and the comb handle 113
- At least one storage area includes two or more storage strips; wherein the first port A of the top of the comb-type magnetic track 110 is a storage area 111 comprises a top port of two or more storage strips; a second port B at the top of the comb-type magnetic track 110 is composed of a top port of two or more storage strips included in the second
- first driving circuit 20 in the memory unit 100 includes a first gate port 201
- second driving circuit 30 includes a second gate port 301.
- the control method may further include:
- the first driving circuit is turned on or the second driving circuit is turned on according to the input voltage magnitude of the first gate port 201 and the second gate port 301 of the memory cell 100.
- the control of the input voltage of the port 50 is such that the voltage difference between the two ends of a storage strip (such as the storage strip a) in the first storage area 111 (ie, the top port corresponding to the storage strip and the first drive port 40) is greater than Or equal to the threshold voltage of the magnetic domain movement, the voltage difference between the two ends of the other storage strips of the first storage area 111 (ie, the top port corresponding to the memory strip and the first driving port 40) is smaller than the threshold voltage of the magnetic domain movement, And a voltage difference between the ends of all the storage strips of the second storage area 112 (ie, the memory strip and the first driving port 50) is smaller than a threshold voltage of the magnetic domain movement; and, the voltage of the first gate port 201 is controlled.
- a storage strip such as the storage strip a
- the storage strips in the first storage area 111 and the storage strips in the second storage area 112 do not work at the same time, that is, each time Only one bank is controlled for read or write operations.
- the other storage strips of the first storage area 111 and the storage strip control operations of the second storage area 112 can refer to the control process of the first storage area 111, and details are not described herein again.
- the memory unit 100 further includes a write circuit 60 and a read circuit 70 disposed at the bottom of the comb-type magnetic track 110, and a memory module connected to the read circuit 70, and thus the method further
- the writing circuit 60 may perform a write operation on the first storage area 111 and the second storage area 112, and the read circuit 70 pairs the first storage area 111 and the second storage area 112 performing a read operation; when a memory strip (such as a) in the first storage area 111 or a magnetic strip in a storage strip (such as b) in the second storage area 1121 moves, the storage module stores from the The data removed by the comb-type magnetic track 110.
- the storage unit 100 control method provided by the embodiment of the present invention is applied to the storage unit 100 as described in the foregoing embodiment, and the method controls that two or more storage strips in the storage unit 100 can be used for storing data, thereby improving Storage density; and, the two or more memory sticks only pass
- the pair of reading and writing devices are controlled to control the two storage strips with respect to the existing pair of reading and writing devices, thereby reducing the manufacturing cost.
- the method also controls the current pulse provided by the driving circuit in the storage unit 100 to drive only the track side. The magnetic domain wall of one of the memory strips moves, thereby reducing the driving voltage and reducing power consumption.
- the disclosed system, apparatus, and method may be implemented in other manners.
- the device embodiments described above are merely illustrative.
- the division of the unit is only a logical function division.
- there may be another division manner for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored or not executed.
- the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be in an electrical, mechanical or other form.
- the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
- each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
- the above integrated unit can be implemented in the form of hardware or in the form of a software functional unit.
- the integrated unit if implemented in the form of a software functional unit and sold or used as a standalone product, may be stored in a computer readable storage medium.
- the storage medium includes instructions for causing a computer device (which may be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present invention.
- the foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and the like. .
Abstract
Description
Claims (8)
- 一种存储单元,其特征在于,包括:梳型磁性轨道,第一驱动电路,第二驱动电路,与所述第一驱动电路连接的第一驱动端口,以及与所述第二驱动电路连接的第二驱动端口;所述梳型磁性轨道包括第一存储区域,第二存储区域以及连接所述第一存储区域和所述第二存储区域的梳柄,所述第一存储区域和所述第二存储区域中的至少一个存储区域包括两个以上存储条;其中,所述第一驱动电路用于驱动所述第一存储区域,所述第二驱动电路用于驱动所述第二存储区域;通过对所述第一端口、所述第二端口以及所述第一驱动端口和所述第二驱动端口的输入电压的控制以及所述第一驱动电路的驱动,所述第一存储区域中的一个存储条产生电流脉冲,并驱动产生电流脉冲的存储条的磁畴移动;通过对所述第一端口、所述第二端口以及所述第一驱动端口和所述第二驱动端口的输入电压的控制以及所述第二驱动电路的驱动,所述第二存储区域中的一个存储条产生电流脉冲,并驱动产生电流脉冲的存储条的磁畴移动。
- 根据权利要求1所述的存储单元,其特征在于:所述第一驱动电路包括第一栅极端口,所述第二驱动电路包括第二栅极端口,所述第一栅极端口用于根据在所述第一栅极端口施加的电压大小,控制接通或关闭所述第一驱动电路;所述第二栅极端口用于根据在所述第二栅极端口施加的电压大小,控制接通或关闭所述第二驱动电路。
- 根据权利要求1所述的存储单元,其特征在于:所述第一存储区域设置于所述第一端口与所述梳柄之间,所述第二存储区域设置于所述第二端口与所述梳柄之间。
- 根据权利要求1至3任一项所述的存储单元,其特征在于:所述存储单元还包括设置于所述梳型磁性轨道底部的写入电路和读取电路,所述写入电路用于对所述第一存储区域中的存储条和所述第二存储区域中的存储条进行写操作,所述读取电路用于对所述第一存储区域中的存储条和所述第二存储区域中的存储条进行读操作。
- 根据权利要求4所述的存储单元,其特征在于:所述存储单元还包括与所述读取电路连接的存储模块,所述存储模块用于当所述梳型磁性轨道中的任一个存储条内的磁畴移动时,存储从所述梳型磁性轨道移出的数据。
- 一种存储器,其特征在于,包括至少一个如权利要求1至5任一项所述的存储单元。
- 一种存储单元控制方法,其特征在于,应用于如权利要求1至5任一项所述的存储单元,所述方法包括:通过对所述存储单元的第一端口、第二端口以及第一驱动端口和第二驱动端口的输入电压的控制以及所述第一驱动电路的驱动,控制所述存储单元的第一存储区域中的一个存储条产生电流脉冲,并驱动产生电流脉冲的存储条的磁畴移动;通过对所述第一端口、所述第二端口以及所述第一驱动端口和所述第二驱动端口的输入电压的控制以及第二驱动电路的驱动,控制所述存储单元的第二存储区域中的一个存储条产生电流脉冲,并驱动产生电流脉冲的存储条的磁畴移动。
- 根据权利要求7所述的控制方法,其特征在于,所述方法还包括:根据所述存储单元的第一栅极端口以及第二栅极端口的输入电压大小,接通所述第一驱动电路,或者接通所述第二驱动电路。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020167012523A KR101814029B1 (ko) | 2013-10-21 | 2014-10-21 | 저장 유닛, 메모리 및 저장 유닛 제어 방법 |
EP14856459.4A EP3048611B1 (en) | 2013-10-21 | 2014-10-21 | Memory unit, memory and control method for the memory unit |
US15/133,452 US9653178B2 (en) | 2013-10-21 | 2016-04-20 | Magnetic track storage unit, memory, and method for controlling magnetic track storage unit |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201310496705.2A CN104575582B (zh) | 2013-10-21 | 2013-10-21 | 一种存储单元、存储器及存储单元控制方法 |
CN201310496705.2 | 2013-10-21 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/133,452 Continuation US9653178B2 (en) | 2013-10-21 | 2016-04-20 | Magnetic track storage unit, memory, and method for controlling magnetic track storage unit |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2015058674A1 true WO2015058674A1 (zh) | 2015-04-30 |
Family
ID=52992274
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/CN2014/089044 WO2015058674A1 (zh) | 2013-10-21 | 2014-10-21 | 一种存储单元、存储器及存储单元控制方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US9653178B2 (zh) |
EP (1) | EP3048611B1 (zh) |
KR (1) | KR101814029B1 (zh) |
CN (1) | CN104575582B (zh) |
WO (1) | WO2015058674A1 (zh) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104575581B (zh) * | 2013-10-21 | 2017-10-10 | 华为技术有限公司 | 一种存储单元、存储器及存储单元控制方法 |
KR20210021225A (ko) | 2019-08-16 | 2021-02-25 | 삼성전자주식회사 | 자기 메모리 장치 |
CN117174139A (zh) * | 2023-08-25 | 2023-12-05 | 合芯科技(苏州)有限公司 | 一种信号生成电路及存储器 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101145571A (zh) * | 2006-09-15 | 2008-03-19 | 三星电子株式会社 | 采用磁畴壁移动的存储器装置 |
CN101154436A (zh) * | 2006-09-29 | 2008-04-02 | 三星电子株式会社 | 数据存储装置以及操作该数据存储装置的方法 |
CN101188271A (zh) * | 2006-11-20 | 2008-05-28 | 三星电子株式会社 | 具有磁畴壁移动的数据存储装置及形成该装置的方法 |
CN101635166A (zh) * | 2008-07-14 | 2010-01-27 | 三星电子株式会社 | 使用磁畴壁移动的信息存储装置以及操作该装置的方法 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7957175B2 (en) | 2006-12-22 | 2011-06-07 | Samsung Electronics Co., Ltd. | Information storage devices using movement of magnetic domain walls and methods of manufacturing the same |
KR101323719B1 (ko) * | 2007-10-12 | 2013-10-30 | 삼성전자주식회사 | 자성층, 자성층의 형성방법, 자성층을 포함하는정보저장장치 및 정보저장장치의 제조방법 |
US7626844B1 (en) | 2008-08-22 | 2009-12-01 | International Business Machines Corporation | Magnetic racetrack with current-controlled motion of domain walls within an undulating energy landscape |
US7551469B1 (en) | 2009-01-05 | 2009-06-23 | Internationa Business Machines Corporation | Unidirectional racetrack memory device |
KR20100104044A (ko) | 2009-03-16 | 2010-09-29 | 삼성전자주식회사 | 정보저장장치 및 그의 동작방법 |
-
2013
- 2013-10-21 CN CN201310496705.2A patent/CN104575582B/zh active Active
-
2014
- 2014-10-21 KR KR1020167012523A patent/KR101814029B1/ko active IP Right Grant
- 2014-10-21 EP EP14856459.4A patent/EP3048611B1/en active Active
- 2014-10-21 WO PCT/CN2014/089044 patent/WO2015058674A1/zh active Application Filing
-
2016
- 2016-04-20 US US15/133,452 patent/US9653178B2/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101145571A (zh) * | 2006-09-15 | 2008-03-19 | 三星电子株式会社 | 采用磁畴壁移动的存储器装置 |
CN101154436A (zh) * | 2006-09-29 | 2008-04-02 | 三星电子株式会社 | 数据存储装置以及操作该数据存储装置的方法 |
CN101188271A (zh) * | 2006-11-20 | 2008-05-28 | 三星电子株式会社 | 具有磁畴壁移动的数据存储装置及形成该装置的方法 |
CN101635166A (zh) * | 2008-07-14 | 2010-01-27 | 三星电子株式会社 | 使用磁畴壁移动的信息存储装置以及操作该装置的方法 |
Also Published As
Publication number | Publication date |
---|---|
CN104575582B (zh) | 2018-05-04 |
US20160232984A1 (en) | 2016-08-11 |
EP3048611A4 (en) | 2016-10-19 |
CN104575582A (zh) | 2015-04-29 |
KR101814029B1 (ko) | 2018-01-02 |
EP3048611B1 (en) | 2022-04-06 |
US9653178B2 (en) | 2017-05-16 |
EP3048611A1 (en) | 2016-07-27 |
KR20160069518A (ko) | 2016-06-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI532043B (zh) | 雙埠靜態隨機存取記憶體 | |
DE112012007140T5 (de) | SRAM-Bitleitungs- und Schreibunterstützungsgerät und Verfahren zum Verringern der dynamischen Leistung und des Spitzenstroms und Pegelumsetzer mit dualem Eingang | |
WO2015058674A1 (zh) | 一种存储单元、存储器及存储单元控制方法 | |
US8228706B2 (en) | Magnetic shift register memory device | |
US10832761B2 (en) | Polarization gate stack SRAM | |
CN105745715A (zh) | 使用电阻式存储器的具有保持性的存储器单元 | |
US20170236566A1 (en) | Data transfer for multi-loaded source synchrous signal groups | |
Chatterjee et al. | Ferroelectric fdsoi fet modeling for memory and logic applications | |
Endoh | Nonvolatile logic and memory devices based on spintronics | |
WO2015058647A1 (zh) | 一种存储单元、存储器及存储单元控制方法 | |
WO2016066053A1 (zh) | 一种磁性存储器 | |
US9761304B1 (en) | Write-bitline control in multicore SRAM arrays | |
Beach | Beyond the speed limit | |
CN107430889A (zh) | 半导体存储装置的改写方法以及半导体存储装置 | |
EP3136390B1 (en) | Write device and magnetic memory | |
US20210183411A1 (en) | Memory array with access line control | |
CN110196821A (zh) | 半导体器件 | |
Tyler | Deterministic write concept unveiled by imec | |
Deepika et al. | T-CAD Design Simulation and Comparative Performance Analysis of 6-T SRAM Cell with Nanoscale SOI and MOS Technology | |
SILIVERI | FIR High Speed VLSI Design for Area Efficient Parallel Digital Filter Structure for Low Power CMOS Voltage Mode SRAM Cell | |
Loy et al. | Optimised circuit configuration for STT-MTJ logic devices | |
Zhu et al. | Leakage Reduction of Improved CAL Registers Using MTCMOS Power-Gating Scheme in Nanometer CMOS Processes | |
Wang | A Question for AAAI: Does AI Need a Reboot? | |
Moni et al. | Device Modeling and Transistor Stacking for High Speed with Low Power Requirements Using Double Gate Devices | |
CN105097008A (zh) | 一种驱动脉冲的确定方法、控制器及磁性存储设备 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 14856459 Country of ref document: EP Kind code of ref document: A1 |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
REEP | Request for entry into the european phase |
Ref document number: 2014856459 Country of ref document: EP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2014856459 Country of ref document: EP |
|
ENP | Entry into the national phase |
Ref document number: 20167012523 Country of ref document: KR Kind code of ref document: A |