WO2015053082A1 - Tableau de connexion à couches multiples et son procédé de fabrication - Google Patents

Tableau de connexion à couches multiples et son procédé de fabrication Download PDF

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Publication number
WO2015053082A1
WO2015053082A1 PCT/JP2014/075255 JP2014075255W WO2015053082A1 WO 2015053082 A1 WO2015053082 A1 WO 2015053082A1 JP 2014075255 W JP2014075255 W JP 2014075255W WO 2015053082 A1 WO2015053082 A1 WO 2015053082A1
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WIPO (PCT)
Prior art keywords
interlayer connection
hole
plating
layer
electrolytic
Prior art date
Application number
PCT/JP2014/075255
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English (en)
Japanese (ja)
Inventor
信之 吉田
Original Assignee
日立化成株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP2014147755A external-priority patent/JP6350063B2/ja
Application filed by 日立化成株式会社 filed Critical 日立化成株式会社
Priority to CN201480055473.XA priority Critical patent/CN105612820B/zh
Priority to US15/027,784 priority patent/US9648759B2/en
Publication of WO2015053082A1 publication Critical patent/WO2015053082A1/fr

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/423—Plated through-holes or plated via connections characterised by electroplating method
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0355—Metal foils
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0388—Other aspects of conductors
    • H05K2201/0397—Tab
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09863—Concave hole or via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/20—Details of printed circuits not provided for in H05K2201/01 - H05K2201/10
    • H05K2201/2072—Anchoring, i.e. one structure gripping into another
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
    • H05K2203/1184—Underetching, e.g. etching of substrate under conductors or etching of conductor under dielectrics; Means for allowing or controlling underetching
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14—Related to the order of processing steps
    • H05K2203/1476—Same or similar kind of process performed in phases, e.g. coarse patterning followed by fine patterning
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
    • H05K3/0032—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
    • H05K3/0035—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material of blind holes, i.e. having a metal layer at the bottom
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
    • H05K3/0032—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
    • H05K3/0038—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material combined with laser drilling through a metal layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern

Definitions

  • the present invention relates to a multilayer wiring board and a method for manufacturing the same, and more particularly to a multilayer wiring board for forming an interlayer connection using an electrolytic filled plating solution and a method for manufacturing the same.
  • a prepreg or resin film and a metal foil are laminated and integrated on an inner layer material on which wiring is formed, and an interlayer connection hole is formed by a laser to form a base electroless plating layer, followed by electrolytic field plating.
  • a multilayer wiring board is used in which the hole for interlayer connection is filled with an electrolytic plating layer (hereinafter, simply referred to as “electrolytic filled plating layer”) formed using a liquid.
  • a plating void (hereinafter simply referred to as “void”) is provided inside the via. There is a tendency to occur).
  • void a plating void
  • Patent Document 1 a multilayer wiring board to which an electroplating method performed for a long time at a low current density or an electroplating method in which the current density is controlled stepwise has been proposed.
  • Patent Document 2 a multilayer wiring board to which a method of forming an electrolytic plating layer in two steps is applied from the viewpoint of surface smoothness
  • the cross-sectional shape of the hole for interlayer connection may be narrower at the opening rather than the inside or the bottom.
  • a current density is used as a method of manufacturing a multilayer wiring board having a multilayer structure in which an insulating layer made of an organic insulating material such as polyimide resin and a wiring made of a conductor material such as copper are alternately laminated.
  • an insulating layer made of an organic insulating material such as polyimide resin
  • a wiring made of a conductor material such as copper
  • An object of the present invention is to provide a multilayer wiring board capable of suppressing plating voids of an electrolytic filled plating layer even for an interlayer connection hole having a diameter comparable to the insulating layer thickness.
  • the present invention relates to the following. 1.
  • a laminated body formed by laminating and integrating an inner layer material forming an inner layer wiring, an insulating layer, and a metal foil for upper layer wiring, and for interlayer connection penetrating the metal foil for upper layer wiring and the insulating layer of this laminated body And a lower space formed between the protrusion of the metal foil for upper layer wiring formed in the opening of the hole for interlayer connection and the inner wall of the hole for interlayer connection.
  • an interlayer connection in which the hole for interlayer connection is filled with an electrolytic filled plating layer, and the electrolytic field plating layer filling the hole for interlayer connection is formed in at least two or more layers Of the metal foil for upper wiring formed in the opening of the hole for interlayer connection by the electrolytic filled plating layer of any one layer except the outermost layer among the two or more electrolytic filled plating layers.
  • the layer indirect formed by any one of the two or more electrolytic filled plating layers excluding the outermost layer is formed in an opening of a hole for interlayer connection.
  • Electrolytic filled plating fills the lower space between the metal foil for upper layer wiring and the inner wall of the hole for interlayer connection, and the maximum inner diameter of the interlayer connection is larger than the minimum diameter of the opening.
  • a multilayer wiring board that is shaped like 3. Item 2 or 2 is that the electrolytic filled plating layer filling the interlayer connection hole is formed in two layers, and among the two electrolytic filled plating layers, an interlayer connection is made by a lower electrolytic filled plating layer.
  • An interlayer formed by a lower electrolytic filling plating layer filled with a lower space between the protrusion of the upper layer wiring metal foil formed in the opening of the hole for use and the inner wall of the interlayer connection hole A multilayer wiring board in which the maximum internal diameter of the connection is equal to or greater than the minimum diameter of the opening. 4).
  • Item 4. The multilayer wiring board according to any one of Items 1 to 3, wherein the interlayer connection hole is a non-through hole that penetrates through the upper layer wiring metal foil and the insulating layer of the laminate and reaches the inner layer wiring. 5.
  • Item 5. The multilayer wiring board according to any one of Items 1 to 4, wherein the aspect ratio of the hole for interlayer connection is 1.0 or more.
  • the present invention it is possible to provide a multilayer wiring board capable of suppressing plating voids of an electrolytic filled plating layer even for an interlayer connection hole having a diameter comparable to the insulating layer thickness.
  • Example 1 is a multilayer wiring board according to an embodiment of the present invention (Examples 1 to 5).
  • Step (1) of the method for manufacturing a multilayer wiring board of one embodiment (Examples 1 to 5) of the present invention is shown.
  • Step (2) of the method for producing a multilayer wiring board according to one embodiment (Examples 1 to 5) of the present invention is shown.
  • Step (3) of the method for producing a multilayer wiring board of one embodiment of the present invention (Examples 1 to 5) is shown.
  • Process (2) of the manufacturing method of the multilayer wiring board of the comparative example 2 is shown.
  • Step (2) of the method for producing a multilayer wiring board of Comparative Example 1 is shown.
  • the electric current density of the electrolytic field plating of the manufacturing method of the multilayer wiring board of one Embodiment (Example 2) of this invention is shown.
  • Multilayer wiring board As an embodiment of the multilayer wiring board of the present invention, as shown in FIG. 1, the inner layer material 2 on which the inner layer wiring 1 is formed, the insulating layer 3 and the metal foil 4 for the upper layer wiring 10 are laminated and integrated. A layered body 22, an interlayer connection hole 5 penetrating the metal foil 4 for the upper layer wiring 10 and the insulating layer 3 of the layered body 22, and an upper layer formed in the opening of the layer connection hole 5.
  • a lower space 13 between the protrusion 12 and the inner wall 18 of the interlayer connection hole 5 is filled, and the interlayer connection 15 is formed by any one of the electrolytic filled plating layers 7a and 7b except the outermost layer.
  • the laminate in the present embodiment is formed by laminating and integrating an inner layer material on which inner layer wiring is formed, an insulating layer, and a metal foil for upper layer wiring.
  • the inner layer material is used for a general inner layer of a multilayer wiring board, and generally, copper, copper, on the upper surface and / or lower surface of a required number of prepregs (resin impregnated base material) impregnated with a resin composition in a reinforcing base material.
  • a metal foil made of aluminum, brass, nickel, iron or the like alone, an alloy, or a composite foil is laminated and integrated, and the metal foil is etched to form an inner layer wiring.
  • the prepreg is an insulating layer that bonds the inner layer material and the copper foil for the upper layer wiring, and impregnates the resin composition (resin varnish) into glass fiber or the like that is the reinforcing base material to bring it into a semi-cured B-stage state.
  • a resin film having adhesive properties As the prepreg, a prepreg used for a general multilayer wiring board can be used. Moreover, the resin film which does not have reinforcement base materials, such as glass fiber, other than a prepreg can also be used.
  • a resin film having no reinforcing substrate such as glass fiber, a polymer epoxy resin or a thermoplastic polyimide adhesive film used for bonding an inner layer material and a copper foil for upper layer wiring in a multilayer wiring board, etc. Is mentioned.
  • thermosetting resin having good heat resistance and chemical resistance
  • one kind of resin such as phenol resin, epoxy resin, polyimide resin, unsaturated polyester resin, polyphenylene oxide resin, fluorine resin or the like.
  • inorganic powder fillers such as talc, clay, silica, alumina, calcium carbonate, aluminum hydroxide, antimony trioxide, and antimony pentoxide, glass fiber, asbestos fiber, pulp fiber
  • a fiber filler such as synthetic fiber or ceramic fiber is added.
  • the resin composition may be blended with a thermoplastic resin in consideration of dielectric properties, impact resistance, film processability, and the like. Further, various additives and fillers such as an organic solvent, a flame retardant, a curing agent, a curing accelerator, thermoplastic particles, a colorant, an ultraviolet light impermeant, an antioxidant and a reducing agent are added as necessary.
  • the reinforcing substrate examples include inorganic fibers such as glass and asbestos, polyester, polyamide, polyacryl, polyvinyl alcohol, polyimide, organic fibers such as fluorine resin, natural fibers such as cotton, nonwoven fabric, paper, mats, etc. Is used.
  • the temperature is usually 100 to 200 ° C. And dried for 1 to 30 minutes to obtain a semi-cured (B-stage) prepreg.
  • 1 to 20 prepregs are stacked and heated and pressed in a configuration in which metal foils are arranged on both sides thereof, and laminated and integrated.
  • a conventional laminate technique can be applied. For example, a multi-stage press, a multi-stage vacuum press, continuous molding, an autoclave molding machine, etc. are used.
  • the thickness of the prepreg serving as the insulating layer varies depending on the application, but a thickness of 0.1 to 5.0 mm is usually preferable.
  • the metal foil a metal foil used for a general multilayer wiring board can be used.
  • the 10-point average roughness (Rz) shown in JIS B0601 is preferably 2.0 ⁇ m or less on both surfaces in terms of electrical characteristics.
  • copper foil, nickel foil, aluminum foil, etc. can be used for metal foil, copper foil is usually used.
  • the production conditions of the copper foil are as follows: in the case of a copper sulfate bath, sulfuric acid 50-100 g / L, copper 30-100 g / L, liquid temperature 20 ° C.-80 ° C., current density 0.5-100 A / dm 2 , pyrophosphoric acid
  • sulfuric acid 50-100 g / L sulfuric acid 50-100 g / L
  • copper 30-100 g / L liquid temperature 20 ° C.-80 ° C.
  • current density 0.5-100 A / dm 2 pyrophosphoric acid
  • potassium pyrophosphate 100-700 g / L, copper 10-50 g / L, liquid temperature 30 ° C.-60 ° C., pH 8-12, current density 1-10 A / dm 2 are generally used.
  • various additives are added in consideration of the physical properties and smoothness of copper.
  • the hole for interlayer connection is a non-through hole that penetrates the metal foil and insulating layer for the upper layer wiring of the laminate and reaches the inner layer wiring, or a through hole that further penetrates the inner layer wiring and reaches the back surface. It is formed.
  • the hole for interlayer connection in this embodiment is a non-through hole or a through hole for forming an interlayer connection called a so-called via hole or through hole, and means a state before the plating layer is formed.
  • the hole for interlayer connection can be formed by applying, for example, a conformal method or a direct laser method.
  • the metal foil for upper layer wiring protrudes from the opening of the hole for interlayer connection.
  • the protrusion of the metal foil is caused by the fact that the laser processing property of the insulating layer is better than that of the metal foil (the thermal decomposition temperature is low).
  • the conformal mask method that performs laser processing of the insulating layer using the edge of the opening (window hole) provided in the metal foil as a mask, and the direct laser method that performs laser processing of the metal foil and the insulating layer without providing an opening in the metal foil are used. As a result, protrusion of the metal foil is formed.
  • a lower space is formed between the protrusion of the metal foil and the inner wall of the hole for interlayer connection.
  • the lower space is a space surrounded by the metal foil for the upper layer wiring and the inner wall of the hole for the interlayer connection.
  • the lower space is a metal foil for the upper layer wiring.
  • Interlayer connection is formed by filling holes for interlayer connection with an electrolytic filled plating layer.
  • the interlayer connection is for connecting a plurality of wiring layers of two or more layers, and is a filled via in which all the holes for interlayer connection are filled with plating layers.
  • the diameter of the interlayer connection is approximately the same as the thickness of the insulating layer (depth of the hole for interlayer connection) to about twice the diameter (metal foil).
  • the diameter of the opening portion approaches the thickness of the insulating layer (depth of the hole for interlayer connection), that is, the ratio of the thickness of the insulating layer to the diameter of the interlayer connection (aspect ratio) is 1.0.
  • voids are likely to occur in the conventional method.
  • An electroless plating layer is formed as an underlayer for the electrolytic filled plating layer.
  • This electroless plating layer is an electroless plating layer provided on the entire surface of the substrate after providing holes for interlayer connection, and is used for metal for upper layer wiring.
  • the surface of the foil, the inner surface of the hole for interlayer connection, the inner wiring surface of the bottom surface of the hole for interlayer connection, etc. are plated.
  • This electroless plating layer can be formed using a thin-type electroless copper plating solution generally used for manufacturing a multilayer wiring board.
  • the electrolytic filled plating layer is an electrolytic plating layer formed by an electrolytic filled plating solution.
  • the thickness of this electrolytic filled plating layer is the thickness of the bottom surface in the hole for interlayer connection rather than the thickness on the metal foil for upper layer wiring. Becomes thicker.
  • the electrolytic filled plating solution is generally obtained by adding a plating inhibitor that suppresses plating growth and a plating accelerator that promotes plating growth to a copper sulfate plating bath.
  • Plating inhibitors apply to the diffusion law of substances, and it is difficult to adsorb inside the hole for interlayer connection, and it is easy to adsorb to the surface of the substrate, so that the substrate is compared with the inside of the hole for interlayer connection.
  • the inside of the hole for interlayer connection is filled with the electrolytic filled copper plating layer, and the part directly above the hole for interlayer connection and the part other than the part directly above the hole for interlayer connection It is said that there is an effect of forming a smooth electrolytic filled copper plating layer on the substrate surface.
  • a nitrogen-containing compound such as a polyether compound such as polyalkylene glycol, a polyvinyl imidazolium quaternized product, and a copolymer of vinyl pyrrolidone and vinyl imidazolium quaternized product.
  • the plating accelerator is uniformly adsorbed on the bottom surface, side surface, and substrate surface in the hole for interlayer connection, and subsequently, the surface area of the interlayer connection hole decreases as the plating grows, Utilizing the fact that the distribution of the accelerator in the connection hole is dense, the plating speed inside the interlayer connection hole becomes faster than the plating speed on the substrate surface, and the inside of the interlayer connection hole is filled with electrolytic filled copper. It is said that there is an effect that a smooth electrolytic filled copper plating layer is formed on the substrate surface by filling with a plating layer, and a portion other than the portion directly above the hole for interlayer connection and the portion directly above the hole for interlayer connection.
  • the plating accelerator is represented by a sulfur compound represented by sodium 3-mercapto-1-propanesulfonate or sodium 2-mercaptoethanesulfonate, or bis- (3-sulfopropyl) -disulfide disodium. Sulfur compounds to be used can be used. These plating accelerators are also a kind of additive added to a copper plating solution called brightener (brightener).
  • the above plating inhibitors and plating accelerators are used alone or in combination of two or more.
  • concentration of these aqueous solutions is not particularly limited, but can be used at a concentration of several mass ppm to several mass%.
  • the electrolytic filled plating layer filling the hole for interlayer connection is formed in at least two layers, and the electrolysis of any of the two or more electrolytic filled plating layers excluding the outermost layer is performed.
  • the filled plating layer fills the lower space between the protrusion of the upper layer wiring metal foil formed in the opening of the interlayer connection hole and the inner wall of the interlayer connection hole, and excludes the outermost layer.
  • the maximum diameter inside the interlayer connection formed by any one of the electrolytic filled plating layers is equal to or greater than the minimum diameter of the opening.
  • the metal foil for upper layer wiring protrudes from the opening of the hole for interlayer connection, and the metal foil for upper layer wiring protrudes and the inner wall of the hole for interlayer connection.
  • a lower space is formed between the two.
  • the immediate lower portion which is a region in the vicinity of the back surface of the metal foil for upper layer wiring, is a region in which the liquid flow of the electrolytic filled plating solution hardly flows in the lower space.
  • the lower space including the immediate lower portion is easy to adsorb the electrolytic filled plating solution promoter, and in the initial stage of electrolytic filled plating, the electrolytic filled plating layer is first formed in the lower space starting from the immediate lower portion. Formed and the lower space is filled.
  • the plating accelerator Once the plating accelerator is adsorbed, it has the property of staying as it is while electrolytic field plating is continued at the same current density. For this reason, as in the prior art, when electrolytic filling plating is continued at the same current density and the electrolytic filling plating layer filling the interlayer connection holes is a single layer, the filled plating layer filling the lower space is directly below. Since the growth is continued starting from the portion and the opening is closed before the inside of the hole for interlayer connection, there is a tendency that plating voids are likely to be generated inside the hole for interlayer connection.
  • the directly lower portion refers to a region near the back surface of the upper layer wiring metal foil that protrudes out of the lower space formed between the protrusion of the upper layer wiring metal foil and the inner wall of the interlayer connection hole.
  • This lower part is easily subjected to laser processing (thermal decomposition) between the resin forming the insulating layer and the metal foil immediately above when the hole for interlayer connection is formed by the conformal method or direct laser method. Due to the large difference in temperature, the inner wall of the insulating layer directly below the metal foil is recessed from the opening end of the metal foil.
  • a resin for adhesion exists immediately below the metal foil, and this resin is more easily laser processed than the reinforcing fiber.
  • it tends to be greatly recessed compared to the inner wall of the metal foil or the hole for interlayer connection. For this reason, since the promoter of the electrolytic filled plating solution is likely to be adsorbed immediately below the electrolytic filled plating solution, the electrolytic filled plating layer tends to grow quickly (thick) and block the opening of the hole for interlayer connection.
  • the electrolytic filled plating layer filling the interlayer connection hole is formed in at least two layers, the current density of the electrolytic filled plating is temporarily reduced during the electrolytic filled plating. Therefore, the accelerator adsorbed on the electrolytic filled plating layer formed immediately below the lower space can be separated at this time.
  • the electrolytic filled plating layer fills the lower space and the inner diameter of the hole for interlayer connection is equal to or greater than the diameter of the opening (plating opening), the interlayer connection corresponding to the immediately lower part The opening portion of the hole is easily adsorbed with the plating inhibitor, while the inside of the hole for interlayer connection is easily adsorbed with the plating accelerator.
  • this effect is greater if the electrolytic filled plating layer fills the lower space and the inner diameter of the interlayer connection is a bowl shape larger than the diameter of the opening (plating opening).
  • the plating opening refers to the narrowest portion where the electrolytic filled plating layer is formed in the metal foil opening. For this reason, after increasing the current density of electrolytic filled plating again, the growth of the electrolytic filled plating layer starting from the bottom is suppressed, so the electrolytic filled plating layer blocks the opening of the hole for interlayer connection. Accordingly, an electrolytic filled plating layer is preferentially formed inside the interlayer connection hole. Therefore, the plating voids of the electrolytic filled plating layer are also applied to the interlayer connection hole having a diameter comparable to the insulating layer thickness, that is, to the interlayer connection hole having an aspect ratio of about 1.0. It becomes possible to suppress.
  • the thickness of the first-stage electrolytic filled plating layer is preferably 1 to 10 ⁇ m, more preferably 2 to 5 ⁇ m as the thickness on the metal foil for the upper wiring, and the inner layer on the bottom surface in the hole for interlayer connection
  • the thickness on the wiring is provided in a range of about 2 to 20 ⁇ m.
  • the thickness of the second stage electrolytic filled plating layer can be used as wiring as the thickness on the metal foil for the upper wiring, and the hole for interlayer connection can be completely embedded with the electrolytic filled plating layer.
  • the thickness on the metal foil for the upper wiring is preferably in the range of 1 to 100 ⁇ m, more preferably in the range of 10 to 50 ⁇ m.
  • the manufacturing method of the multilayer wiring board of the present embodiment is obtained by laminating and integrating the inner layer material in which the inner layer wiring is formed, the insulating layer, and the metal foil for the upper layer wiring, and using the conformal method or the direct laser method, The metal foil for the upper layer wiring, and the metal foil for the upper layer wiring formed in the opening of the hole for the interlayer connection from the metal foil for the upper layer wiring to the inner layer wiring And a step (1) of providing a lower space formed between the protrusion of the metal foil and the inner wall of the hole for interlayer connection, and on the metal foil for the interlayer connection hole and the upper layer wiring. Then, after forming the base electroless plating layer, filling the hole for the interlayer connection by forming the electrolytic filled plating layer, and forming the interlayer connection for connecting the metal foil for upper layer wiring and the inner layer wiring ( 2) and the electrolytic field Forming a metal foil for upper layer wiring after forming a plating layer, and forming an upper layer
  • the hole for the interlayer connection is provided by using the conformal method or the direct laser method.
  • the metal foil for the upper layer wiring jumps out at the opening), and a lower space is formed between the protrusion of the metal foil for the upper layer wiring and the inner wall of the hole for interlayer connection.
  • the immediate lower portion which is a region in the vicinity of the back surface of the metal foil for upper layer wiring, is a region in which the liquid flow of the electrolytic filled plating solution hardly flows in the lower space.
  • the lower space including the immediate lower portion is easy to adsorb the electrolytic filled plating solution promoter, and in the initial stage of electrolytic filled plating, the electrolytic filled plating layer is first formed in the lower space starting from the immediate lower portion. Formed and the lower space is filled.
  • the lower space is a space surrounded between the jump-out of the metal foil for the upper layer wiring and the inner wall of the hole for the interlayer connection. Specifically, from the tip of the jump-out of the metal foil for the upper layer wiring, The space surrounded by the perpendicular line dropped in the direction of the bottom of the hole for interlayer connection and the inner wall of the hole for interlayer connection.
  • the plating accelerator Once the plating accelerator is adsorbed, it has the property of staying as it is while electrolytic field plating is continued at the same current density. For this reason, if electrolytic filling plating is continued at the same current density as in the prior art, the filled plating layer filling the lower space continues to grow starting from the immediately lower part, and before the inside of the hole for interlayer connection. Since the opening is blocked, there is a tendency that plating voids are likely to be generated inside the hole for interlayer connection.
  • the current density of electrolytic filled plating is temporarily reduced during the electrolytic filled plating.
  • the electrolytic filled plated layer formed immediately below the lower space Accelerators adsorbed on can be separated.
  • the electrolytic filled plating layer fills the lower space, and the inner diameter of the hole for connecting the interlayer is an opening (the first stage electrolytic field formed before the current density is once reduced in the opening of the metal foil. If the diameter is equal to or greater than the diameter of the narrowest opening where the plating layer is formed), the opening of the hole for interlayer connection corresponding to the immediately lower part is likely to absorb the plating inhibitor, The plating accelerator is easily adsorbed inside the hole for interlayer connection.
  • the electrolytic filled plating layer fills the lower space, and the inner diameter of the interlayer connection is an opening (the first stage electrolytic filled plating layer formed before the current density is once reduced in the opening of the metal foil is formed. If the diameter is larger than the diameter of the narrowest opening, the effect is greater. For this reason, after increasing the current density of electrolytic filled plating again, the growth of the electrolytic filled plating layer starting from the bottom is suppressed, so the electrolytic filled plating layer blocks the opening of the hole for interlayer connection. Accordingly, an electrolytic filled plating layer is preferentially formed inside the interlayer connection hole. Therefore, it is possible to suppress plating voids in the electrolytic filled plating layer even with respect to the hole for interlayer connection having the same diameter as the insulating layer thickness.
  • the cross-sectional shape of the interlayer connection is formed by protruding the metal foil for the upper wiring formed in the opening of the hole for the interlayer connection and the interlayer.
  • the lower space between the inner wall of the hole for connection is filled with electrolytic filled plating, and the inner diameter of the interlayer connection is set to be equal to or larger than the diameter of the opening.
  • the opening of the hole for interlayer connection is a plating inhibitor.
  • the accelerator can be more easily adsorbed inside the interlayer connection hole.
  • the electrolytic filled plating layer fills the lower space and the inner diameter of the interlayer connection is a bowl shape larger than the diameter of the opening, this effect is more significant.
  • the timing for once reducing the current density of the electrolytic filled plating is such that the metal foil for upper layer wiring formed in the opening of the hole for interlayer connection, the inner wall of the hole for interlayer connection, The lower space is filled with electrolytic filled plating and before plating voids are formed.
  • the electrolytic filled plating layer can be more reliably filled into the hole for interlayer connection.
  • the rate of decrease of the current density when the current density of the electrolytic filled plating is once lowered during the electrolytic filled plating is 50% or more immediately before the reduction.
  • the reduction rate of the current density is a rate of reducing the current density. For example, when the reduction rate from the initial current density of 1 A / dm 2 is 50%, the current density after the reduction is 0. It means 5A / dm2. Further, reducing the current density includes setting the current density to 0 A / dm2. Thereby, the plating accelerator adsorbed on the electrolytic filled plating layer formed immediately below the lower space can be reliably separated.
  • the opening of the hole for interlayer connection has a plating inhibitor.
  • the inside of the hole for interlayer connection can be more easily adsorbed by the promoter.
  • the electrolytic filled plating layer fills the lower space and the inner diameter of the interlayer connection is a bowl shape larger than the diameter of the opening, this effect is more significant.
  • the current density of the electrolytic filled plating is once reduced during the electrolytic filling plating and then increased again to be equal to or higher than the current density immediately before the reduction.
  • the electrolytic filled plating layer can be filled in the hole for interlayer connection in a shorter time, and the production efficiency is improved.
  • the first electrolytic filled copper plating layer and the second electrolytic filled copper plating Streaks are observed between the layers.
  • the boundary between the first-stage electrolytic filled copper plating layer and the second-stage electrolytic copper plating layer can be identified.
  • the first-stage electrolytic filled copper plating layer can be identified from the cross-sectional shape of the interlayer connection. It is possible to check whether or not the inner space of the interlayer connection is equal to or larger than the diameter of the opening by filling the lower space. Therefore, it is easy to manage the conditions of the first stage electrolytic filled copper plating and the thickness of the first stage electrolytic filled copper plating layer.
  • the interlayer connection hole may be either a through hole or a non-through hole, but is preferably a non-through hole.
  • a non-through hole is formed by applying the conformal method or direct laser method, the metal foil for upper layer wiring pops out at the opening of the hole for interlayer connection, and this metal foil for upper layer wiring pops out And a lower space is easily formed between the inner wall of the hole for interlayer connection.
  • the hole for interlayer connection is a non-through hole, it has a bottom, so the electrolytic filled plating layer is filled more inside the hole for interlayer connection by the action of the plating accelerator of the electrolytic filled plating solution. It is easy to be done and the void of the hole for interlayer connection can be suppressed more reliably.
  • the prepreg 3 and the copper foil 4 for the upper layer wiring 10 are laminated and integrated on the inner layer material 2 on which the inner layer wiring 1 is formed.
  • the hole 5 for interlayer connection is provided by direct laser processing.
  • a protrusion 12 of the copper foil 4 for the upper layer wiring 10 occurs at the opening of the hole 5 for the interlayer connection, and between the protrusion 12 of the copper foil 4 for the upper layer wiring 10 and the inner wall 18 of the hole 5 for the interlayer connection.
  • a lower space 13 is formed.
  • the amount of protrusion (length of protrusion) of the copper foil 4 is 3 to 10 ⁇ m.
  • the prepreg 3 which is a resin film having a reinforcing base material such as glass fiber is used as the insulating layer 3 for bonding the inner layer material 2 and the copper foil 4 for the upper layer wiring 10.
  • a resin film such as a polymer epoxy resin or a thermoplastic polyimide adhesive film which is used for a general multilayer wiring board and does not have a reinforcing base material can be used.
  • the copper foil 4 is used as the metal foil 4 for the upper layer wiring 10, but besides this, a nickel foil, an aluminum foil, a composite foil thereof or the like used as a material for the multilayer wiring board is used. Can be used.
  • the insulating layer 3 and the metal foil 4 are formed using a resin film with a single-sided copper foil in which a resin film having a reinforcing base or a resin film having no reinforcing base is disposed on the copper foil 4. Also good.
  • the method of laminating and integrating the prepreg and the copper foil on the upper layer on the inner layer material formed with wiring is a method of laminating and pressing the inner layer material and the prepreg, copper foil, or a method of laminating a resin film with a single-sided copper foil on the inner layer material Is used.
  • the thickness of the insulating layer is about 10 to 100 ⁇ m, preferably 20 to 60 ⁇ m, and the thickness of the copper foil is 3 to 12 ⁇ m.
  • the resin film with a single-sided copper foil in this case has a configuration in which a prepreg (resin film having a reinforcing base material) is disposed on the copper foil.
  • a resin film that does not have a reinforcing substrate other than prepreg as the insulating layer a resin film such as a polymer epoxy resin or a thermoplastic polyimide adhesive film that does not have a reinforcing substrate is disposed on the copper foil. Is used.
  • the copper foil and resin composition (resin varnish) used for the production of the resin film with a single-sided copper foil are the same as those used for general multilayer wiring boards.
  • the resin varnish is heated and dried in order to bring the resin varnish into a B-stage state (semi-cured state). This condition is suitably 100 to 200 ° C.
  • the residual solvent amount in the resin composition (resin varnish) after heating and drying is about 0.2 to 10% by mass. Is appropriate.
  • vacuum or atmospheric pressure is suitable under conditions of 50 to 150 ° C. and 0.1 to 5 MPa.
  • the blackening treatment layer formed on the copper foil for the upper wiring layer can be formed of a known layer formed for adhesion between the copper foil and the insulating layer in a general multilayer wiring board.
  • Examples of such a blackening treatment layer include those formed by forming irregularities on the surface of the copper foil by copper oxide treatment or etching.
  • a laser that can be used for forming a hole for interlayer connection there are a gas laser such as CO 2 , CO, and excimer, and a solid-state laser such as YAG.
  • the CO 2 laser can easily obtain a large output, and according to the direct laser method developed in recent years, it is also possible to process holes for interlayer connection having a diameter of 50 ⁇ m or less.
  • the copper for the upper wiring 10 is etched with an etching solution such as ferric chloride aqueous solution, sodium persulfate, or sulfuric acid-hydrogen peroxide mixed solution.
  • an etching solution such as ferric chloride aqueous solution, sodium persulfate, or sulfuric acid-hydrogen peroxide mixed solution.
  • Half-etching is performed until the thickness of the foil 4 is about 1 to 5 ⁇ m.
  • the blackening treatment layer 8 formed on the copper foil 4 is removed.
  • the bottom 19 is etched in the interlayer connection 15, and a recess 14 is generated. By securing the amount of this recess 14 (etching amount), the laser processing residue at the bottom 19 of the interlayer connection 15 can be removed, and reliability can be ensured.
  • an electroless copper plating layer 6 is formed.
  • the activator Neogant made by Atotech Japan Co., Ltd., trade name; “Neogant” is a registered trademark
  • HS201B manufactured by Hitachi Chemical Co., Ltd.
  • Adsorption amount to the copper foil 4 on the palladium catalyst in the present embodiment is in the range of 0.03 ⁇ 0.6 ⁇ g / cm 2, more desirably, in the range of 0.05 ⁇ 0.3 ⁇ g / cm 2 is there.
  • the treatment temperature for adsorbing the palladium catalyst is preferably 10 to 40 ° C. By controlling the treatment time, the adsorption amount of the palladium catalyst on the copper foil 4 can be controlled.
  • electroless copper plating layer For forming the electroless copper plating layer, commercially available electroless copper such as CUST2000 (manufactured by Hitachi Chemical Co., Ltd., trade name, “CUST” is a registered trademark) and CUST201 (trade name, manufactured by Hitachi Chemical Co., Ltd.).
  • a plating solution can be used.
  • These electroless copper plating solutions contain copper sulfate, formalin, complexing agent and sodium hydroxide as main components.
  • the thickness of the electroless copper plating layer is not particularly limited as long as power can be supplied to form the next electrolytic filled copper plating layer, and is preferably in the range of 0.1 to 5 ⁇ m, more preferably 0.5. It is in the range of ⁇ 1.0 ⁇ m.
  • the first stage electrolytic filled copper plating layer that does not completely fill the hole 5 for interlayer connection 7a is formed.
  • the first-stage electrolytic filled copper plating layer 7a fills the lower space 13, and the inner diameter 20 of the interlayer connection 15 is equal to or greater than the diameter 21 of the opening (plating opening 24b).
  • the first-stage electrolytic filled copper plating layer 7a fills the lower space 13 and the diameter 20 inside the interlayer connection 15 is larger than the diameter 21 of the opening (plating opening 24b), it is more preferable.
  • the thickness of the first-stage electrolytic filled copper plating layer 7a is higher than the thickness of the first-stage electrolytic filled copper plating layer 7a on the copper foil 4 for the upper layer wiring 10 by one step on the bottom surface 19 in the interlayer connection hole 5.
  • the thickness of the electrolytic filled copper plating layer 7a of the eye increases, and the thickness on the copper foil 4 for the upper wiring 10 is in the range of 1.0 to 5.0 ⁇ m, and the bottom surface in the hole 5 for interlayer connection
  • the thickness of 19 is provided in the range of about 1 to 20 ⁇ m.
  • the conditions for such electrolytic filled copper plating are about 4 to 20 minutes at a current density of 1.0 A / dm 2 .
  • the current density of the first-stage electrolytic filled copper plating was temporarily reduced to 0.3 A / dm 2 in the middle of the first-stage electrolytic filled copper plating to reduce the current density.
  • Electrolytic field plating is performed for about 1 minute.
  • the plating accelerator adsorbed on the first-stage electrolytic filled plating layer 7a formed in the lower space 13 can be separated.
  • the time for performing electrolytic filled plating with reduced current density that is, the time for maintaining the current density of electrolytic filled copper plating once reduced is 1 second or more, and has the effect of separating the plating accelerator. If it is within 10 minutes, it is preferable because the work efficiency of electrolytic filled copper plating does not decrease so much.
  • the cross-sectional shape of the interlayer connection 15 immediately before the current density is once reduced is as shown in the step (2-2) in FIG. 3 of the protrusion 12 of the copper foil 4 for the upper layer wiring 10 and the hole 5 for the interlayer connection.
  • the lower space 13 formed between the inner wall 18 and the inner wall 18 is filled with the first-stage electrolytic filled copper plating layer 7a.
  • the diameter 20 inside the interlayer connection 15 has a bowl shape larger than the diameter 21 of the opening (plating opening 24b).
  • the cross-sectional shape of the interlayer connection 15 after the formation of the first stage electrolytic filled plating layer 7a is such that the first stage electrolytic filled plating layer 7a fills the lower space 13, and the inner diameter 20 of the interlayer connection 15 is Since the opening (plating opening 24 b) has a bowl shape larger than the diameter 21, the plating inhibitor adsorbs in the opening of the interlayer connection hole 5 corresponding to the direct lower portion 17 of the copper foil 4. On the other hand, the plating accelerator is easily adsorbed inside the interlayer connection hole 5.
  • the current density of electrolytic filled plating is again increased to 1.0 A / dm 2 , and second-stage electrolytic filled copper plating is performed.
  • the second stage electrolytic field plating starting from the immediately lower portion 17 is used. Since the growth of the layer 7b is suppressed, the second-stage electrolytic filled plating layer 7b does not block the opening of the interlayer connection hole 5, and preferentially enters the interlayer connection hole 5 in two steps. Electrolytic filled plating layer 7a is formed.
  • the plating void 16 of the second-stage electrolytic filled plating layer 7b even for the interlayer connection hole 5 having a diameter comparable to the thickness of the insulating layer 3.
  • the inside of the interlayer connection hole 5 is completely filled by this second-stage electrolytic filled copper plating layer 7 b, and the portion above the interlayer connection hole 5 to be the upper layer wiring 10 and the layer connection hole 5 other than The part becomes flat.
  • the second-stage electrolytic filled plating layer 7b copper sulfate electroplating for filled vias used in ordinary multilayer wiring boards can be used, and even the electrolytic filled plating solution when the first-stage electrolytic filled copper plating layer 7a is formed. It can be different or different.
  • the electrolytic filled copper plating solution used for forming the first-stage electrolytic filled copper plating layer 7a and the second-stage electrolytic filled copper plating layer 7b is the same, it remains immersed in the same electrolytic filled copper plating solution. Since the first stage electrolytic filled copper plating, the electrolytic filled copper plating with reduced current density, and the second stage electrolytic filled copper plating can be formed, workability is good.
  • the thickness of the second-stage electrolytic filled plating layer 7b is only required to be usable as a wiring, and the hole 5 for interlayer connection can be filled with a conductive metal.
  • the thickness on the copper plating layer 7a is preferably in the range of 1 to 100 ⁇ m, and more preferably in the range of 10 to 50 ⁇ m.
  • Such electrolytic filled copper plating is performed at a current density of 1.0 A / dm 2 for about 4 to 400 minutes, preferably about 40 to 200 minutes.
  • copper deposits thicker than the surface at the bottom of the interlayer connection hole 5, so the aspect when the second stage electrolytic filled copper plating 9 is embedded in the interlayer connection hole 5. Is reduced.
  • the hole filling for the interlayer connection by forming the electrolytic filled plating layer is performed in two stages, but the hole filling for the interlayer connection is not limited to two stages. It may be performed in stages.
  • the hole filling for the interlayer connection is not limited to two stages. It may be performed in stages.
  • an etching resist 11 is formed using a dry film resist or the like.
  • the etching resist 11 is removed by development from the portions other than those on the interlayer connection hole 5 and the upper layer wiring 10.
  • step (3-2) of FIG. 4 after etching away portions other than the upper layer wiring 10, the etching resist 11 is stripped using an alkaline stripping solution, sulfuric acid, or a commercially available resist stripping solution, Upper layer wiring 10 is formed.
  • the multilayer wiring board 23 composed of two layers of the inner layer wiring 1 and the upper layer wiring 10 is completed.
  • the surface of the upper wiring 10 of the multilayer wiring board 23 is roughened, and an insulating layer (not shown) formed on the upper wiring 10 is formed.
  • the prepreg and an upper wiring copper foil are laminated on the upper layer of the prepreg and the like.
  • Example 1 First, as shown in step (1-1) of FIG. 2, the inner layer material 2 on which the inner layer wiring 1 is formed, the resin film serving as the insulating layer 3 has a thickness of 30 ⁇ m, and the copper foil 4 for the upper layer wiring 10 is obtained. A single-sided copper foil-attached resin film with a thickness of 5 ⁇ m of copper foil 4 was vacuum-laminated under the conditions of 120 ° C. and 2 MPa. Next, after forming a blackening treatment layer 8 having a thickness of 0.3 to 0.5 ⁇ m on the surface of the copper foil 4 for the upper layer wiring 10, as shown in step (1-2) in FIG.
  • a hole 5 for interlayer connection having a diameter (diameter of copper foil opening 24a) of 35 ⁇ m was processed by a direct laser method using a CO 2 laser. That is, the interlayer connection hole 5 has a depth of 35 ⁇ m, which is the sum of the thickness of the resin film (30 ⁇ m) and the thickness of the copper foil 4 (5 ⁇ m), and the diameter of the copper foil opening 24a is 35 ⁇ m. there were. For this reason, the aspect ratio was about 1.0.
  • a protrusion 12 of the copper foil 4 for the upper layer wiring 10 is generated in the opening 24 of the hole 5 for interlayer connection, and between the protrusion 12 of the copper foil 4 for the upper layer wiring 10 and the inner wall 18 of the hole 5 for interlayer connection.
  • a lower space 13 was formed.
  • the amount of protrusion of the copper foil 4 was about 8 ⁇ m on one side of the hole 5 for interlayer connection. Further, in the lower space 13 formed between the protrusion 12 of the copper foil 4 for the upper layer wiring 10 and the inner wall 18 of the hole 5 for interlayer connection, the vicinity of the back surface of the protrusion 12 of the copper foil 4 for the upper layer wiring 10 The lower part 17 was formed in this area.
  • the copper foil 4 for the upper layer wiring 10 is formed with an etching solution such as ferric chloride aqueous solution, ammonium persulfate, or sulfuric acid-hydrogen peroxide mixed solution.
  • an etching solution such as ferric chloride aqueous solution, ammonium persulfate, or sulfuric acid-hydrogen peroxide mixed solution.
  • half etching was performed until the thickness of the copper foil 4 became 2 to 3 ⁇ m.
  • step (2-1) of FIG. 3 HS201B (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is a palladium colloid catalyst, is used on the copper foil 4 and inside the hole 5 for interlayer connection.
  • an electroless copper plating layer serving as a base of 0.5 ⁇ m thick electrolytic filled copper plating using CUST2000 (trade name, manufactured by Hitachi Chemical Co., Ltd., “CUST” is a registered trademark) 6 was formed.
  • electroless copper plating layer For forming the electroless copper plating layer, commercially available electroless copper such as CUST2000 (manufactured by Hitachi Chemical Co., Ltd., trade name, “CUST” is a registered trademark) and CUST201 (trade name, manufactured by Hitachi Chemical Co., Ltd.).
  • a plating solution can be used.
  • These electroless copper plating solutions contain copper sulfate, formalin, complexing agent and sodium hydroxide as main components.
  • the thickness of the electroless copper plating layer is not particularly limited as long as power can be supplied to form the next electrolytic filled copper plating layer, and is preferably in the range of 0.1 to 5 ⁇ m, more preferably 0.5. It is in the range of ⁇ 1.0 ⁇ m.
  • the thickness on the copper foil 4 for the upper wiring 10 is 2 ⁇ m, and the thickness of the bottom surface 19 in the hole 5 for interlayer connection is 2 to 15 ⁇ m.
  • the first-stage electrolytic filled copper plating layer 7a is formed.
  • the electrolytic filled copper plating solution a commercially available DC electrolytic plating solution CU-BRITE VFIV (manufactured by JCU Corporation, trade name) was used. At this time, the condition of the first stage electrolytic filled copper plating is about 8 minutes at a current density of 1.0 A / dm 2 .
  • the cross-sectional shape of the interlayer connection 15 formed with the first-stage electrolytic filled copper plating layer 7a is such that the first-stage electrolytic filled plating layer 7a fills the lower space 13, and the inner diameter 20 of the interlayer connection 15 is open. It was a bowl shape larger than the diameter 21 of the part (plating opening 24b).
  • the rectifier is turned off once and left at 0 A / dm 2 for 1 minute. Thereafter, the process shown in FIG. ), The thickness of the copper foil 4 for the upper layer wiring 10 and the first-stage electrolytic filled copper plating layer 7a is filled with the interlayer connection 15 by the 18 ⁇ m second-stage electrolytic filled copper plating layer 7b. Went. The condition of the second stage electrolytic filled copper plating at this time was about 80 minutes at a current density of 1.0 A / dm 2 . During this time, the substrate remained immersed in the electrolytic filled copper plating solution.
  • an etching resist 11 having a thickness of 29 ⁇ m is formed using SL-1229 (trade name, Hitachi Chemical Co., Ltd.) which is a dry film resist.
  • the etching resist 11 is removed from the portions other than the portions above the interlayer connection holes 5 and the upper layer wiring 10.
  • the etching resist 11 is stripped using an alkaline stripping solution, sulfuric acid, or a commercially available resist stripping solution. The upper layer wiring 10 was formed.
  • Example 2 In the same manner as in Example 1, the process from Step (1-1) in FIG. 1 to Step (2-1) in FIG. 3 was advanced. Next, as shown in step (2-2) in FIG. 3, the thickness on the copper foil 4 for the upper wiring 10 is 2 ⁇ m, and the thickness of the bottom surface 19 in the hole 5 for interlayer connection is 2 to 15 ⁇ m.
  • the first-stage electrolytic filled copper plating layer 7a is formed. The same electrolytic filled copper plating solution as in Example 1 was used. The condition of the first stage electrolytic filled copper plating at this time was about 8 minutes at a current density of 1.0 A / dm 2 .
  • the current density of electrolytic filled copper plating is reduced from 1.0 A / dm 2 to 0.3 A / dm 2 and the electrolytic filled copper plating is continued while maintaining for 1 minute.
  • the thickness of the copper foil 4 for the upper layer wiring 10 and the first-stage electrolytic filled copper plating layer 7a is determined by the 18 ⁇ m second-stage electrolytic filled copper plating layer 7b. Connection 15 was filled.
  • the conditions of the second stage electrolytic filled copper plating were about 80 minutes at a current density of 1.0 A / dm 2 .
  • the substrate was left immersed in the electrolytic filled copper plating solution.
  • steps (3-1) to (3-3) in FIG. 4 were carried out in the same manner as in Example 1.
  • Example 3 In the same manner as in Example 1, the process from Step (1-1) in FIG. 2 to Step (2-1) in FIG. 3 was advanced. Next, as shown in step (2-2) in FIG. 3, the thickness on the copper foil 4 for the upper wiring 10 is 2 ⁇ m, and the thickness of the bottom surface 19 in the hole 5 for interlayer connection is 2 to 15 ⁇ m.
  • the first-stage electrolytic filled copper plating layer 7a is formed. The same electrolytic plating solution as in Example 1 was used. The condition of the first stage electrolytic filled copper plating at this time was about 8 minutes at a current density of 1.0 A / dm 2 .
  • the current density of electrolytic filled copper plating is reduced from 1.0 A / dm 2 to 0.5 A / dm 2 and the electrolytic filled copper plating is continued while maintaining for 1 minute.
  • the thickness of the copper foil 4 for the upper layer wiring 10 and the first-stage electrolytic filled copper plating layer 7a is determined by the 18 ⁇ m second-stage electrolytic filled copper plating layer 7b. Connection 15 was filled.
  • the conditions of the second stage electrolytic filled copper plating were about 80 minutes at a current density of 1.0 A / dm 2 .
  • the substrate was left immersed in the electrolytic filled copper plating solution.
  • steps (3-1) to (3-3) in FIG. 4 were carried out in the same manner as in Example 1.
  • Example 4 In the same manner as in Example 1, the process from Step (1-1) in FIG. 2 to Step (2-1) in FIG. 3 was advanced. Next, as shown in step (2-2) in FIG. 3, the thickness on the copper foil 4 for the upper wiring 10 is 2 ⁇ m, and the thickness of the bottom surface 19 in the hole 5 for interlayer connection is 2 to 15 ⁇ m.
  • the first-stage electrolytic filled copper plating layer 7a is formed. The same electrolytic plating solution as in Example 1 was used. At this time, the condition of the first-stage electrolytic filled copper plating was about 8 minutes at a current density of 1.0 A / dm 2 .
  • the current density of electrolytic filled copper plating is reduced from 1.0 A / dm 2 to 0.5 A / dm 2 and the electrolytic filled copper plating is continued while maintaining for 1 minute.
  • the thickness of the copper foil 4 for the upper layer wiring 10 and the first-stage electrolytic filled copper plating layer 7a is determined by the 18 ⁇ m second-stage electrolytic filled copper plating layer 7b. Connection 15 was filled.
  • the condition of the second-stage electrolytic filled copper plating was about 56 minutes at a current density of 1.5 A / dm 2 .
  • the substrate was left immersed in the electrolytic filled copper plating solution.
  • steps (3-1) to (3-3) in FIG. 4 were carried out in the same manner as in Example 1.
  • Example 5 In the same manner as in Example 1, the process from Step (1-1) in FIG. 2 to Step (2-1) in FIG. 3 was advanced. Next, as shown in step (2-2) of FIG. 3, the thickness on the copper foil 4 for the upper wiring 10 is 1 ⁇ m, and the thickness of the bottom surface 19 in the hole 5 for interlayer connection is 1 to 7 ⁇ m.
  • the first-stage electrolytic filled copper plating layer 7a is formed. The same electrolytic filled plating solution as in Example 1 was used. At this time, the condition of the first-stage electrolytic filled copper plating was about 4 minutes at a current density of 1.0 A / dm 2 .
  • the current density of electrolytic filled copper plating is reduced from 1.0 A / dm 2 to 0.5 A / dm 2 and the electrolytic filled copper plating is continued while maintaining for 1 minute.
  • the thickness on the copper foil 4 for the upper layer wiring 10 and the first-stage electrolytic filled copper plating layer 7a is determined by the 19 ⁇ m second-stage electrolytic filled copper plating layer 7b. Connection 15 was filled.
  • the condition of the second-stage electrolytic filled copper plating was about 84 minutes at a current density of 1.0 A / dm 2 .
  • the substrate was left immersed in the electrolytic filled copper plating solution.
  • steps (3-1) to (3-3) in FIG. 4 were carried out in the same manner as in Example 1.
  • Step (1-1) in FIG. 2 to Step (2-1) in FIG. 3 was advanced.
  • step (2-2) in FIG. 6 a first electrolytic filled copper plating layer 7a having a thickness of 20 ⁇ m on the copper foil 4 for the upper wiring 10 was formed in one step.
  • the same electrolytic filled copper plating solution as in Example 1 was used.
  • the condition of the first stage electrolytic filled copper plating was about 88 minutes at a current density of 1.0 A / dm 2 .
  • steps (3-1) to (3-3) in FIG. 4 were carried out in the same manner as in Example 1.
  • Step (Comparative Example 2) In the same manner as in Example 1, the process from Step (1-1) in FIG. 2 to Step (2-1) in FIG. 3 was advanced. Next, as shown in step (2-2) of FIG. 5, the thickness on the copper foil 4 for the upper layer wiring 10 is 0.5 ⁇ m, and the thickness of the bottom surface 19 in the hole 5 for interlayer connection is 0. A first electrolytic filled copper plating layer 7a of 5 to 3 ⁇ m is formed. The same electrolytic filled copper plating solution as in Example 1 was used. At this time, the condition of the first-stage electrolytic filled copper plating was about 2 minutes at a current density of 1.0 A / dm 2 . At this time, the cross-sectional shape of the interlayer connection 15 formed with the first-stage electrolytic filled copper plating layer 7 a was such that the first-stage electrolytic filled plating layer 7 a did not fill the lower space 13.
  • the current density of electrolytic filled copper plating is reduced from 1.0 A / dm 2 to 0.5 A / dm 2 and the electrolytic filled copper plating is continued while maintaining for 1 minute, and then the process of FIG.
  • the thickness on the copper foil 4 for the upper wiring 10 and the first-stage electrolytic filled copper plating layer 7a is determined by the 19.5 ⁇ m second-stage electrolytic filled copper plating layer 7b.
  • the interlayer connection 15 was filled.
  • the condition of the second-stage electrolytic filled copper plating was about 86 minutes at a current density of 1.0 A / dm 2 .
  • the substrate was left immersed in the electrolytic filled copper plating solution.
  • steps (3-1) to (3-3) in FIG. 4 were carried out in the same manner as in Example 1.
  • Table 1 summarizes the frequency of occurrence of plating voids in Examples 1 to 5 and Comparative Examples 1 and 2, by observing the cross section of the interlayer connection with a microscope.
  • the void generation frequency was 0%, and the holes for interlayer connection could be filled.
  • the void generation rate was 6.5%, and the holes for interlayer connection could be almost filled.
  • Comparative Example 1 void generation was almost 100%.
  • Comparative Example 2 the void generation rate was 75%.
  • Examples 1 to 5 and Comparative Example 2 in which the current density was once reduced during the electrolytic filled copper plating, between the first electrolytic filled copper plating layer and the second electrolytic filled copper plating layer. The boundary of the plating layer was observed.
  • the boundary between the first-stage electrolytic filled copper plating layer and the second-stage electrolytic copper plating layer can be identified.
  • the cross-sectional shape of the interlayer connection in Examples 1 to 5 is: It was confirmed that the electrolytic filled copper plating layer in the first stage filled the lower space, and the inner diameter of the interlayer connection was larger than the diameter of the opening (plating opening). On the other hand, the cross-sectional shape of the interlayer connection of Comparative Example 1 was observed at the boundary of the plating layer representing the boundary between the first-stage electrolytic filled copper plating layer and the second-stage electrolytic copper plating layer seen in Examples 1 to 5.

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  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

　La présente invention concerne un tableau de connexions à couches multiples et un procédé de fabrication dudit tableau de connexions. Ledit tableau de connexions à couches multiples comporte : un trou de connexion intercouche qui pénètre dans une feuille métallique pour une ligne de câblage de couche supérieure et une couche isolante ; une partie saillante de la feuille métallique pour la ligne de câblage de couche supérieure formée dans la partie ouverte du trou de connexion intercouche ; un espace inférieur formé entre la partie saillante de la couche métallique et des parois intérieures du trou de connexion intercouche ; et une connexion intercouche formée en remplissant le trou de connexion intercouche avec des couches de placage à charge électrolytique, le couches de placage à charge électrolytique remplissant le trou de connexion intercouche, y compris deux couches ou plus, l'espace inférieur étant rempli avec une quelconque des deux, ou plus, couches de placage à charge électrolytique, à l'exclusion de la couche la plus extérieure, le diamètre de la partie intérieure de la connexion intercouche formée par une quelconque des couches de placage à charge électrolytique, à l'exclusion de la couche la plus extérieure, étant supérieur ou égal au diamètre de l'ouverture.
PCT/JP2014/075255 2013-10-09 2014-09-24 Tableau de connexion à couches multiples et son procédé de fabrication WO2015053082A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201480055473.XA CN105612820B (zh) 2013-10-09 2014-09-24 多层配线基板及其制造方法
US15/027,784 US9648759B2 (en) 2013-10-09 2014-09-24 Multilayer wiring board and method for manufacturing same

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
JP2013211871 2013-10-09
JP2013-211871 2013-10-09
JP2014147755A JP6350063B2 (ja) 2013-10-09 2014-07-18 多層配線基板
JP2014-147755 2014-07-18
JP2014147754A JP6350062B2 (ja) 2013-10-09 2014-07-18 多層配線基板の製造方法
JP2014-147754 2014-07-18

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WO2015053082A1 true WO2015053082A1 (fr) 2015-04-16

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007180359A (ja) * 2005-12-28 2007-07-12 Shinko Electric Ind Co Ltd スルーホールの充填方法
JP2009117448A (ja) * 2007-11-02 2009-05-28 Cmk Corp プリント配線板の製造方法
JP2013077807A (ja) * 2011-09-13 2013-04-25 Hoya Corp 基板製造方法および配線基板の製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007180359A (ja) * 2005-12-28 2007-07-12 Shinko Electric Ind Co Ltd スルーホールの充填方法
JP2009117448A (ja) * 2007-11-02 2009-05-28 Cmk Corp プリント配線板の製造方法
JP2013077807A (ja) * 2011-09-13 2013-04-25 Hoya Corp 基板製造方法および配線基板の製造方法

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