WO2015040705A1 - Dispositif à semi-conducteurs et procédé de fabrication de semi-conducteurs - Google Patents

Dispositif à semi-conducteurs et procédé de fabrication de semi-conducteurs Download PDF

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Publication number
WO2015040705A1
WO2015040705A1 PCT/JP2013/075192 JP2013075192W WO2015040705A1 WO 2015040705 A1 WO2015040705 A1 WO 2015040705A1 JP 2013075192 W JP2013075192 W JP 2013075192W WO 2015040705 A1 WO2015040705 A1 WO 2015040705A1
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Prior art keywords
semiconductor layer
gate
insulating film
fin
columnar
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PCT/JP2013/075192
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English (en)
Japanese (ja)
Inventor
舛岡　富士雄
広記 中村
Original Assignee
ユニサンティス エレクトロニクス シンガポール プライベート リミテッド
舛岡　富士雄
広記 中村
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Application filed by ユニサンティス エレクトロニクス シンガポール プライベート リミテッド, 舛岡　富士雄, 広記 中村 filed Critical ユニサンティス エレクトロニクス シンガポール プライベート リミテッド
Priority to PCT/JP2013/075192 priority Critical patent/WO2015040705A1/fr
Publication of WO2015040705A1 publication Critical patent/WO2015040705A1/fr

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
    • H10B63/34—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors of the vertical channel field-effect transistor type
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/061—Patterning of the switching material
    • H10N70/063—Patterning of the switching material by etching of pre-deposited switching material layers, e.g. lithography
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/841—Electrodes
    • H10N70/8413—Electrodes adapted for resistive heating

Definitions

  • the present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.
  • phase change memories have been developed (see, for example, Patent Document 1).
  • the phase change memory stores information by recording the change in resistance of the information storage element of the memory cell.
  • chalcogenide glass Ge 2 Sb 2 in contact with the heater.
  • Te 5 chalcogenide glass melts at high temperature (high current) and cools at high speed (stops current), it becomes amorphous (reset operation), while it melts at relatively low temperature (low current) and slows down. And crystallize (set [Set] operation).
  • a reset current flows as much as 200 ⁇ A.
  • a bipolar transistor or a diode selection element can be used (see, for example, Patent Document 1).
  • the diode Since the diode is a two-terminal element, when one source line is selected to select a memory cell, the current of all the memory cells connected to the source line flows through the one source line. Therefore, the IR drop that is a voltage drop of the IR (current, resistance) product in the resistance of the source line becomes large.
  • a bipolar transistor is a three-terminal element, but since a current flows through the gate, it is difficult to connect many transistors to the word line.
  • SGT Surrounding Gate Transistor
  • a source, a gate, and a drain are arranged in a direction perpendicular to a substrate and a gate electrode surrounds a columnar semiconductor layer
  • SGT can flow a larger amount of current than a double gate transistor per unit gate width (see, for example, Patent Document 2).
  • the SGT has a structure in which the gate electrode surrounds the columnar semiconductor layer, the gate line width per unit area can be increased, so that a larger amount of current can flow.
  • the present invention has been made in view of the above-described problems, and provides a structure and a manufacturing method of a memory having a memory element in which a large amount of current can flow through a selection transistor and resistance is changed. For the purpose.
  • a semiconductor device includes: A first columnar semiconductor layer; A gate insulating film formed around the first columnar semiconductor layer; A gate electrode formed around the gate insulating film; A gate wiring connected to the gate electrode; A first diffusion layer formed on the first columnar semiconductor layer; A second diffusion layer formed below the first columnar semiconductor layer; A storage element having a variable resistance formed on the first diffusion layer. It is characterized by that.
  • the first columnar semiconductor layer is formed on the fin-shaped semiconductor layer,
  • the gate electrode and the gate wiring are made of metal,
  • the gate wiring extends in a direction orthogonal to the fin-like semiconductor layer,
  • the second diffusion layer is formed in the fin-like semiconductor layer. It is preferable.
  • the second diffusion layer is preferably formed on the semiconductor substrate in addition to the fin-like semiconductor layer.
  • the line width outside the gate electrode is equal to the line width of the gate wiring, and the line width of the first columnar semiconductor layer in a direction orthogonal to the fin-shaped semiconductor layer is orthogonal to the fin-shaped semiconductor layer.
  • the line width of the fin-like semiconductor layer in the direction is preferably equal.
  • the gate insulating film is formed between the second columnar semiconductor layer and the contact electrode.
  • the line width of the second columnar semiconductor layer in the direction orthogonal to the fin-shaped semiconductor layer is preferably equal to the line width of the fin-shaped semiconductor layer in the direction orthogonal to the fin-shaped semiconductor layer.
  • the gate insulating film is formed around the contact electrode and the contact wiring.
  • the line width outside the contact electrode is equal to the line width of the contact wiring.
  • the first columnar semiconductor layer is formed on a semiconductor substrate,
  • the gate electrode and the gate wiring are made of metal,
  • the second diffusion layer is formed on the semiconductor substrate; It is preferable.
  • the line width outside the gate electrode is preferably equal to the line width of the gate wiring.
  • the gate insulating film is formed between the second columnar semiconductor layer and the contact electrode.
  • the gate insulating film is formed around the contact electrode and the contact wiring.
  • the line width outside the contact electrode is equal to the line width of the contact wiring.
  • a method for manufacturing a semiconductor device includes: Forming a fin-like semiconductor layer extending in one direction on a semiconductor substrate, and forming a first insulating film around the fin-like semiconductor layer; After the first step, a second insulating film is formed around the fin-like semiconductor layer, and first polysilicon is deposited and planarized on the second insulating film to form a gate wiring, a first wiring Forming a columnar semiconductor layer, a second columnar semiconductor layer, and a second resist for forming a contact wiring so as to extend in a direction orthogonal to a direction in which the fin-shaped semiconductor layer extends; By etching polysilicon, the second insulating film, and the fin-like semiconductor layer, a first columnar semiconductor layer, a first dummy gate derived from the first polysilicon, and a second A second step of forming the columnar semiconductor layer and a second dummy gate derived from the first polysilicon; After the second step, a fourth insulating
  • a second polysilicon is deposited around the fourth insulating film and etched to form the first dummy gate, the first columnar semiconductor layer, the second dummy gate, and the second columnar shape.
  • a second diffusion layer is formed in an upper portion of the fin-shaped semiconductor layer, a lower portion of the first columnar semiconductor layer, and a lower portion of the second columnar semiconductor layer, and the third dummy gate and the fourth
  • a fifth insulating film is formed around the dummy gate and etched to remain in a sidewall shape, thereby forming a sidewall made of the fifth insulating film, on the second diffusion layer.
  • a fourth step of forming a compound layer comprising a metal and a semiconductor After the fourth step, a first interlayer insulating film is deposited and planarized, and the first dummy gate, the second dummy gate, the third dummy gate, and the fourth dummy gate are formed. An upper portion is exposed, and the first dummy gate, the second dummy gate, the third dummy gate, and the fourth dummy gate are removed, and the second insulating film and the fourth insulating film are removed. And a gate insulating film is formed around the first columnar semiconductor layer, around the second columnar semiconductor layer, and inside the fifth insulating film, and is formed on the second columnar semiconductor layer.
  • a fifth step of forming a gate electrode and a gate wiring forms the contact electrode and the contact wires around the second columnar semiconductor layer, After the fifth step, a second interlayer insulating film is deposited and planarized, the upper portion of the first columnar semiconductor layer is exposed, and the resistance changes on the upper portion of the first columnar semiconductor layer.
  • a sixth step of forming It is characterized by that.
  • a third insulating film is formed on the first polysilicon.
  • a third resist is formed. It is preferable that an upper portion of the first columnar semiconductor layer is exposed by forming and etching back, and a first diffusion layer is formed on the upper portion of the first columnar semiconductor layer.
  • (A) is a plan view of a semiconductor device according to an embodiment of the present invention, (b) is a sectional view taken along line XX ′ of (a), and (c) is a YY line of (a). It is sectional drawing in a line.
  • (A) is a plan view of a semiconductor device according to an embodiment of the present invention, (b) is a sectional view taken along line XX ′ of (a), and (c) is a YY line of (a). It is sectional drawing in a line.
  • (A) is a plan view of a semiconductor device according to an embodiment of the present invention
  • (b) is a sectional view taken along line XX ′ of (a)
  • (c) is a YY line of (a). It is sectional drawing in a line.
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention,
  • (b) is sectional drawing in the XX 'line
  • (c) is It is sectional drawing in the YY 'line of (a).
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • FIG. 1 shows a structure of a semiconductor device according to an embodiment of the present invention.
  • the memory cells which are the semiconductor devices of this embodiment are arranged in a 1 ⁇ 1 matrix, a 1 ⁇ 3 column, a 2 ⁇ 1 column, and a 2 ⁇ 3 column in a 3 ⁇ 2 matrix cell array, respectively.
  • Contact devices having contact electrodes and contact wirings for connecting source lines to each other are arranged in one row and two columns and two rows and two columns, respectively, in a 3 ⁇ 2 matrix cell array.
  • the memory cells located in two rows and one column include a fin-like silicon layer 104 formed so as to extend in the left-right direction on the semiconductor substrate 101, a first insulating film 106 formed around the fin-like silicon layer 104, A first columnar silicon layer 129 formed on the fin-like silicon layer 104.
  • the line width of the first columnar silicon layer 129 in the direction perpendicular to the fin-like silicon layer 104 is equal to the line width of the fin-like silicon layer 104 in the direction perpendicular to the fin-like silicon layer 104.
  • the memory cells located in two rows and one column further include a gate insulating film 162 formed around the first columnar silicon layer 129, a gate electrode 168a made of metal formed around the gate insulating film 162, And a gate wiring 168b made of metal connected to the gate electrode 168a.
  • the gate insulating film 162 is formed around and below the bottom of the gate electrode 168a and the gate wiring 168b.
  • the gate wiring 168b extends in a direction orthogonal to the fin-like silicon layer 104, and the line width outside the gate electrode 168a is equal to the line width of the gate wiring 168b.
  • the memory cells located in two rows and one column are further formed in the first diffusion layer 302 formed above the first columnar silicon layer 129 and in the fin-shaped silicon layer 104 below the first columnar silicon layer 129.
  • a second diffusion layer 143a formed on the first diffusion layer 302 and a memory element 181a having a variable resistance.
  • a high-resistance element heater 179a is formed between the memory element 181a whose resistance changes and the first columnar silicon layer 129.
  • the memory element 181a whose resistance is changed is preferably made of a phase change film such as chalcogenide glass (GST: Ge 2 Sb 2 Te 5 ).
  • the heater 179a is preferably made of, for example, titanium nitride.
  • the memory cells located in two rows and three columns include a fin-like silicon layer 104 formed so as to extend in the left-right direction on the semiconductor substrate 101, and a first insulating film 106 formed around the fin-like silicon layer 104. And a first columnar silicon layer 131 formed on the fin-like silicon layer 104.
  • the line width of the first columnar silicon layer 131 in the direction perpendicular to the fin-like silicon layer 104 is equal to the line width of the fin-like silicon layer 104 in the direction perpendicular to the fin-like silicon layer 104.
  • the memory cells located in two rows and three columns further include a gate insulating film 163 formed around the first columnar silicon layer 131, and a gate electrode 170a made of metal formed around the gate insulating film 163. And a gate wiring 170b made of metal connected to the gate electrode 170a.
  • the gate insulating film 163 is formed around and under the gate electrode 170a and the gate wiring 170b.
  • the gate wiring 170b extends in a direction orthogonal to the fin-like silicon layer 104, and the line width outside the gate electrode 170a is equal to the line width of the gate wiring 170b.
  • the memory cells located in two rows and three columns are further provided with a first diffusion layer 304 formed above the first columnar silicon layer 131 and a fin-shaped silicon layer 104 below the first columnar silicon layer 131.
  • a second diffusion layer 143a formed and a memory element 182a formed on the first diffusion layer 304 and having a variable resistance are included.
  • a high-resistance element heater 180 a is formed between the memory element 182 a whose resistance changes and the first columnar silicon layer 131.
  • the memory element 181a whose resistance changes is connected to the memory element 182a whose resistance changes by a bit line 187.
  • the memory cells located in one row and one column include a fin-like silicon layer 105 formed on the semiconductor substrate 101 so as to extend in the left-right direction, a first insulating film 106 formed around the fin-like silicon layer 105, and a fin And a first columnar silicon layer 132 formed on the silicon layer 105.
  • the line width of the first columnar silicon layer 132 in the direction perpendicular to the fin-like silicon layer 105 is equal to the line width of the fin-like silicon layer 105 in the direction perpendicular to the fin-like silicon layer 105.
  • the memory cells located in one row and one column further include a gate insulating film 162 formed around the first columnar silicon layer 132, a gate electrode 168a made of metal formed around the gate insulating film 162, and a gate. And a gate wiring 168b made of metal connected to the electrode 168a.
  • the gate insulating film 162 is formed around and below the bottom of the gate electrode 168a and the gate wiring 168b.
  • the gate wiring 168b extends in a direction orthogonal to the fin-like silicon layer 105, and the line width outside the gate electrode 168a is equal to the line width of the gate wiring 168b.
  • the memory cells located in one row and one column are further formed under the first columnar silicon layer 132 in the fin-like silicon layer 105 and the first diffusion layer 305 formed on the first columnar silicon layer 132.
  • the second diffusion layer 143b and the memory element 181b formed on the first diffusion layer 305 and having a variable resistance.
  • a high-resistance element heater 179b is formed between the memory element 181b whose resistance changes and the first columnar silicon layer 132.
  • the memory cells located in one row and three columns include a fin-like silicon layer 105 formed on the semiconductor substrate 101 so as to extend in the left-right direction, a first insulating film 106 formed around the fin-like silicon layer 105, And a first columnar silicon layer 134 formed on the fin-shaped silicon layer 105.
  • the line width of the first columnar silicon layer 134 in the direction perpendicular to the fin-like silicon layer 105 is equal to the line width of the fin-like silicon layer 105 in the direction perpendicular to the fin-like silicon layer 105.
  • the memory cells located in one row and three columns further include a gate insulating film 163 formed around the first columnar silicon layer 134, a gate electrode 170a made of metal formed around the gate insulating film 163, and And a gate wiring 170b made of metal connected to the gate electrode 170a.
  • the gate insulating film 163 is formed around and under the gate electrode 170a and the gate wiring 170b.
  • the gate wiring 170b extends in a direction orthogonal to the fin-like silicon layer 105, and the line width outside the gate electrode 170a is equal to the line width of the gate wiring 170b.
  • the memory cells located in one row and three columns are further formed on the first columnar silicon layer 134 below the first columnar silicon layer 134 and the first diffusion layer 307 formed on the first columnar silicon layer 134.
  • the second diffusion layer 143b formed and the memory element 182b formed on the first diffusion layer 307 and having a variable resistance.
  • a high-resistance element heater 180b is formed between the memory element 182b whose resistance changes and the first columnar silicon layer 134.
  • the memory element 181b whose resistance changes is connected to the memory element 182b whose resistance changes by a bit line 188.
  • the SGT can pass a larger amount of current per unit gate width than a double gate transistor. Furthermore, since the SGT has a structure in which the gate electrode surrounds the columnar semiconductor layer, the gate line width per unit area can be increased, so that a larger amount of current can flow. Accordingly, since the SGT can flow a large reset current, the phase change films such as the memory elements 181a and 181b whose resistance changes can be melted at a high temperature (high current). In addition, since the SGT subthreshold swing (the gate voltage necessary for the drain-source current of the MOSFET operating in the weak inversion region to change by an order of magnitude) can achieve an ideal value, the off-current can be reduced. The phase change films such as the memory elements 181a and 181b whose resistance changes can be cooled at high speed (the current is stopped).
  • the semiconductor device includes the gate electrodes 168a and 170a and the gate wirings 168b and 170b formed around and below the gate electrodes 168a and 170a and the gate wirings 168b and 170b. Since the gate electrodes 168a and 170a, which are metal gates, are formed by the gate last to be formed, both the metal gate process and the high temperature process can be achieved.
  • the gate insulating films 162 and 163 are formed around and below the bottom of the gate electrodes 168a and 170a and the gate wirings 168b and 170b.
  • the gate electrodes 168a and 170a and the gate wirings 168b and 170b are made of metal.
  • the gate wirings 168 b and 170 b extend in a direction orthogonal to the fin-like silicon layers 104 and 105.
  • the second diffusion layers 143a and 143b are formed in the fin-like silicon layers 104 and 105.
  • the line width outside the gate electrodes 168a and 170a is equal to the line width of the gate wirings 168b and 170b, and the line widths of the first columnar silicon layers 129, 131, 132, and 134 are the fin-shaped silicon layers 104 and 105.
  • the fin-shaped silicon layers 104 and 105, the first columnar silicon layers 129, 131, 132, and 134, the gate electrodes 168a and 170a, and the gate wiring 168b 170b are formed by self-alignment using two masks. Thereby, according to this embodiment, the number of processes required for manufacturing a semiconductor device can be reduced.
  • the contact device located in two rows and two columns includes a fin-like silicon layer 104 formed on the semiconductor substrate 101, a first insulating film 106 formed around the fin-like silicon layer 104, and a fin-like silicon layer 104. And a second columnar silicon layer 130 formed thereon.
  • the line width of the second columnar silicon layer 130 in the direction perpendicular to the fin-like silicon layer 104 is equal to the line width of the fin-like silicon layer 104 in the direction perpendicular to the fin-like silicon layer 104.
  • the contact device located in two rows and two columns further includes a metal contact electrode 169a formed around the second columnar silicon layer 130, and between the second columnar silicon layer 130 and the contact electrode 169a.
  • the gate insulating film 165 formed and the contact electrode 169a are connected to the fin-like silicon layer 104 and extend in a direction orthogonal to the metal contact wiring 169b, and are formed around the contact electrode 169a and the contact wiring 169b.
  • the gate insulating film 164 is provided.
  • the line width outside the contact electrode 169a is equal to the line width of the contact wiring 169b.
  • a second diffusion layer 143 a is formed below the fin-like silicon layer 104 and the second columnar silicon layer 130.
  • the contact electrode 169a is electrically connected to the second diffusion layer 143a.
  • a contact device located in one row and two columns includes a fin-like silicon layer 105 formed on the semiconductor substrate 101, a first insulating film 106 formed around the fin-like silicon layer 105, and the fin-like silicon layer 105. And a second columnar silicon layer 133 formed on the substrate.
  • the line width of the second columnar silicon layer 133 in the direction perpendicular to the fin-like silicon layer 105 is equal to the line width of the fin-like silicon layer 105 in the direction perpendicular to the fin-like silicon layer 105.
  • the contact device located in one row and two columns is further formed between a contact electrode 169a made of metal formed around the second columnar silicon layer 133, and between the second columnar silicon layer 133 and the contact electrode 169a.
  • An insulating film 164 is provided.
  • the line width outside the contact electrode 169a is equal to the line width of the contact wiring 169b.
  • a second diffusion layer 143 b is formed below the fin-like silicon layer 105 and the second columnar silicon layer 133.
  • the contact electrode 169a is electrically connected to the second diffusion layer 143b.
  • the contact wiring 169b extending in parallel to the gate wirings 168b and 170b connected to the second diffusion layers 143a and 143b is provided.
  • the second diffusion layers 143a and 143b are connected to each other, and the resistance of the source line can be lowered.
  • a large reset current can flow through the source line.
  • Such contact wirings 169b extending in parallel with the gate wirings 168b and 170b include, for example, the memory cells 2, 4, 8, 16, 32, and 64 arranged in a line along the direction in which the bit lines 187 and 188 extend. It is preferable to arrange one for each of the numbers.
  • the structure formed of the second columnar silicon layers 130 and 133, the contact electrode 169a formed around the second columnar silicon layers 130 and 133, and the contact wiring 169b is the contact electrode 169a.
  • all source lines including the second diffusion layers 143a and 143b extending in parallel with the gate wirings 168b and 170b are connected to the contact wiring 169b. Thereby, the number of processes required for manufacturing the semiconductor device is reduced.
  • the second diffusion layer 143 c is formed to a deeper position of the semiconductor substrate 101 and is formed in the fin-like silicon layers 104 and 105 than the second diffusion layers 143 a and 143 b shown in FIG. 1.
  • 1 shows a semiconductor device having a structure in which connection similar to that of the second diffusion layers 143a and 143b shown in FIG. 1 is performed. With such a structure, the source resistance can be further reduced.
  • the semiconductor device 3 does not include the fin-like silicon layer 105 shown in FIG. 2 and the first insulating film 106 formed around the fin-like silicon layer 105, and the second diffusion layer is directly formed on the semiconductor substrate 101.
  • the semiconductor device having a structure in which 143d is formed is shown. With such a structure, the source resistance can be further reduced.
  • the semiconductor substrate 101 is a silicon substrate, but may be a substrate made of other materials as long as it is a semiconductor.
  • first resists 102 and 103 for forming fin-like silicon layers 104 and 105 are formed on a silicon substrate 101.
  • the silicon substrate 101 is etched to form the fin-like silicon layers 104 and 105.
  • the fin-like silicon layers 104 and 105 are formed using a resist as a mask, but a hard mask such as an oxide film or a nitride film may be used instead of the resist.
  • a first insulating film 106 is deposited around the fin-like silicon layers 104 and 105.
  • an oxide film formed by high-density plasma or an oxide film formed by low-pressure CVD (Chemical Vapor Deposition) can be used.
  • the first insulating film 106 is etched back to expose the upper portions of the fin-like silicon layers 104 and 105.
  • the first step of this embodiment in which the fin-like silicon layers 104 and 105 are formed on the semiconductor substrate 101 and the first insulating film 106 is formed around the fin-like silicon layers 104 and 105 is shown. .
  • the second step of the embodiment of the present invention will be described.
  • the second insulating films 107 and 108 are formed around the fin-like silicon layers 104 and 105, and the first polysilicon 109 is formed on the second insulating films 107 and 108.
  • second resists 111 and 112 for forming gate wirings 168b and 170b, first columnar silicon layers 129, 131, 132, and 134, second columnar silicon layers 130 and 133, and contact wirings 169b, 113 is formed so as to extend in a direction orthogonal to the direction in which the fin-like silicon layers 104 and 105 extend.
  • the first polysilicon 109, the second insulating films 107 and 108, and the fin-like silicon layers 104 and 105 are etched, thereby 1 columnar silicon layers 129, 131, 132, 134, first dummy gates 117, 119 derived from the first polysilicon 109, second columnar silicon layers 130, 133, and the first polysilicon 109 And a second dummy gate 118 derived from the above.
  • second insulating films 107 and 108 are formed around the fin-like silicon layers 104 and 105 extending in the left-right direction on the semiconductor substrate 101.
  • the second insulating films 107 and 108 are preferably oxide films.
  • a first polysilicon 109 is deposited on the second insulating films 107 and 108 and planarized.
  • a third insulating film 110 is formed on the first polysilicon 109.
  • the third insulating film 110 is preferably a nitride film.
  • the gate wirings 168b, 170b, the first columnar silicon layers 129, 131, 132, 134, the second columnar silicon layers 130, 133, and the contact wiring 169b for forming the first wirings are formed.
  • Two resists 111, 112, and 113 are formed so as to extend in a direction orthogonal to the direction in which the fin-like silicon layers 104 and 105 extend.
  • the third insulating film 110 is separated into a plurality of portions, and third insulating films 114, 115, and 116 are formed on the first dummy gates 117 and 119 and the second dummy gate 118.
  • the second insulating films 107 and 108 are separated into a plurality of portions, and the first dummy gates 117 and 119, the second dummy gate 118, and the first columnar silicon layers 129, 131, 132, and 134 are formed.
  • second insulating films 107 and 108 are formed. Note that when the second resists 111, 112, and 113 are removed during the etching, the third insulating films 114, 115, and 116 function as a hard mask. On the other hand, if the second resists 111, 112, and 113 are not removed during the etching, the third insulating films 114, 115, and 116 need not be used as a mask.
  • the second resists 111, 112, and 113 are removed.
  • the second insulating films 107 and 108 are formed around the fin-like silicon layers 104 and 105, and the first polysilicon 109 is deposited on the second insulating films 107 and 108. Flatten with.
  • second resists 111 and 112 for forming gate wirings 168b and 170b, first columnar silicon layers 129, 131, 132, and 134, second columnar silicon layers 130 and 133, and contact wirings 169b, 113 is formed so as to extend in a direction orthogonal to the direction in which the fin-like silicon layers 104 and 105 extend.
  • the first polysilicon 109, the second insulating films 107 and 108, and the fin-like silicon layers 104 and 105 are etched, thereby 1 columnar silicon layers 129, 131, 132, 134, first dummy gates 117, 119 derived from the first polysilicon 109, second columnar silicon layers 130, 133, and the first polysilicon 109
  • the second step of forming the second dummy gate 118 derived from the above is shown.
  • the third step of the embodiment of the present invention will be described.
  • the first columnar silicon layers 129, 131, 132, 134, the second columnar silicon layers 130, 133, the first dummy gates 117, 119, and the second dummy gate A fourth insulating film 135 is formed around 118.
  • a second polysilicon 136 is deposited and etched around the fourth insulating film 135, and the second polysilicon 136 is removed from the first dummy gates 117 and 119 and the first columnar silicon layer 129.
  • Gate 138 is formed.
  • the first columnar silicon layers 129, 131, 132, 134, the second columnar silicon layers 130, 133, the first dummy gates 117, 119, and the second dummy gate 118 are formed.
  • a fourth insulating film 135 is formed around the periphery.
  • the fourth insulating film 135 is preferably an oxide film.
  • a third resist 301 is formed and etched back to expose the upper portions of the first columnar silicon layers 129, 131, 132, and 134. At this time, the upper portions of the second columnar silicon layers 130 and 133 may be exposed.
  • impurities are introduced to form first diffusion layers 302, 304, 305, 307 on top of the first columnar silicon layers 129, 131, 132, 134.
  • the first diffusion layers 303 and 306 may be formed on the second columnar silicon layers 130 and 133.
  • the impurity to be introduced is an n-type diffusion layer, it is preferable to introduce arsenic or phosphorus.
  • the impurity to be introduced is a p-type diffusion layer, it is preferable to introduce boron.
  • the third resist 301 is removed.
  • a second polysilicon 136 is deposited around the fourth insulating film 135.
  • the second polysilicon 136 is changed into the first dummy gates 117, 119, the first columnar silicon layers 129, 131, 132,
  • the third dummy gates 137 and 139 and the fourth dummy gate 138 are formed by remaining on the sidewalls of the first and second dummy gates 118 and 133 and 133.
  • the fourth insulating film 135 may be separated into a plurality of portions, and the fourth insulating films 140, 141, 142 may be formed.
  • the first columnar silicon layers 129, 131, 132, and 134, the second columnar silicon layers 130 and 133, the first dummy gates 117 and 119, and the second dummy gate 118 are formed.
  • a fourth insulating film 135 is formed around the periphery.
  • a second polysilicon 136 is deposited and etched around the fourth insulating film 135, and the second polysilicon 136 is removed from the first dummy gates 117 and 119 and the first columnar silicon layer 129.
  • a third step of forming the gate 138 is shown.
  • the fourth step of the embodiment of the present invention will be described.
  • second diffusion layers 143a and 143b are formed.
  • a fifth insulating film 144 is formed around the third dummy gates 137 and 139 and the fourth dummy gate 138 and etched to remain in a sidewall shape, and the fifth insulating film 144 is left.
  • Side walls 145, 146, and 147 derived from the above are formed.
  • compound layers 148, 149, 150, 151, 152, 153, 154, and 155 made of a metal and a semiconductor are formed on the second diffusion layers 143a and 143b.
  • the second diffusion layer 143a is formed below the first columnar silicon layers 129, 131, 132, and 134 and below the second columnar silicon layers 130 and 133. , 143b.
  • the impurity to be introduced forms the n-type diffusion layer, it is preferable to introduce arsenic or phosphorus.
  • the impurity to be introduced forms a p-type diffusion layer, it is preferable to introduce boron.
  • Such a diffusion layer may be formed after forming sidewalls 145, 146, and 147 derived from a fifth insulating film 144 described later.
  • a fifth insulating film 144 is formed around the third dummy gates 137 and 139 and the fourth dummy gate 138.
  • the fifth insulating film 144 is preferably a nitride film.
  • the fifth insulating film 144 is etched to remain in a sidewall shape.
  • sidewalls 145, 146, and 147 are formed from the fifth insulating film 144.
  • compound layers 148, 149, 150, 151, 152, 153, 154, and 155 made of metal and semiconductor are formed on the second diffusion layers 143a and 143b.
  • compound layers 156, 158, and 157 made of metal and semiconductor are also formed on the upper portions of the third dummy gates 137 and 139 and the upper portion of the fourth dummy gate 138, respectively.
  • the second diffusion layer 143a is formed on the upper portions of the fin-shaped silicon layers 104 and 105, the lower portions of the first columnar silicon layers 129, 131, 132, and 134, and the lower portions of the second columnar silicon layers 130 and 133. , 143b.
  • a fifth insulating film 144 is formed around the third dummy gates 137 and 139 and the fourth dummy gate 138 and etched to remain in a sidewall shape, so that the fifth insulating film Side walls 145, 146 and 147 derived from 144 are formed.
  • a fourth step of forming compound layers 148, 149, 150, 151, 152, 153, 154, 155 made of metal and semiconductor on the second diffusion layers 143a, 143b is shown.
  • the fifth step of the embodiment of the present invention will be described.
  • the first interlayer insulating film 159 is deposited and planarized, and the first dummy gates 117 and 119, the second dummy gate 118, and the third dummy gates 137 and 139 are formed.
  • the fourth dummy gate 138 are exposed, and the first dummy gates 117 and 119, the second dummy gate 118, the third dummy gates 137 and 139, and the fourth dummy gate 138 are removed. To do.
  • the second insulating films 123, 124, 125, 126, 127, 128 and the fourth insulating films 140, 141, 142 are removed, and the gate insulating film 160 is replaced with the first columnar silicon layers 129, 131, It is formed around 132 and 134, around the second columnar silicon layers 130 and 133, and inside the fifth insulating film 144.
  • a fourth resist 161 for removing the gate insulating film 160 around the bottom of the second columnar silicon layers 130 and 133 is formed, and the gate insulating film around the bottom of the second columnar silicon layers 130 and 133 is formed.
  • gate electrodes 168a and 170a and gate wirings 168b and 170b are formed around the first columnar silicon layers 129, 131, 132, and 134. Thereafter, contact electrodes 169 a and contact wirings 169 b are formed around the second columnar silicon layers 130 and 133.
  • a first interlayer insulating film 159 is deposited.
  • a contact stopper film may be used.
  • the first dummy gates 117 and 119, the second dummy gate 118, the third dummy gates 137 and 139, and the fourth dummy gates are performed.
  • the upper portions of the dummy gates 138 are exposed.
  • the compound layers 156, 158, and 157 made of metal and semiconductor existing on the upper portions of the third dummy gates 137 and 139 and the upper portion of the fourth dummy gate 138 are removed.
  • the first dummy gates 117 and 119, the second dummy gate 118, the third dummy gates 137 and 139, and the fourth dummy gate 138 are removed.
  • the second insulating films 123, 124, 125, 126, 127, 128 and the fourth insulating films 140, 141, 142 are removed.
  • a gate insulating film 160 is formed inside the walls 145, 146, and 147.
  • a fourth resist 161 for removing the gate insulating film 160 around the bottoms of the second columnar silicon layers 130 and 133 is formed.
  • the gate insulating film 160 around the bottom of the second columnar silicon layers 130 and 133 is removed using the fourth resist 161 as a mask.
  • the gate insulating film 160 is separated into a plurality of portions, and gate insulating films 162, 163, 164, 165, and 166 are formed. Note that the gate insulating films 164, 165, and 166 may be removed by isotropic etching.
  • a metal layer 167 is deposited.
  • the metal layers 167 are etched back to form gate electrodes 168a, 170a and gate wirings 168b, 170b around the first columnar silicon layers 129, 131, 132, 134. Then, the contact electrode 169a and the contact wiring 169b are formed around the second columnar silicon layers 130 and 133.
  • the first interlayer insulating film 159 is deposited and planarized, and the first dummy gates 117 and 119, the second dummy gate 118, the third dummy gates 137 and 139, and The upper portions of the fourth dummy gates 138 are exposed, and the first dummy gates 117 and 119, the second dummy gate 118, the third dummy gates 137 and 139, and the fourth dummy gate 138 are removed.
  • the second insulating films 123, 124, 125, 126, 127, 128 and the fourth insulating films 140, 141, 142 are removed, and the gate insulating film 160 is replaced with the first columnar silicon layers 129, 131, 132 and 134, around the second columnar silicon layers 130 and 133, and inside the sidewalls 145, 146 and 147 derived from the fifth insulating film 144.
  • a fourth resist 161 for removing the gate insulating film 160 around the bottom of the second columnar silicon layers 130 and 133 is formed, and the gate insulating film around the bottom of the second columnar silicon layers 130 and 133 is formed.
  • the sixth step of the embodiment of the present invention will be described.
  • the second interlayer insulating film 171 is deposited and flattened to expose the upper portions of the first columnar silicon layers 129, 131, 132, 134, and the first columnar silicon layer Storage elements 181 a, 181 b, 182 a, and 182 b whose resistance is changed are formed on the upper portions of 129, 131, 132, and 134.
  • a second interlayer insulating film 171 is deposited.
  • the second interlayer insulating film 171 is etched back, so that the upper portions of the first columnar silicon layers 129, 131, 132, and 134 and the second columnar silicon layers 130 and 133 are etched. Expose the top of.
  • a metal layer 175 and a film 176 whose resistance changes are deposited.
  • a fifth resist is formed so that the upper portions of the first columnar silicon layers 129, 131, 132, and 134 are connected to the metal layer 175 along the direction orthogonal to the bit lines. 177, 178 are formed.
  • the metal layer 175 and the film 176 whose resistance changes are etched.
  • the metal layer 175 is separated from the film 176 whose resistance changes, and becomes metal lines 179 and 180 and wirings 181 and 182 of the film whose resistance changes, respectively.
  • a third interlayer insulating film 183 is deposited and etched back to expose the upper portions of the wirings 181 and 182 of the film whose resistance changes.
  • a metal layer 184 is deposited.
  • sixth resists 185 and 186 for forming bit lines are formed.
  • the sixth resists 185 and 186 extend in a direction orthogonal to the metal lines 179 and 180 and the wirings 181 and 182 of the film whose resistance changes, so that the first columnar silicon layers 129, 131, 132, It is preferable that the upper part of 134 and the metal wires 179 and 180 are connected to each other.
  • bit lines 187 and 188 are formed by etching the metal layer 184, the metal lines 179 and 180, and the wirings 181 and 182 of the film whose resistance changes.
  • the metal lines 179 and 180 and the wirings 181 and 182 of the film whose resistance changes are separated, and the high resistance heaters 179a, 179b, 180a and 180b, and the storage elements 181a, 181b and 182a whose resistance changes. , 182b.
  • the second interlayer insulating film 171 is deposited and planarized, and the upper portions of the first columnar silicon layers 129, 131, 132, and 134 are exposed, and the first columnar silicon layer 129,
  • a sixth step of forming memory elements 181a, 181b, 182a, and 182b whose resistances change on the upper portions of 131, 132, and 134 is shown.
  • the manufacturing process for forming the structure of the semiconductor device according to the embodiment of the present invention is shown. According to the present embodiment, since the structures of all the semiconductor devices are formed using a linear resist, fine processing is facilitated.
  • SGT can pass a larger amount of current per unit gate width than a double gate transistor. Further, since the SGT has a structure in which the gate electrode surrounds the columnar semiconductor layer, the gate line width per unit area can be increased, and a larger amount of current can flow. Therefore, a large reset current can be passed, and phase change films such as the memory elements 181a and 181b whose resistance changes can be melted at a high temperature (high current). In addition, since the SGT subthreshold swing can realize an ideal value, the off-current can be reduced, so that the phase change film can be cooled at high speed (the current is stopped).
  • the gate electrodes 168a and 170a and the gate wiring 168b are made of metal, the cooling when heated can be accelerated.
  • the gate electrodes 168a and 170a and the gate wirings 168b and 170b formed around and under the bottoms of the gate wirings 168b and 170b are provided so that the gate electrode which is a metal gate by the gate last forming the metal gate after the heat treatment process. Since 168a and 170a are formed, the metal gate process and the high temperature process can be made compatible.
  • Gate electrodes 168a, 170a and gate wirings 168b, 170b, and gate wirings 168b, 170b formed at the bottom and bottom of the gate electrodes 168a, 170a, and the gate wirings 168b, 170b are made of metal.
  • the second diffusion layers 143a and 143b are formed in the fin-like silicon layers 104 and 105, and the line width outside the gate electrodes 168a and 170a is as follows. Since the line widths of the first columnar silicon layers 129, 131, 132, and 134 are equal to the line widths of the fin-like silicon layers 104 and 105, the line widths of the gate wirings 168b and 170b are equal to each other.
  • the second diffusion layers 143a and 143b are provided by having the contact wiring 169b extending in parallel with the gate wirings 168b and 170b connected to the second diffusion layers 143a and 143b. Are connected to each other, and the resistance of the source line can be lowered. As a result, a large reset current can flow through the source line.
  • the contact wiring extending in parallel with the gate wirings 168b and 170b is, for example, one of the memory cells 2, 4, 8, 16, 32, and 64 arranged in a line along the direction in which the bit lines 187 and 188 extend. It is preferable to arrange one for each number.
  • the second columnar silicon layers 130 and 133, the contact electrodes 169 a formed around the second columnar silicon layers 130 and 133, and the contact wiring 169 b are formed.
  • the structure is the same as the transistor structure of the memory cell located in one row and one column except that the contact electrode 169a is electrically connected to the second diffusion layers 143a and 143b. Further, all source lines including the second diffusion layers 143a and 143b extending in parallel with the gate wirings 168b and 170b are connected to the contact wiring 169b. Thereby, the number of processes required for manufacturing the semiconductor device can be reduced.
  • Second columnar silicon layer 131 First columnar silicon layer 132. First columnar silicon layer 133. Second columnar silicon layer 134. First columnar silicon layer 135. Fourth insulating film 136. Second polysilicon 137. Third dummy gate 138. Fourth dummy gate 139. Third dummy gate 140. Fourth insulating film 141. Fourth insulating film 142. Fourth insulating film 143a. Second diffusion layer 143b. Second diffusion layer 143c. Second diffusion layer 143d. Second diffusion layer 144. Fifth insulating film 145. Side wall 146. Sidewall 147. Sidewall 148. Compound layer 149 made of metal and semiconductor. Compound layer made of metal and semiconductor 150. Compound layer 151 made of metal and semiconductor 151.
  • Compound layer made of metal and semiconductor 152 Compound layer 153 composed of metal and semiconductor. Compound layer made of metal and semiconductor 154. Compound layer 155 composed of metal and semiconductor. Compound layer made of metal and semiconductor 156. Compound layer made of metal and semiconductor 157. Compound layer made of metal and semiconductor 158. Compound layer 159 made of metal and semiconductor.
  • First interlayer insulating film 160 Gate insulating film 161. Fourth resist 162. Gate insulating film 163. Gate insulating film 164. Gate insulating film 165. Gate insulating film 166. Gate insulating film 167. Metal layer 168a. Gate electrode 168b. Gate wiring 169a. Contact electrode 169b. Contact wiring 170a. Gate electrode 170b. Gate wiring 171.

Abstract

L'invention porte sur un dispositif à semi-conducteurs qui possède : des premières couches de semi-conducteur en colonnes (129, 131, 132, 134); un film d'isolation de grille (162) qui est formé autour des premières couches de semi-conducteur en colonnes; des électrodes de grille (168a, 170a) qui sont formées autour du film d'isolation de grille; des lignes de câblage de grille (168b, 170b) qui sont connectées aux électrodes de grille; des premières couches de diffusion (302, 304, 305, 307) qui sont formées en tant que parties supérieures des premières couches de semi-conducteur en colonnes; des secondes couches de diffusion (143a, 143b) qui sont formées en tant que parties inférieures des premières couches de semi-conducteur en colonnes; des éléments de stockage (181a, 181b, 182a, 182b), qui sont formés sur les premières couches de diffusion et dans lesquels des valeurs de résistance varient.
PCT/JP2013/075192 2013-09-18 2013-09-18 Dispositif à semi-conducteurs et procédé de fabrication de semi-conducteurs WO2015040705A1 (fr)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005260014A (ja) * 2004-03-12 2005-09-22 Hitachi Ltd 半導体装置
JP2009182318A (ja) * 2008-01-29 2009-08-13 Unisantis Electronics Japan Ltd 半導体装置およびその製造方法
JP2011199017A (ja) * 2010-03-19 2011-10-06 Elpida Memory Inc 半導体装置
WO2013038553A1 (fr) * 2011-09-15 2013-03-21 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド Procédé de production d'un dispositif semiconducteur, ainsi que dispositif semiconducteur
WO2013093988A1 (fr) * 2011-12-19 2013-06-27 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド Procédé de production de dispositif semi-conducteur, et dispositif semi-conducteur

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005260014A (ja) * 2004-03-12 2005-09-22 Hitachi Ltd 半導体装置
JP2009182318A (ja) * 2008-01-29 2009-08-13 Unisantis Electronics Japan Ltd 半導体装置およびその製造方法
JP2011199017A (ja) * 2010-03-19 2011-10-06 Elpida Memory Inc 半導体装置
WO2013038553A1 (fr) * 2011-09-15 2013-03-21 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド Procédé de production d'un dispositif semiconducteur, ainsi que dispositif semiconducteur
WO2013093988A1 (fr) * 2011-12-19 2013-06-27 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド Procédé de production de dispositif semi-conducteur, et dispositif semi-conducteur

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