WO2015032147A1 - 像素电路及显示器 - Google Patents

像素电路及显示器 Download PDF

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Publication number
WO2015032147A1
WO2015032147A1 PCT/CN2013/089302 CN2013089302W WO2015032147A1 WO 2015032147 A1 WO2015032147 A1 WO 2015032147A1 CN 2013089302 W CN2013089302 W CN 2013089302W WO 2015032147 A1 WO2015032147 A1 WO 2015032147A1
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Prior art keywords
transistor
module
pixel
light
circuit
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Ceased
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PCT/CN2013/089302
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English (en)
French (fr)
Inventor
陈俊生
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BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
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BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
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Priority to US14/366,141 priority Critical patent/US9443472B2/en
Publication of WO2015032147A1 publication Critical patent/WO2015032147A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0465—Improved aperture ratio, e.g. by size reduction of the pixel circuit, e.g. for improving the pixel density or the maximum displayable luminance or brightness
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0814—Several active elements per pixel in active matrix panels used for selection purposes, e.g. logical AND for partial update
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a pixel circuit and a display. Background technique
  • LTPS Low Temperature Poly-Silicon
  • the pixel compensation circuit in the prior art is a 6T1C circuit (a circuit composed of 6 thin film transistors and 1 capacitor), and the circuit diagram is as shown in FIG. 1.
  • VDD is a high voltage level signal
  • VSS is a low voltage level.
  • the number of components required to be arranged in two pixels in the horizontal direction of the 6T1C circuit in the prior art is: 2 data signal lines (Data vl and Data v2), 12 TFTs, 2 Capacitor, 1 gate control signal Gate line, 1 illumination control signal EM line, 1 high voltage level signal VDD line, 1 initialization voltage level signal Vinit line, and 1 initialization control signal Reset line, Figure 2
  • OLED1 and OLED2 the cathodes of which are connected to the low voltage level signal VSS line
  • FIG. 2 is a schematic circuit diagram of two pixels arranged horizontally.
  • the pixel arrangement in the horizontal direction or the pixel arrangement in the vertical direction are similar, so similarly, the number of components to be arranged in two pixels in the vertical direction is: 1 data signal line, 12 TFTs, 2 capacitors , 2 gate control signal lines, 1 illumination control signal line, 1 high voltage level signal line, and 1 initialization voltage level signal line.
  • Embodiments of the present invention provide a pixel circuit for reducing the size of a pixel circuit, thereby reducing pixel pitch, increasing the number of pixels in a unit area, and improving picture display quality.
  • the present invention also provides a display.
  • a pixel circuit including: a first pixel sub-circuit and a second pixel sub-circuit, and an initialization module and a data voltage connected to the first pixel sub-circuit and the second pixel sub-circuit Write module,
  • the initialization module is connected to the reset signal end and the low potential end, and is configured to initialize the first pixel sub-circuit and the second pixel sub-circuit under the control of the reset signal input by the reset signal end;
  • the data voltage writing module is connected to the data voltage terminal and the gate signal terminal, and is configured to first write a first data voltage to the first pixel sub-circuit under the control of the signal input by the gate signal terminal, and first The driving module of the pixel sub-circuit compensates, then writes the second data voltage to the second pixel sub-circuit, and compensates the driving module of the second pixel sub-circuit.
  • the pixel circuit provided by the embodiment of the present invention includes: a first pixel sub-circuit and a second pixel sub-circuit, and an initialization module and a data voltage writing module connected to the first pixel sub-circuit and the second pixel sub-circuit.
  • the pixel circuit composed of the first pixel sub-circuit, the second pixel sub-circuit, and the initialization module and the data voltage writing module can reduce the pixel circuit size, thereby reducing the pixel pitch, and increasing the number of pixels in a unit area. , improve the display quality of the screen.
  • the first pixel sub-circuit includes a first driving module, a first lighting module, a first threshold compensation module, and a first lighting control module.
  • the first threshold compensation module is connected to the initialization module, and is initialized under the control of the initialization signal output by the initialization module;
  • the first threshold compensation module is connected to the first driving module, and configured to perform threshold voltage compensation on the first driving module
  • the first illuminating module is connected to the first illuminating control module, and is configured to perform illuminating display under the action of the first driving module and the first illuminating control module.
  • the first pixel sub-circuit composed of the first driving module, the first lighting module, the first threshold compensation module and the first lighting control module is simple and easy to implement in the design of the pixel circuit.
  • the first threshold compensation module includes a first storage capacitor, a second transistor, and a fourth transistor; the first driving module includes a fifth transistor; and the first lighting control module includes a seven-transistor and a ninth transistor; the first light-emitting module includes a first light-emitting diode.
  • the first pixel sub-circuit composed of the storage capacitor, the transistor and the light-emitting diode is easy to implement in the design of the pixel circuit.
  • one end of the first storage capacitor is connected to a high voltage level signal line, and the other end is connected to a source of the second transistor;
  • a gate of the second transistor is connected to the first control signal line, a drain of the second transistor is connected to the initialization module and is connected to a source of the fourth transistor;
  • a gate of the fourth transistor is connected to a signal terminal of the gate, and a source of the fourth transistor is connected to the initialization module;
  • a gate of the fifth transistor is connected to the initialization module and connected to a source of the fourth transistor, a drain of the fifth transistor is connected to a drain of the fourth transistor, the fifth transistor a source connected to the data voltage writing module;
  • a gate of the seventh transistor is connected to the light emission control signal line, a source of the seventh transistor is connected to a high voltage level signal line, and a drain of the seventh transistor is connected to a source of the fifth transistor; a gate of the ninth transistor is connected to the light emission control signal line, a source of the ninth transistor is connected to a drain of the fifth transistor, and a drain of the ninth transistor is connected to the first light emitting diode;
  • An anode of the first light emitting diode is connected to a drain of the ninth transistor, and a cathode of the first light emitting diode is connected to a low voltage level signal line.
  • the connection relationship between the storage capacitor, the transistor, and the light-emitting diode is facilitated in the design of the pixel circuit.
  • the second pixel sub-circuit includes a second driving module, a second lighting module, a second threshold compensation module, and a second lighting control module.
  • the second threshold compensation module is connected to the initialization module, and is initialized under the control of the initialization signal output by the initialization module;
  • the second threshold compensation module is connected to the second driving module, and is configured to perform threshold voltage compensation on the second driving module.
  • the second illuminating module is connected to the second illuminating control module for performing illuminating display under the action of the second driving module and the second illuminating control module.
  • the second pixel sub-circuit composed of the second driving module, the second lighting module, the second threshold compensation module and the second lighting control module is conveniently implemented in the design of the pixel circuit.
  • the second threshold compensation module includes a second storage capacitor and an eighth transistor;
  • the second driving module includes a sixth transistor;
  • the second lighting control module includes a tenth transistor;
  • a second light emitting diode is included.
  • the second pixel sub-circuit consisting of the storage capacitor, the transistor and the light emitting diode is easily implemented in the design of the pixel circuit.
  • one end of the second storage capacitor is connected to the high voltage level signal line, and the other end is connected to the source of the eighth transistor;
  • a gate of the eighth transistor is connected to a second control signal line, a drain of the eighth transistor is connected to the initialization module and is connected to a source of the fourth transistor;
  • a gate of the sixth transistor is connected to a source of the eighth transistor, a source of the sixth transistor is connected to the data voltage writing module and connected to a drain of the seventh transistor; a gate of the tenth transistor is connected to the light emission control signal line, a source of the tenth transistor is connected to a drain of the sixth transistor, and a drain of the tenth transistor is connected to the second light emitting diode;
  • An anode of the second light emitting diode is connected to a drain of the tenth transistor, and a cathode of the second light emitting diode is connected to a low voltage level signal line.
  • the connection relationship between the storage capacitor, the transistor, and the light-emitting diode is facilitated in the design of the pixel circuit.
  • the initialization module includes a third transistor, a gate of the third transistor is connected to a reset signal line, and a source of the third transistor and a first threshold compensation module of the first pixel sub-circuit
  • the source of the four transistor is connected to the drain of the eighth transistor of the second threshold compensation module of the second pixel sub-circuit, and the drain of the third transistor is connected to the low voltage level signal line.
  • the initialization module includes a third transistor, which serves as a switching device of the initialization module in the pixel circuit, and is convenient for implementation in the circuit design.
  • the data voltage writing module includes a first transistor, wherein a gate of the first transistor is connected to a gate signal control line, and a source of the first transistor is connected to a data signal line, The drain of the first transistor is coupled to the source of the fifth transistor of the first driver module of the first pixel sub-circuit and the source of the sixth transistor of the second driver module of the second pixel sub-circuit.
  • the data voltage writing module includes a first transistor, and the first transistor functions as a switching device of the data voltage writing module in the pixel circuit, which is convenient for implementation in the circuit design.
  • the data voltage input in the data voltage writing module includes a first data voltage and a second data voltage, wherein the first data voltage is used to drive the first threshold compensation module to perform threshold voltage compensation on the first driving module, and the second data voltage is used to drive the second threshold compensation module to perform threshold voltage compensation on the second driving module .
  • the data signal is a stepped timing signal, two different voltage values can be input from one data signal line.
  • the first light emitting diode and the second light emitting diode are both organic light emitting diodes.
  • the organic light emitting diode is used as the first light emitting module in the pixel circuit and the light emitting diode in the second light emitting module, which is convenient in the circuit design.
  • the transistors are all P-type thin film transistors.
  • a P-type thin film transistor is used as a thin film transistor in a pixel circuit, which is convenient for implementation in circuit design.
  • the display provided by the embodiment of the invention includes a plurality of pixels, a plurality of data signal lines and a plurality of gate control signal lines, wherein each of the two pixels constitutes a pixel unit, and further includes the above-mentioned connection with each pixel unit Pixel circuit.
  • the display since the display includes the above-described pixel circuit connected to each pixel unit, the display has the advantages of the pixel circuit, and the picture display quality can be improved.
  • two pixels in each pixel unit share one data signal line.
  • two pixels in each pixel unit share a gate control signal line.
  • two pixels in each pixel unit share a gate control signal line, so that two pixels can omit one gate control signal line, and the arrangement method of the gate control signal lines is easy.
  • FIG. 1 is a schematic diagram of a 6T1C AMOLED pixel compensation circuit in a single pixel in the prior art
  • FIG. 2 is a schematic diagram of a 12T2C AMOLED pixel compensation circuit in two pixels in the prior art
  • FIG. 3 is a schematic diagram of a 10T2C AMOLED pixel circuit according to an embodiment of the present invention
  • FIG. 4 is a timing diagram of a 10T2C AMOLED pixel circuit according to an embodiment of the present invention
  • FIG. 6 is a circuit diagram of a 10T2C AMOLED pixel circuit in a first threshold compensation phase according to an embodiment of the present invention
  • FIG. 7 is a circuit diagram of a 10T2C AMOLED pixel circuit in a second threshold compensation phase according to an embodiment of the present invention.
  • FIG. 8 is a circuit diagram of a 10T2C AMOLED pixel circuit in an illumination stage according to an embodiment of the present invention.
  • FIG. 9 is a schematic diagram showing the arrangement of individual pixels in the prior art.
  • FIG. 10 is a schematic diagram of an arrangement of pixel units composed of two pixels in a horizontal direction according to an embodiment of the present disclosure
  • FIG. 11 is a schematic diagram of another arrangement of pixel units composed of two pixels in a horizontal direction according to an embodiment of the present disclosure
  • FIG. 12 is a schematic diagram of an arrangement of pixel units composed of two pixels in a vertical direction according to an embodiment of the present disclosure
  • FIG. 13 is a schematic diagram of another arrangement of pixel units composed of two pixels in a vertical direction according to an embodiment of the present invention. detailed description
  • Embodiments of the present invention provide a pixel circuit and a display for reducing the size of a pixel circuit, thereby reducing pixel pitch, increasing the number of pixels in a unit area, and improving picture display quality.
  • the pixel circuit provided by the embodiment of the present invention is an active matrix light emitting diode pixel circuit. Since the active matrix light emitting diode pixel circuit can compensate the driving module of the pixel, the active matrix light emitting diode pixel in the present invention The circuit can also be referred to as an active matrix light emitting diode pixel compensation circuit.
  • an active matrix light emitting diode pixel circuit provided by an embodiment of the present invention includes: a first pixel sub-circuit and a second pixel sub-circuit, and the first pixel sub-circuit and the second pixel
  • the initialization module 31 is connected to the reset signal end (corresponding to the initialization control signal Reset of the AMOLED pixel circuit) and the low potential end (corresponding to the initialization voltage level signal Vinit of the AMOLED pixel circuit) for controlling the reset signal input at the reset signal end.
  • the reset signal end corresponding to the initialization control signal Reset of the AMOLED pixel circuit
  • the low potential end corresponding to the initialization voltage level signal Vinit of the AMOLED pixel circuit
  • the data voltage writing module 32 is connected to the data voltage end (corresponding to the data signal Data of the AMOLED pixel circuit) and the gate signal end (corresponding to the gate control signal Gate of the AMOLED pixel circuit) for the signal input at the gate signal end. Controlling, by the first pixel sub-circuit, a first data voltage, and compensating the driving module of the first pixel sub-circuit, and then writing a second data voltage to the second pixel sub-circuit, and second The drive module of the pixel sub-circuit compensates.
  • the first pixel sub-circuit includes: a first driving module 331, a first lighting module 341, a first threshold compensation module 351, and a first lighting control module 361.
  • the first threshold compensation module 351 is connected to the initialization module 31 and initialized under the control of the initialization signal output by the initialization module 31;
  • the first threshold compensation module 351 is connected to the first driving module 331 for performing threshold voltage compensation on the first driving module 331;
  • the first light-emitting module 341 is connected to the first light-emitting control module 361 for performing light-emitting display under the action of the first driving module 331 and the first light-emitting control module 361.
  • the first threshold compensation module 351 includes a first storage capacitor C1, a second transistor T2, and a fourth transistor T4; the first driving module 331 includes a fifth transistor T5; the first lighting control module 361 A seventh transistor T7 and a ninth transistor T9 are included; the first light emitting module 341 includes a first light emitting diode OLED1.
  • one end of the first storage capacitor C1 is connected to a high voltage level signal line (corresponding to a high voltage level signal VDD), and the other end is connected to a source of the second transistor T2;
  • a gate of the second transistor T2 is connected to a first control signal line (corresponding to a first control signal SW1 of the AMOLED pixel circuit), and a drain of the second transistor T2 is connected to the initialization module 31;
  • the gate of the fourth transistor T4 is connected to the gate signal end (corresponding to the AMOLED pixel circuit gate control signal Gate), the source of the fourth transistor T4 is connected to the initialization module 31; the fifth transistor T5 The gate of the fifth transistor T5 is connected to the drain of the fourth transistor T4, and the source of the fifth transistor T5 and the data voltage writing module 32 are connected. Connected
  • a gate of the seventh transistor T7 and an emission control signal line (corresponding to an AMOLED pixel circuit) a light emission control signal EM ) is connected, a source of the seventh transistor T7 is connected to a high voltage level signal line (corresponding to a high voltage level signal VDD ), and a drain of the seventh transistor T7 and a fifth transistor T5 Source connected
  • a gate of the ninth transistor T9 is connected to a light emission control signal line (a light emission control signal EM corresponding to the AMOLED pixel circuit), and a source of the ninth transistor T9 is connected to a drain of the fifth transistor T5,
  • the drain of the ninth transistor T9 is connected to the first light emitting diode OLED1; the anode of the first light emitting diode OLED1 is connected to the drain of the ninth transistor T9, and the cathode of the first light emitting diode OLED1 and the low voltage level signal line (corresponding to the low voltage level signal VSS) is connected.
  • the second pixel sub-circuit includes a second driving module 332, a second lighting module 342, a second threshold compensation module 352, and a second lighting control module 362.
  • the second threshold compensation module 352 is connected to the initialization module 31 and initialized under the control of the initialization signal output by the initialization module 31;
  • the second threshold compensation module 352 is connected to the second driving module 332 for performing threshold voltage compensation on the second driving module 332.
  • the second illuminating module 342 is connected to the second illuminating control module 362 for performing illuminating display under the action of the second driving module 332 and the second illuminating control module 362.
  • the second threshold compensation module 352 includes a second storage capacitor C2 and an eighth transistor T8; the second driving module 332 includes a sixth transistor T6; and the second illumination control module 362 includes a tenth transistor T10.
  • the second light emitting module 342 includes a second light emitting diode OLED2.
  • one end of the second storage capacitor C2 is connected to a high voltage level signal line (corresponding to a high voltage level signal VDD), and the other end is connected to a source of the eighth transistor T8;
  • the gate of the eighth transistor T8 is connected to a second control signal line (corresponding to the second control signal SW2 of the AMOLED pixel circuit), and the drain of the eighth transistor T8 is connected to the initialization module 31;
  • a gate of the sixth transistor T6 is connected to a source of the eighth transistor T8, a source of the sixth transistor T6 is connected to the data voltage writing module 32 and a drain of the seventh transistor T7
  • the drain of the sixth transistor T6 is connected to the second light emitting diode OLED2;
  • the gate of the tenth transistor T10 is connected to the light emission control signal line (the light emission control signal EM corresponding to the AMOLED pixel circuit), a source of the ten transistor T10 and the sixth crystal a drain of the transistor T6 is connected, and a drain of the tenth transistor T10 is connected to the second light emitting diode OLED2;
  • the anode of the second light emitting diode OLED2 is connected to the drain of the tenth transistor T10, and the cathode of the second light emitting diode OLED2 is connected to a low voltage level signal line (corresponding to the low voltage level signal VSS).
  • the illuminating control modules 361 and 362 can simultaneously control the illuminating of the OLED 1 and the OLED 2, and can also separately control the illuminating of the OLED 1 and the OLED 2.
  • the initialization module 31 includes a third transistor T3, and a gate of the third transistor T3 is connected to a reset signal line (initialization control signal Reset corresponding to the AMOLED pixel circuit), and a source of the third transistor T3 Connected to the first threshold compensation module 351 of the first pixel sub-circuit and the second threshold compensation module 352 of the second pixel sub-circuit, the drain of the third transistor T3 and the low voltage level signal line (corresponding to the AMOLED pixel circuit The initialization voltage level signal Vinit) is connected.
  • a reset signal line initialization control signal Reset corresponding to the AMOLED pixel circuit
  • the data voltage writing module 32 includes a first transistor T1, and a gate of the first transistor T1 is connected to a gate signal control line (corresponding to a gate control signal Gate of the AMOLED pixel circuit).
  • a source of a transistor T1 is connected to a data signal line (data signal Data corresponding to the AMOLED pixel circuit), a drain of the first transistor T1 and a first driving module 331 and a second pixel sub-circuit of the first pixel sub-circuit
  • the second driving module 332 is connected.
  • the data voltage input in the data voltage writing module 32 includes a first data voltage and a second data voltage, wherein the first data voltage is used to drive the first threshold compensation module 351 to perform the first driving module 331 The threshold voltage is compensated, and the second data voltage is used to drive the second threshold compensation module 352 to perform threshold voltage compensation on the second driving module 332.
  • the first light emitting diode OLED1 and the second light emitting diode OLED2 are both organic light emitting diodes.
  • the transistors T1, ⁇ 2, ⁇ 3, ⁇ 4, ⁇ 5, ⁇ 6, ⁇ 7, ⁇ 8, ⁇ 9 and T10 are ⁇ -type thin film transistors.
  • the gate control signal Gate and the light emission control signal EM are at a high level; the initialization control signal Reset, the first control signal SW1, and the second control signal SW2 are at a low level, at this time,
  • the third transistor T3, the second transistor ⁇ 2, and the eighth transistor ⁇ 8 of 3 are turned on,
  • the first transistor T1, the fourth transistor ⁇ 4, the seventh transistor ⁇ 7, the ninth transistor ⁇ 9, and the tenth transistor T10 are turned off, and therefore, the cylindrical circuit diagram of FIG. 3 is as shown in FIG.
  • the storage capacitors C1 and C2 respectively store the data signal Data input by the previous frame, the two capacitors are all connected to the initialization voltage level signal Vinit having a low potential, and the storage capacitors C1 and C2 are both paired with the initialization voltage level signal. Vinit discharges and discharges to the initialization voltage Vinit.
  • the initialization control signal Reset, the second control signal SW2, and the illumination control signal EM are at a high level; the gate control signal Gate and the first control signal SW1 are at a low level, at this time,
  • the first transistor T1, the second transistor T2, and the fourth transistor T4 in 3 are turned on; the third transistor T3, the eighth transistor T8, the seventh transistor T7, the ninth transistor T9, and the tenth transistor T10 are turned off, and therefore, FIG.
  • the cylindrical circuit diagram is shown in Figure 6.
  • the data level signal Data is input to the first data voltage value VI.
  • the initialization control signal Reset, the first control signal SW1, and the illumination control signal EM are at a high level; the gate control signal Gate and the second control signal SW2 are at a low level, at this time,
  • the first transistor T1, the fourth transistor ⁇ 4, and the eighth transistor ⁇ 8 in 3 are turned on; the second transistor ⁇ 2, the third transistor ⁇ 3, the seventh transistor ⁇ 7, the ninth transistor ⁇ 9, and the tenth transistor T10 are turned off, and therefore, FIG.
  • the cylindrical circuit diagram is shown in Figure 7.
  • the data level signal Data is input to the second data voltage value V2.
  • Vth ( T5 ) Vth ( T6 )
  • Vth ( T6 ) Vth ( T6 ) can be approximated.
  • Vth ( T6 ) is the threshold voltage of the sixth transistor ⁇ 6, then the voltage value V VS - Vth ( T6 ), and the voltage value is stored in the storage capacitor C2.
  • the initialization control signal Reset, the gate control signal Gate, and the second control signal SW2 are at a high level; the first control signal SW1 and the light-emission control signal EM are at a low level,
  • the seventh transistor ⁇ 7, the ninth transistor ⁇ 9, and the tenth transistor T10 in FIG. 3 are turned on, the first transistor T1, the third transistor ⁇ 3, the fourth transistor ⁇ 4, and the eighth transistor ⁇ 8 are turned off,
  • the cylindrical circuit diagram of Figure 3 is shown in Figure 8.
  • the fifth transistor ⁇ 5 and the sixth transistor ⁇ 6 are driving transistors of the OLED, and the current is controlled in the following manner: the sources of the fifth transistor ⁇ 5 and the sixth transistor ⁇ 6 are both connected to the high voltage level signal VDD, The current flowing through the first LED OLED1 is:
  • the current through the second light emitting diode OLED2 is:
  • the AMOLED pixel circuit provided by the embodiment of the present invention includes 10 thin film transistors and two capacitors, that is, a 10T2CAMOLED pixel circuit.
  • a display provided by an embodiment of the present invention includes a plurality of pixels, a plurality of data signal lines, and a plurality of gate control signal lines, wherein each of the two pixels constitutes a pixel unit, and the present invention further includes the present invention
  • the 10T2C AMOLED pixel circuit provided by the embodiment.
  • the pixel arrangement of a single pixel in the prior art is as shown in FIG. 9.
  • the compensation circuit in a single pixel is a 6T1C AMOLED pixel compensation circuit in the prior art. If two pixels are put together to form a pixel unit, then The compensation circuit of the pixel unit in the prior art is a 12T2C AMOLED pixel compensation circuit in the prior art.
  • FIG. 10-13 The arrangement of pixel units including 2 pixels provided by the embodiment of the present invention is as shown in FIG. 10-13, wherein, as shown in FIGS. 10 and 11, two pixels arranged in a horizontal direction in any pixel unit share a data signal.
  • Line Data (m) as shown in FIGS. 12 and 13, two pixels arranged in the vertical direction of any pixel unit share a gate control signal line Gate (N), wherein two of the pixel units are arranged in the horizontal direction.
  • any two pixels in the horizontal direction of the pixels such as: a pixel (Pi xe l) 1 and pixel 2, pixel 2 or with pixel 3, any arbitrary two pixels in the vertical direction of a pixel cells arranged in the vertical direction is Two pixels.
  • the two pixels arranged in the horizontal direction in the pixel unit share a data signal line Data (m) including: the data signal line Data (m) is located in two horizontally arranged Pixel 1 and Between Pixel 2 (as shown in Figure 11); or the data signal line Data (m) is located outside the Pixel 1 and Pixel 2 in two horizontal directions (as shown in Figure 10), of course, this
  • the data signal line Data(m) in the embodiment of the invention is not limited to being located outside the Pixel 1 (inside)
  • the side refers to the side of the pixel unit in which the two pixels are arranged in the horizontal direction, and the side where the two pixels are apart from each other, and may be located outside the any one of the two horizontally arranged pixels ( For example, the left side of pixel 1, or the right side of pixel 2).
  • the two pixels arranged in the vertical direction in the vertical direction share a gate control signal line Gate (N) including: the gate control signal line Gate (N) is arranged in the vertical direction. Between the two pixels in the pixel unit composed of two pixels (as shown in FIG. 12), or the gate control signal line Gate (N) is located in any one of the pixel units of any two pixels arranged in the vertical direction The outside of the pixel (as shown in Figure 13).
  • the AMOLED pixel circuit includes: a first pixel sub-circuit and a second pixel sub-circuit, and is connected to the first pixel sub-circuit and the second pixel sub-circuit
  • the initialization module and the data voltage writing module the initialization module is connected to the reset signal end and the low potential end, and is configured to initialize the first pixel sub-circuit and the second pixel sub-circuit under the control of the reset signal input by the reset signal end;
  • the data voltage writing module is connected to the data voltage and the gate signal terminal for writing the first data voltage to the first pixel sub-circuit under the control of the signal input by the gate signal terminal, and then to the second pixel sub-circuit Writing a second data voltage; the first pixel sub-circuit compensates the driving module of the first pixel, and the second pixel sub-circuit compensates the driving module of the second pixel, wherein the AMOLED pixel circuit can reduce the size of the pixel circuit, and further Reduce the

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Abstract

一种像素电路及显示器，用以减小像素电路尺寸，进而减小像素间距，提高单位面积内的像素数目，提升画面显示品质。像素电路包括：第一像素子电路和第二像素子电路，以及与第一像素子电路和第二像素子电路连接的初始化模块（31）和数据电压写入模块（32），初始化模块（31）连接复位信号端和低电位端，用于在复位信号端输入的复位信号控制下对第一像素子电路和第二像素子电路进行初始化；数据电压写入模块（32）连接数据电压和栅极信号端，用于在栅极信号端输入信号控制下先对第一像素子电路写入第一数据电压，并对第一像素子电路的驱动模块（331）进行补偿，然后对第二像素子电路写入第二数据电压，并对第二像素子电路的驱动模块（332）进行补偿。

Description

像素电路 示器 技术领域
本发明涉及显示器技术领域， 尤其涉及一种像素电路及显示器。 背景技术
目前高端中小尺寸有源矩阵有机发光二极管（ Active Matrix Organic Light Emitting Diode , AMOLED )产品阵列基板多使用低温多晶石圭（ Low Temperature Poly-Silicon, LTPS )工艺技术， 然而由于 LTPS工艺的波动性会导致薄膜晶 体管 （ Thin Film Transistor, TFT ) 器件的阈值电压漂移， 从而使得驱动有机 发光二极管 （Organic Light Emitting Diode, OLED ) 器件的电流不稳定， 进 而导致画面显示品质降低。 现有技术中的像素补偿电路为 6T1C 电路（由 6 个薄膜晶体管和 1个电容组成的电路）， 电路图如图 1所示， 图中， VDD为 高电压电平信号， VSS为低电压电平信号， Data为数据信号， Gate为栅极控 制信号， Reset为初始化控制信号， Vinit为初始化电压电平信号， EM为控 制 OLED发光的信号， 由 OLED面板的发光电路提供此电压。 然而， 需要将 6个薄膜晶体管和 1个电容布置在一个像素中是不容易的， 需要 TFT器件做 得非常小， 所以 TFT器件的性能要求也相对较高， 另一方面， 在一个像素中 布置 6个薄膜晶体管和 1个电容也会导致像素间距（ Pixel Pitch )无法进一步 降低。
如图 2所示， 现有技术中的 6T1C电路在水平方向上在 2个像素里所需 要布置的元器件数目为： 2条数据信号线（ Data vl和 Data v2 )、 12个 TFT、 2个电容、 1条栅极控制信号 Gate线、 1条发光控制信号 EM线、 1条高电压 电平信号 VDD线、 1条初始化电压电平信号 Vinit线、 以及 1条初始化控制 信号 Reset线， 图 2中有两个有机发光二极管 OLED1和 OLED2, 其阴极均 与低电压电平信号 VSS线相连， 图 2为水平排列的 2个像素的电路原理图。 水平方向的像素布置或垂直方向的像素布置是相似的， 因此类似地， 在垂直 方向上在 2个像素里所需要布置的元器件数目为： 1条数据信号线、 12个 TFT、 2个电容、 2条栅极控制信号线、 1条发光控制信号线、 1条高电压电平信号 线、 1条初始化电压电平信号线。
综上所述， 现有技术中在 2个像素中需要布置 12个 TFT和 2个电容。 发明内容
本发明实施例提供了一种像素电路， 用以减小像素电路尺寸， 进而减小 像素间距， 提高单位面积内所拥有的像素数目， 提升画面显示品质。 本发明 还提供了一种显示器。
根据本发明一实施例， 提供了一种像素电路， 包括： 第一像素子电路和 第二像素子电路， 以及与所述第一像素子电路和第二像素子电路连接的初始 化模块和数据电压写入模块，
所述初始化模块连接复位信号端和低电位端， 用于在复位信号端输入的 复位信号的控制下对第一像素子电路和第二像素子电路进行初始化；
所述数据电压写入模块连接数据电压端和栅极信号端， 用于在栅极信号 端输入的信号的控制下先对第一像素子电路写入第一数据电压， 并对所述第 一像素子电路的驱动模块进行补偿， 然后对第二像素子电路写入第二数据电 压， 并对第二像素子电路的驱动模块进行补偿。
由本发明实施例提供的所述像素电路， 包括： 第一像素子电路和第二像 素子电路， 以及与所述第一像素子电路和第二像素子电路连接的初始化模块 和数据电压写入模块， 所述由第一像素子电路、 第二像素子电路以及初始化 模块和数据电压写入模块组成的像素电路能够减小像素电路尺寸， 进而减小 像素间距， 提高单位面积内所拥有的像素数目， 提升画面显示品质。
较佳地， 所述第一像素子电路包括第一驱动模块、 第一发光模块、 第一 阈值补偿模块和第一发光控制模块，
所述第一阈值补偿模块连接初始化模块， 并且在初始化模块输出的初始 化信号的控制下进行初始化；
所述第一阈值补偿模块连接第一驱动模块， 用于对第一驱动模块进行阈 值电压补偿；
所述第一发光模块连接第一发光控制模块， 用于在第一驱动模块和第一 发光控制模块作用下进行发光显示。
这样， 由第一驱动模块、 第一发光模块、 第一阈值补偿模块和第一发光 控制模块组成的第一像素子电路在像素电路的设计中简单便于实施。
较佳地， 所述第一阈值补偿模块包括第一存储电容、 第二晶体管和第四 晶体管； 所述第一驱动模块包括第五晶体管； 所述第一发光控制模块包括第 七晶体管和第九晶体管； 所述第一发光模块包括第一发光二极管。 这样， 由存储电容、 晶体管和发光二极管组成的第一像素子电路在像素 电路的设计中筒单便于实施。
较佳地， 所述第一存储电容的一端与高电压电平信号线相连， 另一端与 第二晶体管的源极相连；
所述第二晶体管的栅极与第一控制信号线相连， 所述第二晶体管的漏极 与所述初始化模块相连并与所述第四晶体管的源极相连；
所述第四晶体管的栅极与栅极信号端相连， 所述第四晶体管的源极与所 述初始化模块相连；
所述第五晶体管的栅极与所述初始化模块相连并与所述第四晶体管的源 极相连， 所述第五晶体管的漏极与所述第四晶体管的漏极相连， 所述第五晶 体管的源极与所述数据电压写入模块相连；
所述第七晶体管的栅极与发光控制信号线连接， 所述第七晶体管的源极 与高电压电平信号线相连，所述第七晶体管的漏极与第五晶体管的源极相连； 所述第九晶体管的栅极与发光控制信号线连接， 所述第九晶体管的源极 与所述第五晶体管的漏极相连， 所述第九晶体管的漏极与第一发光二极管相 连；
所述第一发光二极管的阳极与第九晶体管的漏极相连， 所述第一发光二 极管的阴极与低电压电平信号线相连。
这样， 所述存储电容、 晶体管及发光二极管的连接关系在像素电路的设 计中筒单便于实施。
较佳地， 所述第二像素子电路包括第二驱动模块、 第二发光模块、 第二 阈值补偿模块和第二发光控制模块，
所述第二阈值补偿模块连接初始化模块， 并且在初始化模块输出的初始 化信号的控制下进行初始化；
所述第二阈值补偿模块连接第二驱动模块， 用于对第二驱动模块进行阈 值电压补偿；
所述第二发光模块连接第二发光控制模块， 用于在第二驱动模块和第二 发光控制模块的作用下进行发光显示。
这样， 由第二驱动模块、 第二发光模块、 第二阈值补偿模块和第二发光 控制模块组成的第二像素子电路在像素电路的设计中筒单便于实施。 较佳地， 所述第二阈值补偿模块包括第二存储电容和第八晶体管； 所述 第二驱动模块包括第六晶体管； 所述第二发光控制模块包括第十晶体管； 所 述第二发光模块包括第二发光二极管。
这样， 由存储电容、 晶体管和发光二极管组成的第二像素子电路在像素 电路的设计中筒单便于实施。
较佳地， 所述第二存储电容的一端与高电压电平信号线相连， 另一端与 第八晶体管的源极相连；
所述第八晶体管的栅极与第二控制信号线相连， 所述第八晶体管的漏极 与所述初始化模块相连并与所述第四晶体管的源极相连；
所述第六晶体管的栅极与所述第八晶体管的源极相连， 所述第六晶体管 的源极与所述数据电压写入模块相连并且与所述第七晶体管的漏极相连； 所述第十晶体管的栅极与发光控制信号线连接， 所述第十晶体管的源极 与所述第六晶体管的漏极相连， 所述第十晶体管的漏极与第二发光二极管相 连；
所述第二发光二极管的阳极与第十晶体管的漏极相连， 所述第二发光二 极管的阴极与低电压电平信号线相连。
这样， 所述存储电容、 晶体管及发光二极管的连接关系在像素电路的设 计中筒单便于实施。
较佳地， 所述初始化模块包括第三晶体管， 所述第三晶体管的栅极与复 位信号线相连， 所述第三晶体管的源极与第一像素子电路的第一阈值补偿模 块中的第四晶体管的源极和第二像素子电路的第二阈值补偿模块中的第八晶 体管的漏极相连， 所述第三晶体管的漏极与低电压电平信号线相连。
这样， 所述初始化模块包括第三晶体管， 第三晶体管作为像素电路中的 初始化模块的开关器件， 在电路设计中方便筒单便于实施。
较佳地， 所述数据电压写入模块包括第一晶体管， 其中， 所述第一晶体 管的栅极与栅极信号控制线相连，所述第一晶体管的源极与数据信号线相连， 所述第一晶体管的漏极与第一像素子电路的第一驱动模块中的第五晶体管的 源极和第二像素子电路的第二驱动模块中的第六晶体管的源极相连。
这样， 所述数据电压写入模块包括第一晶体管， 第一晶体管作为像素电 路中的数据电压写入模块的开关器件， 在电路设计中方便筒单便于实施。
较佳地， 所述数据电压写入模块中输入的数据电压包括第一数据电压和 第二数据电压， 其中， 第一数据电压用于驱动第一阈值补偿模块对第一驱动 模块进行阈值电压补偿， 第二数据电压用于驱动第二阈值补偿模块对第二驱 动模块进行阈值电压补偿。
这样， 由于数据信号为阶梯形的时序信号， 可以实现由一条数据信号线 输入两个不同的电压值。
较佳地， 所述第一发光二极管和第二发光二极管均为有机发光二极管。 这样， 用有机发光二极管作为像素电路中的第一发光模块和第二发光模 块中的发光二极管， 在电路设计中方便筒单。
较佳地， 所述晶体管均为 P型薄膜晶体管。
这样， 用 P型薄膜晶体管作为像素电路中的薄膜晶体管， 在电路设计中 方便筒单便于实施。
本发明实施例提供的显示器， 包括多个像素、 多条数据信号线以及多条 栅极控制信号线， 其中， 每两个像素组成一像素单元， 还包括与各像素单元 连接的上面所述的像素电路。
这样， 由于所述显示器包括与各像素单元连接的上面所述的像素电路， 该显示器具有所述像素电路的优点， 能够很好的提升画面显示品质。
较佳地， 所述每一像素单元中的两个像素共用一条数据信号线。
这样， 每一像素单元中的两个像素共用一条数据信号线， 故两个像素可 以省略一条数据信号线， 数据信号线的排列方法筒单易行。
较佳地， 所述每一像素单元中的两个像素共用一条栅极控制信号线。 这样， 每一像素单元中的两个像素共用一条栅极控制信号线， 故两个像 素可以省略一条栅极控制信号线， 栅极控制信号线的排列方法筒单易行。 附图说明
图 1 为现有技术中的单个像素中的 6T1C AMOLED像素补偿电路示意 图；
图 2为现有技术中的 2个像素中的 12T2C AMOLED像素补偿电路示意 图；
图 3为本发明实施例提供的 10T2C AMOLED像素电路示意图； 图 4为本发明实施例提供的 10T2C AMOLED像素电路工作的时序图； 图 5为本发明实施例提供的 10T2C AMOLED像素电路在初始化工作阶 段的筒化电路图；
图 6为本发明实施例提供的 10T2C AMOLED像素电路在第一阈值补偿 阶段的筒化电路图；
图 7为本发明实施例提供的 10T2C AMOLED像素电路在第二阈值补偿 阶段的筒化电路图；
图 8为本发明实施例提供的 10T2C AMOLED像素电路在发光阶段的筒 化电路图；
图 9为现有技术中的单个像素的排列示意图；
图 10 为本发明实施例提供的由水平方向上两个像素组成的像素单元的 一种排列示意图；
图 11 为本发明实施例提供的由水平方向上两个像素组成的像素单元的 另一种排列示意图；
图 12 为本发明实施例提供的由垂直方向上两个像素组成的像素单元的 一种排列示意图；
图 13 为本发明实施例提供的由垂直方向上两个像素组成的像素单元的 另一种排列示意图。 具体实施方式
本发明实施例提供了一种像素电路及显示器， 用以减小像素电路尺寸， 进而减小像素间距， 提高单位面积内所拥有的像素数目， 提升画面显示品质。
其中， 本发明实施例提供的像素电路为有源矩阵发光二极管像素电路， 由于有源矩阵发光二极管像素电路能够起到对像素的驱动模块进行补偿的作 用， 故本发明中有源矩阵发光二极管像素电路也可称为有源矩阵发光二极管 像素补偿电路。
下面给出本发明实施例提供的技术方案的详细介绍。
如图 3所示， 本发明实施例提供的一种有源矩阵发光二极管像素电路， 包括： 第一像素子电路和第二像素子电路， 以及与所述第一像素子电路和第 二像素子电路连接的初始化模块 31和数据电压写入模块 32,
所述初始化模块 31连接复位信号端（对应 AMOLED像素电路的初始化 控制信号 Reset )和低电位端（对应 AMOLED像素电路的初始化电压电平信 号 Vinit ), 用于在复位信号端输入的复位信号的控制下对第一像素子电路和 第二像素子电路进行初始化；
所述数据电压写入模块 32连接数据电压端（对应 AMOLED像素电路的 数据信号 Data )和栅极信号端 （对应 AMOLED像素电路的栅极控制信号 Gate ), 用于在栅极信号端输入的信号的控制下先对第一像素子电路写入第一 数据电压， 并对所述第一像素子电路的驱动模块进行补偿， 然后对第二像素 子电路写入第二数据电压 , 并对第二像素子电路的驱动模块进行补偿。
在图 3所示的电路中， 为了区别导线间的交叉相连和不相连， 将相连的 交叉点以实心圓点表示， 不相连的交叉点以空心圓点表示。
较佳地， 所述第一像素子电路包括： 第一驱动模块 331、 第一发光模块 341、 第一阈值补偿模块 351和第一发光控制模块 361 ,
所述第一阈值补偿模块 351连接初始化模块 31 , 并且在初始化模块 31 输出的初始化信号的控制下进行初始化；
所述第一阈值补偿模块 351连接第一驱动模块 331 , 用于对第一驱动模 块 331进行阈值电压补偿；
所述第一发光模块 341连接第一发光控制模块 361 , 用于在第一驱动模 块 331和第一发光控制模块 361的作用下进行发光显示。
较佳地， 所述第一阈值补偿模块 351包括第一存储电容 Cl、 第二晶体管 T2和第四晶体管 T4; 所述第一驱动模块 331包括第五晶体管 T5; 所述第一 发光控制模块 361包括第七晶体管 T7和第九晶体管 T9; 所述第一发光模块 341包括第一发光二极管 0LED1。
较佳地， 所述第一存储电容 C1 的一端与高电压电平信号线（对应高电 压电平信号 VDD )相连， 另一端与第二晶体管 T2的源极相连；
所述第二晶体管 T2的栅极与第一控制信号线（对应 AMOLED像素电路 的第一控制信号 SW1 )相连， 所述第二晶体管 T2的漏极与所述初始化模块 31相连；
所述第四晶体管 T4的栅极与栅极信号端（对应 AMOLED像素电路栅极 控制信号 Gate )相连，所述第四晶体管 T4的源极与所述初始化模块 31相连； 所述第五晶体管 T5的栅极与所述初始化模块 31相连， 所述第五晶体管 T5的漏极与所述第四晶体管 T4的漏极相连，所述第五晶体管 T5的源极与所 述数据电压写入模块 32相连；
所述第七晶体管 T7的栅极与发光控制信号线（对应 AMOLED像素电路 的发光控制信号 EM )连接， 所述第七晶体管 T7的源极与高电压电平信号线 (对应高电压电平信号 VDD )相连， 所述第七晶体管 T7的漏极与第五晶体 管 T5的源极相连；
所述第九晶体管 T9的栅极与发光控制信号线（对应 AMOLED像素电路 的发光控制信号 EM )连接， 所述第九晶体管 T9 的源极与所述第五晶体管 T5的漏极相连， 所述第九晶体管 T9的漏极与第一发光二极管 OLED1相连； 所述第一发光二极管 OLED1的阳极与第九晶体管 T9的漏极相连，所述 第一发光二极管 OLED1 的阴极与低电压电平信号线（对应低电压电平信号 VSS )相连。
较佳地，所述第二像素子电路包括第二驱动模块 332、第二发光模块 342、 第二阈值补偿模块 352和第二发光控制模块 362 ,
所述第二阈值补偿模块 352连接初始化模块 31 , 并且在初始化模块 31 输出的初始化信号的控制下进行初始化；
所述第二阈值补偿模块 352连接第二驱动模块 332, 用于对第二驱动模 块 332进行阈值电压补偿；
所述第二发光模块 342连接第二发光控制模块 362, 用于在第二驱动模 块 332和第二发光控制模块 362的作用下进行发光显示。
较佳地， 所述第二阈值补偿模块 352包括第二存储电容 C2和第八晶体 管 T8; 所述第二驱动模块 332 包括第六晶体管 T6; 所述第二发光控制模块 362 包括第十晶体管 T10 ; 所述第二发光模块 342 包括第二发光二极管 OLED2。
较佳地， 所述第二存储电容 C2 的一端与高电压电平信号线（对应高电 压电平信号 VDD )相连， 另一端与第八晶体管 T8的源极相连；
所述第八晶体管 T8的栅极与第二控制信号线（对应 AMOLED像素电路 的第二控制信号 SW2 )相连， 所述第八晶体管 T8的漏极与所述初始化模块 31相连；
所述第六晶体管 T6的栅极与所述第八晶体管 T8的源极相连， 所述第六 晶体管 T6的源极与所述数据电压写入模块 32相连并与所述第七晶体管 T7 的漏极相连， 所述第六晶体管 T6的漏极与第二发光二极管 OLED2相连； 所述第十晶体管 T10的栅极与发光控制信号线（对应 AMOLED像素电 路的发光控制信号 EM )连接， 所述第十晶体管 T10的源极与所述第六晶体 管 T6的漏极相连， 所述第十晶体管 T10的漏极与第二发光二极管 OLED2相 连；
所述第二发光二极管 OLED2的阳极与第十晶体管 T10的漏极相连， 所 述第二发光二极管 OLED2的阴极与低电压电平信号线（对应低电压电平信号 VSS )相连。
其中，发光控制模块 361和 362既可以同时控制 OLED1和 OLED2的发 光， 也可以分开控制 OLED1和 OLED2的发光。
较佳地， 所述初始化模块 31 包括第三晶体管 Τ3 , 所述第三晶体管 Τ3 的栅极与复位信号线（对应 AMOLED像素电路的初始化控制信号 Reset )相 连， 所述第三晶体管 T3 的源极与第一像素子电路的第一阈值补偿模块 351 和第二像素子电路的第二阈值补偿模块 352相连，所述第三晶体管 T3的漏极 与低电压电平信号线（对应 AMOLED像素电路的初始化电压电平信号 Vinit ) 相连。
较佳地， 所述数据电压写入模块 32包括第一晶体管 T1 , 所述第一晶体 管 T1 的栅极与栅极信号控制线 （对应 AMOLED像素电路的栅极控制信号 Gate )相连， 所述第一晶体管 T1的源极与数据信号线（对应 AMOLED像素 电路的数据信号 Data )相连， 所述第一晶体管 T1 的漏极与第一像素子电路 的第一驱动模块 331和第二像素子电路的第二驱动模块 332相连。
较佳地，所述数据电压写入模块 32中输入的数据电压包括第一数据电压 和第二数据电压， 其中， 第一数据电压用于驱动第一阈值补偿模块 351对第 一驱动模块 331进行阈值电压补偿， 第二数据电压用于驱动第二阈值补偿模 块 352对第二驱动模块 332进行阈值电压补偿。
较佳地，所述第一发光二极管 OLED1和第二发光二极管 OLED2均为有 机发光二极管。
较佳地， 所述晶体管 Tl、 Τ2、 Τ3、 Τ4、 Τ5、 Τ6、 Τ7、 Τ8、 Τ9 和 T10 均为 Ρ型薄膜晶体管。
下面结合图 3-图 8, 具体说明本发明实施例提供的 AMOLED像素电路 的工作原理。
如图 4所示， 在 I阶段， 栅极控制信号 Gate和发光控制信号 EM为高电 平； 初始化控制信号 Reset、 第一控制信号 SW1和第二控制信号 SW2为低电 平， 此时， 图 3中的第三晶体管 T3、 第二晶体管 Τ2和第八晶体管 Τ8导通， 第一晶体管 Tl、 第四晶体管 Τ4、 第七晶体管 Τ7、 第九晶体管 Τ9和第十晶体 管 T10截止， 因此， 图 3的筒化电路图如图 5所示。 由于存储电容 C1和 C2 分别存储上一帧画面输入的数据信号 Data, 此时 2个电容全部连接在具有低 电位的初始化电压电平信号 Vinit上， 存储电容 C1和 C2均对初始化电压电 平信号 Vinit放电， 放电到初始化电压 Vinit。
如图 4所示， 在 II阶段， 初始化控制信号 Reset、 第二控制信号 SW2和 发光控制信号 EM为高电平； 栅极控制信号 Gate和第一控制信号 SW1为低 电平，此时，图 3中的第一晶体管 Tl、第二晶体管 Τ2和第四晶体管 Τ4导通； 第三晶体管 Τ3、 第八晶体管 Τ8、 第七晶体管 Τ7、 第九晶体管 Τ9和第十晶体 管 T10截止， 因此， 图 3的筒化电路图如图 6所示。 数据电平信号 Data输入 第一数据电压值 VI , 此时由于第四晶体管 T4 的导通， 使得第五晶体管 T5 相当于二极管， 第一节点 P1的电压变为： V=Vl-Vth ( T5 ), 其中， Vth ( T5 ) 为第五晶体管 T5的阈值电压， 并将电压值 V存储在存储电容 C1中。
如图 4所示， 在 III阶段， 初始化控制信号 Reset、 第一控制信号 SW1 和发光控制信号 EM为高电平； 栅极控制信号 Gate和第二控制信号 SW2为 低电平， 此时， 图 3中的第一晶体管 Tl、 第四晶体管 Τ4和第八晶体管 Τ8导 通； 第二晶体管 Τ2、 第三晶体管 Τ3、 第七晶体管 Τ7、 第九晶体管 Τ9和第十 晶体管 T10关闭， 因此， 图 3的筒化电路图如图 7所示。 数据电平信号 Data 输入第二数据电压值 V2, 此时由于第四晶体管 T4的导通， 使得第五晶体管 T5相当于二极管， 第一节点 P1 的电压变为： V^VS-Vth ( T5 ), 其中， Vth ( T5 )为第五晶体管 T5的阈值电压， 设计中， 第五晶体管 T5和第六晶体管 T6的参数完全相同，且放置在接近位置，可以近似认为 Vth ( T5 ) =Vth ( T6 ), Vth ( T6 ) 为第六晶体管 Τ6的阈值电压， 则电压值 V VS-Vth ( T6 ), 并将 电压值 存储在存储电容 C2中。
如图 4所示， 在 IV阶段即发光阶段， 初始化控制信号 Reset、 栅极控制 信号 Gate和第二控制信号 SW2为高电平； 第一控制信号 SW1和发光控制信 号 EM为低电平， 此时， 图 3中的第二晶体管 T2、 第七晶体管 Τ7、 第九晶 体管 Τ9和第十晶体管 T10导通， 第一晶体管 Tl、 第三晶体管 Τ3、 第四晶体 管 Τ4和第八晶体管 Τ8截止， 因此， 图 3的筒化电路图如图 8所示。 第五晶 体管 Τ5和第六晶体管 Τ6为 OLED的驱动晶体管，其对电流的控制方式如下： 第五晶体管 Τ5和第六晶体管 Τ6的源极均与高电压电平信号 VDD相连， 流经第一发光二极管 0LED1的电流为：
Idl= *[VDD-V-Vth(T5)]2= *[VDD- (Vl-Vth (T5) )-Vth (T5)f = *(VDD-V1)2 其中， k为预设常数， 流经第二发光二极管 OLED2的电流为：
Id2= *[vDD-V'-Vth(T6)]2 = *[VDD. ( V2-Vth(T6)-Vth(T6)]2 = *(VDD-V2)2 从上面的方程可以看出，流经第一发光二极管 OLED 1的电流 Id 1和流经 第二发光二极管 OLED2的电流 Id2与第五晶体管 T5的阈值电压 Vth ( T5 ) 和第六晶体管 T6的阈值电压 Vth (T6)无关， 因此可以起到补偿作用。
综上所述，本发明实施例提供的 AMOLED像素电路包括 10个薄膜晶体 管和 2个电容， 即为 10T2CAMOLED像素电路。
本发明实施例提供的一种显示器， 包括多个像素、 多条数据信号线以及 多条栅极控制信号线， 其中， 每两个像素组成一像素单元， 还包括与各像素 单元连接的本发明实施例提供的 10T2C AMOLED像素电路。
下面具体介绍包含 2个像素的像素单元的排列方式：
现有技术中的单个像素的像素排列方式如图 9所示， 单个像素中的补偿 电路为现有技术中的 6T1C AMOLED像素补偿电路， 如果将两个像素放到一 起组成一个像素单元， 则现有技术中的像素单元的补偿电路为现有技术中的 12T2C AMOLED像素补偿电路。
本发明实施例提供的包含 2个像素的像素单元的排列方式如图 10-13所 示， 其中， 如图 10和 11所示， 任一像素单元中水平方向排列的两个像素共 用一条数据信号线 Data (m), 如图 12和 13所示， 任一像素单元中垂直方向 排列的两个像素共用一条栅极控制信号线 Gate (N), 其中， 任一像素单元中 水平方向排列的两个像素为水平方向上的任意两个像素， 如： 像素（Pixel) 1 与 Pixel 2、 或者 Pixel 2与 Pixel 3, 任一像素单元中垂直方向排列的两个像素 为垂直方向上的任意两个像素。
如图 10和 11所示， 所述任一像素单元中水平方向排列的两个像素共用 一条数据信号线 Data (m) 包括： 数据信号线 Data (m)位于两个水平方向 排列的 Pixel 1和 Pixel 2之间 （如图 11所示；)， 或数据信号线 Data ( m )位于 两个水平方向排列的 Pixel 1和 Pixel 2中的 Pixel 1的外侧 (如图 10所示 ), 当然，本发明实施例中的数据信号线 Data(m)不限于位于 Pixel 1的外侧（内 侧指任一像素单元中水平方向排列的两个像素彼此靠近的一侧， 外侧指这两 个像素彼此远离的一侧），可以位于两个水平方向排列的像素中的任一像素的 外侧 (例如， pixel 1的左侧、 或者 pixel 2的右侧）。
如图 12和 13所示， 所述任一像素单元中垂直方向排列的两个像素共用 一条栅极控制信号线 Gate ( N ) 包括： 栅极控制信号线 Gate ( N )位于垂直 方向排列的任意两个像素组成的像素单元中的这两个像素之间 （如图 12 所 示）， 或栅极控制信号线 Gate ( N )位于垂直方向排列的任意两个像素组成的 像素单元中的任一像素的外侧 （如图 13所示）。
综上所述， 本发明实施例提供的技术方案中， 所述 AMOLED像素电路 包括： 第一像素子电路和第二像素子电路， 以及与所述第一像素子电路和第 二像素子电路连接的初始化模块和数据电压写入模块， 所述初始化模块连接 复位信号端和低电位端， 用于在复位信号端输入的复位信号控制下对第一像 素子电路和第二像素子电路进行初始化； 所述数据电压写入模块连接数据电 压和栅极信号端， 用于在栅极信号端输入的信号的控制下先对第一像素子电 路写入第一数据电压， 然后对第二像素子电路写入第二数据电压； 第一像素 子电路对第一像素的驱动模块进行补偿， 第二像素子电路对第二像素的驱动 模块进行补偿， 所述 AMOLED像素电路能够减小像素电路尺寸， 进而减小 像素间距， 提高单位面积内所拥有的像素数目， 提升画面显示品质。 发明的精神和范围。 这样， 倘若本发明的这些修改和变型属于本发明权利要 求及其等同技术的范围之内， 则本发明也意图包含这些改动和变型在内。

Claims

权 利 要 求 书
1、 一种像素电路， 包括： 第一像素子电路和第二像素子电路， 以及与所 述第一像素子电路和第二像素子电路连接的初始化模块和数据电压写入模 块，
所述初始化模块连接复位信号端和低电位端， 用于在复位信号端输入的 复位信号控制下对第一像素子电路和第二像素子电路进行初始化；
所述数据电压写入模块连接数据电压和栅极信号端， 用于在栅极信号端 输入的信号控制下先对第一像素子电路写入第一数据电压， 并对所述第一像 素子电路的驱动模块进行补偿， 然后对第二像素子电路写入第二数据电压， 并对第二像素子电路的驱动模块进行补偿。
2、根据权利要求 1所述的电路， 其中， 所述第一像素子电路包括第一驱 动模块、 第一发光模块、 第一阈值补偿模块和第一发光控制模块，
所述第一阈值补偿模块连接初始化模块， 并且在初始化模块输出的初始 化信号的控制下进行初始化；
所述第一阈值补偿模块连接第一驱动模块， 用于对第一驱动模块进行阈 值电压补偿；
所述第一发光模块连接第一发光控制模块， 用于在第一驱动模块和第一 发光控制模块的作用下进行发光显示。
3、根据权利要求 2所述的电路， 其中， 所述第一阈值补偿模块包括第一 存储电容、 第二晶体管和第四晶体管； 所述第一驱动模块包括第五晶体管； 所述第一发光控制模块包括第七晶体管和第九晶体管； 所述第一发光模块包 括第一发光二极管。
4、根据权利要求 3所述的电路， 其中， 所述第一存储电容的一端与高电 压电平信号线相连， 另一端与第二晶体管的源极相连；
所述第二晶体管的栅极与第一控制信号线相连， 所述第二晶体管的漏极 与所述初始化模块相连并与所述第四晶体管的源极相连；
所述第四晶体管的栅极与栅极信号端相连， 所述第四晶体管的源极与所 述初始化模块相连；
所述第五晶体管的栅极与所述初始化模块相连并与所述第四晶体管的源 极相连， 所述第五晶体管的漏极与所述第四晶体管的漏极相连， 所述第五晶 体管的源极与所述数据电压写入模块相连；
所述第七晶体管的栅极与发光控制信号线连接， 所述第七晶体管的源极 与高电压电平信号线相连，所述第七晶体管的漏极与第五晶体管的源极相连； 所述第九晶体管的栅极与发光控制信号线连接， 所述第九晶体管的源极 与所述第五晶体管的漏极相连， 所述第九晶体管的漏极与第一发光二极管相 连；
所述第一发光二极管的阳极与第九晶体管的漏极相连， 所述第一发光二 极管的阴极与低电压电平信号线相连。
5、根据权利要求 4所述的电路， 其中， 所述第二像素子电路包括第二驱 动模块、 第二发光模块、 第二阈值补偿模块和第二发光控制模块，
所述第二阈值补偿模块连接初始化模块， 并且在初始化模块输出的初始 化信号的控制下进行初始化；
所述第二阈值补偿模块连接第二驱动模块， 用于对第二驱动模块进行阈 值电压补偿；
所述第二发光模块连接第二发光控制模块， 用于在第二驱动模块和第二 发光控制模块的作用下进行发光显示。
6、根据权利要求 5所述的电路， 其中， 所述第二阈值补偿模块包括第二 存储电容和第八晶体管； 所述第二驱动模块包括第六晶体管； 所述第二发光 控制模块包括第十晶体管； 所述第二发光模块包括第二发光二极管。
7、根据权利要求 6所述的电路， 其中， 所述第二存储电容的一端与高电 压电平信号线相连， 另一端与第八晶体管的源极相连；
所述第八晶体管的栅极与第二控制信号线相连， 所述第八晶体管的漏极 与所述初始化模块相连并与所述第四晶体管的源极相连；
所述第六晶体管的栅极与所述第八晶体管的源极相连， 所述第六晶体管 的源极与所述数据电压写入模块相连并与所述第七晶体管的漏极相连， 所述 第六晶体管的漏极与第二发光二极管相连；
所述第十晶体管的栅极与发光控制信号线连接， 所述第十晶体管的源极 与所述第六晶体管的漏极相连， 所述第十晶体管的漏极与第二发光二极管相 连；
所述第二发光二极管的阳极与第十晶体管的漏极相连， 所述第二发光二 极管的阴极与低电压电平信号线相连。
8、根据权利要求 7所述的电路，其中，所述初始化模块包括第三晶体管， 所述第三晶体管的栅极与复位信号线相连， 所述第三晶体管的源极与第一像 素子电路的第一阈值补偿模块中的第四晶体管的源极和第二像素子电路的第 二阈值补偿模块中的第八晶体管的漏极相连， 所述第三晶体管的漏极与低电 压电平信号线相连。
9、根据权利要求 7所述的电路， 其中， 所述数据电压写入模块包括第一 晶体管， 所述第一晶体管的栅极与栅极信号控制线相连， 所述第一晶体管的 源极与数据信号线相连， 所述第一晶体管的漏极与第一像素子电路的第一驱 动模块中的第五晶体管的源极和第二像素子电路的第二驱动模块中的第六晶 体管的源极相连。
10、 根据权利要求 9所述的电路， 其中， 所述数据电压写入模块中输入 的数据电压包括第一数据电压和第二数据电压， 其中， 第一数据电压用于驱 动第一阈值补偿模块对第一驱动模块进行阈值电压补偿， 第二数据电压用于 驱动第二阈值补偿模块对第二驱动模块进行阈值电压补偿。
11、 根据权利要求 7所述的电路， 其中， 所述第一发光二极管和第二发 光二极管均为有机发光二极管。
12、 根据权利要求 3-11任一权项所述的电路， 其中， 所述晶体管均为 P 型薄膜晶体管。
13、 一种显示器， 包括多个像素、 多条数据信号线以及多条栅极控制信 号线， 其中， 每两个像素组成一像素单元， 还包括与各像素单元连接的权利 要求 1-12任一权项所述的像素电路。
14、根据权利要求 13所述的显示器， 其中， 每两个沿水平方向排列的两 个像素组成一像素单元， 并且所述每一像素单元中的两个像素共用一条数据 信号线。
15、根据权利要求 13所述的显示器， 其中， 每两个沿垂直方向排列的两 个像素组成一像素单元， 并且所述每一像素单元中的两个像素共用一条栅极 控制信号线。
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