WO2015014082A1 - 阵列基板及其制作方法和显示装置 - Google Patents

阵列基板及其制作方法和显示装置 Download PDF

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WO2015014082A1
WO2015014082A1 PCT/CN2013/089744 CN2013089744W WO2015014082A1 WO 2015014082 A1 WO2015014082 A1 WO 2015014082A1 CN 2013089744 W CN2013089744 W CN 2013089744W WO 2015014082 A1 WO2015014082 A1 WO 2015014082A1
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Prior art keywords
metal
gate
electrode
layer
pattern
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French (fr)
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闫梁臣
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/691—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator comprising metallic compounds, e.g. metal oxides or metal silicates 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0316—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral bottom-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • H10D30/6739—Conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01332—Making the insulator
    • H10D64/01336—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid
    • H10D64/01338—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid with a treatment, e.g. annealing, after the formation of the conductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/431—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having different compositions, shapes, layouts or thicknesses of gate insulators in different TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an array substrate, a manufacturing method thereof, and a display device.
  • an array substrate a manufacturing method thereof
  • a display device a display device.
  • TFT-LCD Thin Film Transistor-Liquid Crystal Display
  • FIG. 1 is a schematic structural view of a conventional TFT array substrate.
  • the conventional TFT array substrate generally includes a substrate substrate 1, a gate electrode, and a gate line 11 in this order.
  • Cu is generally used to prepare the gate electrode and the gate line, but after the gate electrode and the gate line are formed by using Cu, Cu atoms in the gate electrode and the gate line are easily diffused, and The denseness of the insulating layer is not very good.
  • the technical problem to be solved by the present invention is to provide an array substrate capable of avoiding diffusion of metal atoms in a gate electrode and a gate line in an array substrate, a manufacturing method thereof, and a display device.
  • the technical solution provided by the embodiment of the present invention is as follows:
  • an array substrate is provided, and a gate electrode and a gate line of the array substrate are coated with a metal oxide film.
  • the metal oxide film is formed by reacting the second metal in the gate metal layer including the first metal and the second metal with oxygen.
  • the gate electrode and the gate line which are externally coated with the metal oxide film are the gate electrode in a gas containing oxygen after the pattern of the gate electrode and the gate line is formed by the gate metal layer It is obtained by annealing in a gas containing oxygen in a pattern of gate lines.
  • the first metal is Cu
  • the second metal is at least one of Mg, Cr, Hf, Ca, and Al. Further, in the above solution, the second metal accounts for 15% by weight of the gate metal layer.
  • the array substrate specifically includes: a gate electrode and a gate line coated with a metal oxide film on the substrate, and a metal oxide coated on the outside a gate electrode of the thin film and a gate insulating layer on the gate line; an active layer on the gate insulating layer;
  • the pixel electrode being electrically connected to the drain electrode through the via hole.
  • Embodiments of the present invention also provide a display device including the array substrate as described above.
  • the embodiment of the invention further provides a method for fabricating an array substrate, comprising:
  • the second metal in the gate metal layer including the first metal and the second metal is segregated in the first metal to react with external oxygen to form the metal oxide outside the gate electrode and the gate line film.
  • the pattern of the gate electrode and the gate line is formed by using the gate metal layer, the pattern of the gate electrode and the gate line is annealed in a gas containing oxygen, so that the second metal is in the Segregation occurs in the first metal to react with external oxygen to form the metal oxide thin film outside the gate electrode and the gate line.
  • the first metal is Cu
  • the second metal is at least one of Mg, Cr, Hf, Ca, and Al.
  • the annealing the pattern of the gate electrode and the gate line in the gas containing oxygen includes:
  • the pattern of the gate electrode and the gate line is annealed at a temperature of 200 to 300 ⁇ for 0.5 to 2 hours.
  • the manufacturing method specifically includes:
  • the pattern of the passivation layer including a via corresponding to the drain electrode;
  • a pattern of pixel electrodes is formed on the base substrate on which the passivation layer is formed, and the pixel electrodes are electrically connected to the drain electrodes through the via holes.
  • the gate electrode and the gate line of the array substrate are coated with a metal oxide film, which can effectively block metal atoms in the gate electrode and the gate line from diffusing to other regions of the array substrate, thereby not affecting the performance of the TFT.
  • FIG. 2 is a schematic cross-sectional view showing a gate electrode and a gate line formed on an array substrate according to an embodiment of the present invention
  • FIG. 3 is a schematic cross-sectional view showing annealing of a gate electrode and a gate line on an array substrate according to an embodiment of the present invention
  • FIG. 4 is a schematic cross-sectional view showing a gate insulating layer formed on an array substrate according to an embodiment of the present invention
  • FIG. 5 is a schematic cross-sectional view showing a pattern of an active layer formed on an array substrate according to an embodiment of the present invention
  • FIG. 6 is a cross-sectional view showing a pattern of forming an etch barrier layer on an array substrate according to an embodiment of the present invention
  • FIG. 7 is a schematic cross-sectional view showing a source/drain metal layer formed on an array substrate according to an embodiment of the present invention
  • 8 is a schematic cross-sectional view showing a source electrode, a drain electrode, and a data line formed on an array substrate according to an embodiment of the present invention
  • FIG. 9 is a schematic cross-sectional view showing a pattern of a passivation layer formed on an array substrate according to an embodiment of the present invention.
  • FIG. 10 is a schematic cross-sectional view showing a pixel electrode formed on an array substrate according to an embodiment of the present invention.
  • the embodiments of the present invention are directed to the prior art that Cu atoms in the gate electrode and the gate line are easily diffused, and enter the active layer through the gate insulating layer to increase the conductivity of the active layer, which seriously affects the performance of the TFT, resulting in
  • the problem that the display cannot be normally displayed provides an array substrate capable of avoiding diffusion of metal atoms in the gate electrode and the gate line in the array substrate, a manufacturing method thereof, and a display device.
  • Embodiments of the present invention provide an array substrate, wherein a gate electrode and a gate line of the array substrate are coated with a metal oxide film. Since the metal oxide film is relatively dense, it can effectively block the diffusion of metal atoms in the gate electrode and the gate line to other regions of the array substrate, thereby not affecting the performance of the TFT, and ensuring the normal display of the display.
  • the metal oxide film is formed by reacting the second metal in the gate metal layer including the first metal and the second metal with oxygen.
  • the gate electrode and the gate line which are externally coated with the metal oxide thin film are the gate electrode and the gate line in a gas containing oxygen after the pattern of the gate electrode and the gate line is formed using the gate metal layer The pattern is annealed to obtain an oxygen-containing gas.
  • the gate metal layer is an alloy including a first metal and a second metal, and the first metal is a main body of the gate electrode and the gate line.
  • the first metal may have better conductivity.
  • a metal such as Cu
  • the second metal is formed to form a metal oxide film on the outside of the gate electrode and the gate line.
  • the second metal may be selected from metals susceptible to oxygen, such as Mg, Cr, Hf, Ca, A], etc., the second metal is not limited to one metal, and may be two or more metals.
  • the gas containing the oxygen of the gate electrode and the gate line is annealed in a gas containing oxygen, and in the high temperature of the annealing treatment,
  • the second metal will undergo segregation in the first metal to react with external oxygen, forming a dense metal oxide film on the outside of the gate electrode and the gate line, thereby effectively blocking the diffusion of metal atoms in the gate electrode and the gate line.
  • the role of the second metal is mainly to form a metal oxide film, not as a main body of the gate electrode and the gate line, and therefore, the proportion of the second metal in the gate metal layer does not need to be too large. Usually at 1 5% or less.
  • the array substrate of the present invention includes:
  • a gate electrode and a gate line coated with a metal oxide film on the outer surface of the base substrate a gate insulating layer on the gate electrode and the gate line coated with the metal oxide film on the outside; An active layer on the insulating layer;
  • the pixel electrode being electrically connected to the drain electrode through the via hole.
  • the embodiment of the invention further provides a display device comprising the array substrate according to any of the above embodiments.
  • the structure of the array substrate is the same as the above embodiment, and details are not described herein again.
  • the structure of other parts of the display device can be referred to the prior art, and will not be described in detail herein.
  • the display device can be: a product or a component having any display function such as a liquid crystal panel, an electronic paper, a liquid crystal television, a liquid crystal display, a digital photo frame, a mobile phone, a tablet computer, or the like.
  • the embodiment of the invention further provides a method for fabricating an array substrate, comprising: forming an outer cladding A gate electrode and a gate line having a metal oxide film. Since the externally coated metal oxide film of the gate electrode and the gate line is relatively dense, the metal atoms in the gate electrode and the gate line can be effectively blocked from diffusing to other regions of the array substrate, thereby not affecting the performance of the TFT, and the display is ensured. The normal display.
  • a metal oxide film When forming a gate electrode and a gate line which are externally coated with a metal oxide film, if a metal oxide film is deposited on the gate electrode and the gate line after forming the gate electrode and the gate line, it is coated by a patterning process.
  • the method of fabricating the gate electrode and the gate line of the metal oxide film has a relatively high process requirement and will greatly increase the production cost.
  • a pattern of a gate electrode and a gate line is formed by using a gate metal layer including a first metal and a second metal, and then a pattern of the gate electrode and the gate line is annealed in a gas containing oxygen, Segregation of the second metal in the first metal reacts with external oxygen to form a metal oxide thin film outside the gate electrode and the gate line.
  • the method for fabricating the array substrate of the present invention only needs to prepare an gate electrode and a gate line by using an alloy including a first metal and a second metal, and then annealing the pattern of the gate electrode and the gate line in a gas containing oxygen,
  • the gate electrode and the gate line coated with the metal oxide film can be obtained, and the metal diffusion of the barrier gate electrode and the gate line to the array substrate can be realized without increasing the production cost without adding an additional patterning process.
  • the gate metal layer is an alloy including a first metal and a second metal, and the first metal is a main body of the gate electrode and the gate line.
  • the first metal may be a metal having a relatively good conductivity.
  • Cu the second metal is for forming a metal oxide film on the outside of the gate electrode and the gate line.
  • the second metal may be selected from metals which are easily reacted with oxygen, such as Mg, Cr, Hf, Ca, Ai, etc.
  • the second metal is not limited to one metal, and may be two or more metals.
  • the gate electrode and the ⁇ line are annealed in a gas containing oxygen, and in the high temperature of the annealing treatment, the second metal will be Segregation occurs in the first metal and reacts with external oxygen.
  • A forms a dense metal oxide film on the outside of the gate electrode and the gate line, effectively blocking the diffusion of metal atoms in the gate electrode and the gate line.
  • the role of the second metal is mainly to form a metal oxide film, not as a main body of the gate electrode and the gate line, and therefore, the proportion of the second metal in the gate metal layer does not need to be too large.
  • the first metal is Cu
  • the second metal may be Mg and Al
  • the gate metal layer is a Cu alloy containing a small amount of Al and Mg components, and a small amount of Ai is deposited on the substrate.
  • a Mg alloy of a Mg composition which is patterned to form a gate electrode and a gate line pattern, and then annealed the gas of the gate electrode and the gate line pattern containing oxygen gas in a gas containing oxygen, specifically, in pure oxygen
  • a gas containing oxygen specifically, in pure oxygen
  • Ai 2 0 3 and MgO are relatively dense metal oxides, the diffusion of Cu atoms can be effectively prevented, thereby solving the Cu atom.
  • a thin film transistor of a low resistance Cu gate electrode is obtained by diffusion phenomenon in the TFT array substrate.
  • the method for fabricating the array substrate of the present invention may include:
  • the pattern of the passivation layer including a via corresponding to the drain electrode;
  • the method for fabricating the array substrate of the present embodiment includes the following steps: Step a, providing a substrate 1 on which a pattern of a gate electrode and a gate line composed of the gate metal layer 2 is formed;
  • the base substrate 1 may be a glass substrate or a quartz substrate.
  • a gate metal layer 2 may be deposited on the base substrate 1 by sputtering or thermal evaporation.
  • the gate metal layer 2 is an alloy including a first metal and a second metal.
  • the first metal is a main body of the gate electrode and the gate line.
  • the first metal may be a metal having good conductivity, such as Ox;
  • the second metal is for forming a metal oxide film on the outside of the gate electrode and the gate line.
  • the second metal may be a metal which is easy to react with oxygen, such as Mg, Cr, Hf, Ca, Ai, etc., the second metal It is not limited to one metal and may be two or more metals.
  • a photoresist is coated on the gate metal layer, and the photoresist is exposed by using a mask to form a photoresist unretained region and a photoresist retention region, wherein the photoresist retention region corresponds to In the region where the pattern of the gate line and the gate electrode is located, the unretained area of the photoresist corresponds to a region other than the above-mentioned pattern; the development process is performed, the photoresist in the unretained area of the photoresist is completely removed, and the light in the photoresist remaining area is removed.
  • the thickness of the engraved adhesive remains unchanged; the gate metal layer of the unretained region of the photoresist is completely etched away by an etching process to form a pattern of gate lines and gate electrodes; and the remaining photoresist is stripped.
  • Step 3 As shown in FIG. 3, a gas containing oxygen in a pattern of a gate electrode and a gate line is annealed in a gas containing oxygen to form a gate electrode and a gate line which are externally coated with the metal oxide film 4;
  • the second metal will undergo segregation in the first metal to react with the external oxygen, thereby forming a dense metal oxide film 4 on the outside of the gate electrode and the » line, thereby effectively blocking the gate electrode and » The diffusion of metal atoms in the line.
  • the main portion of the gate electrode and the - line is the metal conductive portion 3, and the metal conductive portion 3 mainly includes the first metal, and may also include a small portion of the second metal that does not react with oxygen.
  • the gate metal layer is a Cu alloy containing a small amount of A1 and Mg.
  • the gas containing oxygen in the pattern of the gate electrode and the gate line may be annealed in a gas containing oxygen at a temperature of 200 to 300° for 0.5 to 2 hours, in order to increase gold. It is an efficiency of oxide film formation, and preferably, it can be annealed in a pure oxygen atmosphere. In annealing,
  • the Ai and Mg components are segregated in the Cii alloy to concentrate on the surface of the gate electrode and the gate line to react with external oxygen to form A1 2 0 3 and MgO, and the central portion of the gate electrode and the gate line is almost completely Cu. Since both A1 2 0 3 and MgO belong to relatively dense metal oxides, the diffusion of Cu atoms can be effectively prevented.
  • Step 4 forming a gate insulating layer 5 on a substrate substrate on which a gate electrode and a gate line externally coated with a metal oxide film 4 are formed ;
  • a gate insulating layer 5 may be formed by depositing a gate insulating layer material having a thickness of 300 A to 800 A on the substrate of the step b by using a plasma enhanced chemical vapor deposition (PECVD) method, wherein the gate insulating layer material may be The ffi oxide, nitride or oxynitride may be selected, and the gate insulating layer may be a single layer, a double layer or a multilayer structure. Different gate insulating layer materials are selected for the material of the active layer.
  • PECVD plasma enhanced chemical vapor deposition
  • the gate insulating layer can be formed by using SiNx; if the active layer is made of a metal oxide layer such as IGZO, a composite layer structure such as SiOx or SiOx/SiNx or SiOx/SiON/SiNx is required.
  • a gate insulating layer is prepared. In short, the gate insulating layer cooperates with A] 2 0 3 and MgO which are formed on the outside of the gate electrode and the gate line to prevent diffusion of the gate electrode and the gate line Cu atoms, resulting in failure of the TFT device.
  • Step d forming a pattern of the active layer 6 on the base substrate on which the gate insulating layer 5 is formed; as shown in FIG. 5, specifically, magnetron sputtering may be employed on the substrate substrate subjected to the step c, Thermal evaporation or other film formation method deposits an active layer material, then applies a photoresist on the active layer material, exposes the photoresist, and forms a photoresist unretained region and lithography. After the development process, the photoresist in the unreserved area of the photoresist is completely removed, and the thickness of the photoresist in the photoresist remaining area remains unchanged; the photoresist is completely etched away by the etching process.
  • the active layer material of the region forms a pattern of the active layer 6; the remaining photoresist of the photoresist retention region is stripped.
  • the active layer material may be a-Si, IGZO or other materials.
  • Step e forming a pattern of the etch stop layer 7 on the base substrate on which the active layer 6 is formed as shown in FIG. 6;
  • the etch barrier material is deposited on the substrate substrate subjected to the step d by magnetron sputtering, thermal evaporation or other film formation methods, wherein the etch barrier material may be an oxide or a nitride. Applying a layer of photoresist on the etch barrier material, and exposing the photoresist using a mask.
  • the photoresist is formed into a photoresist unretained region and a photoresist remaining region, wherein the photoresist remaining region corresponds to a region where the pattern of the etch barrier layer 7 is located, and the photoresist unretained region corresponds to a region other than the above pattern
  • the photoresist in the unreserved area of the photoresist is completely removed, and the thickness of the photoresist in the photoresist remaining area remains unchanged; the etching of the unretained area of the photoresist is completely etched by the etching process Etching the barrier material to form a pattern of the etch stop layer 7; stripping the remaining photoresist.
  • Step f as shown in FIG. 7 and FIG. 8, a pattern of a source electrode, a drain electrode and a data line composed of a source/drain metal layer 8 is formed on the base substrate on which the etch barrier layer 7 is formed;
  • a source/drain metal layer 8 is deposited on the substrate substrate subjected to the step e by magnetron sputtering, thermal evaporation or other film formation methods.
  • the material of the source/drain metal layer 8 may be a metal such as Gr, W, ⁇ ⁇ 3 ⁇ 4, Mo, Al, Cu or the like, and the source/drain metal layer 8 may also be composed of a plurality of metal thin films.
  • a layer of photoresist is coated on the source/drain metal layer 8, and the photoresist is exposed by a mask to form a photoresist unretained region and a photoresist retention region, wherein the photoresist
  • the reserved area corresponds to the area where the pattern of the source electrode, the drain electrode and the data line is located, and the unretained area of the photoresist corresponds to the area other than the above-mentioned pattern; the development process is performed, and the photoresist in the unretained area of the photoresist is completely removed, the light is completely removed.
  • the thickness of the photoresist in the adhesive-retained region remains unchanged; the source-drain metal layer of the unretained region of the photoresist is completely etched by the etching process to form a pattern of the source electrode, the drain electrode, and the data line; As shown in FIG. 9, a pattern of the passivation layer 9 is formed on the base substrate on which the source electrode, the drain electrode, and the data line are formed;
  • a passivation layer material having a thickness of 1500A to 2500A is deposited on the substrate substrate subjected to the step f by magnetron sputtering, thermal evaporation or other film formation method, wherein the passivation layer material may be an oxide or a nitride. .
  • the photoresist unretained region corresponds to a region other than the above-mentioned pattern; the development process, the photoresist in the unreserved region of the photoresist is completely removed, and the photoresist is preserved in the photoresist-retained region.
  • the thickness of the adhesive remains unchanged; the passivation layer material of the unretained region of the photoresist is completely etched away by an etching process to form a pattern of the passivation layer 9 including via holes; and the remaining photoresist is stripped.
  • Steps are as shown in FIG. 10, forming a pixel electrode on the base substrate i on which the passivation layer 9 is formed In the pattern of 10, the pixel electrode 10 is connected to the drain electrode through a via.
  • a transparent conductive layer having a thickness of 300 A 600 A is deposited on the substrate substrate subjected to the step g by magnetron sputtering, thermal evaporation or other film forming method, wherein the transparent conductive layer may be indium tin oxide (yttrium). Materials such as oxidized radium zinc ( ⁇ ). Coating a layer of photoresist on the transparent conductive layer; exposing the photoresist by using a mask to form a photoresist unretained region and a photoresist retention region, wherein the photoresist retention region corresponds to On the pixel electrode!
  • the unretained area of the photoresist corresponds to the area other than the above-mentioned pattern; the development process is performed, the photoresist in the unretained area of the photoresist is completely removed, and the thickness of the photoresist in the photoresist remaining area is not maintained.
  • the transparent conductive layer of the unretained region of the photoresist is completely etched away by an etching process to form a pattern of the pixel electrode 10; after the above steps a-li, the array substrate of the embodiment shown in FIG. 10 is obtained.
  • the gate electrode and the gate line of this embodiment are externally coated with a metal oxide film. Because the metal oxide film is relatively dense, it can effectively block the diffusion of metal atoms in the gate electrode and the gate line to other regions of the array substrate, thereby not affecting the performance of the TFT, and ensuring the normal display of the display.

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Abstract

提供一种阵列基板及其制作方法和显示装置，属于显示技术领域。该阵列基板的栅电极和栅线的外部包覆有金属氧化物薄膜。通过该方法能够避免栅电极和栅线中的金属原子在阵列基板中发生扩散。

Description

本发明涉及显示技术领域， 特别涉及一种阵列基板及其制作方法和显示 装置 随着科技的不断进步， 用户对液晶显示设备的需求日益增加，
TFT-LCD(Thin Film Transistor-Liquid Crystal Display, 薄膜场效应晶体管液晶 显示器） 也成为了手机、 平板电脑等产品中使用的主流显示器。
TFT的性能决定了液晶显示器的显示品质， 图 1为现有 TFT阵列基板的 结构示意图， 如图 1所示， 现有 TFT阵列基板一般依次包括有衬底基板 1、 栅电极和栅线 11、栅绝缘层 5、 有源层 6、 刻蚀阻挡层 7、源电极和漏电极 8、 钝化层 9和像素电极 ！0。 为了提高栅电极和栅线的导电性能， 一般采用 Cu 来制备栅电极和栅线，但是在采用 Cu制备栅电极和栅线之后，栅电极和栅线 中的 Cu原子容易发生扩散， 并且由于栅绝缘层的致密性不是很好， Qi原子 会通过栅绝缘层进入到有源层中，增大有源层的导电性，从而会严重影响 TFT 的性能， 导致显示器不能正常显示。 本发明要解决的技术问题是提供一种能避免栅电极和栅线中的金属原子 在阵列基板中发生扩散的阵列基板及其制作方法和显示装置。
为解决上述技术问题， 本发明的实施例提供的技术方案如下：
一方面， 提供一种阵列基板， 所述阵列基板的栅电极和栅线的外部包覆 有金属氧化物薄膜。
进一步地， 上述方案中， 所述金属氧化物薄膜为包括有第一金属和第二 金属的栅金属层中的所述第二金属与氧气发生反应后形成。
进一步地， 上述方案中， 外部包覆有金属氧化物薄膜的栅电极和栅线为 在利用所述栅金属层形成栅电极和栅线的图案之后、 在含有氧气的气体中对 所述栅电极和栅线的图案含有氧气的气体中进行退火而得到的。
迸一歩地， 上述方案中， 所述第一金属为 Cu, 所述第二金属为 Mg、 Cr、 Hf, Ca、 Al中的至少一种。 迸一步地， 上述方案中， 所述第二金属在所述栅金属层中所占的重量百 分比为 1 5%。
迸一步地， 上述方案中， 所述阵列基板具体包括： 在所述衬底基板上的所述外部包覆有金属氧化物薄膜的栅电极和栅线； 在所述外部包覆有金属氧化物薄膜的栅电极和栅线上的栅绝缘层； 在所述栅绝缘层上的有源层；
在所述有源层上的刻蚀阻挡层；
在所述刻蚀阻挡层上的由源漏金属层构成的漏电极、 源电极和数据线； 在所述漏电极、 所述源电极和所述数据线上的钝化层， 所述钝化层包括 对应所述漏电极的过孔；
在所述钝化层上的像素电极， 所述像素电极通过所述过孔与所述漏电极 电连接。
本发明实施例还提供了一种显示装置， 包括如上所述的阵列基板。
本发明实施例还提供了一种阵列基板的制作方法， 包括：
使包括有第一金属和第二金属的栅金属层中所述第二金属在所述第一金 属中发生偏析与外部的氧气反应从而在所述栅电极和栅线外部形成所述金属 氧化物薄膜。
迸一步地， 上述方案中， 利用所述栅金属层形成栅电极和栅线的图案之 后在含有氧气的气体中对所述栅电极和栅线的图案进行退火， 使所述第二金 属在所述第一金属中发生偏析与外部的氧气反应从而在所述栅电极和栅线外 部形成所述金属氧化物薄膜。
迸一歩地， 上述方案中， 所述第一金属为 Cu, 所述第二金属为 Mg、 Cr、 Hf, Ca、 Al中的至少一种。
迸一步地， 上述方案中， 所述在含有氧气的气体中对所述栅电极和栅线 的图案进行退火包括：
在 200- 300Ό的温度下对所述栅电极和栅线的图案进行退火 0.5- 2h。
进一步地， 上述方案中， 所述制作方法具体包括：
提供一衬底基板； 在所述衬底基板上利用栅金属层形成栅电极和栅线的图案， 然后在含有 氧气的气体中对所述栅电极和栅线的图案含有氧气的气体中迸行退火， 从而 得到外部包覆有金属氧化物薄膜的栅电极和栅线；
在形成有所述外部包覆有金属氧化物薄膜的栅电极和栅线的衬底基板上 形成栅绝缘层；
在形成有所述栅绝缘层的衬底基板上形成有源层的图案；
在形成有所述有源层的衬底基板上形成刻蚀阻挡层的图案；
在形成有所述刻蚀阻挡层的衬底基板上形成数据线、 源电极和漏电极的 图案；
在形成有所述数据线、 所述源电极和所述漏电极的衬底基板上形成钝化 层的图案， 所述钝化层的图案包括对应所述漏电极的过孔；
在形成有所述钝化层的衬底基板上形成像素电极的图案， 所述像素电极 遥过所述过孔与所述漏电极电连接。
本发明的实施例具有以下有益效果：
上述方案中， 阵列基板的栅电极和栅线的外部包覆有金属氧化物薄膜， 能够有效阻挡栅电极和栅线中的金属原子扩散到阵列基板的其他区域， 从而 不会影响 TFT的性能， 保证了显示器的正常显示。 图 1为现有技术中 TFT阵列基板的结构示意图；
图 2 为本发明实施例的在阵列基板上形成栅电极和栅线后的截面示意 图；
图 3为本发明实施例的在阵列基板上对形成栅电极和栅线进行退火后的 截面示意图；
图 4为本发明实施例的在阵列基板上形成栅绝缘层后的截面示意图； 图 5 为本发明实施例的在阵列基板上形成有源层的图案后的截面示意 图；
图 6为本发明实施例的在阵列基板上形成刻蚀阻挡层的图案后的截面示 意图；
图 7为本发明实施例的在阵列基板上形成源漏金属层后的截面示意图； 图 8为本发明实施例的在阵列基板上形成源电极、 漏电极和数据线后的 截面示意图；
图 9 为本发明实施例的在阵列基板上形成钝化层的图案后的截面示意 图；
图 10为本发明实施例的在阵列基板上形成像素电极后的截面示意图。
1 衬底基板 2栅金属层 3 金属导电部分
4金属氧化物薄膜 5 栅绝缘层 6有源层
7 刻蚀阻挡层 8 源漏金属层 9 钝化层
10 像素电极
具体实施方式
为使本发明的实施例要解决的技术问题、 技术方案和优点更加清楚， 下 面将结合 ^图及具体实施例进行详细描述。
本发明的实施例针对现有技术中栅电极和栅线中的 Cu原子容易发生扩 散， 通过栅绝缘层进入到有源层中， 增大有源层的导电性， 严重影响 TFT的 性能， 导致显示器不能正常显示的问题， 提供一种能够避免栅电极和栅线中 的金属原子在阵列基板中发生扩散的阵列基板及其制作方法和显示装置。
本发明实施例提供了一种阵列基板， 所述阵列基板的栅电极和栅线的外 部包覆有金属氧化物薄膜。 因为金属氧化物薄膜比较致密， 因此能够有效阻 挡栅电极和栅线中的金属原子扩散到阵列基板的其他区域， 从而不会影响 TFT的性能， 保证了显示器的正常显示。
具体地， 所述金属氧化物薄膜为包括有第一金属和第二金属的栅金属层 中的所述第二金属与氧气发生反应后形成。
更具体地， 外部包覆有金属氧化物薄膜的栅电极和栅线为在利用所述栅 金属层形成栅电极和栅线的图案之后、 在含有氧气的气体中对所述栅电极和 栅线的图案进行退火而得到的含有氧气的气体。
本发明中， 栅金属层为包括有第一金属和第二金属的合金， 第一金属是 作为栅电极和栅线的主体， 一般情况下， 第一金属可以选用导电性能比较好 的金属，比如 Cu;第二金属是为了在栅电极和栅线外部形成金属氧化物薄膜， 一般情况下， 第二金属可以选用易与氧气发生反应的金属， 比如 Mg、 Cr、 Hf, Ca、 A】等， 第二金属并不局限为一种金属， 可以为两种或三种以上的金 属。 采 ^包含有第一金属和第二金属的合金形成栅电极和栅线的图案后， 在 含有氧气的气体中对栅电极和栅线含有氧气的气体进行退火处理， 在退火处 理的高温中， 第二金属将在第一金属中发生偏析与外部的氧气反应， 在栅电 极和栅线外侧形成一层致密的金属氧化物薄膜， 认而有效阻挡栅电极和栅线 中金属原子的扩散。
本发明的技术方案中，第二金属的作用主要是为了形成金属氧化物薄膜, 而不是作为栅电极和栅线的主体， 因此， 栅金属层中第二金属所占的比重不 需要太大， 一般在 1 5%或者更少。
具体地， 本发明的阵列基板包括：
衬底基板；
在所述衬底基板上的外部包覆有金属氧化物薄膜的栅电极和栅线； 在所述外部包覆有金属氧化物薄膜的栅电极和栅线上的栅绝缘层； 在所述栅绝缘层上的有源层；
在所述有源层上的刻蚀阻挡层；
在所述刻蚀阻挡层上的由源漏金属层构成的漏电极、 源电极和数据线； 在所述漏电极、 所述源电极和所述数据线上的钝化层， 所述钝化层包括 对应所述漏电极的过孔；
在所述钝化层上的像素电极， 所述像素电极通过所述过孔与所述漏电极 电连接。
本发明实施例还提供了一种显示装置， 包括如上任一实施例所述的阵列 基板。 其中， 阵列基板的结构同上述实施例， 在此不再赘述。 另外， 显示装 置其他部分的结构可以参考现有技术， 对此本文不再详细描述。 该显示装置 可以为： 液晶面板、 电子纸、 液晶电视、 液晶显示器、 数码相框、 手机、 平 板电脑等具有任何显示功能的产品或部件。
本发明实施例还提供了一种阵列基板的制作方法， 包括： 形成外部包覆 有金属氧化物薄膜的栅电极和栅线。 因为栅电极和栅线的外部包覆的金属氧 化物薄膜比较致密， 因此能够有效阻挡栅电极和栅线中的金属原子扩散到阵 列基板的其他区域， 从而不会影响 TFT的性能， 保证了显示器的正常显示。
在形成外部包覆有金属氧化物薄膜的栅电极和栅线时， 如果采用在形成 栅电极和栅线之后， 再在栅电极和栅线上沉积金属氧化物薄膜、 通过构图工 艺得到包覆有金属氧化物薄膜的栅电极和栅线的制作方法， 对工艺的要求比 较高， 将会大大增加生产成本。 因此， 本发明的技术方案中， 利用包括有第 一金属和第二金属的栅金属层形成栅电极和栅线的图案， 之后在含有氧气的 气体中对栅电极和栅线的图案进行退火， 使第二金属在第一金属中发生偏析 与外部的氧气反应， 从而在栅电极和栅线外部形成金属氧化物薄膜。
本发明的阵列基板的制作方法， 只需要采用包括有第一金属和第二金属 的合金来制备栅电极和栅线， 之后再在含有氧气的气体中对栅电极和栅线的 图案进行退火， 即可得到包覆有金属氧化物薄膜的栅电极和栅线， 无需增加 额外的构图工艺， 在不增加生产成本的情况下就能实现阻挡栅电极和栅线中 的金属原子扩散到阵列基板的其他区域。
本发明中， 栅金属层为包括有第一金属和第二金属的合金， 第一金属是 作为栅电极和栅线的主体， 一般情况下， 第一金属可以选用导电性能比较好 的金属，比如 Cu;第二金属是为了在栅电极和栅线外部形成金属氧化物薄膜， 一般情况下， 第二金属可以选 ffi易与氧气发生反应的金属， 比如 Mg、 Cr、 Hf、 Ca、 Ai等， 第二金属并不局限为一种金属， 可以为两种或三种以上的金 属。 采用包含有第一金属和第二金属的合金形成栅电极和 »线的图案后， 对 栅电极和 »线在含有氧气的气体中进行退火处理， 在退火处理的高温中， 第 二金属将在第一金属中发生偏析与外部的氧气反应， A而在栅电极和栅线外 侧形成一层致密的金属氧化物薄膜， 有效阻挡栅电极和栅线中金属原子的扩 散。
本发明的技术方案中，第二金属的作用主要是为了形成金属氧化物薄膜, 而不是作为栅电极和栅线的主体， 因此， 栅金属层中第二金属所占的比重不 需要太大， 一般在 1 5%或者更少。 优选地， 本发明一具体实施例中， 第一金属为 Cu， 第二金属可以为 Mg 和 Al， 栅金属层为包含有少量 Al、 Mg成分的 Cu合金， 在衬底基板上沉积 含有少量 Ai、Mg成分的 Cu合金，经过构图工艺后形成栅电极和栅线的图案， 之后在含有氧气的气体中对栅电极和栅线的图案含有氧气的气体进行退火处 理， 具体地， 可以在纯氧中， 在 200到 300°C的环境下退火 0,5-211， 由于 Ai、 Mg成分在 Cu合金中的偏析使其聚集在栅电极和栅线的表面与外部的氧气发 生反应生成 A1203和 MgO， 而栅电极和栅线的中心部分则几乎完全成为 Cu， 由于 Ai203和 MgO都属于比较致密的金属氧化物， 因此可以有效的防止 Cu 原子的扩散， 从而解决了 Cu原子在 TFT阵列基板中的扩散现象， 获得低电 阻的 Cu栅电极的薄膜晶体管。
具体地， 本发明的阵列基板的制作方法可以包括：
提供一衬底基板；
在所述衬底基板上利用栅金属层形成栅电极和栅线的图案， 然后在含有 氧气的气体中对所述栅电极和栅线的图案含有氧气的气体进行退火， 得到外 部包覆有金属氧化物薄膜的栅电极和栅线；
在形成有所述外部包覆有金属氧化物薄膜的栅电极和栅线的衬底基板上 形成概绝缘层；
在形成有所述栅绝缘层的衬底基板上形成有源层的图案；
在形成有所述有源层的衬底基板上形成刻蚀阻挡层的图案；
在形成有所述刻蚀阻挡层的衬底基板上形成数据线、 源电极和漏电极的 图案；
在形成有所述数据线、 所述源电极和所述漏电极的衬底基板上形成钝化 层的图案， 所述钝化层的图案包括有对应所述漏电极的过孔；
在形成有所述钝化层的衬底基板上形成像素电极的图案， 所述像素电极
Figure imgf000008_0001
下面结合具体的工艺流程对本实施例的阵列基板的制作方法进行进一歩 如图 2〜图 10所示， 本发明的阵列基板的制作方法包括以下步骤: 歩骤 a、 提供一衬底基板 1， 在衬底基板 1上形成由栅金属层 2构成的栅 电极和栅线的图案；
如图 2所示， 首先通过一次构图工艺在衬底基板 1上形成由栅金属层 2 构成的包括栅电极和与栅电极连接的栅线的图案。 其中， 衬底基板 1可为玻 璃基板或石英基板。
具体地， 可以采用溅射或热蒸发的方法在衬底基板 1上沉积一层栅金属 层 2。 栅金属层 2为包括有第一金属和第二金属的合金， 第一金属是作为栅 电极和栅线的主体， 一般情况下， 第一金属可以选用导电性能比较好的金属， 比如 Ox; 第二金属是为了在栅电极和栅线外部形成金属氧化物薄膜， 一般情 况下， 第二金属可以选用易与氧气发生反应的金属， 比如 Mg、 Cr、 Hf、 Ca、 Ai等， 第二金属并不局限为一种金属， 可以为两种或三种以上的金属。 在栅 金属层上涂覆一层光刻胶， 采用掩膜板对光刻胶进行曝光， 使光刻胶形成光 刻胶未保留区域和光刻胶保留区域， 其中， 光刻胶保留区域对应于栅线和栅 电极的图案所在区域， 光刻胶未保留区域对应于上述图案以外的区域； 进行 显影处理， 光刻胶未保留区域的光刻胶被完全去除， 光刻胶保留区域的光刻 胶厚度保持不变； 通过刻蚀工艺完全刻蚀掉光刻胶未保留区域的栅金属层， 形成栅线和栅电极的图案； 剥离剩余的光刻胶。
步骤 如图 3所示， 在含有氧气的气体中对栅电极和栅线的图案含有 氧气的气体进行退火处理， 形成外部包覆有金属氧化物薄膜 4的栅电极和栅 线；
在退火处理的高温中， 第二金属将在第一金属中发生偏析与外部的氧气 反应， 从而在栅电极和 »线外部形成一层致密的金属氧化物薄膜 4， 从而有 效阻挡栅电极和»线中金属原子的扩散。 栅电极和 »线的主体部分为金属导 电部分 3 , 金属导电部分 3主要包括第一金属， 还可能包括有少部分未与氧 气发生反应的第二金属。
在第一金属选用 Cu, 第二金属为 A1和 Mg时， 栅金属层为包含有少量 A1和 Mg的 Cu合金。 具体地， 可以在含有氧气的气体中， 在 200到 300°的 环境下对栅电极和栅线的图案含有氧气的气体进行退火 0.5- 2h， 为了提高金 属氧化物薄膜形成的效率， 优选地， 可以在纯氧环境中进行退火。 在退火中，
Ai、 Mg成分在 Cii合金中发生偏析使其聚集在栅电极和栅线的表面与外部的 氧气发生反应生成 A1203和 MgO， 而栅电极和栅线的中心部分则几乎完全成 为 Cu , 由于 A1203和 MgO都属于比较致密的金属氧化物， 因此可以有效的 防止 Cu原子的扩散。
步骤 如图 4所示，在形成有外部包覆有金属氧化物薄膜 4的栅电极和 栅线的衬底基板上形成栅绝缘层 5 ;
具体地， 可以采用等离子体增强化学气相沉积 （PECVD ) 方法， 在经过 步骤 b的衬底基板上沉积厚度为 300 A〜800A的栅绝缘层材料形成栅绝缘层 5， 其中， 栅绝缘层材料可以选 ffi氧化物、 氮化物或者氮氧化物， 栅绝缘层可 以为单层、 双层或多层结构。 针对于有源层材料的不同， 选择不同的栅绝缘 层材料。 例如， 如果有源层采用 a Si,则可以采用 SiNx形成栅绝缘层;如果有 源层选用 IGZO 等金属氧化物层， 则需要采用 SiOx 或者 SiOx/SiNx 或者 SiOx/SiON/SiNx等复合层结构来制备栅绝缘层。 总之栅绝缘层与之前在栅电 极和栅线外部形成的 A】203和 MgO共同作用， 防止栅电极及栅线 Cu原子的 扩散， 造成 TFT器件的失效。
步骤 d: 在形成有栅绝缘层 5的衬底基板上形成有源层 6的图案； 如图 5所示， 具体地， 可以先在经过歩骤 c的衬底基板上采用磁控溅射、 热蒸发或其它成膜方法沉积一层有源层材料， 之后在有源层材料上涂覆光刻 胶， 对光刻胶迸行曝光， 使光刻胶形成光刻胶未保留区域和光刻胶保留区域; 之后进行显影处理， 光刻胶未保留区域的光刻胶被完全去除， 光刻胶保留区 域的光刻胶厚度保持不变； 通过刻蚀工艺完全刻蚀掉光刻胶未保留区域的有 源层材料， 形成有源层 6的图案； 剥离光刻胶保留区域的剩余的光刻胶。 其 中， 有源层材料可以选用 a- Si, IGZO或者其他材料。
步骤 e: 如图 6所示， 在形成有源层 6的衬底基板上形成刻蚀阻挡层 7 的图案；
具体地， 在经过步骤 d的衬底基板上采用磁控溅射、 热蒸发或其它成膜 方法沉积刻蚀阻挡层材料， 其中， 刻蚀阻挡层材料可以选用氧化物或者氮化 物。 在刻蚀阻挡层材料上涂覆一层光刻胶， 采用掩膜板对光刻胶进行曝光， 使光刻胶形成光刻胶未保留区域和光刻胶保留区域， 其中， 光刻胶保留区域 对应于刻蚀阻挡层 7的图案所在区域， 光刻胶未保留区域对应于上述图案以 外的区域； 迸行显影处理， 光刻胶未保留区域的光刻胶被完全去除， 光刻胶 保留区域的光刻胶厚度保持不变； 通过刻蚀工艺完全刻蚀掉光刻胶未保留区 域的刻蚀阻挡层材料， 形成刻蚀阻挡层 7的图案； 剥离剩余的光刻胶。
步骤 f: 如图 7和图 8所示，在形成有刻蚀阻挡层 7的衬底基板上形成由 源漏金属层 8构成的源电极、 漏电极和数据线的图案；
具体地， 在经过步骤 e的衬底基板上采用磁控溅射、 热蒸发或其它成膜 方法沉积一层源漏金属层 8。 源漏金属层 8的材料可以是 Gr、 W、 Τ Τ¾、 Mo, Al、 Cu等金属及其合金， 源漏金属层 8也可以是由多层金属薄膜组成。 在源漏金属层 8上涂覆一层光刻胶， 采用掩膜板对光刻胶迸行曝光， 使光刻 胶形成光刻胶未保留区域和光刻胶保留区域， 其中， 光刻胶保留区域对应于 源电极、 漏电极和数据线的图案所在区域， 光刻胶未保留区域对应于上述图 案以外的区域； 进行显影处理， 光刻胶未保留区域的光刻胶被完全去除， 光 刻胶保留区域的光刻胶厚度保持不变； 通过刻蚀工艺完全刻蚀掉光刻胶未保 留区域的源漏金属层， 形成源电极、 漏电极和数据线的图案； 剥离剩余的光 步骤 如图 9所示， 在形成有形成源电极、 漏电极和数据线的衬底基 板上形成钝化层 9的图案；
具体地， 在经过步骤 f 的衬底基板上采用磁控溅射、 热蒸发或其它成膜 方法沉积厚度为 1500A〜2500A的钝化层材料， 其中， 钝化层材料可以选用氧 化物或者氮化物。 在钝化层材料上涂敷一层光刻胶； 采用掩膜板对光刻胶进 行曝光， 使光刻胶形成光刻胶未保留区域和光刻胶保留区域， 其中， 光刻胶 保留区域对应于钝化层的图案所在区域， 光刻胶未保留区域对应于上述图案 以外的区域； 进行显影处理， 光刻胶未保留区域的光刻胶被完全去除， 光刻 胶保留区域的光刻胶厚度保持不变； 通过刻蚀工艺完全刻蚀掉光刻胶未保留 区域的钝化层材料， 形成包括过孔的钝化层 9的图案； 剥离剩余的光刻胶。
步骤 如图 10所示， 在形成有钝化层 9的衬底基板 i上形成像素电极 10的图案， 像素电极 10通过过孔与漏电极连接。
具体地， 在经过步骤 g的衬底基板上采用磁控溅射、 热蒸发或其它成膜 方法沉积厚度为 300A〜600A的透明导电层， 其中， 透明导电层可以采用氧化 铟锡 （ΙΤΟ)、 氧化镭锌 （ΙΖΟ) 等材料。 在透明导电层上涂敷一层光刻胶； 采用掩膜板对光刻胶进行曝光， 使光刻胶形成光刻胶未保留区域和光刻胶保 留区域， 其中， 光刻胶保留区域对应于像素电极！ 0的图案所在区域， 光刻胶 未保留区域对应于上述图案以外的区域； 进行显影处理， 光刻胶未保留区域 的光刻胶被完全去除， 光刻胶保留区域的光刻胶厚度保持不变； 通过刻蚀工 艺完全刻蚀掉光刻胶未保留区域的透明导电层， 形成像素电极 10的图案； 剥 经过上述步骤 a-li即得到如图 10所示的本实施例的阵列基板。 本实施例 的栅电极和栅线外部包覆有金属氧化物薄膜。因为金属氧化物薄膜比较致密， 因此能够有效阻挡栅电极和栅线中的金属原子扩散到阵列基板的其他区域， 从而不会影响 TFT的性能， 保证了显示器的正常显示。
以上所述是本发明的优选实施方式， 应当指出， 对于本技术领域的普通 技术人员来说， 在不脱离本发明所述原理的前提下， 还可以作出若干改进和 润饰， 这些改迸和润饰也应视为本发明的保护范围。
以上所述仅是本发明的优选实施方式， 应当指出， 对于本技术领域的普 通技术人员来说， 在不脱离本发明原理的前提下， 还可以做出若千改进和润 饰， 这些改进和润饰也应视本发明的保护范围。

Claims

1、 一种阵列基板， 其特征在于， 所述阵列基板的栅电极和栅线的外部包 覆有金属氧化物薄膜。
2、 根据权利要求 1所述的阵列基板， 其特征在于， 所述金属氧化物薄膜 为包括有第一金属和第二金属的栅金属层中的所述第二金属与氧气发生反应
3、 根据权利要求 2所述的阵列基板， 其特征在于， 外部包覆有金属氧化 物薄膜的栅电极和栅线为在利用所述栅金属层形成栅电极和栅线的图案之 后、 在含有氧气的气体中对所述栅电极和栅线的图案进行退火后得到的。
4、 根据权利要求 2所述的阵列基板， 其特征在于， 所述第一金属为 Cu, 所述第二金属为 Mg、 Cr、 Hf, Ca、 Al中的至少一种。
5、 根据权利要求 2所述的阵列基板， 其特征在于， 所述第二金属在所述 栅金属层中所占的重量百分比为 1-5%。
6、 根据权利要求 1 5中任一项所述的阵列基板， 其特征在于， 所述阵列 基板具体包括：
衬底基板；
在所述衬底基板上的所述外部包覆有金属氧化物薄膜的栅电极和栅线； 在所述外部包覆有金属氧化物薄膜的栅电极和栅线上的栅绝缘层； 所述栅绝缘层上的有源层；
在所述有源层上的刻蚀阻挡层；
在所述刻蚀阻挡层上的由源漏金属层组成的漏电极、 源电极和数据线； 在所述漏电极、 所述源电极和所述数据线上的钝化层， 所述钝化层包括 对应所述漏电极的过孔；
在所述钝化层上的像素电极， 所述像素电极通过所述过孔与所述漏电极 电连接。
Ί、 一种显示装置， 其特征在于， 包括如权利要求 1-6中任一项所述的阵 列基板。
8、 一种阵列基板的制作方法， 其特征在于， 包括：
使包括有第一金属和第二金属的栅金属层中所述第二金属在所述第一金 属中发生偏析并与外部的氧气反应认而在栅电极和栅线外部形成所述金属氧
9、 根据权利要求 8所述的阵列基板的制作方法， 其特征在于， 利用所述 栅金属层形成所述栅电极和所述栅线的图案之后， 在含有氧气的气体中对所 述栅电极和所述栅线的图案进行退火， 使所述第二金属在所述第一金属中发 生偏析与外部的氧气反应， 认而在所述栅电极和所述栅线外部形成所述金属 氧化物薄膜。
10、 根据权利要求 8所述的阵列基板的制作方法， 其特征在于， 所述第 一金属为 Cu， 所述第二金属为 Mg、 Cr、 Hf、 Ca、 Ai中的至少一种。
I 根据权利要求 9所述的阵列基板的制作方法， 其特征在于， 所述在 含有氧气的气体中对所述栅电极和所述栅线的图案进行退火包括：
在 200-300'Ό的温度下对所述栅电极和所述栅线的图案进行退火 0.5-2h。
12、 根据权利要求 8-U中任一项所述的阵列基板的制作方法， 其特征在 于， 所述制作方法具体包括：
提供一衬底基板；
在所述衬底基板上利用所述栅金属层形成所述栅电极和所述栅线的图 案， 然后在含有氧气的气体中对所述栅电极和所述栅线的图案在含有氧气的 气体中进行退火， 从而得到外部包覆有金属氧化物薄膜的栅电极和栅线； 在形成有所述外部包覆有金属氧化物薄膜的栅电极和 »线的衬底基板上 形成栅绝缘层；
在形成有所述栅绝缘层的衬底基板上形成有源层的图案；
在形成有所述有源层的衬底基板上形成刻蚀阻挡层的图案；
在形成有所述刻蚀阻挡层的衬底基板上形成数据线、 源电极和漏电极的 图案；
在形成有所述数据线、 所述源电极和所述漏电极的衬底基板上形成钝化 层的图案， 所述钝化层的图案包括对应所述漏电极的过孔； 在形成有所述钝化层的衬底基板上形成像素电极的图案， 所述像素电极 通过所述过孔与所述漏电极电连接。
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