WO2015014022A1 - 阵列基板及其制作方法 - Google Patents

阵列基板及其制作方法 Download PDF

Info

Publication number
WO2015014022A1
WO2015014022A1 PCT/CN2013/085219 CN2013085219W WO2015014022A1 WO 2015014022 A1 WO2015014022 A1 WO 2015014022A1 CN 2013085219 W CN2013085219 W CN 2013085219W WO 2015014022 A1 WO2015014022 A1 WO 2015014022A1
Authority
WO
WIPO (PCT)
Prior art keywords
area
detection
pixel unit
array substrate
separation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2013/085219
Other languages
English (en)
French (fr)
Inventor
郭建
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Beijing BOE Optoelectronics Technology Co Ltd
Original Assignee
Beijing BOE Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Beijing BOE Optoelectronics Technology Co Ltd filed Critical Beijing BOE Optoelectronics Technology Co Ltd
Publication of WO2015014022A1 publication Critical patent/WO2015014022A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/1306—Details
    • G02F1/1309—Repairing; Testing
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133374—Constructional arrangements; Manufacturing methods for displaying permanent signs or marks
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133388—Constructional arrangements; Manufacturing methods with constructional differences between the display region and the peripheral region
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136254—Checking; Testing

Definitions

  • Embodiments of the present invention relate to an array substrate and a method of fabricating the same. Background technique
  • a conventional liquid crystal display includes: an array substrate, a color filter substrate, and a liquid crystal layer disposed between the array substrate and the color filter substrate.
  • the array substrate 100 includes: a display area 101, a routing area 102, and a peripheral area 103.
  • the display area 101 includes a plurality of pixel units formed by staggered gate lines and data lines, each of which includes a thin film transistor.
  • the trace area 102 includes signal elements that effect electrical connection of signal lines in the display area 101, such as input traces of the data line signals of the display area 101. Since the thin film transistor of each pixel unit of the display region 101 is disturbed by other layers, it is difficult to detect its performance, and thus the detection region 104 is also provided in the peripheral region 103 of the substrate.
  • the detection area 104 includes pixel units formed by staggered gate lines and data lines, and each pixel unit includes a thin film transistor for detecting characteristics of a thin film transistor on a substrate.
  • the detection region 104 is generally cut away with the peripheral region 103 during the process of cutting the mother substrate to obtain a single panel.
  • Embodiments of the present invention provide an array substrate and a method of fabricating the same, such that the thin film transistor characteristics of the detection region on the array substrate are uniform, similar to the characteristics of the thin film transistor of the display region, and the test result is closer to the true value.
  • Embodiments of the present invention provide an array substrate including a display area and a peripheral area; the display area includes a plurality of first pixel units for display; the peripheral area includes a detection area and includes a surround a separation area of the detection area, a second pixel unit for detecting is disposed in the detection area, and each of the second pixel units is correspondingly provided with a thin film transistor.
  • the separation area is provided with a third pixel unit for non-detection.
  • the pixel density of the third pixel unit of the separation region is not less than 10.
  • a space is provided between the separation zone and the detection zone.
  • the separation zone and the detection zone are separated by 15-100 ⁇ m.
  • the second pixel unit of the detection area is arranged in a matrix of n*m, and both n and m are positive integers greater than 3.
  • n and m are 50, respectively.
  • the third pixel unit of the separation region is in the same row as the second pixel unit of the detection region.
  • the line width of the second pixel unit of the detection area is smaller than the line width of the first pixel unit of the display area.
  • Embodiments of the present invention provide a method of fabricating an array substrate, including: forming a display region and a peripheral region on a substrate; the display region includes a plurality of first pixel units for display; and the peripheral region includes detection And a separation area surrounding the detection area, wherein the detection area is provided with a second pixel unit for detection, and each second pixel unit is correspondingly provided with a thin film transistor.
  • the separation area is provided with a third pixel unit for non-detection.
  • the third pixel unit of the separation region is fabricated simultaneously with the second pixel unit of the detection region.
  • the line width of the pixel unit of the peripheral area is smaller than the line width of the first pixel unit of the display area.
  • 1 is a schematic plan view showing a conventional array substrate
  • FIG. 2 is a schematic structural view of a peripheral region on a conventional array substrate
  • 3A is a schematic plan view of an array substrate according to an embodiment of the present invention.
  • FIG. 3B is a schematic structural view of a peripheral region of an array substrate according to an embodiment of the present invention
  • FIG. 4 is a schematic structural view of a peripheral region of another array substrate according to an embodiment of the present invention
  • FIG. 5 is a schematic cross-sectional view of a peripheral region of an array substrate according to an embodiment of the present invention.
  • an embodiment of the present invention provides an array substrate including a display area 101 and a peripheral area 103.
  • the display area 101 includes a plurality of first pixel units 1011 arranged in an array for display.
  • the peripheral area 103 includes a detection area 104.
  • the detection area 104 is provided with a plurality of second pixel units 1041 for detection (FIG. 3B), and each of the second pixel units 1041 is correspondingly provided with a thin film transistor (TFT).
  • TFT thin film transistor
  • the peripheral region 103 also includes a separation region 105 that surrounds the detection region 104. The separation region 105 can make the characteristics of the thin film transistor of the detection region 104 uniform.
  • the peripheral area 103 may be disposed around the display area 101 and includes at least one detection area 104, which may be disposed on at least one side of the array substrate, such as on opposite sides of each other.
  • each of the pixel units 1041 is correspondingly provided with at least one thin film transistor (TFT), and each of the second pixel units 1041 may be correspondingly provided with a thin film transistor, or may be corresponding to a second pixel unit 1041.
  • TFT thin film transistor
  • a plurality of thin film transistors are provided.
  • a thin film transistor corresponding to each of the second pixel units 1041 will be described in detail below as an example.
  • a routing area 102 may also be included, including signal elements (not shown) that effect electrical connection of the signal lines in the display area 101.
  • the second pixel unit 1041 for detection in the detection area 104 also constitutes an array and can be electrically connected, for example, to a signal element in the routing area 102.
  • the concentration of the liquid medicine in the pixel unit at the edge of the detection area is small, and the concentration of the chemical liquid in the middle portion of the detection area is relatively small.
  • the big finger is the detection area, and therefore, the uneven concentration of the chemical liquid also leads to the formation.
  • the thin film transistors have different characteristics and cannot reflect the characteristics of the thin film transistors in the display region.
  • the array substrate in the peripheral region 103, since the separation region 105 is further disposed around the detection region 104, the array substrate may be in the process of being fabricated.
  • the concentration of the chemical liquid (for example, the etching liquid used for the patterning process) for preparing the second pixel unit in the detection region 104 is normal and uniform, thereby enhancing the thin film transistor and the display region 101 in the second pixel unit 1041 of the detection region 104.
  • the separation zone may be a bank structure (or a wall structure) to surround the detection zone, so that the chemical solution is locally concentrated in the detection zone, so that the concentration of the chemical liquid is relatively uniform, and the characteristics of the formed thin film transistor are uniform.
  • the separation zone may also be other structures that allow the properties of the thin film transistor of the detection zone to be hooked.
  • the bank structure can be obtained, for example, using the dummy pixel unit 1051, so that the structure of the detection region 104 and the partition region 105 can be similar, as shown in FIG.
  • the enlarged view on the right side of Fig. 5 shows a cross-sectional view of the second pixel unit 1041 and the third pixel unit 1051 in the detection area 104 and the separation area 105, respectively.
  • the array substrate provided by the embodiment of the invention includes a display area and a peripheral area, the peripheral area includes a detection area and a separation area, the detection area is provided with a second pixel unit for detecting, and the separation area is mainly used for ensuring the detection area second
  • the uniformity of the thin film transistor of the pixel unit ensures that the detection result is closer to the characteristics of the thin film transistor in the pixel unit of the display region, and the test structure is more accurate.
  • the separation area is provided with a third pixel unit 1051 (virtual pixel unit) for non-detection, as shown in FIG. 5.
  • the separation region includes a plurality of non-detection third pixel units 1051, and each of the third pixel units 1051 is correspondingly provided with a thin film transistor, and the third pixel unit 1051 and the correspondingly disposed thin film transistors are not used for detection. It can be fabricated simultaneously with the second pixel unit 1041 of the detection area, the concentration of the chemical solution in the separation area is small, the concentration of the chemical solution in the detection area is uniform, and the characteristics of the thin film transistor corresponding to the second pixel unit 1041 of the fabricated detection area are ensured. Evenly.
  • the pixel density of the third pixel unit 1051 of the separation region is not less than 10.
  • Pixel (pixel per inch) refers to the number of pixel units per inch of screen. The higher the pixel density, the richer the display details.
  • the conventional detection area since the number of pixel units is small, the characteristics of the thin film transistors of the pixel units in the detection area are not uniform, resulting in a large difference in detection results.
  • the pixel density of the third pixel unit of the separation area may be not less than 10.
  • the concentration of the drug solution in the detection zone is uniform, and the concentration of the drug solution in the separation zone at the edge is small, but since the thin film transistor of the separation zone is not used for detection, this can ensure the second pixel unit of the detection zone. Uniformity in the fabrication of thin film transistors.
  • a space is provided between the separation area 105 and the detection area 104.
  • the interval between the partition 105 and the detection zone 104 is greatly different from d. Since the separation zone 105 and the detection zone 104 are separated by a certain distance, the chemical liquid can be deposited in this zone, thereby reducing the influence of the change of the chemical concentration of the separation zone 105 on the detection zone 104.
  • the spacing d between the separation zone 105 and the detection zone 104 may be 15-100 ⁇ m. That is, as shown in Fig. 3, the separation distance d between the partition 105 and the detection zone 104 is 15-100 ⁇ m, including 15 ⁇ m and 100 ⁇ m. It should be noted that the separation distance between the separation area 105 and the detection area 104 is not limited to 15-100 ⁇ m. The embodiment of the present invention is only described by taking an example in which the separation distance is 15-100 ⁇ m, which is an example. The distance may also be ⁇ , that is, no interval is set; it may be less than 15 ⁇ m, but the interval is preferably not more than 100 ⁇ m.
  • the second pixel cells of the detection zone are arranged in a matrix of n*m, and for example, both n and m are positive integers greater than three.
  • the conventional detection area is only formed by detecting the characteristics of the thin film transistor of the display area. For example, only a few or nine pixel units are formed, that is, n and m are respectively 2 or n and m is 3, and then one or two of them are tested to determine the characteristics of the thin film transistor on the substrate. Since the number of thin film transistors produced in the detection area is small, the concentration of the drug solution during production is unevenly distributed, and the characteristics of the thin film transistor in the display region are largely different, and the characteristics of the thin film transistor in the display region cannot be truly reflected.
  • the characteristics of the thin film transistor formed are similar to those of the thin film transistor in the display region.
  • the n and m are 50, respectively.
  • only n and m are respectively taken as an example for illustration.
  • the third pixel unit of the separation zone may be in the same row as the second pixel unit of the detection zone.
  • the second pixel unit of the detection area is arranged in a matrix, and the third pixel unit of the separation area is in the same row as the second pixel unit of the detection area, that is, the second pixel unit and the third pixel unit form multiple rows and more Column, this is convenient to make.
  • the line width of the pixel unit of the peripheral area may be smaller than the line width of the first pixel unit of the display area.
  • the peripheral area includes a detection area and a separation area, and the line width is a line width of the data line and/or the gate line.
  • the line widths of the gate lines and the data lines of the second pixel unit of the detection area and the line widths of the gate lines and the data lines of the third pixel unit of the separation area are smaller than the line width of the first pixel unit of the display area.
  • the display area Due to the influence of the production process and the surrounding environment, in the initial stage of production, the display area
  • the line width of the domain is the same as the line width of the peripheral region, but the line width formed by the final display region and the peripheral region is different, and the line width formed by the peripheral region is larger than the line width of the display region, so that the characteristics of the thin film transistor are greatly different.
  • the line width formed by the peripheral area is different from the line width formed by the display area by about 0.8 ⁇ m. This difference is produced when the design line width and the actual line width are approximately 3 to 40 ⁇ m.
  • the line width of the pixel unit in the peripheral region may be made smaller than the first in the display region at the initial stage of fabrication of the array substrate. The line width of the pixel unit.
  • the line width a of the detection area and the line spacing b are as shown in Fig. 3.
  • the line width c of the display area can be referred to the line width of the detection area shown in Fig. 3.
  • the line width is a line width of the data line and/or the gate line, and the line spacing includes a line spacing between the gate lines and/or a line spacing between the data lines.
  • the line width is The line width of the gate lines, which is an example of the line spacing between the gate lines, will be described.
  • the higher the pixel density the greater the difference in line width between the detection area and the display area, and the greater the difference in the characteristics of the thin film transistor between the detection area and the display area. Then, in order to reduce the difference in the characteristics of the thin film transistors between the detection area and the display area, the difference in line width between the detection area and the display area is smaller, that is, the difference of a-c is reduced.
  • the line width of the peripheral area is made smaller than the line width of the display area.
  • the ratio of the line width a of the detection area to the line spacing b of the detection area is a constant value. It has been found through many practices that the ratio of the line width a of the detection zone to the line spacing b of the detection zone is about 0.7. Therefore, the line spacing can be set correspondingly according to the line width of the detection area.
  • the line width of the pixel unit of the peripheral area is smaller than the line width of the first pixel unit of the display area, the line spacing of the pixel unit of the peripheral area is greater than the first of the display area The line spacing of the pixel units.
  • Embodiments of the present invention provide a method of fabricating an array substrate, including forming a display region and a peripheral region on a substrate, the display region including a plurality of first pixel units for display, and the peripheral region including the detection region and A separation area surrounding the detection area, the detection area is provided with a second pixel unit for detection, and each second pixel unit is correspondingly provided with a thin film transistor.
  • the separation region can be used to make the characteristics of the thin film transistor of the second pixel unit of the detection region uniform.
  • the separation area is provided with a third pixel unit for non-detection.
  • the separation zone The third pixel unit has a pixel density of not less than 10.
  • the pixel density of the third pixel unit of the separation area may be not less than 10, the concentration of the chemical liquid or the like in the detection area is uniform, and the concentration of the chemical solution in the separation area of the edge is small, but since the thin film transistor of the separation area is not used for detection, This ensures uniformity of fabrication of the thin film transistors in the second pixel unit of the detection region.
  • a space is provided between the separation zone and the detection zone. As shown in FIG.
  • the separation zone 105 and the detection zone 104 are separated by a certain distance, the chemical liquid can be deposited in the zone, thereby reducing the influence of the concentration change of the chemical solution in the separation zone on the detection zone.
  • the separation zone and the detection zone are separated by 15-100 ⁇ m, including 15 ⁇ m and 100 ⁇ m.
  • the second pixel units of the detection area are arranged in a matrix of n *m, and the n and m are both positive integers greater than 3.
  • the n and m are 50, respectively.
  • the concentration of the chemical solution during production is unevenly distributed, and the characteristics of the thin film transistor in the display region are largely different, and the characteristics of the thin film transistor in the display region cannot be truly reflected.
  • the characteristics of the thin film transistor formed are similar to those of the thin film transistor in the display region.
  • the third pixel unit of the separation region is fabricated simultaneously with the second pixel unit of the detection region.
  • the gate lines, data lines, and the like of the separation region are simultaneously formed with the gate lines, data lines, and the like of the detection area, which may be formed by the same steps and processes, which is convenient for fabrication.
  • the line width of the pixel unit of the peripheral area is smaller than the line width of the first pixel unit of the display area.
  • the peripheral area includes a detection area and a separation area
  • the line width may be a data line and a line width of the gate line, that is, a line width of the second pixel unit of the detection area and a line width of the data line and a separation
  • the line widths of the gate lines and the data lines of the third pixel unit of the region are smaller than the line width of the first pixel unit of the display region, so that the characteristics of the thin film transistors of the detection region and the display region are closer.

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Liquid Crystal (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Thin Film Transistor (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种阵列基板，包括显示区域（101）和周边区域（103），显示区域（101）包括多个用于显示的第一像素单元（1011）；周边区域（103）包括检测区（104）和围绕检测区（104）的分隔区（105），在检测区（104）设置有用于检测的第二像素单元（1041），每一第二像素单元（1041）对应设置有薄膜晶体管。还公开了一种阵列基板的制作方法。

Description

阵列基板及其制作方法 技术领域
本发明的实施例涉及一种阵列基板及其制作方法。 背景技术
传统的液晶显示器包括： 阵列基板、 彩膜基板以及设置在阵列基板和彩 膜基板之间的液晶层。
如图 1所示， 在制作的前期， 阵列基板 100包括： 显示区域 101、 走线 区域 102和周边区域 103。 显示区域 101包括多个由交错设置的栅线和数据 线形成的像素单元， 每一像素单元包括一个薄膜晶体管。 走线区域 102包括 实现显示区域 101中的信号线电连接的信号元件， 例如显示区域 101数据线 信号的输入走线。 由于显示区域 101的各像素单元的薄膜晶体管受其他图层 的干扰， 很难对其的性能进行检测， 因此在所述基板的周边区域 103还设置 有检测区 104。
所述检测区 104如图 2所示， 包括由交错设置的栅线和数据线形成的像 素单元， 且每一像素单元包括一个薄膜晶体管， 用于检测基板上薄膜晶体管 的特性。 当阵列基板与彩膜基板贴合以形成显示面板后， 为了得到最终的液 晶面板， 检测区 104—般在对母板进行切割以得到单个面板的过程中会随周 边区域 103被切掉。
但由于检测区 104和显示区域 101上薄膜晶体管的制作有差异， 且检测 区的薄膜晶体管特性不均匀， 测试值相差较大， 无法反应真实结果。 发明内容
本发明的实施例提供了一种阵列基板及其制作方法， 使得所述阵列基板 上的检测区的薄膜晶体管特性均匀， 与显示区域的薄膜晶体管特性相近， 测 试结果更接近真实值。
本发明的实施例提供了一种阵列基板， 其包括显示区域和周边区域； 显 示区域包括多个用于显示的第一像素单元； 周边区域包括检测区和包括环绕 所述检测区的分隔区， 在所述检测区设置有用于检测的第二像素单元， 每一 第二像素单元对应设置有薄膜晶体管。
例如， 所述分隔区设置有非检测用的第三像素单元。
例如， 所述分隔区的第三像素单元的像素密度不小于 10。
例如， 所述分隔区与检测区之间设置有间隔。
例如， 所述分隔区和检测区之间间隔 15-100μηι。
例如， 所述检测区的第二像素单元以 n*m的矩阵形式排布， 且所述 n和 m均为大于 3的正整数。
例如， 所述 n和 m分别为 50。
例如，所述分隔区的第三像素单元与检测区的第二像素单元位于同一排。 例如， 在制作初期， 检测区域的第二像素单元的线宽小于显示区域的第 一像素单元的线宽。
本发明的实施例提供了一种阵列基板的制作方法， 其包括： 在衬底基板 上形成显示区域和周边区域； 显示区域包括多个用于显示的第一像素单元； 所述周边区域包括检测区以及环绕所述检测区的分隔区， 其中， 所述检测区 设置有用于检测的第二像素单元 ,每一第二像素单元对应设置有薄膜晶体管。
例如， 所述分隔区设置有非检测用的第三像素单元。
例如， 分隔区的第三像素单元与检测区的第二像素单元同时制作。
例如， 所述周边区域的像素单元的线宽小于显示区域的第一像素单元的 线宽。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 筒单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为传统的阵列基板俯视结构示意图；
图 2为传统的阵列基板上周边区域的结构示意图；
图 3A为本发明实施提供的一种阵列基板的平面示意图；
图 3B为本发明实施提供的一种阵列基板的周边区域的结构示意图； 图 4为本发明实施提供的另一种阵列基板的周边区域的结构示意图； 图 5为本发明实施提供的一种阵列基板的周边区域的截面示意图。
附图标记：
100-阵列基板； 101-显示区域； 1011-第一像素单元；
102-走线区域； 103-周边区域； 104-检测区；
1041-第二像素单元； 105-分隔区； 1051-第三像素单元。 具体实施方式
下面将结合本发明实施例中的附图， 对本发明实施例中的技术方案进行 清楚、 完整地描述， 显然， 所描述的实施例仅仅是本发明一部分实施例， 而 不是全部的实施例。
如图 3A和 3B所示，本发明的实施例提供了一种阵列基板， 其包括显示 区域 101和周边区域 103 , 显示区域 101包括多个按阵列排列的用于显示的 第一像素单元 1011 ; 周边区域 103包括检测区 104, 在所述检测区 104设置 有多个用于检测的第二像素单元 1041 (图 3B ) , 每一第二像素单元 1041对 应设置有薄膜晶体管（ TFT )。所述周边区域 103还包括环绕所述检测区 104 的分隔区 105。 所述分隔区 105可以使得检测区 104的薄膜晶体管的特性均 匀。
周边区域 103可设置在显示区域 101四周， 包括至少一个检测区 104, 该检测区域 104可以设置在阵列基板的至少一侧， 又比如设置在彼此相对的 两侧。在检测区 104内，所述每一像素单元 1041对应设置有至少一个薄膜晶 体管 （TFT ) , 可以是每一第二像素单元 1041对应设置有一个薄膜晶体管， 也可以是一个第二像素单元 1041对应设置有多个薄膜晶体管。下面以每一第 二像素单元 1041对应设置有一个薄膜晶体管为例进行详细说明。
在显示区域 101和周边区域 103之间， 还可以包括走线区域 102, 包括 实现显示区域 101中的信号线电连接的信号元件（未示出） 。
例如，检测区 104中用于检测的第二像素单元 1041也构成阵列，并且例 如可以与走线区域 102中的信号元件电连接。
传统的阵列基板的制备过程中在形成检测区时， 由于检测区的像素单元 较少， 在检测区的边缘的像素单元的药液的浓度较小， 在检测区的中间部分 的药液浓度较大指的是检测区域， 因而， 药液浓度的不均匀也导致了所形成 的薄膜晶体管的特性不一， 无法反应显示区域薄膜晶体管的特性。
本发明实施例的一个示例中， 如图 3A和 3B所示， 在周边区 103之中， 由于在所述检测区 104的四周还设置有分隔区 105 , 所以在阵列基板在制作 过程中， 可以保持用于制备检测区 104中的第二像素单元的药液（例如用于 构图工艺的蚀刻液）浓度正常、 均匀， 进而提升检测区 104的第二像素单元 1041中的薄膜晶体管与显示区域 101的第一像素单元 1011的薄膜晶体管的 特性的准确性。 例如， 所述分隔区可以是堤结构 （或挡墙区结构） ， 以将检 测区包围起来， 这样药液会局部聚集在检测区， 使得药液的浓度比较均匀， 形成的薄膜晶体管特性均匀。 当然， 分隔区还可以是可使得检测区的薄膜晶 体管的特性均勾的其他结构。 该堤结构例如可以使用虚拟像素单元 1051 得 到， 从而检测区 104与分隔区 105的结构可以是类似的， 如图 5所示。 该图 5 中右侧的放大图分别给出了检测区 104 与分隔区 105 中的第二像素单元 1041以及第三像素单元 1051的横截面示意图。
本发明实施例提供的阵列基板包括显示区域和周边区域， 周边区域包括 检测区和分隔区， 所述检测区设置有用于检测的第二像素单元， 所述分隔区 主要用于保证检测区第二像素单元的薄膜晶体管的均一性， 进而保证检测结 果与显示区域的像素单元中薄膜晶体管的特性更为接近， 测试结构更准确。
可选的， 所述分隔区设置有非检测用的第三像素单元 1051 (虚拟像素单 元），如图 5所示。例如，所述分隔区包括多个非检测用的第三像素单元 1051 , 且每一第三像素单元 1051对应设置有薄膜晶体管， 所述第三像素单元 1051 以及对应设置的薄膜晶体管均不用于检测， 其可以与检测区的第二像素单元 1041同时制作， 则在分隔区的药液浓度较小， 检测区的药液浓度均匀， 保证 制作的检测区的第二像素单元 1041对应的薄膜晶体管特性的均匀。
例如， 所述分隔区的第三像素单元 1051的像素密度不小于 10。 像素密 度（PPi, pixels per inch ) , 是指每英寸屏幕所拥有的像素单元的个数， 像素 密度越大， 显示画面细节就越丰富。 传统的检测区， 由于设置的像素单元较 少，则检测区的像素单元的薄膜晶体管特性不均匀，致使检测结果差异较大。
本发明实施例中， 所述分隔区的第三像素单元的像素密度可不小于 10。 药液等在检测区的浓度一致， 在边缘的分隔区的药液浓度较小， 但由于分隔 区的薄膜晶体管并不用于检测， 所以这样可以保证检测区的第二像素单元的 中薄膜晶体管的制作的均一性。
例如， 所述分隔区 105与检测区 104之间设置有间隔。 如图 3所示， 分 隔区 105和检测区 104之间间隔巨离 d。 由于分隔区 105和检测区 104之间 间隔一定距离， 则药液可以沉积在此区域内， 进而可以减轻分隔区 105药液 浓度变化对检测区 104的影响。
例如，所述分隔区 105和检测区 104之间间隔 d可以为 15-100μηι。 即如 图 3所示，分隔区 105和检测区 104之间间隔距离 d为 15-100μηι,包括 15μηι 和 100μηι。 需要说明的是， 分隔区 105和检测区 104之间的间隔距离也不局 限于 15-100μηι, 本发明实施例仅以其间隔距离在 15-100μηι为优选的实施例 为例进行说明，该间隔距离也可以是 Ομηι,即不设置间隔；也可以小于 15μηι, 但其间隔优选的不大于 100μηι。
例如， 所述检测区的第二像素单元以 n*m的矩阵形式排布， 且例如所述 n和 m均为大于 3的正整数。 需要说明的是， 传统的检测区， 由于只是检测 显示区域的薄膜晶体管的特性， 因此， 一般只是形成几个， 例如形成有 4个 或者 9个像素单元， 即 n和 m分别为 2或者 n和 m分别为 3 ,再对其中的一 两个进行检测， 确定基板上薄膜晶体管的特性。 由于检测区制作的薄膜晶体 管较少， 制作时的药水浓度等分布不均， 与显示区域薄膜晶体管的特性差别 较大， 无法真实反映显示区域的薄膜晶体管的特性。 本发明实施例中， 通过 增加检测区的薄膜晶体管的数量， 使其形成的薄膜晶体管的特性与显示区域 的薄膜晶体管的特性相近。例如， 所述 n和 m分别为 50。 图 4中仅以 n和 m 分别为 6为例进行示例说明。
例如，分隔区的第三像素单元可以与检测区的第二像素单元位于同一排。 检测区的第二像素单元以矩阵的形式排布， 分隔区的第三像素单元与所述检 测区的第二像素单元位于同一排， 即第二像素单元与第三像素单元形成多排 和多列， 这样方便制作。
例如， 在制作前期， 周边区域的像素单元的线宽可以小于显示区域的第 一像素单元的线宽。 需要说明的是， 周边区域包括检测区和分隔区， 所述线 宽为数据线和 /或栅线的线宽。 例如， 检测区的第二像素单元的栅线和数据线 的线宽以及分隔区的第三像素单元的栅线和数据线的线宽小于显示区域的第 一像素单元的线宽。 由于制作工艺和周边环境的影响， 在制作初期， 显示区 域的线宽和周边区域的线宽设置相同， 但最终显示区域和周边区域形成的线 宽不同， 周边区域形成的线宽大于显示区域的线宽， 进而使得薄膜晶体管的 特性差异较大。 且经过多次实践检测， 周边区域形成的线宽与显示区域形成 的线宽相差 0.8μηι左右。 该差值在该设计线宽和实际线宽大致为 3~40μηι时 候产生。 因此， 为了减小周边区域形成的像素单元的薄膜晶体管与显示区域 的像素单元的薄膜晶体管的特性差异， 可以在阵列基板的制作初期就使得周 边区域的像素单元的线宽小于显示区域的第一像素单元的线宽。
另外， 显示区域第一像素单元的线宽和周边区域的第二像素单元以及第 三像素单元的线宽具有以下关系： a=c-(x/200-a/b), 单位为 μηι, 其中， a为 检测区的线宽， c为显示区域的线宽， b为检测区的线间距， X为像素密度。 检测区的线宽 a以及线间距 b如图 3所示， 显示区域的线宽 c可以参照图 3 所示的检测区的线宽的设置。 所述线宽为数据线和 /或栅线的线宽， 所述线间 距包括栅线之间的线间距和 /或数据线之间的线间距； 本发明实施中， 以所述 线宽为栅线的线宽， 所述线间距为栅线之间的线间距为例进行说明。 且像素 密度越高， 检测区和显示区域的线宽差异越大， 检测区与显示区域的薄膜晶 体管特性差别越大。则为了减小检测区与显示区域的薄膜晶体管特性的差异， 使得检测区和显示区域的线宽差异越小， 即减小 a-c的差值。 即在制作前期 使得周边区域的线宽小于显示区域的线宽。 又由于传统的显示面板上像素密 度 X—般为定值， 则检测区的线宽 a和检测区的线间距 b的比为一定值。 经 过多次实践发现， 检测区的线宽 a和检测区的线间距 b的比约为 0.7。 因此， 可以根据检测区的线宽对线间距进行相应的设置。 且当显示区域和周边区域 的像素单元大小相同时， 若周边区域的像素单元的线宽小于显示区域的第一 像素单元的线宽， 则周边区域的像素单元的线间距大于显示区域的第一像素 单元的线间距。
本发明实施例提供了一种阵列基板的制作方法， 其包括在衬底基板上形 成显示区域和周边区域， 显示区域包括多个用于显示的第一像素单元； 所述 周边区域包括检测区以及环绕所述检测区的分隔区， 所述检测区设置有用于 检测的第二像素单元， 每一第二像素单元对应设置有薄膜晶体管。 该分隔区 可用于使得检测区的第二像素单元的薄膜晶体管的特性均匀。
例如， 所述分隔区设置有非检测用的第三像素单元。 例如， 所述分隔区 的第三像素单元的像素密度不小于 10。所述分隔区的第三像素单元的像素密 度可不小于 10, 药液等在检测区的浓度一致， 在边缘的分隔区的药液浓度较 小， 但由于分隔区域的薄膜晶体管不用于检测， 所以这样可以保证检测区的 第二像素单元的中薄膜晶体管的制作的均一性。 所述分隔区与检测区之间设 置有间隔。 如图 3所示， 分隔区 105和检测区 104之间间隔一定距离， 则药 液可以沉积在此区域内，进而可以减轻分隔区药液浓度变化对检测区的影响。 所述分隔区和检测区之间间隔 15-100μηι, 包括 15μηι和 100μηι。 所述检测区 的第二像素单元以 n*m的矩阵形式排布， 且所述 n和 m均为大于 3的正整 数。 所述 n和 m分别为 50。 由于， 检测区制作的薄膜晶体管较少， 制作时 的药水浓度等分布不均， 与显示区域薄膜晶体管的特性差别较大， 无法真实 反映显示区域的薄膜晶体管的特性。 本发明实施例中， 通过增加检测区的薄 膜晶体管的数量， 使其形成的薄膜晶体管的特性与显示区域的薄膜晶体管的 特性相近。
例如，分隔区的第三像素单元与检测区的第二像素单元同时制作。例如， 分隔区的栅线、 数据线等与检测区的栅线、 数据线等同时制作， 其可以是通 过同一步骤和工艺形成， 这样方便制作。
例如， 所述周边区域的像素单元的线宽小于显示区域的第一像素单元的 线宽。 需要说明的是， 所述周边区域包括检测区和分隔区， 所述线宽可以为 数据线以及栅线的线宽， 即检测区的第二像素单元的栅线和数据线的线宽以 及分隔区的第三像素单元的栅线和数据线的线宽小于显示区域的第一像素单 元的线宽， 以使得检测区和显示区域的薄膜晶体管的特性更加接近。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。

Claims

权利要求书
1、 一种阵列基板， 包括显示区域和周边区域，
其中， 所述显示区域包括多个用于显示的第一像素单元； 所述周边区域 包括检测区和环绕所述检测区的分隔区， 在所述检测区设置有用于检测的第 二像素单元， 每一所述第二像素单元对应设置有薄膜晶体管。
2、根据权利要求 1所述的阵列基板， 其中， 在所述分隔区设置有非检测 用的第三像素单元。
3、根据权利要求 2所述的阵列基板， 其中， 所述分隔区的第三像素单元 的像素密度不小于 10。
4、 根据权利要求 1-3任一所述的阵列基板， 其中， 所述分隔区与检测区 之间设置有一间隔。
5、根据权利要求 4所述的阵列基板， 其中， 所述分隔区和检测区之间的 间隔为 15-100μηι。
6、 根据权利要求 1-5任一所述的阵列基板， 其中， 所述检测区的第二像 素单元以 n*m的矩阵形式排布, 且所述 n和 m均为大于 3的正整数。
7、 根据权利要求 6所述的阵列基板， 其中， 所述 n和 m分别为 50。
8、根据权利要求 6所述的阵列基板， 其中， 在所述分隔区设置有非检测 用的第三像素单元， 所述分隔区的第三像素单元与检测区的第二像素单元位 于同一排。
9、 根据权利要求 1-8所述的阵列基板， 其中， 在制作初期， 检测区域的 第二像素单元的线宽小于显示区域的第一像素单元的线宽。
10、 一种阵列基板的制作方法， 包括： 在衬底基板上形成显示区域和周 边区域，
其中， 所述显示区域包括多个用于显示的第一像素单元； 所述周边区域 包括检测区以及环绕所述检测区的分隔区，
其中， 所述检测区设置有用于检测的第二像素单元， 每一所述第二像素 单元对应设置有薄膜晶体管。
11、根据权利要求 10所述的制作方法， 其中， 所述分隔区设置有非检测 用的第三像素单元。
12、根据权利要求 11所述的制作方法， 其中， 所述分隔区的第三像素单 元与检测区的第二像素单元同时制作。
13、 根据权利要求 11-12任一所述的制作方法， 其中， 所述检测区域的 像素单元的线宽小于所述显示区域的第一像素单元的线宽。
PCT/CN2013/085219 2013-07-30 2013-10-15 阵列基板及其制作方法 Ceased WO2015014022A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201310323825.2 2013-07-30
CN201310323825.2A CN103412419B (zh) 2013-07-30 2013-07-30 一种阵列基板及其制作方法

Publications (1)

Publication Number Publication Date
WO2015014022A1 true WO2015014022A1 (zh) 2015-02-05

Family

ID=49605446

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2013/085219 Ceased WO2015014022A1 (zh) 2013-07-30 2013-10-15 阵列基板及其制作方法

Country Status (2)

Country Link
CN (1) CN103412419B (zh)
WO (1) WO2015014022A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104090391A (zh) * 2014-06-27 2014-10-08 京东方科技集团股份有限公司 一种阵列基板和显示装置
CN104252098B (zh) * 2014-09-18 2019-03-01 京东方科技集团股份有限公司 相移掩膜板及其制作方法、阵列基板及其制作方法
CN116794866B (zh) * 2023-06-29 2024-05-10 京东方科技集团股份有限公司 显示面板、显示装置及母板

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002350802A (ja) * 2001-05-25 2002-12-04 Matsushita Electric Ind Co Ltd 液晶表示装置およびその製造方法
CN1892393A (zh) * 2005-07-01 2007-01-10 中华映管股份有限公司 有源元件阵列以及有源元件阵列的检测方法
CN101013233A (zh) * 1997-07-23 2007-08-08 精工爱普生株式会社 液晶装置及电子设备
US20080192197A1 (en) * 2007-02-08 2008-08-14 Kazuhiro Takahashi Liquid crystal display element and method for manufacturing the same
CN102169260A (zh) * 2010-10-15 2011-08-31 京东方科技集团股份有限公司 Tft-lcd像素电极层结构、制备方法及其掩膜板

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101013233A (zh) * 1997-07-23 2007-08-08 精工爱普生株式会社 液晶装置及电子设备
JP2002350802A (ja) * 2001-05-25 2002-12-04 Matsushita Electric Ind Co Ltd 液晶表示装置およびその製造方法
CN1892393A (zh) * 2005-07-01 2007-01-10 中华映管股份有限公司 有源元件阵列以及有源元件阵列的检测方法
US20080192197A1 (en) * 2007-02-08 2008-08-14 Kazuhiro Takahashi Liquid crystal display element and method for manufacturing the same
CN102169260A (zh) * 2010-10-15 2011-08-31 京东方科技集团股份有限公司 Tft-lcd像素电极层结构、制备方法及其掩膜板

Also Published As

Publication number Publication date
CN103412419B (zh) 2016-04-06
CN103412419A (zh) 2013-11-27

Similar Documents

Publication Publication Date Title
CN104777692B (zh) 阵列基板及制作方法、触控显示面板
US9927911B2 (en) Touch display panel and fabrication method thereof, and touch display apparatus
CN104503650B (zh) 一种内嵌式触摸屏及显示装置
US20160328055A1 (en) Touch panel and touch screen display device
US9772710B2 (en) Array substrate and manufacturing method thereof, touch screen and display apparatus
US10282005B2 (en) Touch display panel, manufacturing method and detecting method for the same
WO2016201838A1 (zh) 触控面板及其制备方法、触控显示装置
US10978493B2 (en) Display substrate and manufacturing method thereof, and display device
US9171869B1 (en) Array substrate and display device
WO2016119373A1 (zh) 阵列基板、触控面板及阵列基板的制作方法
WO2016078272A1 (zh) 一种基板及其制造方法、显示装置
WO2016180045A1 (zh) 自电容式指纹识别触摸屏及其制备方法、显示装置
WO2018040578A1 (zh) 阵列基板及其制造方法、显示面板和显示装置
WO2016192121A1 (zh) 自电容式内嵌触摸屏及其制备方法、液晶显示器
CN105047722A (zh) 一种薄膜晶体管及其制作方法、阵列基板、显示面板
WO2015184654A1 (zh) 一种基于hsd结构的tft-lcd显示面板及制作方法
CN104319274A (zh) 阵列基板及其制作方法、显示面板及显示装置
WO2016206133A1 (zh) 像素结构、阵列基板及显示装置
WO2017076158A1 (zh) 像素结构及其制作方法、阵列基板和显示面板
WO2014146349A1 (zh) 阵列基板及显示装置
WO2014015636A1 (zh) 阵列基板及其制备方法、显示装置
CN105892125A (zh) 一种彩膜基板、其制作方法、显示面板及显示装置
CN104330911A (zh) 一种显示面板及其制作方法、显示装置
CN103838048A (zh) 一种阵列基板及其制作方法、显示装置
CN104090678A (zh) 一种阵列基板、显示装置及其驱动方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 13890666

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 13890666

Country of ref document: EP

Kind code of ref document: A1