WO2015000202A1 - 阵列基板的扇出线结构及显示面板 - Google Patents

阵列基板的扇出线结构及显示面板 Download PDF

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Publication number
WO2015000202A1
WO2015000202A1 PCT/CN2013/080452 CN2013080452W WO2015000202A1 WO 2015000202 A1 WO2015000202 A1 WO 2015000202A1 CN 2013080452 W CN2013080452 W CN 2013080452W WO 2015000202 A1 WO2015000202 A1 WO 2015000202A1
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WIPO (PCT)
Prior art keywords
fan
conductive film
out line
additional
array substrate
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PCT/CN2013/080452
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English (en)
French (fr)
Inventor
杜鹏
施明宏
姜佳丽
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深圳市华星光电技术有限公司
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Priority to US14/113,582 priority Critical patent/US9204532B2/en
Publication of WO2015000202A1 publication Critical patent/WO2015000202A1/zh

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals

Definitions

  • the present invention relates to the field of display devices, and more particularly to a fan-out line structure of an array substrate and a display panel.
  • the liquid crystal panel is an important component of the liquid crystal display device, and the liquid crystal panel can display an image under the cooperation of the backlight module and the driving circuit.
  • a TFT array region 120 is disposed on the array substrate 100 of the liquid crystal panel, the TFT array region 120 is covered with signal lines 13, and the driving circuit board 130 passes through the fanout line 11 (fanout line)
  • the signal line 13 of the array substrate 100 is connected to the solder tail 12 of the driving circuit board 130, and the installation area of the fan-out line 11 is referred to as a fanout area 14.
  • solder tails 12 are closely arranged and the signal lines 13 are dispersedly arranged, that is, the distances between the solder tails 12 and the signal lines 13 are different, such that the fan-out lines 11 are disposed to cause uneven resistance, and fans of different lengths and different resistances are formed.
  • the outgoing line will distort the waveform of the signal, which will affect the display quality of the liquid crystal display device.
  • the technical problem to be solved by the present invention is to provide a fan-out line structure and a display panel of an array substrate having a small fan-out area, an excellent display effect when applied to a display device, and a narrower frame.
  • a fan-out line structure of an array substrate comprising: a first fan-out line and a second fan-out line disposed in a fan-out area of the array substrate; and a bottom portion of the second fan-out line
  • An additional conductive film is formed, and the additional conductive film and the first conductive film of the second fan-out line form an additional capacitance for reducing a difference in impedance between the fan-out lines, the size of the additional capacitance being The area of overlap between the additional conductive film and the first conductive film is determined.
  • only one layer of the first conductive film is disposed in the first fan-out line and the second fan-out line.
  • Fan-out The use of a single-layer conductive film on the wire can better avoid ESD (Electro-Static discharge) in the manufacturing process of the liquid crystal panel.
  • the width of the additional conductive film is greater than the width of the first conductive film.
  • Such a process can be more easily realized, and the width of the additional conductive film overlapping the first conductive film is not changed.
  • the additional conductive film is a plurality of traces which are laid along the direction of each of the second fan-out lines, wherein the length of the additional conductive film laid at the bottom of the second fan-out line of different lengths is different.
  • the coverage width is the same, so that different coverage lengths can be set according to the length of the fanout line, so that the corresponding coverage area can be conveniently calculated, and the corresponding additional capacitance value can be obtained.
  • the length of the additional conductive film laid on the bottom of the fan-out line is:
  • the length of an optional one of the first fan-out line and the second fan-out line, the long fan-out line is a reference line
  • the L 2 is a length of the second fan-out line
  • the L 22 is a length of an additional conductive film laid on the bottom of the fan-out line of the length L 2 , which is a relative dielectric constant of the liquid crystal layer in the liquid crystal panel, wherein the thickness is the thickness of the liquid crystal layer, a relative dielectric constant of a dielectric between the first conductive film and the additional conductive film, the d 2 being a thickness of the dielectric.
  • the reference line is the longest one of the first fanout line and the second fanout line.
  • the longest fan-out line is used as a reference to calculate the required coverage area for other fan-out lines, and the longest fan-out line has no need to add additional conductive film due to its large resistance.
  • the additional conductive film is a conductive film block covering a plurality of fan-out lines at the same time. This avoids the creation of complex mask patterns and is more convenient to implement in the process.
  • the dielectric between the additional conductive film and the first conductive film is a passivation insulating film.
  • the passivation film has a good insulating effect.
  • the first conductive film is a metal conductive film; and the additional conductive film is an indium tin oxide conductive film or a metal conductive film.
  • the metal conductive film has excellent electrical conductivity and less influence on signal delay.
  • the additional conductive film when the additional conductive film is selected as indium tin oxide, it can be realized in the panel process of FFS (Fringe Field Switching) structure. Because the bottom layer of the array substrate of the FFS structure is an indium tin oxide conductive film, and when the metal conductive film is selected as the additional conductive film, it can be realized in the process of the array substrate, such as the metal conductive film on the TFT of the array substrate. Or when the metal wiring film is used for other signal lines, these implementation processes only need to adjust the etching process, without adding a new mask process.
  • a fan-out line structure of an array substrate comprising:
  • the second fan-out line includes an additional conductive film formed on the bottom layer of the array substrate, a first insulating layer formed over the additional conductive film, a first conductive film formed over the first insulating layer, and formed in the a second insulating layer above the first conductive film;
  • An additional capacitor is formed between the additional conductive film and the first conductive film to reduce a difference in impedance between fan-out lines; the size of the additional capacitor is determined by the additional conductive film and the first conductive film The area of overlap between the two is determined.
  • a display panel comprising the fan-out line structure of any of the above.
  • an additional conductive film is laid on the bottom of the second fan-out line among the plurality of fan-out lines of the array substrate, and an additional capacitance is formed between the additional conductive film and the first conductive film of the second fan-out line.
  • the additional capacitance has a significant RC delay effect on the signal passing through the fan-out line. Therefore, for a fan-out line with a small resistance, the impedance of the fan-out line can be increased by adding a large additional capacitance, so that the signal is generated.
  • FIG. 1 is a schematic structural view of an array substrate in a conventional liquid crystal panel
  • FIG. 2 is a schematic view showing a fan-out line arrangement of a fan-out area of an array substrate in a conventional liquid crystal panel;
  • Figure 3 is a cross-sectional view in the direction of A in Figure 2
  • FIG. 4 is a schematic structural view of a fan-out line of a liquid crystal panel according to Embodiment 1 of the present invention.
  • Figure 5 is a cross-sectional view taken along line B in Figure 4,
  • FIG. 6 is a schematic view showing the structure of two fan outlet lines according to an embodiment of the present invention.
  • Figure 7 is a partial enlarged view of E in Figure 6,
  • FIG. 8 is a structural view showing the arrangement of three fan-out wires and an additional conductive film according to an embodiment of the present invention.
  • FIG. 9 is a view showing the arrangement structure of four fan-out wires and an additional conductive film according to an embodiment of the present invention.
  • Fig. 10 is a view showing the arrangement of another fan-out line and an additional conductive film according to a fourth embodiment of the present invention
  • Fig. 11 is a view showing the structure of the common line in Fig. 10.
  • the present embodiment provides a liquid crystal panel, which includes: an array substrate 100 and a color filter substrate 200, wherein the color filter substrate 200 includes: a glass substrate 203, the black matrix 202 and the ITO conductive film 201; and the fan-out line of the array substrate 100 is disposed in the fan-out area (refer to FIG. 4 and FIG. 5, and referring to FIG. 1 and FIG. 2, the present embodiment provides a liquid crystal panel, which includes: an array substrate 100 and a color filter substrate 200, wherein the color filter substrate 200 includes: a glass substrate 203, the black matrix 202 and the ITO conductive film 201; and the fan-out line of the array substrate 100 is disposed in the fan-out area (refer to FIG.
  • the structure thereof includes: a plurality of first fan-out lines 11a and a plurality of strips arranged on the glass substrate 103
  • the second fan-out line llx is provided with an additional conductive film 101 at the bottom of the second fan-out line llx, and the additional conductive film 101 is formed to form an attached surface with the first conductive film 106 of the second fan-out line 11x.
  • Adding a capacitance C x the size of the additional capacitance is determined by the overlapping area between the additional conductive film 101 and the first conductive film 106; in this embodiment, different sizes of additional capacitances are used.
  • the impedance difference between the first fan-out line 11a and the second fan-out line l lx or the second fan-out line llx is reduced.
  • the additional conductive film 101 is formed on the bottom layer of the array substrate 100, and has a first insulating layer 102 as a dielectric between the first conductive film 106 and a gate insulating layer (GI) formed on the array substrate. Simultaneously formed on the additional conductive film 101, and the first conductive film 106 is formed on the first insulating layer 102; a second insulating layer 104 is formed on the first conductive film 106.
  • the second insulating layer 104 is made of a passivation layer (PVA) having a good insulating effect, and the additional conductive film 101 can be combined with Array Com (Public Electrode), Ground ( Ground wire) or other electrodes are turned on.
  • PVA passivation layer
  • the additional conductive film 101 laid on the bottom of the different second fan-out lines l lx is different, wherein the second fan-out line l lx having a longer length has a larger resistance, and thus the length is longer.
  • the area of the additional conductive film 101 laid at the bottom of the long second fan-out line l lx is smaller than the area of the additional conductive film covered on the fan-out line 11 having a smaller length (as shown in FIG. 4). Since the additional conductive film 101 is different from the overlapping area of the first conductive film 106 in the second fan-out line l lx , the additional capacitance C x generated is also different.
  • the additional capacitor C x is a parasitic capacitor, and an RC delay is generated for the signal passing through the second fan-out line l lx . Therefore, for the second fan-out line l lx with a small resistance, the The additional capacitance C x exerts a delay on the signal to be synchronized with the signals of the longer first fan-out line 11a and the second fan-out line 11x, which themselves have a large delay.
  • the time constant ⁇ of the fanout line 11 signal delay can be calculated by the following formula:
  • the additional capacitance c x applied to each of the fan-out lines 11 is also different, and the size of the additional capacitance c x is laid in the second fan.
  • the bottom of the line l lx is related to the size of the area in which the first conductive film 106 overlaps. As shown in FIG. 3 and FIG.
  • the parasitic capacitance Q is also present between the first fan-out line 11a and the second fan-out line l lx that are not covered with the additional conductive film 101 and the ITO conductive film 201 on the color filter substrate 200.
  • Q is formed by the first conductive film 104 of the fan-out line 11, the second conductive film 106, and the ITO conductive film 201.
  • This parasitic capacitance ⁇ due to the large thickness of the liquid crystal layer, its size is much smaller than the additional capacitance C x , so its RC delay is also limited, although, in order to calculate the accuracy, in calculating the effect of the capacitance on the fan-out line, Also count it.
  • the parasitic capacitance between the fan-out line 11 and the ITO conductive film 201 can be calculated according to the following formula:
  • ⁇ r are the absolute dielectric constant and the relative dielectric constant of the liquid crystal, respectively
  • L and W represent the length and width of the fan-out line, respectively
  • d is the thickness of the liquid crystal layer, which is generally about 3 to 4 ⁇ ⁇ .
  • the additional conductive film 106 is designed to have a constant width, and a plurality of traces are laid along the direction of each of the second fan-out lines l lx , wherein the additional conductive lines laid on the bottom of the second fan-out line l lx of different lengths are provided.
  • the length of the membrane 106 is different.
  • the width of the additional conductive film 101 is the same as the width of the second fan-out line l lx, so that the width of the overlapping portion of the additional conductive film 101 and the first conductive film 106 is the same, so as to facilitate Calculation.
  • one of the plurality of fanout lines needs to be selected as the reference line.
  • the longest one of the first fanout lines 11a is selected in this embodiment. l is used as a reference line, and the size of the capacitance formed between the bottom additional conductive film 101 and the second fan-out line l lx is calculated by using the longest l is in the first fan-out line 11a as a reference, so that the calculation should be covered.
  • the specific calculation process is as follows: Let the resistances of the longest one l is and the second fan out l lx of the first fan-out line 11a as the reference line be Ri and R 2 , respectively, and their calculations are as follows:
  • the capacitance is mainly the first conductive film 106 and the second conductive film in the fan-out line 11.
  • 104 is formed with the ITO conductive film 201 on the color filter substrate 200.
  • Cl ie, C LC
  • 5 ⁇ is the relative dielectric constant of the liquid crystal in the liquid crystal panel
  • W is the length and width of the longest l is in the first fan-out line 11a, respectively, which is the thickness of the liquid crystal layer in the liquid crystal panel, wherein Can be calculated by the current layout tool (the layout tool is a designer-specific tool).
  • the time constant ⁇ is:
  • ⁇ r2 and d 2 represent that the relative dielectric constant ⁇ r of the first insulating layer 102 and the liquid crystal are not much different, but since the thickness is small, the new capacitance C x is much larger than the fan-out line and the area is equal.
  • the capacitance formed by the TIO conductive film on the color filter substrate is as shown in Fig. 5 in the present embodiment, and C x is generally about 10 times that of ⁇ (i.e., C 21 ).
  • Capacitor C 21 and capacitor C 22 are in parallel relationship, so the capacitance C 2 of the entire fan-out line llx is:
  • the first conductive film 106 is a metal conductive film, and the metal conductive film has excellent electrical conductivity and less influence on signal delay.
  • the additional conductive film 101 may be selected from an indium tin oxide conductive film (ITO) or a metal conductive film.
  • ITO indium tin oxide conductive film
  • the first fan-out line 11a and the second fan-out line l lx of the embodiment are only provided with a first conductive film 106 for signal transmission.
  • the fan-out line structure using a single-layer conductive film can be used in liquid crystal. ESD (Electro-Static discharge) is better avoided in the manufacturing process of the panel.
  • the additional conductive film 101 is selected as an indium tin oxide conductive film (ITO), it can be realized in a panel process of an FFS (Fringe Field Switching) structure, because the bottom layer of the array substrate of the FFS structure is indium oxide. Tin conductive film.
  • the additional conductive film 101 is selected as the metal conductive film, it can be realized in the process of the array substrate, such as when the array substrate is completed on the metal conductive film on the TFT or the metal conductive film on other signal lines, and these implementation processes only need to be performed. The adjustment of the etch process can be performed without adding a new mask process.
  • the second fan-out line l lx For the second fan-out line l lx with a short linear distance between the two end points, the second fan-out line l lx is taken.
  • a winding portion 121 is disposed in the line, and the length of the second fan-out line l lx is increased by providing the winding portion 121, and at the same time, the additional conductive film 101 is added on the basis of the winding to form an additional capacitance C X , thereby reducing
  • the winding can be selected simultaneously with the laying of the additional conductive film.
  • this solution is more suitable, which can solve the problem that the fan-out area has a large height H due to too many windings, and can solve the problem of fan-out line signal synchronization.
  • the difference from the first embodiment is that the width of the additional conductive film 101 in this embodiment is smaller than the width of the second fan-out line 11A, and different widths can be selected according to the size of the panel and the process requirements.
  • Embodiment 3 is that the width of the additional conductive film 101 in this embodiment is smaller than the width of the second fan-out line 11A, and different widths can be selected according to the size of the panel and the process requirements.
  • the width of the additional conductive film 101 is larger than the width of the second fan-out line llx. This embodiment can ensure that the width of the overlapping portion of the additional conductive film 101 and the first conductive film is always The width of the first conductive film is the same, thereby ensuring the accuracy of obtaining additional capacitance.
  • the present embodiment uses a monolithic triangular-shaped conductive film block to be laid under a plurality of fan-out lines to achieve an additional capacitance between the fan-out lines. This method is more convenient in the manufacturing process of the panel, does not need to make a complicated mask, and the production cost is relatively low.
  • the fan-out line and the COM electrode trace may be overlapped. Therefore, the additional conductive film 101 may be formed when the common line is formed. .
  • the common conductive film 101 having a triangular conductive film block shape is disposed in a portion overlapping the second fan-out line llx, and the triangular shape is arranged between the second fan-out lines llx.
  • the cloth has different sizes of the additional capacitance C x formed between the second fan-out lines llx.
  • the size of the obtuse angle of the triangle can be adjusted approximately, so that the additional capacitance C on each fan-out line can solve the technical result. , thereby reducing the impedance difference between the fanout lines.
  • the shape of the conductive film block is not limited to the shape of a triangle, and the hyperbola, the convex portion may be elliptical, parabolic or other shapes.

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Abstract

提供了一种阵列基板（100）的扇出线结构及显示面板，扇出线结构包括：布置在阵列基板（100）扇出区的第一扇出线（11a）以及第二扇出线（11x）；第二扇出线（11x）底部设置有附加导电膜（101），附加导电膜（101）与第二扇出线（11x）的第一导电膜（106）之间形成一个用以减小扇出线之间的阻抗差异的附加电容（Cx），附加电容（Cx）的大小由附加导电膜（101）与第一导电膜（106）之间的重叠面积确定。

Description

阵列！ ^的扇出线结构及显示面板
【技术领域】
本发明涉及显示装置领域， 更具体的说， 涉及一种阵列基板的扇出线结构 及显示面板。
【背景技术】
液晶面板是液晶显示装置的重要组件， 在背光模组的配合以及驱动电路的 驱动下， 液晶面板能够显示出图像。
如图 1、 图 2及图 3所示， 在液晶面板的阵列基板 100上设置有 TFT阵列 区域 120, TFT阵列区域 120内布满了信号线 13 , 驱动电路板 130通过扇出线 11 ( fanout line )将阵列基板 100的信号线 13与驱动电路板 130的焊脚 12连接， 而扇出线 11的设置区域则称为扇出区 14 ( fanout area )。
由于焊脚 12紧密排列而信号线 13分散排列，也就是说焊脚 12到信号线 13 的距离各不相同， 这样扇出线 11设置之后就造成了电阻不均的情况， 不同长度 不同电阻的扇出线会使信号的波形发生变形， 从而会影响液晶显示装置的显示 质量。
【发明内容】
本发明所要解决的技术问题是提供一种扇出区高度小、 应用于显示装置时 显示效果更优秀、 边框更窄的阵列基板的扇出线结构及显示面板。
本发明的目的是通过以下技术方案来实现的： 一种阵列基板的扇出线结构， 包括： 布置在阵列基板扇出区的第一扇出线以及第二扇出线； 所述第二扇出线 底部设置有附加导电膜， 所述附加导电膜与所述第二扇出线的第一导电膜之间 形成一个用以减小扇出线之间的阻抗差异的附加电容， 所述附加电容的大小由 所述附加导电膜与所述第一导电膜之间的重叠面积确定。
优选的， 所述第一扇出线、 第二扇出线内仅设置有一层第一导电膜。 扇出 线采用单层导电膜可以在液晶面板的制程中更好的避免发生 ESD ( Electro-Static discharge, 静电释放）。
优选的， 所述附加导电膜的宽度大于所述第一导电膜宽度。 这样制程中可 以更容易实现， 并且保证附加导电膜与所述第一导电膜重叠的宽度不变。
优选的， 所述附加导电膜为宽度不变， 沿所述每条第二扇出线的走向铺设 的多条走线， 其中， 不同长度的第二扇出线底部铺设的附加导电膜的长度不同。 覆盖宽度相同， 从而可以根据扇出线长度的不同而设置不同的覆盖长度， 这样 可以方便计算对应的覆盖面积， 进而获得相应的附加电容值。
优选的， 所述扇出线底部铺设的附加导电膜的长度为：
Figure imgf000003_0001
( 2- 2 ) /L2(di£r2-d2£ri);
所述 为所述第一扇出线以及第二扇出线中任选的一条扇出线的长度， 该 长的扇出线为参照线， 所述 L2为所述第二扇出线的长度， 所述 L22为所述长 为 L2的扇出线底部铺设的附加导电膜的长度，所述 为液晶面板中液晶层的相 对介电常数， 所述 ^为所述液晶层的厚度， 所述 为所述第一导电膜与所述附 加导电膜之间的电介质的相对介电常数， 所述 d2为所述电介质的厚度。
优选的， 所述参照线为所述第一扇出线以及第二扇出线中最长的一条。 利 用最长的扇出线作为参照， 以计算其它扇出线所需要的覆盖面积， 而最长的扇 出线由于本身电阻较大， 不需要再增加附加导电膜。
优选的， 所述附加导电膜为同时覆盖多条扇出线的导电膜区块。 这样可以 避免制造复杂的掩膜图案， 在制程中更方便实现。
优选的， 所述附加导电膜与所述第一导电膜之间的电介质为钝化绝缘膜。 钝化膜拥有良好的绝缘效果。
优选的， 所述第一扇出线以及第二扇出线中， 两个端点的直线距离比其它 扇出线的两个端点的直线距离小的扇出线设置有用于加长该扇出线的绕线部。 由于扇出线对信号波形的影响是电阻 R以及寄生电容 C的综合影响， 扇出线信 号延迟的时间常数为 T =RC, 需要使每一条的扇出线的信号延迟的时间常数相 等， 则可以同时对电阻 R以及电容 C进行调整， 以达到最佳的工艺要求、 设计 要求以及产品要求， 而对电阻 R直接调整的话则可以通过增加扇出线的长度实 现， 本方案则是通过既增加扇出线的长度， 又设置附加电容来实现各扇出线之 间的阻抗差异减小。
优选的， 所所述第一导电膜为金属导电膜； 所述附加导电膜为氧化铟锡导 电膜或金属导电膜。 金属导电膜的导电效果优秀， 信号延时影响较小， 对于附 加导电膜，当附加导电膜选用为氧化铟锡时，可以在 FFS( Fringe Field Switching, 边缘场开关技术） 结构的面板制程中实现， 因为 FFS结构的面板的阵列基板最 底层是氧化铟锡导电膜， 而对于附加导电膜选用为金属导电膜时， 可以在阵列 基板的工艺中实现， 如阵列基板在完成 TFT上的金属导电膜或其它信号线时的 金属导电膜时实现， 这些实现过程只需要对蚀刻制程进行筒单的调整即可， 而 不会增加新的掩膜工艺。
一种阵列基板的扇出线结构， 包括：
布置在阵列基板扇出区的第一扇出线以及第二扇出线；
所述第二扇出线包括形成在阵列基板底层的附加导电膜， 形成在附加导电 膜之上的第一绝缘层， 形成在所述第一绝缘层之上的第一导电膜， 以及形成在 所述第一导电膜之上的第二绝缘层；
所述附加导电膜与所述第一导电膜之间形成一个用以减小扇出线之间阻抗 差异的附加电容； 所述附加电容的大小由所述附加导电膜与所述第一导电膜之 间的重叠面积确定。
一种显示面板， 包括上述任一所述的扇出线结构。
本发明通过在阵列基板的多条扇出线中， 在第二扇出线的底部铺设有附加 导电膜， 所述附加导电膜与第二扇出线的第一导电膜之间形成一附加电容。 该 附加电容对通过扇出线的信号会产生明显 RC延迟效果， 因而，对于电阻较小的 扇出线来说， 可以通过添加较大的附加电容来使扇出线的阻抗变大， 使其对信 号产生延迟的影响， 这样其与较长、 电阻较大的扇出线的信号达到同步的状态； 另， 由于采用在扇出线底部设置附加导电膜， 从而可以在阵列基板的前面几道 掩膜制程中实现， 在前面几道掩膜制程中形成的 ITO导电膜、 金属导电膜等都 可以在制程中将这些导电膜同时形成在扇出线设置区域形成所述附加导电膜。 【附图说明】
图 1是现有液晶面板中阵列基板的结构示意图，
图 2是现有液晶面板中阵列基板的扇出区的扇出线布置示意图，
图 3是图 2中 A方向剖面图，
图 4是本发明实施例一的液晶面板扇出线结构示意图，
图 5是图 4中 B方向剖面图，
图 6是本发明实施例二扇出线结构示意图，
图 7是图 6中 E的局部放大图，
图 8是本发明实施例三扇出线与附加导电膜的设置结构图，
图 9是本发明实施例四扇出线与附加导电膜的设置结构图，
图 10是本发明实施例四另一种扇出线与附加导电膜的设置结构图， 图 11是图 10中共通线结构图。
【具体实施方式】
下面结合附图和较佳的实施例对本发明作进一步说明。
实施例一
如图 4及图 5所示， 并参考图 1及图 2, 本实施例提供一种液晶面板， 该液 晶面板包括： 阵列基板 100以及彩膜基板 200, 其中， 彩膜基板 200包括： 玻璃 基板 203、 黑矩阵 202以及 ITO导电膜 201 ; 而阵列基板 100的扇出线设置在扇 出区 （参考图 1 ), 其结构包括： 布置在玻璃基板 103的多条第一扇出线 11a以 及多条第二扇出线 llx, 所述第二扇出线 llx底部设置有附加导电膜 101 , 所述 附加导电膜 101用以与所述第二扇出线 llx的第一导电膜 106之间形成一个附 加电容 Cx，所述附加电容(^的大小由所述附加导电膜 101与所述第一导电膜 106 之间的重叠面积确定； 在本实施例中， 不同大小的附加电容 (^用以减小所述第 一扇出线 11a与所述第二扇出线 l lx之间，或第二扇出线 llx相互之间的阻抗差 异。
附加导电膜 101形成在阵列基板 100的底层， 与第一导电膜 106之间具有第 一绝缘层 102作为电介质， 该第一绝缘层为在阵列基板上形成栅极绝缘层（GI, gate insulator ) 的同时形成在所述附加导电膜 101之上， 而所述第一导电膜 106 则是形成在所述第一绝缘层 102之上； 在第一导电膜 106之上形成有第二绝缘 层 104, 用以保护第一导电膜 106, 该第二绝缘层 104采用拥有良好绝缘效果的 钝化绝缘层（PVA, passivation layer ), 所述附加导电膜 101可以与 Array Com (公共电极）、 Ground (接地线）或其他电极导通。
如图 4所示， 不同的第二扇出线 l lx之间， 其底部所铺设的附加导电膜 101 也是不同的， 其中， 长度较长的第二扇出线 l lx 的电阻较大， 因而长度较长的 第二扇出线 l lx底部所铺设的附加导电膜 101的面积小于长度较小的扇出线 11 上覆盖的附加导电膜的面积（如图 4所示）。 因为， 由于附加导电膜 101与第二 扇出线 l lx内的第一导电膜 106的重叠面积不同，产生的附加电容 Cx也是不同 的。 而所述附加电容 Cx是一个寄生的电容， 对通过第二扇出线 l lx的信号会产 生 RC延迟（RC delay ), 因而， 对于电阻较小的第二扇出线 l lx来说， 可以通 过附加电容 Cx来对信号产生延迟的影响， 使其与本身存在较大延迟的较长的第 一扇出线 11a以及第二扇出线 llx的信号达到同步的状态。 扇出线 11信号延迟 的时间常数 τ我们可以通过以下公式计算：
x =RC
其中， R为扇出线的电阻， C为电容。 也就是说， 扇出线 11信号延迟的时间 常数是电阻 R以及电容 C共同作用的结果。因此，只需对应的在第二扇出线 l lx 上施加相应的附加电容即可达到信号同步的目的。
由于第一扇出线 11a与第二扇出线 l lx的长度不同， 多条第二扇出线 llx相 互之间的长度也不同， 因而其电阻不同， 要达到信号同步的状态， 则施加在各 条扇出线 11上的附加电容 cx也不同，而附加电容 cx的大小与其铺设在第二扇 出线 l lx底部并与第一导电膜 106重叠的面积大小相关。 如图 3及图 5所示， 没有覆盖附加导电膜 101的第一扇出线 11a以及第二扇出线 l lx与彩膜基板 200 上的 ITO导电膜 201之间也存在寄生电容 Q , 该寄生电容 Q 由扇出线 11的 第一导电膜 104、 第二导电膜 106与 ITO导电膜 201形成。 这个寄生电容 Ο 由于液晶层的厚度较大， 其大小远远小于附加电容 Cx, 因而其所造成的 RC延 迟也有限， 虽然这样， 为了计算的准确， 在计算电容对扇出线的影响时， 也要 将其计算在内。扇出线 11与 ITO导电膜 201之间的寄生电容大小可以按照下面 的计算公式算出：
Figure imgf000007_0001
d d
其中 ε。和 ε r分别是绝对介电常数和液晶相对介电常数， L和 W分别表示扇 出线的长度和宽度， d是液晶层的厚度， 一般为 3 ~ 4 μ ηι左右。
下面， 我们通过计算应当在一条第二扇出线 l lx底部铺设附加导电膜 101的 面积的大小对本发明进一步进行说明。
为方便计算，附加导电膜 106设计成为宽度不变，沿所述每条第二扇出线 l lx 的走向铺设的多条走线， 其中， 不同长度的第二扇出线 l lx底部铺设的附加导 电膜 106的长度不同。 在本实施例中， 附加导电膜 101的宽度与所述第二扇出 线 l lx的宽度一致， 从而附加导电膜 101与所述第一导电膜 106的重叠部分的 宽度是相同的， 以便于进行计算。
要确定附加电容在第二扇出线 l lx底部的铺设长度， 需要在多条扇出线中选 出一条作为参照线， 如图 4所示， 本实施例选用第一扇出线 11a中最长的一条 l is作为参照线， 以第一扇出线 11a中最长的一条 l is作为参照计算出底部附加 导电膜 101与第二扇出线 l lx之间形成的电容的大小， 从而计算应该覆盖在第 二扇出线 l lx底部应当铺设的附加导电膜 101的长度。 具体计算过程如下： 设作为参照线的第一扇出线 11a中最长的一条 l is以及第二扇出线 l lx的电 阻分别为 Ri和 R2, 它们的计算如下：
^ 1
W s 2
W
对于没有任何附加导电膜覆盖的第一扇出线 11a中最长的一条 l is来说， 如 图 3-5所示， 其电容主要是扇出线 11 内的第一导电膜 106、 第二导电膜 104与 彩膜基板 200上的 ITO导电膜 201形成，我们可以设其寄生电容为 Cl(即 CLC ), 则 al 其中， ε。是绝对介电常数， 5 ^是液晶面板中液晶的相对介电常数， W 是分别是第一扇出线 11a中最长的一条 l is的长度和宽度， 是液晶面板中液晶 层的厚度， 其中 可以通过现在 layout (扇出）工具计算得到（ layout工具为设 计人员专用工具）。 对于第一扇出线 11a 中最长的一条 l is来讲， 时间常数^ 为：
S · £ο ' £r\ ·
Figure imgf000008_0001
由于时间常数只和 的平方成正比，所以可以得出结论： 整个扇出区的扇出 线中两侧的最长的 l is的时间常数最大， 即 τ 在这里的算法中， 就以这个时 间常数为基准， 这样可以更方便计算其它所有扇出线应当铺设的附加导电膜长 度。
设第二扇出线 l lx底部没有铺设附加导电膜 101部分的长度为 L21 , 底部铺 设有附加导电膜 101部分长度为 L22, 它们满足以下关系：
2 = L21 + L22 底部没有铺设附加导电膜 101部分的电容 c21 (与彩膜基板侧形成的电容）： 底部铺设有附加导电膜 101的部分的电容 c22:
Figure imgf000009_0001
其中 ε r2和 d2分别代表第一绝缘层 102的相对介电常数 ε r和液晶相差不大， 但由于厚度小， 所以在面积相等的情况下新的电容 Cx会远远大于扇出线和彩膜 基板上 TIO导电膜形成的电容， 如本实施例中图 5所示， Cx—般是 Ο (即 C21 ) 的 10倍左右。
电容 C21与电容 C22为并联关系， 因此整个扇出线 llx的电容 C2:
c = c + C 在调整扇出线的阻抗时， 以扇出线 lis的时间常数 τ ι为基准：
τ2 = R2 C2 = τγ 从这个由此可以建立方程
Figure imgf000009_0002
h2{dxsrl—d2srl) 其中 L22即是在第二扇出线 llx底部应该铺设的附加导电膜 101的长度。 由此我们可以知道第二扇出线 llx底部应当铺设的附加导电膜 101 的面积
Θ
疋：
S=WL22
在本实施例中， 所述第一导电膜 106为金属导电膜， 金属导电膜的导电效果 优秀， 信号延时影响较小。 而所述附加导电膜 101 则可以选用为氧化铟锡导电 膜（ITO )或者金属导电膜。 值得注意的是， 本实施例的第一扇出线 lla、 第二扇出线 l lx仅设置有一层 第一导电膜 106用以实现信号传递， 这种采用单层导电膜的扇出线结构可以在 液晶面板的制程中更好的避免发生 ESD ( Electro-Static discharge, 静电释放）。
当附加导电膜 101选用为氧化铟锡导电膜（ ITO )时，可以在 FFS( Fringe Field Switching, 边缘场开关技术） 结构的面板制程中实现， 因为 FFS结构的面板的 阵列基板最底层是氧化铟锡导电膜。 而当附加导电膜 101选用为金属导电膜时， 可以在阵列基板的工艺中实现， 如阵列基板在完成 TFT上的金属导电膜或其它 信号线时的金属导电膜时实现， 这些实现过程只需要对蚀刻制程进行筒单的调 整即可， 而不会增加新的掩膜工艺。
由于扇出线对信号波形的影响是电阻 R以及寄生电容 C的综合影响，扇出线 信号延迟的时间常数为 T =RC,也就是说，需要使每一条的扇出线的信号延迟的 时间常数相等， 可以同时对电阻 R以及电容 C进行调整， 以达到最佳的工艺要 求、 设计要求以及产品要求。 因此， 作为本实施例的一种改进， 如图 4所示， 也可以通过缩小扇出线之间的长度差异来缩小阻抗差异， 如图中可看出， 不同 扇出线之间， 一个端点到另一该端点的直线距离具有差异， 如第一扇出线 11a 与第二扇出线 l lx, 对于两个端点直线距离较短的第二扇出线 l lx来说， 在第二 扇出线 l lx的走线中设置有绕线部 121 , 通过设置绕线部 121使得第二扇出线 l lx的长度得以增加， 同时， 在绕线的基础上增加底部附加导电膜 101形成附加 电容 CX, 从而可以减少绕线长度， 对于电阻与参照线的时间常数相差太大的扇 出线来说， 可以选择绕线与铺设附加导电膜同时进行。 特别是针对较大尺寸的 液晶电视来说， 这种方案更为合适， 既可以解决扇出区由于绕线过多而高度 H 较大的问题， 又可以解决扇出线信号同步的问题。
实施例二
如图 6及图 7所示， 与实施例一不同的是， 本实施例中附加导电膜 101的宽 度小于第二扇出线 11χ 的宽度， 根据面板的大小及工艺需求， 可以选择不同的 宽度。 实施例三
如图 8所示为另一种实施方式， 附加导电膜 101的宽度大于第二扇出线 llx 的宽度， 这种实施方式可以保证附加导电膜 101 与第一导电膜的重叠部分的宽 度始终是与所述第一导电膜的宽度是相同的， 从而保证了获得附加电容的精确 度。
实施例四
如图 9所示， 与上述实施例均不同的是， 本实施例采用一整块呈三角形形状 的导电膜区块铺设在多根扇出线之下， 达到与扇出线之间形成附加电容的目的， 此种方式在面板的制程中显得更为筒便， 不需要制作复杂的掩膜， 制作成本相 对较低。
另外， 针对的窄边框的液晶面板设计中， 为了起到节约空间的目的， 可以把 扇出线和 COM电极走线（共通线）重叠， 因此， 也可以在形成共通线的时候形 成附加导电膜 101。 如图 10及图 11所示， 共通线 108与各条第二扇出线 llx重 叠部分设置有呈三角形导电膜区块形状的附加导电膜 101 ,三角形的形状在第二 扇出线 llx之间的排布使得其各第二扇出线 llx之间形成的附加电容 Cx的大小 不同， 根据上述实施例的计算， 可以近似的调整三角形钝角的大小， 使各条扇 出线上的附加电容 C解决技术结果， 从而减小扇出线之间阻抗差异。 当然， 导 电膜区块的形状也不限于三角形的形状， 双曲线、 凸起部分呈橢圓、 抛物线或 其它形状也可以。
以上内容是结合具体的优选实施方式对本发明所作的进一步详细说明， 不能 认定本发明的具体实施只局限于这些说明。 对于本发明所属技术领域的普通技 术人员来说， 在不脱离本发明构思的前提下， 还可以做出若干筒单推演或替换， 都应当视为属于本发明的保护范围。

Claims

权利要求
1、 一种阵列基板的扇出线结构， 包括：
布置在阵列基板扇出区的第一扇出线以及第二扇出线；
所述第二扇出线底部设置有附加导电膜， 所述附加导电膜与所述第二扇出 线的第一导电膜之间形成一个用以减小扇出线之间的阻抗差异的附加电容， 所 述附加电容的大小由所述附加导电膜与所述第一导电膜之间的重叠面积确定。
2、 如权利要求 1所述的阵列基板的扇出线结构， 其中， 所述第一扇出线、 第二扇出线内仅设置有一层第一导电膜。
3、 如权利要求 1所述的阵列基板的扇出线结构， 其中， 所述附加导电膜为 宽度不变， 沿所述每条第二扇出线的走向铺设的多条走线， 其中， 不同长度的 第二扇出线底部铺设的附加导电膜的长度不同。
4、 如权利要求 3所述的阵列基板的扇出线结构， 其中， 所述扇出线底部铺 设的附加导电膜的长度为：
Figure imgf000012_0001
( Li2-L2 2 ) /L2(di£r2-d2£ri);
所述 为所述第一扇出线以及第二扇出线中任选的一条扇出线的长度，该 长的扇出线为参照线， 所述 L2为所述第二扇出线的长度， 所述 L22为所述长 为 L2的扇出线底部铺设的附加导电膜的长度，所述 为液晶面板中液晶层的相 对介电常数， 所述 ^为所述液晶层的厚度， 所述 为所述第一导电膜与所述附 加导电膜之间的电介质的相对介电常数， 所述 d2为所述电介质的厚度。
5、 如权利要求 4所述的阵列基板的扇出线结构， 其中， 所述参照线为所述 第一扇出线以及第二扇出线中最长的一条。
6、 如权利要求 1所述的阵列基板的扇出线结构， 其中， 所述附加导电膜为 同时覆盖多条扇出线的导电膜区块。
7、 如权利要求 1所述的阵列基板的扇出线结构， 其中， 所述第一扇出线以 及第二扇出线中， 两个端点的直线距离比其它扇出线的两个端点的直线距离小 的扇出线设置有用于加长该扇出线的绕线部。
8、 如权利要求 1所述的阵列基板的扇出线结构， 其中， 所述第一导电膜为 金属导电膜； 所述附加导电膜为氧化铟锡导电膜或金属导电膜。
9、 一种阵列基板的扇出线结构，， 包括：
布置在阵列基板扇出区的第一扇出线以及第二扇出线；
所述第二扇出线包括形成在阵列基板底层的附加导电膜， 形成在附加导电 膜之上的第一绝缘层， 形成在所述第一绝缘层之上的第一导电膜， 以及形成在 所述第一导电膜之上的第二绝缘层；
所述附加导电膜与所述第一导电膜之间形成一个用以减小扇出线之间阻抗 差异的附加电容； 所述附加电容的大小由所述附加导电膜与所述第一导电膜之 间的重叠面积确定。
10、 一种显示面板， 包括：
布置在阵列基板扇出区的第一扇出线以及第二扇出线；
所述第二扇出线底部设置有附加导电膜， 所述附加导电膜与所述第二扇出 线的第一导电膜之间形成一个用以减小扇出线之间的阻抗差异的附加电容， 所 述附加电容的大小由所述附加导电膜与所述第一导电膜之间的重叠面积确定。
11、 如权利要求 10所述的显示面板， 其中， 所述第一扇出线、 第二扇出线 内仅设置有一层第一导电膜。
12、 如权利要求 10所述的阵列基板的显示面板， 其中， 所述附加导电膜为 宽度不变， 沿所述每条第二扇出线的走向铺设的多条走线， 其中， 不同长度的 第二扇出线底部铺设的附加导电膜的长度不同。
13、 如权利要求 12所述的阵列基板的显示面板， 其中， 所述扇出线底部铺 设的附加导电膜的长度为：
Figure imgf000013_0001
( L!2-L2 2 ) /L2(di£r2-d2£ri);
所述 为所述第一扇出线以及第二扇出线中任选的一条扇出线的长度，该 长的扇出线为参照线， 所述 L2为所述第二扇出线的长度， 所述 L22为所述长 为 L2的扇出线底部铺设的附加导电膜的长度，所述 为液晶面板中液晶层的相 对介电常数， 所述 ^为所述液晶层的厚度， 所述 为所述第一导电膜与所述附 加导电膜之间的电介质的相对介电常数， 所述 d2为所述电介质的厚度。
14、 如权利要求 13所述的阵列基板的显示面板， 其中， 所述参照线为所述 第一扇出线以及第二扇出线中最长的一条。
15、 如权利要求 10所述的阵列基板的显示面板， 其中， 所述附加导电膜为 同时覆盖多条扇出线的导电膜区块。
16、 如权利要求 10所述的阵列基板的显示面板， 其中， 所述第一扇出线以 及第二扇出线中， 两个端点的直线距离比其它扇出线的两个端点的直线距离小 的扇出线设置有用于加长该扇出线的绕线部。
17、 如权利要求 10所述的阵列基板的显示面板， 其中， 所述第一导电膜为 金属导电膜； 所述附加导电膜为氧化铟锡导电膜或金属导电膜。
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