WO2017197934A1 - 阵列基板及其制作方法、触控显示装置 - Google Patents

阵列基板及其制作方法、触控显示装置 Download PDF

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Publication number
WO2017197934A1
WO2017197934A1 PCT/CN2017/073546 CN2017073546W WO2017197934A1 WO 2017197934 A1 WO2017197934 A1 WO 2017197934A1 CN 2017073546 W CN2017073546 W CN 2017073546W WO 2017197934 A1 WO2017197934 A1 WO 2017197934A1
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Prior art keywords
lead
sub
touch
pixel
self
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PCT/CN2017/073546
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English (en)
French (fr)
Inventor
刘冲
赵海生
王薇
黄雄天
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京东方科技集团股份有限公司
北京京东方光电科技有限公司
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Priority to US15/552,576 priority Critical patent/US10324571B2/en
Publication of WO2017197934A1 publication Critical patent/WO2017197934A1/zh

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    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
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    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
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    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an array substrate, a method for fabricating the same, and a touch display device.
  • the Touch Screen Panel has gradually spread throughout people's lives.
  • the touch screen can be divided into an on-cell touch panel (On Cell Touch Panel) and an in-cell touch panel (In Cell Touch Panel) according to the composition structure. Since the in-cell touch panel has the characteristics of high light transmittance and thin thickness, it is increasingly used in high-performance display products.
  • the structure of the existing in-cell touch screen is mainly divided into a mutual capacitance type structure and a self capacitance type structure.
  • the current self-capacitive touch screen may include a plurality of block-shaped self-capacitance electrodes 10. Each self-capacitance electrode 10 is connected to the drive circuit 20 through a touch lead 11 .
  • the capacitance of the self-capacitance electrode 10 at the finger touch position is changed, and the touch position of the finger is determined according to the horizontal and vertical coordinates of the self-capacitance electrode 10 that has changed.
  • the above self-capacitance electrode 10 is square. Each self-capacitance electrode 10 corresponds to the position of M x M pixel units.
  • the number of self-capacitance electrodes 10 in the same column is N, and N and M are different.
  • the self-capacitance electrodes 10 in the same column can be respectively connected to the driving circuit 20 through 32 mutually insulated touch leads 11.
  • the touch lead 11 is usually disposed in the pixel unit and the 32 touch-insulated touch leads 11 may be located in different columns of pixel units.
  • the pixel unit in which the touch lead 11 is not provided exists in the M-column pixel unit corresponding to the position of the same column self-capacitance electrode 10.
  • the parasitic capacitance can be formed between the touch lead 11 and the gate line and the parasitic capacitance affects the display gray scale of the pixel unit, the touch lead 11 is provided under the control of the same data voltage.
  • the display gray scale of the pixel unit and the pixel unit in which the touch lead 11 is not provided may be different, for example, a square display is poor, which reduces display uniformity.
  • an array substrate including: a common electrode layer including a plurality of self-capacitance electrodes distributed in an array; a driving circuit; and a plurality of pixel units distributed in an array .
  • N self-capacitance electrodes in the same column form an electrode column, each electrode column corresponds to M column pixel units, and N self-capacitance electrodes in the same column pass N touches disposed in pixel units of different columns
  • a lead is connected to the drive circuit, M and N being positive integers and M>N ⁇ 1.
  • a dummy lead is disposed in the M-N column pixel unit in which the touch control lead is not disposed in the M column pixel unit, and the dummy lead is connected to the driving circuit.
  • the driving circuit is configured to input a common voltage signal to the dummy lead and the touch lead.
  • the touch lead includes a first sub-lead and a second sub-lead disposed at different layers and overlapping, the first sub-lead being coupled to the second sub-lead through a via.
  • the array substrate further includes a data line
  • the second sub-lead is disposed in the same layer and the same material as the data line of the array substrate.
  • the dummy leads are disposed in the same layer as the first sub-leads.
  • the number of pixel cells between any two adjacent dummy leads is a fixed constant.
  • each of the touch leads runs through all of the pixel cells in the same column, and/or each of the dummy leads runs through all of the pixel cells in the same column.
  • the pixel unit includes a blue sub-pixel, a red sub-pixel, and a green sub-pixel, and the touch lead and/or the dummy lead are disposed within the blue sub-pixel.
  • the pixel unit includes a sub-pixel in which a pixel electrode is disposed, the common electrode layer is located above the pixel electrode, and the first sub-lead is located in the second sub-pixel Above the lead, the self-capacitance electrode is connected to the first sub-lead through a via.
  • the pixel electrode is in a block shape, and the self-capacitance electrode has a stripe slit pattern at a position corresponding to the pixel electrode.
  • a touch display device which may include any of the array substrates described above.
  • a method for fabricating any of the array substrates as described above comprising: fabricating a driving circuit, the method further comprising: forming a gate line on the substrate; Forming a data line and a second sub-lead on the base substrate on which the gate line is formed; forming a first insulating layer on the base substrate on which the data line and the second sub-lead are formed; An insulating layer forms a via corresponding to a position of the second sub-lead; a dummy lead is formed on the base substrate on which the first insulating layer is formed, and a first portion is formed at a position corresponding to the second sub-lead a sub-lead, the first sub-lead being connected to the second sub-lead through the via hole to form a touch lead, and the dummy lead and the touch lead are both connected to the driving circuit; And forming a plurality of self-capacitance electrodes arranged in an array on the base substrate
  • the method further includes forming a second insulating layer on the base substrate on which the dummy lead and the touch lead are formed, before forming the plurality of self-capacitance electrodes distributed in an array, and Another via hole is formed at a position corresponding to the first sub-lead of the second insulating layer, and the self-capacitance electrode is connected to the touch lead through the other via hole.
  • Embodiments of the present invention provide an array substrate, a manufacturing method thereof, and a touch display device.
  • the array substrate includes: a common electrode layer including a plurality of self-capacitance electrodes distributed in an array; a driving circuit; and a plurality of pixel units distributed in an array.
  • N self-capacitance electrodes in the same column constitute an electrode column, each electrode column corresponds to M column pixel units, and N self-capacitance electrodes in the same column pass N contacts in pixel units arranged in different columns
  • the control lead is connected to the driving circuit, and M and N are positive integers and M>N ⁇ 1.
  • a dummy lead is disposed in the MN column pixel unit in which the touch control lead is not disposed in the M column pixel unit, the dummy lead is connected to the driving circuit, and the driving circuit is configured to input a common voltage signal to the dummy lead and the touch lead .
  • the driving circuit can input the same common voltage signal as the touch lead to the dummy lead, thereby generating between the dummy lead and the gate line.
  • the parasitic capacitance and the parasitic capacitance generated between the touch lead and the gate line are the same.
  • the pixel unit provided with the touch lead and the pixel unit not provided with the touch lead can be affected by the same parasitic capacitance. Therefore, under the control of the same data voltage, the display gray scale difference between the pixel units can be reduced, thereby improving the display effect.
  • FIG. 1 is a schematic structural view of an array substrate provided by the prior art
  • FIG. 2 is a schematic structural diagram of an array substrate according to an embodiment of the present invention.
  • Figure 3 is an enlarged view of A in Figure 2;
  • FIG. 4 is a schematic diagram of partitioning of a touch block according to an embodiment of the present invention.
  • Figure 5 is a schematic view showing the arrangement of the dummy leads of Figure 2;
  • FIG. 6 is a schematic structural diagram of another array substrate according to an embodiment of the present disclosure.
  • Figure 7 is a cross-sectional view taken along line O-O of Figure 5;
  • Figure 8 is a cross-sectional view taken along line O'-O' of Figure 5;
  • Figure 9 is a schematic view taken along line F in Figure 7;
  • FIG. 10 is a flowchart of a method for fabricating an array substrate according to an embodiment of the present invention.
  • Embodiments of the present invention provide an array substrate.
  • the array substrate package A common electrode layer and a driving circuit 20 are included.
  • the common electrode layer includes a plurality of self-capacitance electrodes 10 distributed in an array.
  • the array substrate further includes a plurality of pixel units 30 distributed in an array.
  • the self-capacitance electrode 10 described above can be used as a common electrode to achieve display.
  • the self-capacitance electrode 10 can be multiplexed as a touch electrode to implement touch.
  • the position where each self-capacitance electrode 10 is located may be referred to as a touch block Touch.
  • the touch block Touch is generally square, and therefore, the self-capacitance electrode 10 described above is also generally square.
  • each of the pixel units 30 may include at least three sub-pixels 301 of different colors, such as red (R), green (G), and blue (B) sub-pixels 301.
  • each of the pixel units 30 may include a red sub-pixel, a blue sub-pixel, a green sub-pixel, and a white sub-pixel.
  • the area in which each sub-pixel 301 is located may be defined by a horizontally intersecting gate line Gate and a data line Data.
  • the N self-capacitance electrodes 10 in the same column constitute an electrode column 100
  • each electrode column 100 corresponds to the M-column pixel unit 30, and N self-sequences in the same column
  • the capacitor electrode 10 is connected to the driving circuit 20 through N touch leads 11 provided in the pixel units 30 of different columns.
  • M and N are positive integers, and M>N ⁇ 1.
  • the dummy lead 12 is provided in the M-N column pixel unit 30 in which the touch lead 11 is not provided in the M column pixel unit.
  • the dummy lead 12 is connected to the driving circuit 20, and the driving circuit 20 is for inputting a common voltage signal (Vcom) to the dummy lead 12 and the touch lead 11.
  • Vcom common voltage signal
  • the division of the touch block Touch is as shown in FIG. 4, for example.
  • Each row has 18 touch blocks Touch
  • each column has 32 touch blocks Touch
  • each touch block Touch corresponds to 40 ⁇ 40 pixel units 30.
  • one touch block Touch corresponds to one self-capacitance electrode 10
  • one electrode column 100 in FIG. 2 includes 32 self-capacitance electrodes 10
  • the electrode column 100 corresponds to 40 columns of pixel units 30. Therefore, the 32 self-capacitance electrodes 10 in the electrode array 100 can be connected to the driving circuit 20 through 32 touch leads 11 disposed in the pixel units 30 of different columns.
  • the dummy lead 12 can be disposed in the pixel unit 30 in which the touch lead 11 is not provided.
  • the number of pixel units 30 between any adjacent two dummy leads 12 may be a fixed constant. For example, for a scheme in which the position of the electrode column 100 corresponds to 40 columns of pixel units 30, as shown in FIG. 5, four pixel units 30 may be spaced between adjacent two dummy leads 12.
  • the driving circuit can input the same common voltage signal as the touch lead to the dummy lead, thereby generating between the dummy lead and the gate line.
  • the parasitic capacitance and the parasitic capacitance generated between the touch lead and the gate line are the same.
  • both the pixel unit provided with the touch lead and the pixel unit not provided with the touch lead can be affected by the same parasitic capacitance. Therefore, under the control of the same data voltage, the display gray scale difference between the pixel units can be reduced, thereby improving the display effect.
  • the touch lead 11 can be prevented from being disposed between the adjacent two touch blocks, thereby causing the occurrence of the touch dead zone.
  • the dummy leads 12 may be disposed in the pixel unit 30 even if the dummy leads 12 need not be connected to the self-capacitance electrodes 10.
  • the touch lead 11 and The dummy lead 12 can be disposed within the blue (B) sub-pixel 301. In this way, the influence of providing the touch lead 11 and/or the dummy lead 12 in the pixel unit 30 on the display effect can be reduced.
  • the touch lead 11 can be connected to the self-capacitance electrode 10 through the via hole 14. If the touch lead 11 is formed from the position of the via hole 14, the distribution of the touch leads 11 in a part of the array substrate may be dense, and the distribution of the touch leads 11 in another portion may be sparse, which is easy to generate. Display uneven. Therefore, according to another embodiment, as shown in FIG. 6, each of the touch leads 11 runs through all of the pixel units 30 in the same column, and/or each of the dummy leads 12 runs through all of the pixel units 30 in the same column. Thereby, the touch lead 11 and the dummy lead 12 can be evenly distributed over the entire array substrate to reduce display difference.
  • One end of the touch lead 11 can be connected to the self-capacitance electrode 10 through the via hole 14
  • the other end of the control lead 11 is connected to the drive circuit 20. Therefore, the common voltage signal (Vcom) outputted by the driving circuit 20 can be output to the self-capacitance electrode 10 through the touch lead 11, so that the self-capacitance electrode 10 can be charged, so that the self-capacitance electrode 10 can constitute one of the liquid crystal capacitors in the display phase. electrode.
  • the self-capacitance electrode 10 can constitute one electrode of the self-capacitance. Therefore, if the resistance of the touch lead 11 is large, in order to ensure that the voltage signal received by the self-capacitance electrode 10 does not change, the load of the drive circuit 20 needs to be increased correspondingly, which increases the driving power consumption.
  • the touch lead 11 may be composed of two layers of metal wires. Specifically, the touch lead 11 may include a first sub-lead 111 and a second sub-lead 112 which are disposed at different layers and overlapped.
  • the first sub-lead 111 is connected to the second sub-lead 112 through a via.
  • the first sub-lead 111 can be connected to the self-capacitance electrode 10 through the via 14 described above. In this way, the first sub-lead 111 can be connected in parallel with the second sub-lead 112, so that the resistance of the touch lead 11 can be reduced to reduce the power consumption of the driving circuit 20.
  • the second sub-lead 112 may be disposed in the same layer and the same material as the data line Data on the array substrate. In this way, the preparation of the second sub-lead 112 can be completed in the process of preparing the data line Data.
  • the material constituting the second sub-lead 112 may be referred to as SDT (Source Data Touch).
  • the material constituting the first sub-lead 111 may be the same as the material constituting the data line Data, or other conductive metal materials may be used. Therefore, the material constituting the first sub-lead 111 can be referred to as a TPM (Touch Panel Metal).
  • the second sub-lead is disposed in the same layer as the data line Data
  • the process of fabricating the second sub-lead it is possible to cause the second sub-lead and A short circuit occurs between the data line Data adjacent thereto.
  • the voltage on the data line Data in which the short circuit occurs is pulled down to the common voltage on the second sub-lead, thereby causing the data voltage not to be input to the sub-pixel provided with the data line Data through the data line Data in which the short circuit occurs during display.
  • the sub-pixel 301 is not displayed normally, and a square display failure occurs.
  • the dummy lead 12 may be composed of only a single layer of metal wire. In order to simplify the fabrication process, the dummy leads 12 may be disposed in the same layer as the first sub-leads 111.
  • the dummy lead 12 does not include the second sub-lead, that is, there is no need to set and The data line Data is the second sub-lead of the same layer, and therefore, it can be ensured that the data line Data in the sub-pixel 301 provided with the dummy lead 12 is not short-circuited, so that a square display failure of about 20% can be reduced.
  • the dummy lead 12 does not need to be connected to the self-capacitance electrode 10, and the dummy lead 12 is only used to receive the common voltage signal (Vcom) output from the drive circuit 20 without the signal transmission path that drives the load as the drive circuit 20, even if The use of a single layer of metal wire does not increase the power consumption of the driver circuit 20.
  • Vcom common voltage signal
  • the self-capacitance formed between the self-capacitance electrode 10 and the ground GND needs to be changed by finger pressing, and the touch position is determined according to the changed coordinates of the self-capacitance electrode 10. Therefore, in order to improve the touch sensitivity, the self-capacitance electrode 10 should be placed as close as possible to the side of the finger. Therefore, as shown in FIG. 5, when the pixel unit 30 includes the sub-pixel 301 and the pixel electrode 13 is disposed in the sub-pixel 301, as shown in FIG. 7 or as shown in FIG. 8, the common electrode layer including the plurality of self-capacitance electrodes 10 Located above the pixel electrode 13. That is, the self-capacitance electrode 10 is away from the base substrate 01 with respect to the pixel electrode 13.
  • the first sub-lead 111 is located above the second sub-lead 112.
  • the self-capacitance electrode 10 is connected to the first sub-lead 111 through a via hole to connect the touch lead 11 and the self-capacitance electrode 10.
  • the array substrate can be used to form an AD-SDS (Advanced-Super Dimensional Switching, abbreviated as ADS, advanced super-dimensional field switch) type display device.
  • ADS Advanced-Super Dimensional Switching
  • FIG. 9 the pixel electrode 13 is in a block shape, and the self-capacitance electrode 10 included in the common electrode layer has a stripe slit pattern at a position corresponding to the pixel electrode 13.
  • a parallel electric field generated by the edge of the pixel electrode in the same plane and a longitudinal electric field generated between the pixel electrode and the common electrode layer can form a multi-dimensional electric field, so that liquid crystal molecules of all orientations between the pixel electrodes in the liquid crystal cell and directly above the electrode can be The rotation conversion is generated, thereby improving the working efficiency of the plane-oriented liquid crystal and increasing the light transmission efficiency.
  • the embodiment of the invention further provides a touch display device, which may include any of the above array substrates. Since the structure of the array substrate has been described in detail in the foregoing embodiment, it will not be described herein.
  • the display device may include, for example, a liquid crystal display device.
  • the display device may be any product or component having a display function such as a liquid crystal display, a liquid crystal television, a digital photo frame, a mobile phone, or a tablet computer.
  • the embodiment of the invention further provides a method for fabricating any of the array substrates as described above, comprising: fabricating a driving circuit. Further, as shown in FIG. 10, the method may further include the following steps.
  • a gate line on the base substrate.
  • a gate metal layer is formed on the base substrate 01 as shown in FIG. 7 or FIG. 8, and a gate line Gate is formed by a patterning process.
  • a gate G of a thin film transistor TFT Thin Film Transistor
  • TFT Thin Film Transistor
  • the patterning process may include a photolithography process, or may include a photolithography process and an etching process.
  • the patterning process may also include other processes for forming a predetermined pattern, such as printing, inkjet, and the like.
  • the photolithography process may refer to a process of forming a pattern using a photoresist, a mask, an exposure machine, or the like including a process of film formation, exposure, development, and the like.
  • the corresponding patterning process can be selected in accordance with the structure to be formed in the embodiment of the present invention.
  • S102 Form a data line and a second sub-lead on the base substrate on which the gate line is formed.
  • a data metal layer is formed on the base substrate 01 on which the gate lines are formed, and the data lines Data and the second sub-leads 112 are formed by a patterning process.
  • the source S and the drain D of the TFT may also be formed while forming the data line Data and the second sub-lead 112.
  • the material constituting the first insulating layer 15 may include silicon nitride.
  • the first insulating layer 15 may be formed using a low dielectric constant resin material.
  • a via hole is formed at a position where the first insulating layer 15 corresponds to the second sub-lead 112.
  • the first sub-lead 111 is connected to the second sub-lead 112 through a via formed in step S104 to form the touch lead 11.
  • the first sub-lead 111 may be disposed in the same layer as the dummy lead 12 The materials are the same.
  • the formed dummy lead 12 and the touch lead 11 are both connected to the driving circuit 20 for receiving the common voltage signal (Vcom) output from the driving circuit 20.
  • the N self-capacitance electrodes 10 constitute an electrode column 100.
  • the method further includes: after step S105, before step S106, forming a second insulating layer on the base substrate on which the dummy lead and the touch lead are formed, and corresponding to the first in the second insulating layer
  • the position of the sub-leads forms another via.
  • the self-capacitance electrode can be connected to the touch lead through another via.
  • a second insulating layer 16 is formed on the base substrate 01 on which the touch lead 11 and the dummy lead 12 are formed, and then another via is formed at a position where the second insulating layer 16 corresponds to the first sub-lead 111, thereby
  • the self-capacitance electrode 10 formed in step S106 can be connected to the touch lead 11 including the first sub-lead 111 and the second sub-lead 112 through another via (as shown in FIG. 7).
  • the second insulating layer 16 may be the same material as the first insulating layer 15.
  • the dummy lead 12 does not need to be connected to the self-capacitance electrode 10, as shown in FIG. 8, it is not necessary to make a via hole at a position where the second insulating layer 16 corresponds to the dummy lead 12.
  • the driving circuit can input the same common voltage signal to the dummy lead as the touch lead, thereby causing parasitic between the dummy lead and the gate line.
  • the parasitic capacitance generated between the capacitor and the touch lead and the gate line is the same.
  • the pixel unit provided with the touch lead and the pixel unit not provided with the touch lead can be affected by the same parasitic capacitance, and therefore, under the control of the same data voltage, the display gray between the pixel units can be reduced. Differences in order, which improves the display.
  • the touch lead includes the first sub-lead and the second sub-lead that are connected through the via
  • the resistance of the touch lead can be reduced, thereby reducing the power consumption of the driving circuit.
  • the preparation of the second sub-lead can be completed in the process of preparing the data line, thereby simplifying the manufacturing process.
  • the dummy lead is disposed in the same layer as the first sub-lead, not only the process can be simplified, but also the data line in the sub-pixel provided with the dummy lead can be prevented from being short-circuited, thereby reducing the display failure of the square.
  • the dummy leads do not need to be connected to the self-capacitance electrodes, and are only used to receive the driving circuit.
  • the output common voltage signal does not need to be a signal transmission path for driving the load as a driving circuit, and therefore, even if a single-layer metal line is used to form the dummy wiring, the power consumption of the driving circuit is not increased.

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Abstract

一种阵列基板及其制作方法以及触控显示装置。阵列基板包括：公共电极层，公共电极层包括呈阵列分布的多个自电容电极（10）；驱动电路（20）；以及呈阵列分布的多个像素单元。位于同一列的N个自电容电极（10）构成一电极列（100），每一电极列（100）与M列像素单元相对应。位于同一列的N个自电容电极（10）通过设置于不同列的像素单元内的N条触控引线（11）与驱动电路相连接。M和N为正整数，且M＞N≥1。M列像素单元中未设置触控引线（11）的M-N列像素单元内设置有虚设引线（12），虚设引线（12）与驱动电路相连接，并且驱动电路用于向虚设引线（12）和触控引线（11）输入公共电压信号。通过上述阵列基板，能够减轻或避免在同一数据电压的控制下，设置有触控引线的像素单元与未设置触控引线的像素单元之间出现显示灰阶差异的现象。

Description

阵列基板及其制作方法、触控显示装置 技术领域
本发明涉及显示技术领域，尤其涉及一种阵列基板及其制作方法、触控显示装置。
背景技术
随着显示技术的飞速发展，触摸屏(Touch Screen Panel)已经逐渐遍及人们的生活中。目前，触摸屏按照组成结构可以分为：外挂式触摸屏(On Cell Touch Panel)和内嵌式触摸屏(In Cell Touch Panel)。由于内嵌式触控屏具有透光率高，厚度薄等特点，其越来越多地被应用于高性能显示产品当中。
现有的内嵌式触摸屏的结构主要分为互电容式结构和自电容式结构。如图1所示，当前的自电容式触摸屏可以包括多个块状的自电容电极10。每一个自电容电极10通过一条触控引线11连接至驱动电路20。当用户触摸该触摸屏时，会导致手指触摸位置处的自电容电极10的电容发生变化，从而根据发生变化的自电容电极10的横纵坐标判断出手指的触摸位置。
通常上述自电容电极10为正方形。每一个自电容电极10与M×M个像素单元的位置相对应。而位于同一列的自电容电极10的个数为N个，N与M不相同。例如，当M＝40，N＝32时，可以通过32条相互绝缘的触控引线11将位于同一列的自电容电极10分别连接于驱动电路20。为了避免触控盲区，上述触控引线11通常设置于像素单元内且32条相互绝缘的触控引线11可以位于不同列的像素单元内。然而，由于M＝40，N＝32，M大于N，因此，与同一列自电容电极10的位置相对应的M列像素单元中存在没有设置触控引线11的像素单元。在此情况下，由于触控引线11与栅线之间可以构成寄生电容且上述寄生电容会对像素单元的显示灰阶产生影响，因此，在同一数据电压的控制下，设置有触控引线11的像素单元与未设置触控引线11的像素单元的显示灰阶可能出现差异，例如出现方格显示不良，这降低了显示均匀性。
发明内容
因此，所期望的是提供一种阵列基板及其制作方法以及触控显示装置，从而减轻或避免在同一数据电压的控制下，设置有触控引线的像素单元与未设置触控引线的像素单元之间出现显示灰阶差异的现象。
根据本发明实施例的一个方面，提供了一种阵列基板，包括：公共电极层，所述公共电极层包括呈阵列分布的多个自电容电极；驱动电路；以及呈阵列分布的多个像素单元。位于同一列的N个自电容电极构成一电极列，每一电极列与M列像素单元相对应，并且位于同一列的N个自电容电极通过设置于不同列的像素单元内的N条触控引线与所述驱动电路相连接，M和N为正整数且M＞N≥1。所述M列像素单元中未设置所述触控引线的M-N列像素单元内设置有虚设引线，所述虚设引线与驱动电路相连接。并且所述驱动电路用于向所述虚设引线和所述触控引线输入公共电压信号。
根据另一实施例，所述触控引线包括位于不同的层且交叠设置的第一子引线和第二子引线，所述第一子引线通过过孔与所述第二子引线相连接。
根据另一实施例，所述阵列基板还包括数据线，所述第二子引线与所述阵列基板的数据线同层设置且材料相同。
根据另一实施例，所述虚设引线与所述第一子引线同层设置。
根据另一实施例，任意相邻两条虚设引线之间的像素单元的数目为一固定的常数。
根据另一实施例，每一条触控引线贯穿位于同一列的所有像素单元，和/或，每一条虚设引线贯穿位于同一列的所有像素单元。
根据另一实施例，所述像素单元包括蓝色亚像素、红色亚像素以及绿色亚像素，所述触控引线和/或所述虚设引线设置于所述蓝色亚像素内。
根据另一实施例，所述像素单元包括亚像素，所述亚像素内设置有像素电极，所述公共电极层位于所述像素电极上方，并且，所述第一子引线位于所述第二子引线的上方，所述自电容电极通过过孔与所述第一子引线相连接。
根据另一实施例，所述像素电极为块状，所述自电容电极在对应于所述像素电极的位置呈条状狭缝图案。
根据本发明实施例的另一方面，提供了一种触控显示装置，其可以包括如上所述的任意一种阵列基板。
根据本发明实施例的又一方面，提供了一种用于制作如上所述的任意一种阵列基板的方法，包括：制作驱动电路，所述方法还包括：在衬底基板上形成栅线；在形成有所述栅线的衬底基板上形成数据线以及第二子引线；在形成有所述数据线和所述第二子引线的衬底基板上形成第一绝缘层；在所述第一绝缘层对应于所述第二子引线的位置形成过孔；在形成有所述第一绝缘层的衬底基板上形成虚设引线，且在对应于所述第二子引线的位置形成第一子引线，所述第一子引线通过所述过孔与所述第二子引线相连接以形成触控引线，并且所述虚设引线和所述触控引线均与所述驱动电路相连接；以及，在形成有所述虚设引线和所述触控引线的衬底基板上形成呈阵列分布的多个自电容电极。
根据另一实施例，所述方法还包括：在形成呈阵列分布的多个自电容电极之前，在形成有所述虚设引线和所述触控引线的衬底基板上形成第二绝缘层，并且在所述第二绝缘层对应于所述第一子引线的位置形成另一过孔，所述自电容电极通过所述另一过孔与所述触控引线相连接。
本发明实施例提供了一种阵列基板及其制作方法、触控显示装置。该阵列基板包括：公共电极层，所述公共电极层包括呈阵列分布的多个自电容电极；驱动电路；以及，呈阵列分布的多个像素单元。位于同一列的N个自电容电极构成一电极列，每一电极列与M列像素单元相对应，并且，位于同一列的N个自电容电极通过设置于不同列的像素单元内的N条触控引线与驱动电路相连接，M和N为正整数且M＞N≥1。M列像素单元中未设置所述触控引线的M-N列像素单元内设置有虚设引线，所述虚设引线与驱动电路相连接，并且该驱动电路用于向虚设引线和触控引线输入公共电压信号。
这样一来，通过在未设置触控引线的M-N列像素单元内设置虚设引线，能够使得驱动电路向虚设引线输入与触控引线相同的公共电压信号，进而使得虚设引线与栅线之间产生的寄生电容和触控引线与栅线之间产生的寄生电容相同。在此情况下，设置有触控引线的像素单元与未设置触控引线的像素单元均能够受到相同的寄生电容的影响， 因此，在同一数据电压的控制下，能够降低像素单元之间的显示灰阶差异，从而提高了显示效果。
附图说明
为了更清楚地说明本发明的实施例，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍。显而易见地，下面描述中的附图仅仅是用于说明本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为现有技术提供的一种阵列基板的结构示意图；
图2为本发明实施例提供的一种阵列基板的结构示意图；
图3为图2中A处的放大图；
图4为本发明实施例提供的一种触控块的划分示意图；
图5为图2中虚设引线的设置方式示意图；
图6为本发明实施例提供的另一种阵列基板的结构示意图；
图7为图5中沿线O-O得到的剖视图；
图8为图5中沿线O’-O’得到的剖视图；
图9为图7中沿F方向得到的示意图；
图10为本发明实施例提供的一种阵列基板的制作方法流程图。
附图标记：
01-衬底基板；10-自电容电极；100-电极列；11-触控引线；111-第一子引线；112-第二子引线；12-虚设引线；13-像素电极；14-过孔；15-第一绝缘层；16-第二绝缘层；20-驱动电路；30-像素单元；301-亚像素；G-TFT的栅极；S-TFT的源极；D-TFT的漏极。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本发明的一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明实施例提供了一种阵列基板。如图2所示，该阵列基板包 括公共电极层和驱动电路20。公共电极层包括呈阵列分布的多个自电容电极10。此外，如图3(图2中A处的放大图)所示，该阵列基板还包括呈阵列分布的多个像素单元30。
需要说明的是，在显示阶段，上述自电容电极10可以用作公共电极以实现显示。而在触控阶段，自电容电极10又可以被复用为触控电极，以实现触控。每一个自电容电极10所在的位置可以被称为一个触控块Touch。触控块Touch通常为正方形，因此，上述自电容电极10通常也为正方形。
当上述自电容电极10为正方形时，一个自电容电极10例如与M×M个像素单元30的位置相对应。每一个像素单元30可以包括至少三个不同颜色的亚像素301，例如红色(R)、绿色(G)以及蓝色(B)亚像素301。或者，每一个像素单元30可以包括红色亚像素，蓝色亚像素、绿色亚像素以及白色亚像素。每一个亚像素301所在的区域可以由横纵交叉的栅线Gate和数据线Data界定而成。
在此情况下，如图2所示，位于同一列的N个自电容电极10构成一电极列100，每一电极列100与M列像素单元30相对应，并且，位于同一列的N个自电容电极10通过设置于不同列的像素单元30内的N条触控引线11与驱动电路20相连接。M和N为正整数，且M＞N≥1。此外，M列像素单元中未设置触控引线11的M-N列像素单元30内设置有虚设引线12。虚设引线12与驱动电路20相连接，并且驱动电路20用于向虚设引线12和触控引线11输入公共电压信号(Vcom)。
例如，对于分辨率为1280×720的显示装置而言，触控块Touch的划分例如如图4所示。每一行具有18个触控块Touch，每一列具有32个触控块Touch，且每一个触控块Touch对应40×40个像素单元30。由于一个触控块Touch与一个自电容电极10相对应，因此，图2中的一个电极列100包括32个自电容电极10，且电极列100与40列像素单元30相对应。因此，电极列100中的32个自电容电极10可以通过32条设置于不同列的像素单元30内的触控引线11与驱动电路20相连接。
在此情况下，与上述电极列100的位置相对应的40列像素单元30中，存在8列(40-32＝8)未设置上述触控引线11的像素单元30。因此，可以在未设置上述触控引线11的像素单元30内设置虚设引线12。 为了使虚设引线12在阵列基板上能够分布均匀，任意相邻两条虚设引线12之间的像素单元30的数目可以为一固定的常数。例如，对于电极列100的位置对应于40列像素单元30的方案而言，如图5所示，相邻两条虚设引线12之间可以间隔4个像素单元30。
综上所述，通过在未设置触控引线的M-N列像素单元内设置虚设引线，能够使得驱动电路向虚设引线输入与触控引线相同的公共电压信号，进而使得虚设引线与栅线之间产生的寄生电容和触控引线与栅线之间产生的寄生电容相同。在此情况下，设置有触控引线的像素单元与未设置触控引线的像素单元均能够受到相同寄生电容的影响。因此，在同一数据电压的控制下，能够降低像素单元之间的显示灰阶差异，从而提高了显示效果。
此外，通过将触控引线11设置于像素单元30内，能够避免将触控引线11设置于相邻的两个触控块之间而导致触控盲区的出现。另外，由于相邻的两个触控块之间可能没有预留足够的布线空间，因此，即使虚设引线12无需与自电容电极10相连接，也可以将虚设引线12设置于像素单元30内。
当像素单元30包括蓝色(B)、红色(R)以及绿色(G)亚像素301时，由于人眼对蓝色的敏感度较弱，因此，根据另一实施例，触控引线11和/或虚设引线12可以设置于蓝色(B)亚像素301内。这样一来，能够降低在像素单元30内设置触控引线11和/或虚设引线12对显示效果的影响。
进一步的，如图2所示，触控引线11可以通过过孔14与自电容电极10相连接。如果从过孔14的位置才开始制作触控引线11，则可能会导致阵列基板的一部分区域内触控引线11的分布较密集，而另一部分区域内触控引线11的分布稀疏，从而容易产生显示不均。因此，根据另一实施例，如图6所示，每一条触控引线11贯穿位于同一列的所有像素单元30，和/或，每一条虚设引线12贯穿位于同一列的所有像素单元30。由此，能够使触控引线11和虚设引线12均匀分布于整个阵列基板上，以降低显示差异。
以下，对触控引线11和虚设引线12的具体结构进行详细的举例说明。
触控引线11的一端可以通过过孔14与自电容电极10相连接，触 控引线11的另一端与驱动电路20相连接。因此，驱动电路20输出的公共电压信号(Vcom)能够通过触控引线11输出至自电容电极10，从而可以向自电容电极10充电，以使得自电容电极10能够在显示阶段构成液晶电容的一个电极。此外，在触控阶段，自电容电极10可以构成自电容的一个电极。因此，如果触控引线11的电阻较大，为了保证自电容电极10接收到的电压信号不变，则需要相应增加驱动电路20的负载，这增加了驱动功耗。
因此，为了降低驱动电路20的功耗，如图7(图5中沿线O-O得到的剖视图)所示，触控引线11可以由两层金属线构成。具体的，触控引线11可以包括位于不同的层且交叠设置的第一子引线111和第二子引线112。第一子引线111通过过孔与第二子引线112相连接。第一子引线111可以通过上述过孔14与自电容电极10相连接。这样一来，第一子引线111可以与第二子引线112并联，从而能够降低触控引线11的电阻，以降低驱动电路20的功耗。
进一步的，为了简化制作工艺，第二子引线112可以与阵列基板上的数据线Data同层设置且材料相同。这样一来，可以在制备数据线Data的过程中完成第二子引线112的制备。在此情况下，构成上述第二子引线112的材料可以称为SDT(Source Data Touch)。而构成第一子引线111的材料可以与构成数据线Data的材料相同，或者还可以采用其他导电金属材料。因此，构成第一子引线111的材料可以称为TPM(Touch Panel Metal)。
对于包括第一子引线和第二子引线的引线来说，在第二子引线与数据线Data同层设置的情况下，在制作第二子引线的过程中，有可能导致第二子引线和与其相邻的数据线Data之间发生短路。发生短路的数据线Data上的电压会被拉低至第二子引线上的公共电压，从而导致显示过程中，数据电压无法通过发生短路的数据线Data输入至设置有该数据线Data的亚像素301中，进而导致该亚像素301无法正常显示，产生方格显示不良。
为了降低方格显示不良的发生几率，如图8(图5中沿线O’-O’得到的剖视图)所示，虚设引线12可以仅由单层金属线构成。为了简化制作工艺，虚设引线12可以与第一子引线111同层设置。
这样一来，由于虚设引线12不包括第二子引线，即，无需设置与 数据线Data同层的第二子引线，因此，可以确保设置有虚设引线12的亚像素301中的数据线Data不会发生短路，从而可以降低大约20％的方格显示不良。此外，由于虚设引线12无需与自电容电极10相连接，且虚设引线12只用于接收驱动电路20输出的公共电压信号(Vcom)而无需作为驱动电路20带动负载的信号传输路径，因此，即使采用单层金属线，也不会增加驱动电路20的功耗。
进一步的，由于在触控过程中，需要通过手指按压使得由自电容电极10与接地端GND之间构成的自电容发生变化，并根据发生变化的自电容电极10的坐标来确定出触控位置，因此，为了提高触控灵敏度，自电容电极10应当尽量设置于靠近手指的一侧。因此，如图5所示，在像素单元30包括亚像素301且该亚像素301内设置有像素电极13时，如图7或如图8所示，包括多个自电容电极10的公共电极层位于像素电极13上方。即，自电容电极10相对于像素电极13而言，远离衬底基板01。
在此情况下，第一子引线111位于第二子引线112的上方。自电容电极10通过过孔与第一子引线111相连接，以实现触控引线11与自电容电极10相连接。
当公共电极层与像素电极均设置于阵列基板上时，该阵列基板可以用于构成AD-SDS(Advanced-Super Dimensional Switching，简称为ADS，高级超维场开关)型显示装置。在此情况下，如图9所示，像素电极13为块状，而公共电极层所包括的自电容电极10在对应于像素电极13的位置呈条状狭缝图案。因此，可以由同一平面内像素电极边缘所产生的平行电场以及像素电极与公共电极层之间产生的纵向电场形成多维电场，使液晶盒内像素电极间、电极正上方所有取向的液晶分子都能够产生旋转转换，从而提高了平面取向系液晶的工作效率并增大了透光效率。
本发明实施例还提供了一种触控显示装置，其可以包括上述任意一种阵列基板。由于前述实施例已经对阵列基板的结构进行了详细的描述，因此此处不再赘述。
需要说明的是，在本发明实施例中，显示装置例如可以包括液晶显示装置。例如，该显示装置可以为液晶显示器、液晶电视、数码相框、手机或平板电脑等任何具有显示功能的产品或者部件。
本发明实施例还提供了一种用于制作如上所述的任意一种阵列基板的方法，包括：制作驱动电路。此外，如图10所示，该方法还可以包括以下步骤。
S101、在衬底基板上形成栅线。例如，在如图7或图8所示的衬底基板01上形成栅极金属层，并通过构图工艺形成栅线Gate。此外，在形成栅线的同时，还可以形成薄膜晶体管TFT(Thin Film Transistor)的栅极G。
需要说明的是，在本发明的实施例中，构图工艺可以包括光刻工艺，或者，可以包括光刻工艺以及刻蚀步骤。此外，构图工艺还可以包括打印、喷墨等其他用于形成预定图形的工艺。光刻工艺可以指包括成膜、曝光、显影等工艺过程的利用光刻胶、掩模板、曝光机等形成图形的工艺。可根据本发明实施例中所要形成的结构选择相应的构图工艺。
S102、在形成有栅线的衬底基板上形成数据线以及第二子引线。例如，在形成有栅线的衬底基板01上形成数据金属层，通过构图工艺形成数据线Data以及第二子引线112。
在形成数据线Data和第二子引线112的同时，还可以形成TFT的源极S和漏极D。
S103、在形成有数据线Data和第二子引线112的衬底基板上形成第一绝缘层15。
构成第一绝缘层15的材料可以包括氮化硅。或者，为了降低显示功耗，可以采用低介电常数的树脂材料来形成第一绝缘层15。
S104、在第一绝缘层15对应于第二子引线112的位置形成过孔。
S105、在形成有第一绝缘层的衬底基板上形成虚设引线，且在对应于第二子引线的位置形成第一子引线。第一子引线通过过孔与第二子引线相连接以形成触控引线，并且虚设引线和触控引线均与驱动电路相连接。
例如，在形成有第一绝缘层15的衬底基板上形成另一数据金属层，通过构图工艺，形成如图8所示的虚设引线12，并且，如图7所示，在对应于第二子引线112的位置形成第一子引线111。第一子引线111通过步骤S104中形成的过孔与第二子引线112相连接以形成触控引线11。此外，为了简化工艺，第一子引线111可以与虚设引线12同层设 置且材料相同。
所形成的虚设引线12和触控引线11均与驱动电路20相连接，用于接收驱动电路20输出的公共电压信号(Vcom)。
S106、在形成有虚设引线12和触控引线11的衬底基板01上形成呈阵列分布的多个自电容电极10。例如，N个自电容电极10构成一电极列100。
根据另一实施例，上述方法还包括：在步骤S105之后，步骤S106之前，在形成有虚设引线和触控引线的衬底基板上形成第二绝缘层，并且在第二绝缘层对应于第一子引线的位置形成另一过孔。自电容电极可以通过另一过孔与触控引线相连接。
例如，在形成有触控引线11和虚设引线12的衬底基板01上形成第二绝缘层16，然后在该第二绝缘层16对应于第一子引线111的位置形成另一过孔，从而使得步骤S106中形成的自电容电极10能够通过另一过孔与包括第一子引线111和第二子引线112的触控引线11相连接(如图7所示)。第二绝缘层16可以与第一绝缘层15的材料相同。
相比之下，由于虚设引线12无需与自电容电极10相连接，因此，如图8所示，无需在第二绝缘层16对应于虚设引线12的位置制作过孔。
一方面，通过在未设置触控引线的M-N列像素单元内设置虚设引线，能够使得驱动电路向虚设引线输入与触控引线相同的公共电压信号，进而使得虚设引线与栅线之间产生的寄生电容和触控引线与栅线之间产生的寄生电容相同。在此情况下，设置有触控引线的像素单元与未设置触控引线的像素单元均能够受到相同寄生电容的影响，因此，在同一数据电压的控制下，能够降低像素单元之间的显示灰阶差异，从而提高了显示效果。另一方面，在触控引线包括通过过孔相连通的第一子引线和第二子引线的情况下，可以降低触控引线的电阻，从而降低驱动电路的功耗。在触控引线中的第二子引线与阵列基板上的数据线同层设置且材料相同的情况下，可以在制备数据线的过程中完成第二子引线的制备，从而简化了制作工序。在虚设引线与第一子引线同层设置的情况下，不仅可以简化工艺，还可以确保设置有虚设引线的亚像素中的数据线不会发生短路，从而可以降低方格显示不良。此外，由于虚设引线无需与自电容电极相连接，且只用于接收驱动电路 输出的公共电压信号而无需作为驱动电路带动负载的信号传输路径，因此，即使采用单层金属线来形成虚设引线，也不会增加驱动电路的功耗。
以上所述仅为本发明的具体实施方式，但本发明的保护范围并不局限于此。任何熟悉本技术领域的技术人员在本发明揭露的技术范围内可轻易想到的变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所附权利要求的保护范围为准。

Claims (12)

  1. 一种阵列基板，包括：
    公共电极层，所述公共电极层包括呈阵列分布的多个自电容电极；
    驱动电路；以及
    呈阵列分布的多个像素单元，
    其中，位于同一列的N个自电容电极构成一电极列，每一电极列与M列像素单元相对应，并且，位于同一列的N个自电容电极通过设置于不同列的像素单元内的N条触控引线与所述驱动电路相连接，M和N为正整数，且M＞N≥1，并且
    其中，所述M列像素单元中未设置所述触控引线的M-N列像素单元内设置有虚设引线，所述虚设引线与驱动电路相连接，并且所述驱动电路用于向所述虚设引线和所述触控引线输入公共电压信号。
  2. 根据权利要求1所述的阵列基板，其中，所述触控引线包括位于不同的层且交叠设置的第一子引线和第二子引线，所述第一子引线通过过孔与所述第二子引线相连接。
  3. 根据权利要求2所述的阵列基板，其中，所述阵列基板还包括数据线，所述第二子引线与所述阵列基板的数据线同层设置且材料相同。
  4. 根据权利要求2或3所述的阵列基板，其中，所述虚设引线与所述第一子引线同层设置。
  5. 根据权利要求1所述的阵列基板，其中，任意相邻两条虚设引线之间的像素单元的数目为一固定的常数。
  6. 根据权利要求1所述的阵列基板，其中，每一条触控引线贯穿位于同一列的所有像素单元，和/或，每一条虚设引线贯穿位于同一列的所有像素单元。
  7. 根据权利要求1所述的阵列基板，其中，所述像素单元包括蓝色亚像素、红色亚像素以及绿色亚像素，所述触控引线和/或所述虚设引线设置于所述蓝色亚像素内。
  8. 根据权利要求2所述的阵列基板，其中，所述像素单元包括亚像素，所述亚像素内设置有像素电极，所述公共电极层位于所述像素电极上方，并且
    其中，所述第一子引线位于所述第二子引线的上方，所述自电容电极通过过孔与所述第一子引线相连接。
  9. 根据权利要求8所述的阵列基板，其中，所述像素电极为块状，所述自电容电极在对应于所述像素电极的位置呈条状狭缝图案。
  10. 一种触控显示装置，包括如权利要求1-9中任一项所述的阵列基板。
  11. 一种用于制作如权利要求1-9中任一项所述的阵列基板的方法，包括：制作驱动电路，
    其中，所述方法还包括：
    在衬底基板上形成栅线；
    在形成有所述栅线的衬底基板上形成数据线以及第二子引线；
    在形成有所述数据线和所述第二子引线的衬底基板上形成第一绝缘层；
    在所述第一绝缘层对应于所述第二子引线的位置形成过孔；
    在形成有所述第一绝缘层的衬底基板上形成虚设引线，且在对应于所述第二子引线的位置形成第一子引线，所述第一子引线通过所述过孔与所述第二子引线相连接以形成触控引线，并且所述虚设引线和所述触控引线均与所述驱动电路相连接；以及
    在形成有所述虚设引线和所述触控引线的衬底基板上形成呈阵列分布的多个自电容电极。
  12. 如权利要求11所述的方法，还包括：在形成呈阵列分布的多个自电容电极之前，在形成有所述虚设引线和所述触控引线的衬底基板上形成第二绝缘层，并且在所述第二绝缘层对应于所述第一子引线的位置形成另一过孔，
    其中，所述自电容电极通过所述另一过孔与所述触控引线相连接。
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