WO2014183327A1 - 阵列基板的扇出线结构及显示面板 - Google Patents

阵列基板的扇出线结构及显示面板 Download PDF

Info

Publication number
WO2014183327A1
WO2014183327A1 PCT/CN2013/078292 CN2013078292W WO2014183327A1 WO 2014183327 A1 WO2014183327 A1 WO 2014183327A1 CN 2013078292 W CN2013078292 W CN 2013078292W WO 2014183327 A1 WO2014183327 A1 WO 2014183327A1
Authority
WO
WIPO (PCT)
Prior art keywords
fan
conductive film
out line
line
additional
Prior art date
Application number
PCT/CN2013/078292
Other languages
English (en)
French (fr)
Inventor
杜鹏
Original Assignee
深圳市华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to US14/008,539 priority Critical patent/US9082665B2/en
Publication of WO2014183327A1 publication Critical patent/WO2014183327A1/zh

Links

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/20—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 delay line

Definitions

  • the present invention relates to the field of display devices, and more particularly to a fan-out line structure and a display panel of an array substrate.
  • the display panel usually includes a liquid crystal panel and an OLED panel.
  • the display panel is an important component of a device such as a liquid crystal display device, and the liquid crystal panel can display an image under the cooperation of the backlight module and the driving circuit.
  • a TFT array region 120 is disposed on the array substrate 100 of the liquid crystal panel.
  • the TFT array region is covered with signal lines and TFTs, and the driving circuit board 130 transmits signals of the array substrate through a fanout line 111.
  • the wire is connected to the solder fillet of the drive circuit board, and the set area of the fan-out line 111 is called a fanout area.
  • the soldering legs are closely arranged and the signal lines are dispersed, that is, the distance between the soldering legs and the signal lines is different, such that the fan-out lines are arranged to cause uneven resistance, and the fan-out lines of different lengths of different resistors may cause signals.
  • the waveform is deformed, which affects the display quality of the liquid crystal display device.
  • the normalization of the fan-out area line resistance of the conventional array substrate is completed by the winding design. As shown in FIG. 2, the curved portion 112 is formed on the fan-out line 111 of the fan-out area by the winding, and the fan is enlarged by the curved portion.
  • the length of the outgoing line in turn increases the resistance, causing the signals to be synchronized.
  • the curved portion 112 increases the height H of the fan-out area, and the shorter the linear distance between the two end points of the fan-out line (ie, the linear distance between the two end points of the fan-out line), the longer the line that needs to be wound, due to the limitation of the length of the fan-out line interval. Therefore, the fan line having a shorter linear distance between the two ends requires a plurality of curved portions 112 to increase the winding length (only two curved portions are indicated for each fan-out line in the figure), which causes the height H of the fan-out region to increase. Further, the width of the frame of the liquid crystal display device is affected, which is disadvantageous for the design of the narrow frame.
  • the signal waveform changes The shape is not only the influence of the fan-out line resistance, but also the parasitic capacitance is an important factor affecting the signal waveform; as shown in FIG. 3 is a cross-sectional view of the liquid crystal panel in the fan-out region, and the first conductive film 106 in the fan-out line 111 on the array substrate 100
  • the parasitic capacitance CLC exists between the second conductive film 104 and the ITO conductive layer 201 (indium tin oxide) on the color filter substrate 200. Due to the existence of parasitic capacitance, the signal also has a delay effect, but different lengths
  • the fan-out line has different overlapping areas of the first and second conductive films and the ITO conductive layer on the color filter substrate 200. Therefore, the size of the parasitic capacitance CLC is also different, and the influence on the signal is also different.
  • the technical problem to be solved by the present invention is to provide a fan-out line structure and a display panel of an array substrate having a small fan-out area, an excellent display effect when applied to a display device, and a narrow frame.
  • a fan-out line structure of an array substrate comprising: a plurality of fan-out lines disposed in a fan-out area of the array substrate, and fan-out lines of different lengths among the plurality of fan-out lines
  • the resistance has a difference
  • each of the fan-out lines includes a first conductive film, and at least a part of the plurality of fan-out lines has a smaller resistance than the fan-out line of the other fan-out line, and the fan-out line is covered with an additional conductive film and has a large resistance.
  • the area covering the additional conductive film is smaller than the area of the additional conductive film covered on the fan-out line having a small resistance, and an additional capacitance is formed between the additional conductive film and the first conductive film.
  • the additional conductive film on each of the fan-out lines covers the same width of the first conductive film on the fan-out line, and the length of the additional conductive film covered on the fan-out line of the different resistors is different.
  • the coverage width is the same, so that different coverage lengths can be set according to the length of the fanout line, and the corresponding coverage area is obtained, thereby obtaining corresponding additional capacitance values.
  • the length of the conductive film covered on the fan-out line is: ( Li 2 -L 2 2 ) /L 2 (di £r2-d 2 £rl);
  • the L1 is the length of one of the plurality of fan-out lines
  • the L1 long fan-out line is a reference line
  • the L2 is the length of the fan-out line covered with the additional conductive film
  • the L22 is the L2-length fan.
  • the output line covers the length of the additional conductive film
  • the srl is the relative dielectric constant of the liquid crystal layer in the liquid crystal panel
  • the dl is the thickness of the liquid crystal layer
  • the sr2 is the first conductive film and the additional conductive
  • the relative dielectric constant of the dielectric between the films, the d2 being the thickness of the insulating layer.
  • the reference line is the longest one of the plurality of fanout lines.
  • the longest fan-out line is used as a reference to calculate the required coverage area for the other fan-out lines, and the longest fan-out line has no need to add additional conductive film due to its large resistance.
  • the dielectric between the additional conductive film and the first conductive film is a passivation insulating film.
  • the passivation film has a good insulating effect.
  • a linear distance between one end point and the other end point of at least one of the plurality of fan-out lines has a difference, wherein a straight line distance of at least one of the two end points is shorter than a straight line distance between the two end points of the other fan-out lines
  • the first conductive film is a metal conductive film.
  • the conductive film of the metal conductive film is excellent, and the influence of the signal delay is small.
  • the additional conductive film is an indium tin oxide conductive film.
  • Indium tin oxide conductive film can be It is added directly during the fabrication of the array substrate, so that no additional process is required.
  • the fan-out line further includes a second conductive film disposed under the first conductive film. The fan-out line of the double-layer conductive film has good stability.
  • a display panel comprising the fan-out line structure of any of the above.
  • the invention covers an fan-out line with at least part of the resistance smaller than the other fan-out lines in the plurality of fan-out lines of the array substrate, and the additional conductive film is covered on the fan-out line with larger resistance, and the area of the additional conductive film is smaller than the resistance.
  • An area of the additional conductive film covered on the fan-out line, and an additional capacitance is formed between the additional conductive film and the first conductive film.
  • the additional capacitor has a significant RC delay effect on the signal passing through the fan-out line. Therefore, for a fan-out line with a small resistance, the delay of the signal can be affected by the additional capacitor, making it longer and more resistant.
  • the signal of the fanout line is synchronized.
  • FIG. 1 is a schematic structural view of an array substrate in a conventional liquid crystal panel
  • FIG. 2 is a schematic view showing a fan-out line arrangement of a fan-out area of an array substrate in a conventional liquid crystal panel
  • FIG. 3 is a cross-sectional view in the direction of A in FIG.
  • FIG. 4 is a schematic structural view of a fan-out line of a liquid crystal panel according to Embodiment 1 of the present invention
  • FIG. 5 is a cross-sectional view taken along line B in FIG.
  • FIG. 6 is a schematic view showing the structure of two fan outlet lines according to an embodiment of the present invention.
  • Figure 7 is a partial enlarged view of E in Figure 6,
  • FIG. 8 is a structural view showing the arrangement of three fan-out wires and an additional conductive film according to an embodiment of the present invention
  • FIG. 9 is a structural view showing the arrangement of four fan-out wires and an additional conductive film in the embodiment of the present invention
  • FIG. 10 is a fan in the liquid crystal panel of the fifth embodiment of the present invention. Sectional view of the exit area
  • FIG. 11 is a cross-sectional view of a fan-out area in a liquid crystal panel according to Embodiment 6 of the present invention.
  • Figure 12 is a cross-sectional view showing a fan-out area in a liquid crystal panel according to a seventh embodiment of the present invention. ⁇ detailed description ⁇
  • the embodiment provides a liquid crystal panel, which includes: an array substrate 100 and a color filter substrate 200, wherein the color filter substrate 200 includes: a glass substrate 203, the black matrix 202 and the ITO conductive film 201; and the fan-out line of the array substrate 100 is disposed in the fan-out area 110 (refer to FIG. 4 and FIG. 5, and referring to FIG. 1, the embodiment provides a liquid crystal panel, which includes: an array substrate 100 and a color filter substrate 200, wherein the color filter substrate 200 includes: a glass substrate 203, the black matrix 202 and the ITO conductive film 201; and the fan-out line of the array substrate 100 is disposed in the fan-out area 110 (refer to FIG.
  • the structure thereof includes: a plurality of fan-out lines 111 disposed on the glass substrate 105, the plurality of strips The fan-out lines of different lengths in the fan-out line 111 have different resistances; each of the fan-out lines 111 includes at least a first conductive film 106, and at least a part of the plurality of fan-out lines 111 has a resistance smaller than that of the other fan-out lines. Lllx (as shown in FIG.
  • the fanout line is labeled as lllx for convenience of distinction) is covered with an additional conductive film 101, and a first insulating layer 102 is provided between the additional conductive film 101 and the first conductive film 106 (passivation insulation) Layer, PVA) as a dielectric, in a fan-out line 111X covered with an additional conductive film, an additional conductive film covered on the fan-out line 111 having a larger resistance covering the additional conductive film 101 than the fan-out line 111 having a small resistance
  • the area of the additional conductive film 101 may be electrically connected to an Array Com (ground electrode), a ground (ground line) or other electrodes, and the additional conductive film 101 and the first conductive film 106
  • An additional capacitor CX is formed to reduce the additional capacitance of the difference in impedance between the fan-out lines.
  • the additional capacitor CX is a parasitic capacitor, and an RC delay (RCdelay) is generated for the signal passing through the fan-out line 111. Therefore, for the fan-out line 111 having a small resistance, The signal can be delayed by the additional capacitance CX to be synchronized with the signal of the longer fan-out line 111, which itself has a large delay.
  • the time constant ⁇ of the fanout line 111 signal delay can be calculated by the following formula:
  • R is the resistance of the fan-out line and C is the capacitance. That is, the fan-out line 111 is used as an optimized structure of the present embodiment, and the first insulating layer 102 is a passivation layer (PVA) having a good insulating effect, and the first conductive film 106 is The metal conductive film and the metal conductive film have excellent electrical conductivity effects and have less influence on signal delay.
  • the additional conductive film 101 is an indium tin oxide conductive film (ITO), and the indium tin oxide conductive film can be directly added in the process of the array substrate, so that no additional process is required.
  • the fan-out line 111 further includes a second conductive film 104 disposed under the first conductive film 106, and the second conductive film 104 is also a metal conductive film disposed between the first conductive film 106 and the second conductive film 104.
  • the second insulating layer 103 (gate insulating layer, GI, gate insulator) has a good stability by using the fan-out line 111 of the double-layer conductive film.
  • GI gate insulating layer
  • the structural level of the fan-out line 111 includes: a second conductive film 104 formed on the bottom layer of the array substrate, and a second insulating layer 103 formed on the second conductive film 104, formed on the second insulating layer 103 a first conductive film 106 thereon, and a first insulating layer 102 formed on the first conductive film 106; wherein, the first insulating layer 102 of the partial fan-out line 111 is covered with at least the additional conductive film 101, and the resistor
  • the larger fan-out line 111 (the larger the length, the larger the resistance) covers the area of the additional conductive film 101 over the area of the additional conductive film covered on the fan-out line 111 having a smaller resistance.
  • each fan-out line 111 Since the length of each fan-out line is different, the resistance is different. To achieve the state of signal synchronization, the additional capacitance CX applied to each fan-out line 111 is also different, and the size of the additional capacitor CX is covered on the fan-out line 111. And related to the size of the area in which the first conductive film 106 overlaps. As shown in FIGS. 3 and 5, a parasitic capacitance CLC is also present between the fan-out line 111 not covering the additional conductive film 101 and the ITO conductive film 201 on the color filter substrate 200, and the parasitic capacitance CLC is made of the first conductive line of the fan-out line 111. The film 104 and the second conductive film 106 are formed with the ITO conductive film 201.
  • the parasitic capacitance between the fan-out line 111 and the ITO conductive film 201 can be calculated according to the following calculation formula: dd
  • ⁇ 0 and ⁇ r are the absolute dielectric constant and the relative dielectric constant of the liquid crystal, respectively
  • L and W represent the length and width of the fan-out line, respectively
  • d is the thickness of the liquid crystal layer, which is generally about 3 to 4 ⁇ m.
  • the additional conductive film on each fan-out line 111 has the same width as the overlapping portion of the first conductive film 106 on the fan-out line (the effective area of the capacitor is formed), and the fan-out line 111 of different resistance is covered.
  • the length of the additional conductive film 111 is different, and the fan-out line having a short length needs to cover the longer additional conductive film 101.
  • additional conductive The width of the film 101 coincides with the width of the fan-out line, so that the width of the overlapping portion of the additional conductive film 101 and the first conductive film 106 is the same, so that the process is simple and easy to operate.
  • one of the multiple fan-out lines needs to be selected as the reference line.
  • the longest fan-out line 111a is selected as the reference line, and 111a is used as the reference.
  • the size of the capacitance on the fan-out line 111b covered with the additional conductive film 101 is calculated, that is, the length of the additional conductive film 101 which should be covered on the fan-out line 111b is calculated.
  • the specific calculation process is as follows:
  • the resistances of the fanout line 111a and the fanout line 111b are R1 and R2, respectively, and their calculations are as follows:
  • the capacitance is mainly the first conductive film 106 in the fan-out line 111, the second conductive film 104, and the ITO on the color filter substrate 200.
  • the conductive film 201 is formed, we can set its parasitic capacitance to C1 (CLC), Bay' J
  • ⁇ ⁇ is the absolute dielectric constant
  • s rl is the relative dielectric constant of the liquid crystal in the liquid crystal panel
  • L1 are the length and width of the fan-out line 111a, respectively
  • dl is the thickness of the liquid crystal layer in the liquid crystal panel
  • L1 can Calculated by the current layout tool (the layout tool is a designer-specific tool).
  • the time constant ⁇ 1 is: Since the time constant is only proportional to the square of L1, it can be concluded that the longest fan-out line 111 a on both sides of the fan-out line of the entire fan-out area has the largest time constant, ie ⁇ 1 , in the algorithm here, Based on this time constant.
  • the portion not covered by the ITO conductive film 101 is L21, and the portion covered by the ITO conductive film 101 is L22, which satisfies the following relationship:
  • the capacitor C21 which is not covered by the ITO conductive film 101:
  • ⁇ r2 and d2 represent the first insulating layer 102, that is, the passivation insulating layer (PAV), respectively
  • the relative dielectric constant sr of the PAV and the liquid crystal are not much different, but due to the small thickness, the new capacitor CX is equal in area. It will be much larger than the capacitance formed by the fan-out line and the TIO conductive film on the color film substrate. As shown in Fig. 5 in this embodiment, CX is generally about 10 times that of CLC.
  • Capacitor C21 and capacitor C22 are in parallel relationship, so the capacitance of the entire fan-out line 111b
  • the linear distances from one end of at least a part of the fan-out lines 111 to the other end point of the plurality of fan-out lines 111 are different, and the fan-out line 111a and the fan are still used.
  • the straight line distance between the two end points of the fan-out line 111b is shorter than the linear distance between the two end points of the fan-out line 111a. Therefore, the present embodiment is provided with the curved portion 112 for lengthening the fan-out line 111b.
  • Resistor R and capacitor C can be adjusted at the same time to achieve the best process requirements, design requirements and product requirements.
  • the winding length can be reduced, and for the fan-out line whose resistance between the resistance and the reference line is too large, the winding can be selected. Increase the coverage of the additional conductive film.
  • this kind of The case is more suitable, which can solve the problem that the fan-out area is highly entangled due to too many windings, and can solve the problem of signal synchronization of the fan-out line.
  • the difference from the first embodiment is that the width of the additional conductive film 101 in this embodiment is smaller than the width of the fan-out line 111, and different widths may be selected according to the size of the panel and the process requirements.
  • the width of the additional conductive film 101 is larger than the width of the fan-out line 111.
  • This embodiment can ensure that the width of the overlapping portion of the additional conductive film 101 and the first conductive film is always the same as The width of the first conductive film is the same, thereby ensuring the accuracy of obtaining additional capacitance.
  • the present embodiment uses an integral conductive film 101 covering a plurality of fan-out lines to achieve the purpose of obtaining additional capacitance, which is seen in the manufacturing process of the panel. It's more convenient, it doesn't need to make complicated masks, and the production cost is relatively low.
  • the fan-out line 111 is a single-layer conductive structure, that is, the transmission portion of the fan-out line 111 is provided with only one first conductive film 106, and the first conductive film 106 is disposed. It is a metal conductive film, and the insulating medium of the additional capacitor CX is the first insulating layer 102, which is a passivation insulating layer (PAV).
  • PAV passivation insulating layer
  • the fan-out line 111 of the present embodiment also adopts a single-layer conductive structure.
  • the insulating medium of the capacitor CX is the first insulating layer 102 and the second insulating layer 103, which is blunt. The insulating layer and the gate insulating layer.
  • the fan-out line 111 of the present embodiment still adopts a single-layer conductive structure, but the difference is that the additional conductive film 101 is a metal conductive film, and the additional conductive film 101 is covered with the first insulating layer 102.
  • the insulating medium between the first conductive film 106 and the additional conductive film 101 is a second insulating layer 103, that is, a gate insulating layer.

Abstract

一种阵列基板的扇出线结构及液晶面板，所述扇出线结构包括：布置在阵列基板扇出区的多条扇出线，所述多条扇出线中长度不同的扇出线的电阻具有差异；所述每条扇出线包括第一导电膜，所述多条扇出线中至少一部分其电阻小于其它扇出线的扇出线上覆盖有附加导电膜，电阻较大的扇出线上覆盖所述附加导电膜的面积小于电阻较小的扇出线上覆盖的附加导电膜的面积，所述附加导电膜与所述第一导电膜之间形成一附加电容。

Description

阵列 的扇出线结构及显示面板
【技术领域】
本发明涉及显示装置领域， 更具体的说， 涉及一种阵列基板的扇 出线结构及显示面板。
【背景技术】
显示面板通常包括有液晶面板和 OLED 面板。 显示面板是诸如 液晶显示装置等装置的重要组件，在背光模组的配合以及驱动电路的 驱动下， 液晶面板能够显示出图像。
如图 1所示， 在液晶面板的阵列基板 100上设置有 TFT阵列区 域 120, TFT阵列区域内布满了信号线以及 TFT, 驱动电路板 130通 过扇出线 111 ( fanout line )将阵列基板的信号线与驱动电路板的焊脚 连接， 而扇出线 111的设置区域则称为扇出区 （ fanout area )。
由于焊脚紧密排列而信号线分散排列，也就是说焊脚到信号线的 距离各不相同， 这样扇出线设置之后就造成了电阻不均的情况， 不同 长度不同电阻的扇出线会使信号的波形发生变形，从而会影响液晶显 示装置的显示质量。 目前常规的阵列基板扇出区线电阻均一化都是通 过绕线设计完成， 如图 2所示， 通过绕线在扇出区的扇出线 111上形 成了弯曲部 112, 利用弯曲部增大扇出线的长度进而增大电阻， 使信 号趋于同步。 弯曲部 112增加了扇出区的高度 H, 扇出线两个端点的 直线距离越短（即扇出线两个端点的直线距离）的其需要绕的线就越 长， 由于扇出线间隔长度的限制， 因而两端直线距离越短的扇出线则 需要设置多个弯曲部 112提高绕线长度（图中每条扇出线仅示意两个 弯曲部）， 这样则会造成扇出区域的高度 H增加， 进而影响到液晶显 示装置的边框宽度， 不利于窄边框化的设计。 但是， 信号波形发生变 形不仅仅在于扇出线电阻的影响，寄生电容也是影响信号波形的重要 因素； 如图 3所示为液晶面板在扇出区域的剖面图， 阵列基板 100上 扇出线 111内的第一导电膜 106、 第二导电膜 104与彩膜基板 200上 的 ITO导电层 201 (氧化铟锡）之间存在寄生电容 CLC, 由于寄生电 容的存在， 也对信号造成了延时的影响， 但是， 不同长度的扇出线， 第一、第二导电膜与彩膜基板 200上的 ITO导电层重叠面积不同， 因 此寄生电容 CLC的大小也不同， 对于信号造成的影响也不相同。
【发明内容】
本发明所要解决的技术问题是提供一种扇出区高度小、应用于显 示装置时显示效果更优秀、边框更窄的阵列基板的扇出线结构及显示 面板。
本发明的目的是通过以下技术方案来实现的：一种阵列基板的扇 出线结构， 包括： 布置在阵列基板扇出区的多条扇出线， 所述多条扇 出线中长度不同的扇出线的电阻具有差异；所述每条扇出线包括一第 一导电膜，所述多条扇出线中至少一部分其电阻小于其它扇出线电阻 的扇出线上覆盖有附加导电膜，电阻较大的扇出线上覆盖所述附加导 电膜的面积小于电阻较小的扇出线上覆盖的附加导电膜的面积，所述 附加导电膜与所述第一导电膜之间形成一附加电容。 优选的，所述每条扇出线上的附加导电膜在该扇出线上覆盖所述 第一导电膜的宽度相同，所述不同电阻的扇出线上覆盖的附加导电膜 的长度不同。覆盖宽度相同， 从而可以根据扇出线长度的不同而设置 不同的覆盖长度，获得相应的覆盖面积，进而获得相应的附加电容值。 优选的， 所述扇出线上覆盖的导电膜的长度为：
Figure imgf000004_0001
( Li2-L2 2 ) /L2(di £r2-d2£rl) ;
所述 L I为多条扇出线中一条扇出线的长度， 该 L1长的扇出线 为参照线， 所述 L2为覆盖有附加导电膜的扇出线的长度， 所述 L22 所述长为 L2的扇出线上覆盖附加导电膜的长度， 所述 srl为液晶面 板中液晶层的相对介电常数， 所述 dl为所述液晶层的厚度， 所述 sr2 为所述第一导电膜与所述附加导电膜之间的电介质的相对介电常数， 所述 d2为所述绝缘层的厚度。
优选的， 所述参照线为所述多条扇出线中最长的一条。 利用最长 的扇出线作为参照， 以计算其它扇出线所需要的覆盖面积， 而最长的 扇出线由于本身电阻较大， 不需要再增加附加导电膜。
优选的 ,所述附加导电膜与所述第一导电膜之间的电介质为钝化 绝缘膜。 钝化膜拥有良好的绝缘效果。
优选的，所述多条扇出线中至少一部分扇出线的一个端点到另一 个端点的直线距离具有差异，其中至少一条两个端点的直线距离短于 其它扇出线的两个端点的直线距离的扇出线设置有用于加长该扇出 线的弯曲部。由于扇出线对信号波形的影响是电阻 R以及寄生电容 C 的综合影响， 扇出线信号延迟的时间常数为 T =RC, 需要使每一条的 扇出线的信号延迟的时间常数相等，则可以同时对电阻 R以及电容 C 进行调整， 以达到最佳的工艺要求、 设计要求以及产品要求。
优选的， 所述第一导电膜为金属导电膜。金属导电膜的导电效果 优秀， 信号延时影响较小。
优选的， 所述附加导电膜为氧化铟锡导电膜。 氧化铟锡导电膜可 以在阵列基板的制作过程中直接添加， 从而不需要另外增加工艺。 优选的，所述扇出线还包括设置在所述第一导电膜之下的第二导 电膜。 双层导电膜的扇出线拥有较好的稳定性。
一种显示面板， 包括上述任一所述的扇出线结构。 本发明通过在阵列基板的多条扇出线中对至少部分电阻小于其 它扇出线的扇出线上覆盖有附加导电膜，电阻较大的扇出线上覆盖所 述附加导电膜的面积小于电阻较小的扇出线上覆盖的附加导电膜的 面积， 所述附加导电膜与所述第一导电膜之间形成一附加电容。 该附 加电容对通过扇出线的信号会产生明显 RC延迟效果， 因而， 对于电 阻较小的扇出线来说， 可以通过附加电容来对信号产生延迟的影响， 使其与较长、 电阻较大的扇出线的信号达到同步的状态。
【附图说明】
图 1是现有液晶面板中阵列基板的结构示意图，
图 2是现有液晶面板中阵列基板的扇出区的扇出线布置示意图， 图 3是图 2中 A方向剖面图，
图 4是本发明实施例一的液晶面板扇出线结构示意图， 图 5是图 4中 B方向剖面图，
图 6是本发明实施例二扇出线结构示意图，
图 7是图 6中 E的局部放大图，
图 8是本发明实施例三扇出线与附加导电膜的设置结构图， 图 9是本发明实施例四扇出线与附加导电膜的设置结构图， 图 10是本发明实施例五液晶面板中扇出区的截面图，
图 11是本发明实施例六液晶面板中扇出区的截面图，
图 12是本发明实施例七液晶面板中扇出区的截面图。 【具体实施方式】
下面结合附图和较佳的实施例以液晶面板为例对本发明作进一 步说明。
实施例一 如图 4及图 5所示， 并参考图 1 , 本实施例提供一种液晶面板， 该液晶面板包括： 阵列基板 100以及彩膜基板 200, 其中， 彩膜基板 200包括： 玻璃基板 203、 黑矩阵 202以及 ITO导电膜 201 ; 而阵列 基板 100的扇出线设置在扇出区 110 (参考图 1 ), 其结构包括： 多条 布置在玻璃基板 105的扇出线 111 , 所述多条扇出线 111中长度不同 的扇出线的电阻具有差异；所述每条扇出线 111至少包括第一导电膜 106, 所述多条扇出线 111 中至少一部分其电阻小于其它扇出线的电 阻的扇出线 lllx (如图 5所示， 为方便区别， 将该扇出线标为 lllx ) 上覆盖有附加导电膜 101 , 附加导电膜 101与第一导电膜 106之间具 有第一绝缘层 102 (钝化绝缘层， PVA )作为电介质， 在覆盖有附加 导电膜的扇出线 111X中， 电阻较大的扇出线 111上覆盖所述附加导 电膜 101的面积小于电阻较小的扇出线 111上覆盖的附加导电膜的面 积（如图 4所示 ), 所述附加导电膜 101可以与 Array Com (公共电 极）、 Ground (接地线）或其他电极导通， 所述附加导电膜 101与所 述第一导电膜 106之间形成一附加电容 CX用以减小扇出线之间阻抗 差异的附加电容。 所述附加电容 CX是一个寄生的电容，对通过扇出线 111的信号 会产生 RC延迟（RCdelay ), 因而，对于电阻较小的扇出线 111来说， 可以通过附加电容 CX来对信号产生延迟的影响，使其与本身存在较 大延迟的较长的扇出线 111的信号达到同步的状态。扇出线 111信号 延迟的时间常数 τ我们可以通过以下公式计算：
τ =RC
其中， R为扇出线的电阻， C为电容。 也就是说， 扇出线 111信 作为本实施例的一种优化结构，所述第一绝缘层 102采用拥有良 好绝缘效果的钝化绝缘层（PVA, passivation layer ), 所述第一导电膜 106为金属导电膜，金属导电膜的导电效果优秀，信号延时影响较小。 所述附加导电膜 101为氧化铟锡导电膜（ITO ),氧化铟锡导电膜可以 在阵列基板的制程中直接添加， 从而不需要另外增加工艺。
扇出线 111还包括设置在所述第一导电膜 106之下的第二导电膜 104, 所述第二导电膜 104也为金属导电膜第一导电膜 106与第二导 电膜 104之间设置有第二绝缘层 103(栅极绝缘层， GI, gate insulator ), 采用双层导电膜的扇出线 111拥有较好的稳定性， 当然， 也可以使增 加第三层导电膜或者更多。 由此， 扇出线 111的结构层次包括： 形成 在阵列基板底层的第二导电膜 104, 形成在所述第二导电膜 104之上 的第二绝缘层 103 , 形成在所述第二绝缘层 103 之上的第一导电膜 106, 以及形成在所述第一导电膜 106之上的第一绝缘层 102; 其中， 部分扇出线 111的第一绝缘层 102至少覆盖有附加导电膜 101 , 且电 阻较大的扇出线 111 (长度越大， 电阻越大）上覆盖所述附加导电膜 101的面积小于电阻较小的扇出线 111上覆盖的附加导电膜的面积。 由于每条扇出线的长度不同， 因而其电阻不同，要达到信号同步 的状态， 则施加在各条扇出线 111上的附加电容 CX也不同， 而附加 电容 CX 的大小与其覆盖在扇出线 111上并与第一导电膜 106重叠的 面积大小相关。如图 3及图 5所示， 没有覆盖附加导电膜 101的扇出 线 111与彩膜基板 200上的 ITO导电膜 201之间也存在寄生电容 CLC, 该寄生电容 CLC由扇出线 111 的第一导电膜 104、 第二导电膜 106 与 ITO导电膜 201形成。这个寄生电容 CLC由于液晶层的厚度较大， 其大小远远小于附加电容 CX, 因而其所造成的 RC延迟也有限， 虽 然这样， 为了计算的准确， 在计算电容对扇出线的影响时， 也要将其 计算在内。扇出线 111与 ITO导电膜 201之间的寄生电容大小可以按 照下面的计算公式算出： d d
其中 ε 0和 ε r分别是绝对介电常数和液晶相对介电常数， L和 W分别表示扇出线的长度和宽度， d是液晶层的厚度， 一般为 3 ~ 4 μ m左右。
下面，我们通过计算一条扇出线上应当覆盖附加导电膜的面积对 本发明进一步进行说明。
为方便计算，每条扇出线 111上的附加导电膜在该扇出线上与所 述第一导电膜 106的重叠部分的宽度相同 （形成电容的有效面积）， 不同电阻的扇出线 111上覆盖的附加导电膜 111的长度不同， 长度较 短的扇出线需要覆盖更长附加导电膜 101。 在本实施例中， 附加导电 膜 101的宽度与扇出线的宽度一致，从而附加导电膜 101与所述第一 导电膜 106的重叠部分的宽度是相同的， 这样工艺筒单， 操作方便。
要确定附加电容在扇出线上的覆盖长度，需要在多条扇出线中选 出一条作为参照线， 如图 4所示， 本实施例选用最长的扇出线 111a 作为参照线， 以 111a作为参照计算出覆盖有附加导电膜 101的扇出 线 111b上电容的大小， 也就是计算应该覆盖在扇出线 111b上的附加 导电膜 101的长度。 具体计算过程如下：
设扇出线 111a以及扇出线 111b的电阻分别为 R1和 R2 , 它们的 计算如下：
'. ¾
¾ =―—— -
1 .
对于没有任何附加导电膜覆盖的扇出线 111a来说， 如图 3或 5 所示，其电容主要是扇出线 111内的第一导电膜 106、第二导电膜 104 与彩膜基板 200上的 ITO导电膜 201形成，我们可以设其寄生电容为 C1 ( CLC ), 贝' J
其中， ε θ是绝对介电常数， s rl是液晶面板中液晶的相对介电 常数， Ll、 W是分别是扇出线 111a的长度和宽度， dl是液晶面板中 液晶层的厚度， 其中 L1可以通过现在 layout (扇出）工具计算得到 ( layout工具为设计人员专用工具）。 对于扇出线 111a来讲， 时间常 数 τ 1为：
Figure imgf000010_0001
由于时间常数只和 L1的平方成正比， 所以可以得出结论： 整个 扇出区的扇出线中两侧的最长的扇出线 111 a的时间常数最大，即 τ 1 , 在这里的算法中， 就以这个时间常数为基准。
设扇出线 11 lb上，没有被 ITO导电膜 101覆盖的部分长度为 L21 , 被 ITO导电膜 101覆盖的部分长度为 L22, 它们满足以下关系：
没有被 ITO导电膜 101覆盖部分的电容 C21 :
€ll = ' .4一
被 ITO覆盖部分的电容 C22:
Figure imgf000010_0002
其中 ε r2和 d2分别代表第一绝缘层 102即钝化绝缘层（ PAV ), PAV的相对介电常数 s r和液晶相差不大， 但由于厚度小， 所以在面 积相等的情况下新的电容 CX会远远大于扇出线和彩膜基板上 TIO导 电膜形成的电容， 如本实施例中图 5所示， CX—般是 CLC的 10倍 左右。
电容 C21与电容 C22为并联关系， 因此整个扇出线 111b的电容
C2:
在调整扇出线的阻抗时， 以扇出线 llla的时间常数 τ 1为基准： 从这个由此可以建立方程组并解出： ξ _ ETld2!j -
_ ^ i^; : i¾一 ■)
2:2: = 1- ~~ ~ " 7 其中 L22即是在扇出线 111b上应该覆盖的附加导电膜 101的长 度。 由此我们可以知道扇出线 111b上需要覆盖的 ITO导电膜的面积
Θ
疋：
S=WL22 作为本实施例的一种改进， 如图 4所示， 多条扇出线 111中至少 一部分扇出线的一个端点到另一该端点的直线距离具有差异，仍然以 扇出线 111a与扇出线 111b为例， 扇出线 111b两个端点的直线距离 短于扇出线 111a的两个端点的直线距离， 因而， 本实施例通过在其 上设置用于加长该扇出线 111b的弯曲部 112。由于扇出线对信号波形 的影响是电阻 R以及寄生电容 C的综合影响， 扇出线信号延迟的时 间常数为1 =1^, 也就是说， 需要使每一条的扇出线的信号延迟的时 间常数相等， 可以同时对电阻 R以及电容 C进行调整， 以达到最佳 的工艺要求、 设计要求以及产品要求。 本实施例中， 通过在绕线的基 础上增加覆盖附加导电膜形成附加电容， 从而可以减少绕线长度， 对 于电阻与参照线的时间常数相差太大的扇出线来说，可以选择绕线与 增加覆盖附加导电膜。特别是针对较大尺寸的液晶电视来说， 这种方 案更为合适， 既可以解决扇出区由于绕线过多而高度 Η较大的问题， 又可以解决扇出线信号同步的问题。
实施例二
如图 6及图 7所示， 与实施例一不同的是，本实施例中附加导电 膜 101的宽度小于扇出线 111的宽度， 根据面板的大小及工艺需求， 可以选择不同的宽度。
实施例三
如图 8所示为另一种实施方式，附加导电膜 101的宽度大于扇出 线 111的宽度，这种实施方式可以保证附加导电膜 101与第一导电膜 的重叠部分的宽度始终是与所述第一导电膜的宽度是相同的，从而保 证了获得附加电容的精确度。
实施例四
如图 9所示， 与上述实施例均不同的是，本实施例采用一整块覆 盖在多根扇出线上的附加导电膜 101达到获取附加电容的目的，此种 方式在面板的制程中显得更为筒便， 不需要制作复杂的掩膜， 制作成 本相对较低。
实施例五
如图 10所示， 与实施例一不同的是， 扇出线 111采用的是单层 导电结构， 也就是， 扇出线 111的传输部分仅设置有一层第一导电膜 106, 该第一导电膜 106为金属导电膜， 而附加电容 CX的绝缘介质 是第一绝缘层 102, 该第一绝缘层 102为钝化绝缘层（PAV )。 这种设 置方式可以减少一道面板的制程， 但其稳定性没有实施例一的高。 实施例六
如图 11所示， 本实施例的扇出线 111也是采用单层导电结构， 与实施例五不同的是，加电容 CX的绝缘介质是第一绝缘层 102以及 第二绝缘层 103 , 也就是钝化绝缘层以及栅极绝缘层。
实施例七
如图 12所示， 本实施例的扇出线 111仍然采用单层导电结构， 但不同的是， 附加导电膜 101 采用的是金属导电膜， 在附加导电膜 101之上覆盖有第一绝缘层 102用以保护该附加导电膜 101 , 第一导 电膜 106与所述附加导电膜 101之间的绝缘介质是第二绝缘层 103即 栅极绝缘层。
以上内容是结合具体的优选实施方式对本发明所作的进一步详 细说明， 不能认定本发明的具体实施只局限于这些说明。对于本发明 所属技术领域的普通技术人员来说， 在不脱离本发明构思的前提下， 还可以做出若干筒单推演或替换， 都应当视为属于本发明的保护范 围。

Claims

权利要求
1、 一种阵列基板的扇出线结构， 包括：
多条布置在阵列基板扇出区的扇出线，所述多条扇出线中长度不 同的扇出线的电阻具有差异；
所述每条扇出线包括第一导电膜，
所述多条扇出线中至少一部分其电阻小于其它扇出线电阻的扇 出线上覆盖有附加导电膜， 在覆盖有所述附加导电膜的扇出线中， 电 阻较大的扇出线上覆盖所述附加导电膜的面积小于电阻较小的扇出 线上覆盖的附加导电膜的面积，所述附加导电膜与所述第一导电膜之 间形成一附加电容。
2、 如权利要求 1所述的阵列基板的扇出线结构， 其中， 所述每 条扇出线上的附加导电膜在该扇出线上与所述第一导电膜重叠部分 的宽度相同， 所述不同电阻的扇出线上覆盖的附加导电膜的长度不 同。
3、 如权利要求 2所述的阵列基板的扇出线结构， 其中， 所述扇 出线上覆盖的附加导电膜的长度为：
Figure imgf000014_0001
(Li2-L22 ) /L2(di £r2"d2£rl)；
所述 Ll为多条扇出线中一条扇出线的长度， 该 L1长的扇出线 为参照线， 所述 L2为覆盖有附加导电膜的扇出线的长度， 所述 L22 所述长为 L2的扇出线上覆盖附加导电膜的长度， 所述 srl为液晶面 板中液晶层的相对介电常数， 所述 dl为所述液晶层的厚度， 所述 sr2 为所述第一导电膜与所述附加导电膜之间的电介质的相对介电常数， 所述 d2为所述电介质的厚度。
4、 如权利要求 3所述的阵列基板的扇出线结构， 其中， 所述参 照线为所述多条扇出线中最长的一条。
5、 如权利要求 1所述的阵列基板的扇出线结构， 其中， 所述附 加导电膜与所述第一导电膜之间的电介质为钝化绝缘膜。
6、 如权利要求 1所述的阵列基板的扇出线结构， 其中， 所述多 条扇出线中至少一部分扇出线的一个端点到另一个端点的直线距离 具有差异，其中至少一条两个端点的直线距离短于其它扇出线的两个 端点的直线距离的扇出线设置有用于加长该扇出线的弯曲部。
7、 如权利要求 1所述的阵列基板的扇出线结构， 其中， 所述第 一导电膜为金属导电膜。
8、 如权利要求 1所述的阵列基板的扇出线结构， 其中， 所述附 加导电膜为氧化铟锡导电膜或金属导电膜。
9、 如权利要求 1所述的阵列基板的扇出线结构， 其中， 所述扇 出线还包括设置在所述第一导电膜之下的第二导电膜。
10、 如权利要求 1所述的阵列基板的扇出线结构， 其中， 所述附 加导电膜是覆盖在多条扇出线上的一整块结构。
11、 一种阵列基板的扇出线结构， 包括：
多条布置在阵列基板扇出区的扇出线，所述多条扇出线中长度不 同的扇出线的电阻具有差异；
所述扇出线包括形成在阵列基板底层的第二导电膜，形成在所述 第二导电膜之上的第二绝缘层，形成在所述第二绝缘层之上的第一导 电膜， 以及形成在所述第一导电膜之上的第一绝缘层；
多条扇出线中的部分扇出线的第一绝缘层之上覆盖有附加导电 膜与所述第一导电膜之间形成一个用以减小扇出线之间阻抗差异的 附加电容；电阻较大的扇出线上覆盖所述附加导电膜的面积小于电阻 较小的扇出线上覆盖的附加导电膜的面积。
12、 一种显示面板， 包括：
多条布置在阵列基板扇出区的扇出线，所述多条扇出线中长度不 同的扇出线的电阻具有差异；
所述每条扇出线包括一第一导电膜，
所述多条扇出线中至少一部分其电阻小于其它扇出线的扇出线 上覆盖有附加导电膜，电阻较大的扇出线上覆盖所述附加导电膜的面 积小于电阻较小的扇出线上覆盖的附加导电膜的面积，所述附加导电 膜与所述第一导电膜之间形成一附加电容。
13、 如权利要求 12所述的显示面板， 其中， 所述每条扇出线上 的附加导电膜在该扇出线上与所述第一导电膜重叠部分的宽度相同， 所述不同电阻的扇出线上覆盖的附加导电膜的长度不同。
14、 如权利要求 13所述的显示面板， 其中， 所述扇出线上覆盖 的导电膜的长度为：
Figure imgf000016_0001
(Li2-L2 2) /L2(di£r2-d2£rl);
所述 L1为多条扇出线中一条扇出线的长度， 该 L1长的扇出线 为参照线， 所述 L2为覆盖有附加导电膜的扇出线的长度， 所述 L22 所述长为 L2的扇出线上覆盖附加导电膜的长度， 所述 srl为液晶面 板中液晶层的相对介电常数， 所述 dl为所述液晶层的厚度， 所述 sr2 为所述第一导电膜与所述附加导电膜之间的电介质的相对介电常数， 所述 d2为所述电介质的厚度。
15、 如权利要求 14所述的显示面板， 其中， 所述参照线为所述 多条扇出线中最长的一条。
16、 如权利要求 12所述的显示面板， 其中， 所述附加导电膜与 所述第一导电膜之间的电介质为钝化绝缘膜。
17、 如权利要求 12所述的显示面板， 其中， 所述多条扇出线中 至少一部分扇出线的一个端点到另一个端点的直线距离具有差异，其 中至少一条两个端点的直线距离短于其它扇出线的两个端点的直线 距离的扇出线设置有用于加长该扇出线的弯曲部。
18、 如权利要求 12所述的显示面板， 其中， 所述第一导电膜为 金属导电膜。
19、 如权利要求 12所述的显示面板， 其中， 所述附加导电膜为 氧化铟锡导电膜或金属导电膜。
20、 如权利要求 12所述的显示面板， 其中， 所述附加导电膜是 覆盖在多条扇出线上的一整块结构。
PCT/CN2013/078292 2013-05-13 2013-06-28 阵列基板的扇出线结构及显示面板 WO2014183327A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/008,539 US9082665B2 (en) 2013-05-13 2013-06-28 Fanout line structure of array substrate and display panel

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201310173613.0 2013-05-13
CN201310173613.0A CN103309107B (zh) 2013-05-13 2013-05-13 阵列基板的扇出线结构及显示面板

Publications (1)

Publication Number Publication Date
WO2014183327A1 true WO2014183327A1 (zh) 2014-11-20

Family

ID=49134487

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2013/078292 WO2014183327A1 (zh) 2013-05-13 2013-06-28 阵列基板的扇出线结构及显示面板

Country Status (2)

Country Link
CN (1) CN103309107B (zh)
WO (1) WO2014183327A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20220082878A1 (en) * 2019-01-30 2022-03-17 HKC Corporation Limited Driver circuit and display panel

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104062789A (zh) * 2014-07-21 2014-09-24 深圳市华星光电技术有限公司 显示装置
CN104765169B (zh) * 2015-02-04 2018-01-05 深圳市华星光电技术有限公司 一种阵列基板的检测线路及阵列基板
CN105188259B (zh) * 2015-10-23 2017-12-19 重庆京东方光电科技有限公司 印刷电路板、显示面板及用于印刷电路板的布线方法
CN107689208A (zh) * 2016-08-04 2018-02-13 上海和辉光电有限公司 一种改善oled驱动线信号延迟的结构及其制备方法
CN106125418A (zh) * 2016-08-11 2016-11-16 深圳市华星光电技术有限公司 显示装置及其显示面板
KR20180041281A (ko) * 2016-10-13 2018-04-24 삼성디스플레이 주식회사 유기 발광 표시 장치
CN106531119A (zh) * 2017-01-10 2017-03-22 深圳市华星光电技术有限公司 一种驱动电路及显示装置
CN107329313A (zh) * 2017-08-17 2017-11-07 惠科股份有限公司 一种显示面板和显示装置
CN107479276B (zh) 2017-08-28 2020-08-04 厦门天马微电子有限公司 触控显示面板及包含其的触控显示装置
KR102352312B1 (ko) * 2017-09-29 2022-01-19 삼성디스플레이 주식회사 표시 장치
CN107544189B (zh) * 2017-10-20 2020-05-15 上海天马微电子有限公司 一种阵列基板、显示面板和显示装置
CN110416254B (zh) * 2018-04-27 2022-03-01 上海和辉光电股份有限公司 阵列基板及显示面板
CN108732813A (zh) 2018-05-29 2018-11-02 深圳市华星光电技术有限公司 液晶面板、液晶显示器及电子设备
CN108873516A (zh) * 2018-06-22 2018-11-23 惠科股份有限公司 显示面板及其应用的显示装置
CN108919578A (zh) * 2018-06-22 2018-11-30 惠科股份有限公司 显示面板及其应用的显示装置
CN113325642B (zh) * 2018-06-29 2022-12-30 上海中航光电子有限公司 一种阵列基板、显示面板及显示装置
TWI679467B (zh) * 2018-12-17 2019-12-11 友達光電股份有限公司 用於虛擬實境裝置之顯示螢幕
CN114167652B (zh) * 2021-11-09 2024-03-29 Tcl华星光电技术有限公司 显示面板以及移动终端
CN115332268A (zh) * 2022-07-07 2022-11-11 惠科股份有限公司 显示面板及其阵列基板

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040107744A (ko) * 2003-06-12 2004-12-23 삼성전자주식회사 액정표시장치
CN101086995A (zh) * 2006-06-08 2007-12-12 三星电子株式会社 薄膜晶体管基板及具有该薄膜晶体管基板的液晶显示面板
CN101728344A (zh) * 2008-10-10 2010-06-09 华映视讯（吴江）有限公司 可补偿走线信号传输时间延迟差异的信号连接线路
CN201590281U (zh) * 2009-12-04 2010-09-22 华映视讯（吴江）有限公司 扇形导线结构及其应用的显示面板
JP2012252216A (ja) * 2011-06-03 2012-12-20 Renesas Electronics Corp パネル表示装置のデータドライバ

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040107744A (ko) * 2003-06-12 2004-12-23 삼성전자주식회사 액정표시장치
CN101086995A (zh) * 2006-06-08 2007-12-12 三星电子株式会社 薄膜晶体管基板及具有该薄膜晶体管基板的液晶显示面板
CN101728344A (zh) * 2008-10-10 2010-06-09 华映视讯（吴江）有限公司 可补偿走线信号传输时间延迟差异的信号连接线路
CN201590281U (zh) * 2009-12-04 2010-09-22 华映视讯（吴江）有限公司 扇形导线结构及其应用的显示面板
JP2012252216A (ja) * 2011-06-03 2012-12-20 Renesas Electronics Corp パネル表示装置のデータドライバ

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20220082878A1 (en) * 2019-01-30 2022-03-17 HKC Corporation Limited Driver circuit and display panel

Also Published As

Publication number Publication date
CN103309107B (zh) 2016-09-21
CN103309107A (zh) 2013-09-18

Similar Documents

Publication Publication Date Title
WO2014183327A1 (zh) 阵列基板的扇出线结构及显示面板
KR101412849B1 (ko) 전자기 감응 타입 액정 패널 및 이를 제조하는 방법 및 액정 표시 장치
US9711541B2 (en) Display panel and method for forming an array substrate of a display panel
US10229938B2 (en) Array substrate and fabrication method thereof
US9857922B2 (en) Touch panel and manufacturing method thereof
CN103376605B (zh) 显示装置
US20150173232A1 (en) Display panel and fan out-line structure thereof
CN203241671U (zh) 阵列基板的扇出线结构及显示面板
TWI528239B (zh) 觸控顯示裝置
CN103309069B (zh) 阵列基板的扇出线结构及显示面板
US9210797B2 (en) Array substrate, manufacturing method thereof, and flat panel display device
CN100369258C (zh) 有源元件阵列基板
WO2014153886A1 (zh) 阵列基板及其扇出线结构
CN101673004B (zh) 触控显示面板以及显示装置
KR20080076519A (ko) 표시 기판
US11086460B2 (en) Touch substrate, method for manufacturing same, and touch device
US9619085B2 (en) Pattern of a capacitive touch device and manufacturing method thereof
WO2014176876A1 (zh) 显示面板及其制作方法、液晶显示器
US20150338976A1 (en) Touch display device
JP2014106437A (ja) 液晶表示パネルおよびその製造方法
US9171664B2 (en) Touch input device and induction coil thereof
TWI510985B (zh) 觸控屏模組
JP5656094B2 (ja) 引出線配線装置及び画像表示装置
TW201721263A (zh) 顯示面板
TWM474202U (zh) 觸控輸入裝置及其之感應線圈

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 14008539

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 13884853

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 13884853

Country of ref document: EP

Kind code of ref document: A1