WO2014190771A1 - 淀积在锗基或三五族化合物基衬底上的栅介质的处理方法 - Google Patents

淀积在锗基或三五族化合物基衬底上的栅介质的处理方法 Download PDF

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WO2014190771A1
WO2014190771A1 PCT/CN2014/070302 CN2014070302W WO2014190771A1 WO 2014190771 A1 WO2014190771 A1 WO 2014190771A1 CN 2014070302 W CN2014070302 W CN 2014070302W WO 2014190771 A1 WO2014190771 A1 WO 2014190771A1
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gate dielectric
fluorine
plasma
electric field
tri
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French (fr)
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黄如
林猛
安霞
黎明
云全新
李志强
李敏
刘朋强
张兴
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Peking University
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    • H—ELECTRICITY
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    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/65—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials
    • H10P14/6516—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials
    • H10P14/6518—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by introduction of substances into an already-existing insulating layer
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    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01356—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being a Group IV material and not being silicon, e.g. Ge, SiGe or SiGeC
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01358—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being a Group III-V material
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/691—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator comprising metallic compounds, e.g. metal oxides or metal silicates 
    • H—ELECTRICITY
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/65—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials
    • H10P14/6516—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials
    • H10P14/6529—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by exposure to a gas or vapour
    • H10P14/6532—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by exposure to a gas or vapour by exposure to a plasma
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    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6938—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides
    • H10P14/6939—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides characterised by the metal
    • H10P14/69391—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides characterised by the metal the material containing aluminium, e.g. Al2O3
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6938—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides
    • H10P14/6939—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides characterised by the metal
    • H10P14/69392—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides characterised by the metal the material containing hafnium, e.g. HfO2
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/40—Ion implantation into wafers, substrates or parts of devices into insulating materials
    • H—ELECTRICITY
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/20—Diffusion for doping of insulating layers
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P70/00—Cleaning of wafers, substrates or parts of devices
    • H10P70/20—Cleaning during device manufacture
    • H10P70/23—Cleaning during device manufacture during, before or after processing of insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/90—Thermal treatments, e.g. annealing or sintering
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/90—Thermal treatments, e.g. annealing or sintering
    • H10P95/904—Thermal treatments, e.g. annealing or sintering of Group III-V semiconductors

Definitions

  • TECHNICAL FIELD The present invention relates to the field of semiconductor devices, and in particular to a method of processing a gate dielectric deposited on a ruthenium-based or tri-five-based substrate. Background technique
  • MOSFET metal-oxide-semiconductor field-effect transistor
  • Tantalum and tri-five compound semiconductors are considered to be the preferred materials for the next generation of high-speed CMOS circuits due to their high hole and electron mobility.
  • the preparation techniques of ruthenium-based and tri-five-based MOS devices are still immature. After the high-k gate dielectric is directly deposited on the substrate, there is a defect in interface interface density and poor interface quality, which affects ⁇ . Performance of base and tri-five compound based MOS devices. Summary of the invention
  • the present invention proposes a method of processing a gate dielectric deposited on a ruthenium-based or tri-five-based substrate.
  • a method for processing a gate dielectric deposited on a bismuth-based or tri-five-based substrate specifically comprising: after depositing a high-k gate dielectric on a bismuth-based or tri-five-based substrate, The medium is subjected to fluorine plasma treatment, and a guiding electric field is applied during the treatment, and the electric field accelerates the fluoride ions to the surface of the gate medium.
  • the fluorine plasma drifts into the gate medium, and the ratio of the density of fluoride ions in the high-k medium to the density of oxygen atoms in the high-k medium is 0.01 0.15:1.
  • the surface of the ruthenium-based or tri-five-based compound substrate may be cleaned before depositing the gate dielectric. To remove surface contamination and natural oxide layers.
  • a passivation treatment method are, for depositing a passivation layer, such as Si, Si0 2, ⁇ 1 2 0 3, ⁇ , GeN x, Ge0 2, Y 2 0 3, La 2 0 3, Ce0 2 and the like; may be a single atomic layer passivation, S, N and P atoms passivation.
  • the deposition gate dielectric may be Hf0 2 , A1 2 0 3 , Zr0 2 , Ti0 2 , Ta0 2 , Zr0 2 , Y 2 0 3 ,
  • the gas generating the fluorine plasma may be CF 4 , CHF 3 , CH 2 F 2 , CH 3 F, but is not limited to the above fluorine-containing gas.
  • the reaction gas may be one of the above gases, or a combination of two or more gases, and the flow rate of the fluorine-containing gas is 20 to 100 SCC m ; an inert gas such as Ar or He may be added to the reaction gas, and the flow rate is 0 ⁇ 100 SCC m ; To prevent contamination such as carbon, 0 2 can be added to the reaction gas, and the flow ratio of the added 0 2 to the fluorine-containing gas (such as CF 4 ) is 1:20 to 1:5.
  • the device for generating a fluorine plasma may be an inductively coupled plasma (ICP) device, or any other device capable of generating a plasma.
  • ICP inductively coupled plasma
  • the gas pressure during the fluorine plasma treatment is 10 to 200 mTorr ; the power for generating the plasma is generally 15 60 W; and the plasma treatment time is 30 s to 60 min.
  • the guiding electric field applied during the fluorine plasma treatment can generate the guiding electric field by using an existing plasma processing apparatus, for example, using RIE in a plasma chamber device (such as an ICP etching system). Eclipse) Power produces a guiding electric field.
  • the annealing can be performed after the fluorine plasma treatment, and the annealing temperature and time are respectively 350 to 550 ° C for 30 s to 5 min. Subsequent processes are then performed to prepare MOS capacitors or devices.
  • the germanium-based substrate of the present invention may be a bulk Ge substrate, a GOI substrate or any substrate having a Ge epitaxial layer on its surface, or a germanium-containing compound semiconductor substrate such as SiGe, GeSn or the like.
  • the tri-five compound-based substrate of the present invention may be GaAs, InP, GaSb, InGaAs or the like, or may be other tri-five compound substrates.
  • the advantages of the invention are as follows: The invention adopts fluorine plasma treatment on the gate dielectric to realize the defect at the interface between the substrate and the gate dielectric and the passivation of defects in the gate dielectric, but if the fluorine plasma is directly used, the fluorine plasma is in the plasma source.
  • the present invention further applies a guiding electric field during the process to guide the fluorine plasma drift to the gate dielectric.
  • the density ratio of fluoride ions in the high K medium to the density ratio of oxygen atoms in the high K medium is 0.01 0.15: 1, thereby improving the gate dielectric quality and the passivation defect efficiency, reducing the interface state density, and improving Interface texture description
  • FIG. 1(a) to 1(c) are schematic views showing a surface passivation method according to an embodiment
  • Step 1 Clean the tantalum substrate and remove the surface oxide layer, as shown in Figure 1 (a);
  • Step 2 Deposit a gate dielectric on the germanium substrate.
  • the gate dielectric may be Hf0 2, A1 2 0 3, Zr0 2, Ti0 2, Ta0 2, Zr0 2, Y 2 0 3, La 2 0 3, Ge0 2, GeN x and the like, may be employed sputtering, CVD, ALD , PLD, MBE, etc.; a preferred embodiment of the present embodiment is Hf0 2 , and the thickness of the gate dielectric is between 2 and 20 nm, such as 5 nm, as shown in FIG. 1(b);
  • Step 3 The ruthenium substrate deposited with ⁇ 1 ⁇ 2 is placed in the plasma chamber, the plasma is generated by the reaction gas, and the ruthenium is subjected to plasma treatment, and a guiding electric field is applied simultaneously with the plasma treatment to guide the plasma drift to the gate.
  • the medium when the ions are accelerated to the surface of the gate dielectric, has an energy of 5 to 50 eV.
  • the gas generating the fluorine plasma may be CF 4 , CHF 3 , CH 2 F 2 , CH 3 F, but is not limited to the above fluorine-containing gas.
  • the reaction gas may be one of the above gases, or a combination of two or more gases, and the flow rate of the fluorine-containing gas is 20 to 100 SCC m; and an inert gas such as Ar or He may be added to the fluorine-containing gas.
  • the flow rate is 0 ⁇ 100 SCC m ; in order to prevent carbon and other pollution, 0 2 can be added to the reaction gas, and the ratio of the added 0 2 to the fluorine-containing gas (such as CF 4 ) is 1:20 ⁇ 1:5.
  • a preferred embodiment of the present embodiment is a mixed gas of CF 4 and 02 .
  • the flow rates of CF 4 and 0 2 were 50 sccm and 5 sccm.
  • the device that generates the fluorine plasma may be an inductively coupled plasma (ICP) device, or any other device that can generate a plasma.
  • ICP inductively coupled plasma
  • a preferred embodiment of the present embodiment employs an inductively coupled plasma (ICP) device.
  • the gas pressure during plasma treatment is 10 to 200 mTorr, and the preferred embodiment of the present embodiment is 100 mTorr; the power of plasma treatment is 15-60 W, and the preferred embodiment of the present embodiment is to apply ICP power of 20 W; this embodiment utilizes RIE in an ICP etching system.
  • the power generation guides the electric field, the applied RIE power is 10W; the plasma treatment time is 30s ⁇ 60min, such as 3min, as shown in Figure 1(c); for the Hf0 2 medium, the ideal oxygen atom density is 5.55 X 10 22 Cm- 3 , the final fluoride ion density into Hf0 2 is 5.55 X 10 20 ⁇ 8.3 X 10 21 cm_ 3 ; for A1 2 0 3 medium, the ideal oxygen atom density is 7.02 X 10 22 cm- 3 , the final fluoride ion density into A1 2 0 3 is 7.0 X 10 2Q ⁇ 1.0 X 10 22 cnT 3 . Step 4. Annealing the plasma treated substrate.
  • Annealing temperature and time are 350 ⁇ 550 °C, 30s ⁇ 5min respectively.
  • a preferred embodiment of this embodiment is 500 ° C, 60 s.
  • the invention has been described in detail above by way of specific embodiments. It will be understood by those skilled in the art that the above description is only a specific embodiment of the present invention, and that other materials may be used to achieve the passivation effect of the present invention, and the same method may be employed in the embodiment without departing from the spirit of the invention. The same effect is obtained on other semiconductor substrates than the mid-base substrate, and the preparation methods are not limited to those disclosed in the embodiments, and all the equivalent changes and modifications according to the claims of the present invention belong to the present invention. Coverage.

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Abstract

提供一种沉积在锗基或三五族化合物基衬底上的栅介质的处理方法。该方法包括：在锗基或三五族化合物基衬底（1）上沉积高K栅介质（2），对高K栅介质（2）进行氟等离子体处理，并在处理过程中施加引导电场，电场使得氟离子加速到栅介质表面时能量达到5-50eV，氟等离子体漂移到栅介质中，高K介质（2）中的氟离子密度与氧原子密度比为0.01-0.15:1。该方法提高了栅介质质量和钝化缺陷效率，减小了界面态密度，提高了锗基或三五族化合物基MOS器件的性能。

Description

淀积在锗基或三五族化合物基衬底上的栅介质的处理方法 相关申请的交叉引用
本申请要求于 2013年 5月 30日提交的中国专利申请 （201310208388.X) 的优 先权， 其全部内容通过引用合并于此。 技术领域 本发明属于半导体器件领域， 具体涉及一种淀积在锗基或三五族化合物基衬底 上的栅介质的处理方法。 背景技术
随着硅基金属-氧化物-半导体场效应晶体管（MOSFET)几何尺寸缩小到纳米尺 度，传统通过缩小器件尺寸提升性能和集成度的方法正面临物理和技术的双重极限考 验。 为了进一步提高器件性能， 有效方法之一是引入高迁移率沟道材料。
锗和三五族化合物半导体由于高的空穴和电子移率， 被认为是下一代实现高速 CMOS电路的优选材料。但是目前锗基和三五族化合物基 MOS器件的制备技术还不 成熟， 将高 K栅介质直接淀积在衬底上后， 存在界面处界面态密度高、 界面质量差 的缺陷， 影响了锗基和三五族化合物基 MOS器件的性能。 发明内容
为了提高锗基和三五族化合物基 MOS器件性能，本发明提出了一种淀积在锗基 或三五族化合物基衬底上的栅介质的处理方法。
本发明的具体技术方案如下：
一种淀积在锗基或三五族化合物基衬底上的栅介质的处理方法， 具体包括： 在 锗基或三五族化合物基衬底上淀积高 K栅介质后， 对高 K栅介质进行氟等离子体处 理， 并在处理过程中施加引导电场， 电场使氟离子加速到栅介质表面时能量达到
5~50eV, 氟等离子体漂移到栅介质中， 高 K介质中的氟离子的密度与高 K介质中氧 原子密度比为 0.01 0.15: 1。 上述方法中， 在淀积栅介质前， 可对锗基或三五族化合物基衬底表面进行清洗， 以去除表面沾污和自然氧化层。 上述方法中， 淀积栅介质前， 可对锗基或三五族化合物基衬底进行表面钝化处 理，钝化处理的方法有， 淀积钝化层， 如 Si， Si02， Α1203， ΑΙΝχ, GeNx, Ge02， Y203， La203, Ce02等； 也可进行单原子层钝化处理， S、 N和 P等原子钝化处理。
上述方法中， 淀积栅介质可以是 Hf02， A1203， Zr02, Ti02， Ta02， Zr02, Y203，
La203, Ge02， GeNx等， 但不局限于上述栅介质材料。 上述方法中， 产生氟等离子体的气体可以是 CF4， CHF3， CH2F2， CH3F， 但不 局限于上述含氟气体。 反应气体可以是以上气体中的一种， 或者两种、两者两种以上 气体的组合， 含氟气体流量为 20~100SCCm; 可以在反应气体中添加 Ar， He等惰性气 体， 流量为 0~100SCCm; 为了防止碳等污染， 可在反应气体中添加 02， 添加的 02与 含氟气体 (如 CF4) 的流量比例为 1 :20~1 :5。
上述方法中， 产生氟等离子体的设备可以是感应耦合等离子体（ICP)设备， 也 可以是其它任何可以产生等离子体的设备。
上述方法中，氟等离子体处理过程中的气压为 10~200mTorr;用于产生等离子体 的功率一般为 15 60W; 等离子体处理时间为 30s~60min。
上述方法中， 氟等离子体处理过程中所施加的引导电场可以利用现有的等离子 体处理设备来产生所述引导电场， 例如利用等离子体腔设备（如 ICP刻蚀系统）中的 RIE (反应离子刻蚀） 功率产生引导电场。 上述方法中， 氟等离子体处理后可以进行退火， 退火温度与时间分别为 350~550°C , 30s~5min。 然后进行后续工艺以制备 MOS电容或器件。 本发明的锗基衬底可以是体 Ge衬底、 GOI衬底或任何表面含有 Ge外延层的衬 底， 也可以是含锗的化合物半导体衬底， 比如 SiGe， GeSn等。 本发明的三五族化合 物基衬底可以是 GaAs、 InP、 GaSb、 InGaAs等， 也可以是其它三五族化合物衬底。 本发明优点如下： 本发明对栅介质采用氟等离子体处理， 实现衬底与栅介质界 面处缺陷和栅介质中缺陷的钝化，但如直接采用氟等离子体处理， 氟等离子体在等离 子体源处产生，通过扩散运输到栅介质及界面处，在扩散过程中由于碰撞会发生使等 离子体活性失效， 运输效率低， 本发明进一步在处理过程中施加引导电场， 引导氟等 离子体漂移向栅介质， 实现了高 K介质中的氟离子的密度与高 K介质中氧原子的密 度比为 0.01 0.15: 1， 从而提高了栅介质质量和钝化缺陷效率， 减小界面态密度， 提高 界面质 附图说明
图 1 (a) 至图 1 (c) 示出根据实施例的表面钝化方法的示意图；
图中： 〗一半导体锗衬底； 2一 Hf02。 具体实施方式 以下结合附图和体锗衬底， 通过具体的实施例对本发明所述的方法做进一步描 述。 步骤 1. 对锗衬底进行清洗， 并清除表面氧化层， 如图 1 (a) 所示；
步骤 2. 锗衬底上淀积栅介质。 其中栅介质可以是 Hf02， A1203， Zr02， Ti02， Ta02， Zr02， Y203， La203， Ge02， GeNx等， 可以采用溅射、 CVD、 ALD、 PLD、 MBE等方法； 本实施优选例为 Hf02， 栅介质厚度在 2~20nm之间， 如 5nm， 如图 1 (b) 所示；
步骤 3. 将淀积有 Η1Ό2的锗衬底放入等离子体腔， 利用反应气体产生等离子体 并对锗片进行等离子体处理， 并在等离子体处理的同时施加引导电场， 引导等离子体 漂移向栅介质， 使离子加速到栅介质表面时， 能量为 5~50eV。 产生氟等离子体的气 体可以为 CF4， CHF3， CH2F2， CH3F， 但不局限于上述含氟气体。 反应气体可以是以 上气体中的一种，或者两种、两者两种以上气体的组合，含氟气体流量为 20~100SCCm; 并可以在含氟气体中添加 Ar， He等惰性气体， 流量为 0~100SCCm; 为了防止碳等污 染， 可在反应气体中添加 02， 添加的 02与含氟气体 （如 CF4) 的比例为 1 :20~1 :5。 本实施优选例为用 CF4与 02混合气体。 CF4与 02的流量为 50sccm、 5sccm。 产生氟 等离子体的设备可以是感应耦合等离子体 （ICP) 设备， 也可以是其它任何可以产生 等离子体的设备。 本实施优选例采用感应耦合等离子体 （ICP) 设备。 等离子体处理 时的气压为 10~200mTorr， 本实施优选例为 lOOmTorr; 等离子体处理的功率为 15-60W, 本实施优选例为施加 20W的 ICP功率； 本实施例利用 ICP刻蚀系统中的 RIE功率产生引导电场，施加的 RIE功率为 10W;等离子体处理的时间为 30s~60min， 如 3min， 如图 1 (c) 所示； 对于 Hf02介质， 其理想的氧原子密度为 5.55 X 1022cm-3, 最终进入到 Hf02中的 氟离子密度为 5.55 X 1020~8.3 X 1021cm_3 ; 而对于 A1203介质， 其理想的氧原子密度为 7.02 X 1022cm-3, 最终进入到 A1203中的氟离子密度为 7.0 X 102Q~1.0 X 1022cnT3。 步骤 4. 对等离子体处理后的基片进行退火处理。 退火温度与时间分别为 350~550°C , 30s~5min。 本实施优选例为 500°C， 60 s。 以上通过特定实施例详细描述了本发明。 本领域的技术人员应当理解， 以上所 述仅为本发明的特定实施例，在不脱离本发明实质的范围内，可以使用其它材料实现 本发明的钝化效果，亦可以采用同样方法在实施例中锗衬底之外的其它半导体衬底上 获得同样的效果， 制备方法均不限于实施例中所公开的内容， 凡依本发明权利要求所 做的均等变化与修饰， 皆应属本发明的涵盖范围。

Claims

权 利 要 求
1. 一种淀积在锗基或三五族化合物基衬底上的栅介质的处理方法， 包括： 在锗基或三五族化合物基衬底上淀积高 κ栅介质后， 对高 K栅介质进行氟等离 子体处理， 并在处理过程中施加引导电场， 电场使氟离子加速到栅介质表面时能 量达到 5~50eV， 氟等离子体漂移到高 K栅介质中， 高 K栅介质中的氟离子的密 度与高 K介质中氧原子密度比为 0.01 0.15: 1。
2. 如权利要求 1所述的方法， 其特征在于， 在淀积高 K栅介质前， 对锗基 或三五族化合物基衬底表面进行清洗， 以去除表面沾污和自然氧化层。
3. 如权利要求 1所述的方法， 其特征在于， 淀积高 K栅介质前， 对锗基或 三五族化合物基衬底进行表面钝化处理， 钝化处理的方法有， 淀积钝化层 Si、 Si02、 A1203、 A1NX、 GeNx、 Ge02、 Y203、 La203或 Ce02 ; 或者进行单原子 S、 N或 P原子钝化处理。
4. 如权利要求 1所述的方法， 其特征在于， 高 K栅介质为 Hf02、 A1203、 Zr02、 Ti02、 Ta02、 Zr02、 Y203、 La203、 Ge02或 GeNx。
5. 如权利要求 1 所述的方法， 其特征在于， 产生氟等离子体的含氟气体是 CF4、 CHF3、 CH2F2或 CH3F中的一种， 或者两种、 两种以上气体的组合， 含氟 气体流量为 20~100sccm; 或者在含氟气体中添加 Ar、 He 惰性气体， 流量为 0~100sccm;或者在含氟气体中添加 02，添加的 02与含氟气体的流量比例为 1 :20 ~1 :5。
6. 如权利要求 1 所述的方法， 其特征在于， 产生氟等离子体的设备是感应 耦合等离子体 ICP设备， 氟等离子体处理过程中的气压为 10~200mToiT; 用于产 生等离子体的功率为 15 60W; 等离子体处理时间为 30s~60min。
7. 如权利要求 1 所述的方法， 其特征在于， 氟等离子体处理过程中所施加 的引导电场是利用等离子体腔设备 ICP刻蚀系统中的反应离子刻蚀 RIE功率产 生的电场。
8. 如权利要求 1 所述的方法， 其特征在于， 氟等离子体处理后进行退火， 退火温度为 350~550°C， 退火时间为 30s~5min。
PCT/CN2014/070302 2013-05-30 2014-01-08 淀积在锗基或三五族化合物基衬底上的栅介质的处理方法 Ceased WO2014190771A1 (zh)

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