WO2014188563A1 - 半導体ガスセンサ - Google Patents
半導体ガスセンサ Download PDFInfo
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- WO2014188563A1 WO2014188563A1 PCT/JP2013/064374 JP2013064374W WO2014188563A1 WO 2014188563 A1 WO2014188563 A1 WO 2014188563A1 JP 2013064374 W JP2013064374 W JP 2013064374W WO 2014188563 A1 WO2014188563 A1 WO 2014188563A1
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- effect transistor
- field effect
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Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N27/00—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means
- G01N27/02—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance
- G01N27/04—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance by investigating resistance
- G01N27/12—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance by investigating resistance of a solid body in dependence upon absorption of a fluid; of a solid body in dependence upon reaction with a fluid, for detecting components in the fluid
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N27/00—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means
- G01N27/26—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating electrochemical variables; by using electrolysis or electrophoresis
- G01N27/403—Cells and electrode assemblies
- G01N27/414—Ion-sensitive or chemical field-effect transistors, i.e. ISFETS or CHEMFETS
- G01N27/4148—Integrated circuits therefor, e.g. fabricated by CMOS processing
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N33/00—Investigating or analysing materials by specific methods not covered by groups G01N1/00 - G01N31/00
- G01N33/0004—Gaseous mixtures, e.g. polluted air
- G01N33/0009—General constructional details of gas analysers, e.g. portable test equipment
- G01N33/0027—General constructional details of gas analysers, e.g. portable test equipment concerning the detector
- G01N33/0036—General constructional details of gas analysers, e.g. portable test equipment concerning the detector specially adapted to detect a particular component
- G01N33/005—H2
Definitions
- the present invention relates to a gas sensor using a semiconductor material, that is, a so-called semiconductor gas sensor, and more particularly to a technique effective when applied to a semiconductor gas sensor used for detection of hydrogen gas, hydrogen compound gas, or polar molecular gas.
- a gas sensor for detecting hydrogen gas or the like for example, there is a semiconductor gas sensor having a MOS (metal-oxide-semiconductor) structure using a catalytic metal as a gate.
- MOS metal-oxide-semiconductor
- Patent Document 1 describes a Ti modified film in which oxygen-doped titanium containing oxygen and titanium microcrystals are mixed, and a plurality of crystal grains formed on the Ti modified film.
- a gate structure is disclosed in which oxygen and titanium are present in a grain boundary region between a plurality of crystal grains.
- Patent Document 2 Japanese Patent Laying-Open No. 2012-073154 includes a gate insulating film provided on a substrate and a gate electrode provided on the gate insulating film, and the gate electrode contains oxygen. And a metal oxide mixed film in which an oxygen-doped amorphous metal and an oxide crystal of the metal are mixed, and a platinum film provided on the metal oxide mixed film.
- Patent Document 3 discloses a MISFET type hydrogen gas sensor with low power consumption that enables operation for one year or more with a low-voltage power supply.
- a FET for a sensor is formed in a MEMS region obtained by hollowing out an Si substrate of an SOI substrate, and between the Pt-Ti-O gate and the source electrode of the sensor FET and between the Pt-Ti-O gate and the drain electrode, respectively.
- a technique for bending and arranging the heater wiring is described.
- Patent Document 4 Japanese Patent Laid-Open No. 2010-008371
- Patent Document 4 has a sensor chip, a stem on which the sensor chip is mounted, an upper part and a side part, and the lowermost part of the side part is welded to the outer periphery of the stem.
- a combustible gas sensor is disclosed in which a sensor chip is surrounded by a stem and a metal cap.
- the present invention provides a semiconductor gas sensor that can detect a specific gas concentration of one or two or more with respect to hydrogen gas, hydrogen compound gas, or polar molecular gas, and can give a warning or alarm accurately.
- the present invention provides a semiconductor gas sensor that can detect a specified gas concentration simply by changing input settings.
- the present invention also provides a semiconductor gas sensor with reduced temperature compensation (drift or fluctuation) of the threshold voltage due to the MOS structure, which is not derived from the detection gas.
- the semiconductor gas sensor of the present invention has a CMOS inverter including an n-channel field effect transistor having a catalyst gate and a p-channel field effect transistor having a catalyst gate.
- a semiconductor gas sensor capable of detecting a specific gas concentration of one or two or more with respect to hydrogen gas, hydrogen compound gas, or polar molecular gas and accurately issuing a warning or alarm. Can do.
- the present invention it is possible to provide a semiconductor gas sensor that is reduced in temperature compensation (drift or fluctuation) of the threshold voltage due to the MOS structure, which is not derived from the detection gas.
- FIG. 6 is a graph summarizing experimental data of response intensity ( ⁇ Vg) with respect to air diluted hydrogen concentration (C) in the Si-MOSFET type gas sensor according to Example 1.
- FIG. 6 is a graph showing an example of IV characteristics of an nMOS transistor and a pMOS transistor having a Pt—Ti—O gate structure with respect to 0.1% hydrogen irradiation according to Example 1.
- FIG. 6 is a graph showing an example of IV characteristics of an nMOS transistor and a pMOS transistor having a Pt—Ti—O gate structure measured at room temperature (about 24 ° C.) and at a high temperature (115 ° C.) according to Example 1.
- FIG. 1 is a circuit diagram showing a CMOS inverter including a gate having catalytic action according to Example 1.
- FIG. FIG. 3 is a graph showing a logic inversion characteristic of an output potential (Vout) with respect to an input potential (Vin) of the CMOS inverter according to the first embodiment.
- FIG. 6 is a graph showing the logic inversion characteristic of the output potential (Vout) with respect to the sensor response strength ( ⁇ Vg) of the CMOS inverter according to Example 1; 6 is a schematic diagram illustrating an inverting addition amplifier circuit using operational amplifiers according to Embodiments 1 and 3.
- FIG. 2 is a schematic cross-sectional view showing an enlarged gate structure portion of the catalyst gate CMOS type hydrogen sensor according to Example 1;
- 1 is an example of a plan view of a CMOS inverter according to Embodiment 1.
- FIG. FIG. 10 is a fragmentary cross-sectional view of the nMOS transistor constituting the CMOS inverter according to the first embodiment (a fragmentary cross-sectional view along the line AA ′ in FIG. 9).
- FIG. 10 is a fragmentary cross-sectional view of the pMOS transistor constituting the CMOS inverter according to the first embodiment (a fragmentary cross-sectional view along the line BB ′ in FIG. 9).
- FIG. 6 is an enlarged schematic cross-sectional view of a gate structure portion of a Si-MISFET type gas sensor according to Example 2.
- FIG. It is a graph which shows the ethanol gas density
- FIG. 6 is an example of a plan view of a pMOS transistor and an nMOS transistor that constitute a gas sensor according to Embodiment 3.
- FIG. 6 is an enlarged schematic cross-sectional view of a gate structure portion of a catalyst gate CMOS type hydrogen sensor according to Example 4.
- FIG. 10 is an example of a plan view of a CMOS inverter according to a fourth embodiment.
- FIG. 17 is a fragmentary cross-sectional view of an nMOS transistor constituting a CMOS inverter according to a fourth embodiment (a fragmentary cross-sectional view along the line AA ′ in FIG. 16).
- FIG. 17 is a cross-sectional view of main parts of a pMOS transistor constituting a CMOS inverter according to Example 4 (main part cross-sectional view along the line BB ′ in FIG. 16).
- the constituent elements are not necessarily indispensable unless otherwise specified and clearly considered essential in principle. Needless to say.
- MOSFETs Metal-Oxide-Semiconductor-Field-Effect-Transistors
- MOS transistors Metal-Oxide-Semiconductor-Field-Effect-Transistors
- pMOS transistors p-channel MOSFETs
- nMOS transistors nMOS transistors
- a semiconductor gas sensor is described as a gas sensor
- a gate having a catalytic action is described as a catalytic gate
- a CMOS inverter having a gate having a catalytic action is described as a catalytic gate CMOS inverter.
- This embodiment relates to the sensing technology of the gas sensor, and as the gas type, hydrogen gas, hydrogen compound gas, or polar molecular gas is assumed.
- the gas detection mechanisms are different, the gas concentration is detected by taking out the shift amount of the threshold voltage as a sensor signal.
- the gas detection mechanism is determined by the type of gas and the nature of the catalyst gate structure.
- hydrogen molecules are dissociated into hydrogen atoms by the catalytic action of the catalyst gate, and the gas concentration is determined from the amount of threshold voltage shift caused by the hydrogen-induced dipole formed at the interface between the catalyst gate and the gate insulating film. Detect.
- hydrogen compound gas hydrogen atoms are dissociated from the hydrogen compound molecules (ammonia, hydrogen sulfide, etc.) by the catalytic action of the catalyst gate, and the gas concentration is detected by the same sensing principle as hydrogen gas.
- a catalyst gate structure using a nanocomposite structure or the like is used.
- Polar molecules eg, ethanol, ammonia, etc.
- the gas concentration is detected from the shift amount of the threshold voltage at this time.
- Many polar molecules (the molecule itself has a dipole moment) cannot dissociate hydrogen atoms by catalysis, but ethanol or ammonia can dissociate hydrogen atoms.
- polarization occurs after adsorption. Therefore, there is a high possibility that a threshold voltage shift occurs due to both sensing mechanisms, although both are strong and weak.
- Si silicon
- MOSFET metal-oxide-semiconductor / field effect transistor
- the sensing principle for detecting hydrogen gas has been proposed as follows, for example.
- hydrogen molecules are dissociated by the catalytic action on the surface of the Pd gate, and hydrogen atoms (or protons) move to the interface between the Pd gate and the gate insulating film by diffusion.
- a proton-electron pair polarized in a form having a dipole moment (a state where the center of gravity of the proton and the electron is separated) is formed in the vicinity of the interface between the Pd gate and the gate insulating film.
- the threshold voltage of the Si-MOSFET type gas sensor having the Pd gate structure is shifted. By utilizing this phenomenon, the hydrogen gas concentration can be detected.
- MOSFET type gas sensor using a catalytic metal such as Pd or Pt (platinum) as a gate to a gas other than hydrogen gas, for example, a hydrogen compound gas or a polar molecular gas (for example, I. Lundstrom, Sensors and Actuators, B1 (1990) 15-20).
- a MISFET metal--Pt—Ti—O gate structure using Pt—Ti—O (platinum-titanium-oxygen) as a gate is used.
- MIS is an abbreviation for metal-insulator-semiconductor and is a superordinate concept of MOS.
- ⁇ Vgmax is the maximum value of the sensor response intensity ⁇ Vg
- C is the hydrogen gas concentration near the gas sensor
- C 0 is the hydrogen concentration when half of the hydrogen adsorption site of the gas sensor is filled (for example, T. Usagawa et al., IEEE Sensors Journal , 12 (2012) 2243-2248). Therefore, the hydrogen gas concentration can be detected by measuring the sensor response intensity ⁇ Vg.
- the sensing principle for detecting the polar molecular gas is slightly different from the above formula (1), but the sensor response of the MOSFET type gas sensor is the same as in the case of hydrogen gas.
- the polar molecular gas concentration can be detected from the intensity ⁇ Vg (for example, Patent Document 2 described above).
- a MIS capacitor metal-insulator-semiconductor / capacitor
- SiC silicon carbide
- GaAs gallium arsenide
- GaN gallium nitride
- diamond carbon
- the gas concentration is converted into an electric signal (in many cases, a voltage signal), (2) it is amplified when the electric signal is small, and (3) The gas concentration is taken in as analog data (continuous amount), and (4) the gas concentration is determined by converting the analog data into digital data by an AD converter.
- the mechanism for detecting the gas concentration is the same.
- the sensor signal is also detected using a similar analog circuit.
- an alarm (red lamp + sound) is used when the lower explosive limit concentration is 25% or less, and a warning (red lamp blinks) when the explosive lower limit concentration is approximately 1%. It is a gas sensor installation standard to emit. When a gas sensor is used as an alarm device, the better the gas sensor, the fewer “false alarms” that give an alarm when the gas concentration does not reach the lower explosion limit concentration.
- the lower explosion limit concentration of hydrogen gas is 4.0%.
- the 500ppm hydrogen leak warning level is about 1% of the lower explosion limit concentration in the gas alarm installation manual.
- 1% system power-off level is 25% or less, corresponding to warnings.
- the reason why the standards are provided in such a multi-stage is that specific measures change depending on the range of the gas concentration.
- a differential circuit is considered to be effective.
- a differential circuit method has been devised that cancels the change in threshold voltage due to the cause not derived from the detected gas by taking the difference between the output of the sensor element and the output of the reference element. ing.
- this method it is possible to perform temperature compensation for changes in the external environment temperature of the MOSFET type gas sensor and sensor temperature fluctuations.
- this method cannot reduce the variation caused by the structural difference between the sensor element and the reference element.
- the first problem is that a gas sensor that can detect one or two or more specific gas concentrations with respect to hydrogen gas, hydrogen compound gas, or polar molecular gas and issue a warning or an alarm has not yet been realized.
- the second problem is that a gas sensor that can detect the specified gas concentration simply by changing the input settings has not yet been realized.
- the third problem is that the problem of temperature compensation (drift or fluctuation) of the threshold voltage due to the MOS structure, which does not originate from the detection gas, has not been solved.
- FIG. 1 shows a graph summarizing experimental data of sensor response strength ( ⁇ Vg) with respect to air dilution hydrogen concentration (C) in a Si-MOSFET type gas sensor.
- the sensor response strength is an absolute value of the shift amount of the threshold voltage.
- the sensor response intensity ⁇ Vg is good by the equation (2) obtained in the range of 0.1 ⁇ C / C 0 ⁇ 10 from the Langmuir formula of the equation (1). It can be approximated with accuracy.
- Equation (2) indicates that the physical phenomenon can be accurately reproduced by the Langmuir formula of Equation (1).
- the sharp rise of the sensor response intensity ⁇ Vg with respect to the air diluted hydrogen concentration C indicates the high sensitivity and high strength of the Pt—Ti—O gate structure.
- This is different from the Si-MOSFET type gas sensor having a Pd gate structure.
- ⁇ Vgmax and C 0 of the Pt—Ti—O gate structure shown in Table 1 is higher than ⁇ Vgmax and C 0 of other structures supports the high sensitivity and high strength of the Pt—Ti—O gate structure. is doing.
- the rising hydrogen concentration of the step type gas response SGR indicated by the thick line in FIG. 1 may be adjusted to the 0.05% concentration.
- two gas sensors may be prepared. In the case of a semiconductor device, two types of gas sensors may be integrated on the same chip.
- an nMOS transistor has been used in the Si-MOSFET type gas sensor, but a pMOS transistor can be used in the same manner. That is, if the gate structure of the pMOS transistor is the same as the gate structure of the nMOS transistor, the threshold voltage control mechanism and the hydrogen response mechanism of the Si-MOSFET type gas sensor can be understood from the sensor model based on the dipole moment ( T.Usagawa et al., Japanese Journal of Applied Physics, Vol51 (2012) 024101-1-024101-7, and T.Usagawa et al., Sensors and Actuators, B160 (2011) 105-114).
- the sensor response intensity ⁇ Vg hardly depends on the planar structure (gate length or gate width) of the MOS transistor.
- the gate structure is the gate region of the MOS transistor.
- the cross section means the structure up to the semiconductor interface.
- the gas sensor according to the first embodiment is configured by a MOS transistor including a gate having a rising edge of a step type gas response SGR in which the sensor response intensity ⁇ Vg increases rapidly at a predetermined gas concentration.
- the gas sensor according to the first embodiment is a CMOS (Complementary Metal Oxide Semiconductor) type composed of an nMOS transistor and a pMOSFET to avoid a threshold voltage drift phenomenon. It is characterized by that.
- FIG. 2 is a graph showing an example of IV characteristics (current-voltage characteristics) of an nMOS transistor and a pMOS transistor having a Pt—Ti—O gate structure with respect to 0.1% hydrogen irradiation.
- FIG. 3 is a graph showing an example of IV characteristics of an nMOS transistor and a pMOS transistor having a Pt—Ti—O gate structure measured at room temperature (about 24 ° C.) and high temperature (115 ° C.).
- the horizontal axis represents the source-gate voltage (Vgs), and the vertical axis represents the source-drain current (Ids).
- Vgs source-gate voltage
- Ids source-drain current
- the source-drain voltage (Vds) of the nMOS transistor is 1.5V
- the source-drain voltage (Vds) of the pMOS transistor is -1.5V.
- the threshold voltage of the nMOS transistor and the threshold voltage of the pMOS transistor are indicated by Vth (n) and Vth (p), respectively, and the state of the parallel movement of the IV characteristic at the time of hydrogen irradiation is indicated by arrows.
- the shift amount of the threshold voltage of the nMOS transistor and the shift amount of the threshold voltage of the pMOS transistor are represented by ⁇ Vg (n) and ⁇ Vg (p), respectively.
- the threshold voltage of the nMOS transistor and the threshold voltage of the pMOS transistor are indicated by Vth (n) and Vth (p), respectively, and are changed from room temperature (about 24 ° C.) to high temperature (115 ° C.).
- the state of parallel movement of the IV characteristic is indicated by arrows.
- the shift amount of the threshold voltage of the nMOS transistor and the shift amount of the threshold voltage of the pMOS transistor are represented by ⁇ Vth (n) and ⁇ Vth (p), respectively.
- the gate structure of the nMOS transistor and the gate structure of the pMOS transistor are designed with the channel, the gate length, and the gate width so that the function types of the IV characteristics are substantially the same. However, since the other gate structures are the same, this phenomenon at the time of hydrogen irradiation can be explained by the physics of the MOSFET type gas sensor.
- Vtn Vtn0 ⁇ Kn (T ⁇ T0) (3)
- Vtp Vtp0 + Kp (T ⁇ T0) (4) It is expressed.
- the specific values of Kn and Kp depend on the semiconductor material Si, SiC, GaC (gallium carbide), or diamond (carbon), but the temperature characteristics of the threshold voltages Vtn and Vtp and the relationship Kn ⁇ Kp Is maintained.
- FIG. 4 is a circuit diagram showing a CMOS inverter provided with a gate having catalytic action.
- a load composed of an enhancement type pMOS transistor PTr and a driver composed of an enhancement type nMOS transistor NTr are arranged in a complementary manner (logic inversion circuit).
- Vdd is a high potential
- Vss is a low potential
- Vin is an input potential
- Vout is an output potential
- Vtp is a threshold potential of a pMOS transistor
- Vtn is a threshold potential of an nMOS transistor.
- the high potential Vdd is generally set to a potential difference that is 3 to 24 V higher than the low potential Vss.
- the high potential Vdd is a power supply voltage
- the low potential Vss is a ground voltage.
- the output potential Vout is substantially equal to the high potential Vdd.
- the pMOS transistor is turned off and the nMOS transistor is turned on.
- the output potential Vout is substantially equal to the low potential Vss. That is, a potential opposite to the input potential Vin appears in the output potential Vout.
- FIG. 5 is a graph showing the logic inversion characteristics of the output potential (Vout) with respect to the input potential (Vin) of the CMOS inverter.
- the threshold voltage of the nMOS transistor and the threshold voltage of the pMOS transistor are denoted by Vtn and Vtp, respectively.
- Vtn and Vtp are denoted by Vtn and Vtp, respectively.
- Equation (6) is equal to Equation (8) and the high potential Vdd is larger than the threshold input potential Vtc (Vdd> Vtc)
- abs is an absolute value signal
- ⁇ R ⁇ n / ⁇ p (11) It is.
- Gate lengths Lg (n), Lg (p), gate widths Wg (n), Wg (p), and gate capacities COx (n), COx (p) per unit area are design parameters, and n-channel effective electrons If ⁇ p can measure the mobility ⁇ n and the p-channel effective electron mobility, the threshold input potential Vtc having the logic inversion characteristic can be designed.
- the pMOS transistor and the nMOS transistor are enhancement type, the threshold voltage Vtp of the pMOS transistor is a negative value, and the threshold voltage Vtn of the nMOS transistor is a positive value.
- the gas sensor according to the first embodiment uses a catalytic metal that detects hydrogen gas, hydrogen compound gas, or polar molecular gas at the gate of each of the pMOS transistor and the nMOS transistor constituting the CMOS inverter, and the gate on the channel is in a gas environment. It has a direct contact structure.
- FIG. 6 is a graph showing the logic inversion characteristic of the output potential (Vout) with respect to the sensor response strength ( ⁇ Vg) of the CMOS inverter.
- each catalyst gate CMOS inverter is placed in a gas environment with a known gas concentration, the input potential Vin is gradually increased from the low potential Vss, and the input potential when the CMOS inverter is inverted. If Vin is defined as Vin (D), the catalyst gate CMOS inverter can be adjusted.
- the input setting gate potential Vin (D) of the CMOS inverter may be determined by the equation (12) using the adjustment result.
- Vin (D) Vtc ⁇ Vgth (12)
- Vin (D) Vtc ⁇ Vgth (12)
- the threshold input potential Vtc does not have a strict meaning for the step response with respect to the input potential Vin, and the response characteristic is inclined, but the output potential Vout is (Vdd ⁇ Vss) / 2. Can be substituted at the midpoint.
- the threshold voltage Vtn of the nMOS transistor is a positive voltage
- the threshold voltage Vtp of the pMOS transistor is a negative voltage
- Vin (D) ⁇ Vtc is established as a condition for ensuring that the CMOS inverter is not inverted.
- Vtn ⁇ Vtp + Vdd is necessary.
- the corresponding input setting gate potential Vin (D) can be set, so that a gas sensor that outputs multiple warnings can be formed.
- a plurality of the same sensor chips can be prepared and multiple warnings can be issued.
- a plurality of catalyst gate CMOS inverters can be prepared in the same chip and multiple warnings can be issued.
- the sensing principle common to the gas sensor of the MOS structure by the catalyst gate does not change to measure the shift amount of the threshold voltage. Therefore, it is necessary to devise a step-type gas response to a low gas concentration that sets a small sensor response threshold strength ⁇ Vgth.
- the adjustment described above may be performed first to determine the input setting gate potential Vin (D). However, if the variation of the threshold voltage with time is large, it is more greatly affected at a low gas concentration that sets a small sensor response threshold strength ⁇ Vgth.
- the detected gas concentration becomes indeterminate (characteristic variation or characteristic reproducibility variation, etc.) corresponding to the variation in the sensor response threshold strength ⁇ Vgth.
- the gas sensor is limited to the Pt—Ti—O gate structure, the gas response intensity is extremely large as shown in FIG. 1 described above, so that the influence of the sensor response threshold intensity ⁇ Vgth is small.
- a gas sensor for a gas that may cause a gas explosion issues a warning (red lamp + sound) when the concentration is below 25% of the lower explosive limit concentration, and a warning (flashing red light) at about 1% of the explosive lower limit concentration. Therefore, it is sufficient that the sensor response threshold strength ⁇ Vgth is within a range within this range. For example, in 1 atm air, it is only necessary to reliably detect a reference value of 1% at 3% or less, and according to equation (2), there is a margin of 0.169 V between 1% hydrogen concentration and 3% hydrogen concentration. Therefore, it can respond sufficiently.
- the temperature characteristics of the threshold voltages Vtp and Vtn are opposite in phase between the nMOS transistor and the pMOS transistor. That is, when the temperature rises, the threshold voltage Vtp of the pMOS transistor shifts in the positive direction as shown in the equations (3), (4), and (5), and the threshold value of the nMOS transistor is increased. The voltage Vtn shifts in the negative direction. Further, when the operating temperatures of the nMOS transistor and the pMOS transistor change in the same manner, the temperature coefficient Kn and the temperature coefficient Kp defined by the equations (3) and (4) become substantially the same value.
- the threshold input potential Vtc of the logic inversion characteristic does not depend on the temperature change and realizes a stable (non-drift) inverter characteristic. be able to. Further, as shown in the equation (10), since the fluctuation of the threshold voltage that changes in the opposite phase can be canceled, the fluctuation of the threshold input potential Vtc itself is suppressed, and the gas detection accuracy is improved. In particular, the detection accuracy at a low gas concentration that sets a small sensor response threshold strength ⁇ Vgth can be significantly improved.
- the fluctuation of the threshold voltage due to temperature is opposite in phase between the nMOS transistor and the pMOS transistor. Therefore, in order to exclude the fluctuation of the threshold voltage due to temperature, the sum of the sensor response strength ⁇ Vg (n) of the nMOS transistor and the sensor response strength ⁇ Vg (p) of the pMOS transistor can be obtained and 1 ⁇ 2 thereof can be obtained. Good.
- the fluctuation due to the temperature characteristic is the sensor response strength ⁇ Vg (n) of the nMOS transistor and the pMOS.
- the difference from the sensor response strength ⁇ Vg (p) of the transistor is taken and can be obtained as 1 ⁇ 2 thereof. Thereby, the sensor response strength ⁇ Vg can be accurately obtained.
- FIG. 7 is a schematic diagram illustrating an inverting addition amplifier circuit using an operational amplifier.
- the signal drifting in the opposite phase between the nMOS transistor and the pMOS transistor related to the threshold voltage can be removed by the above-described two methods if the magnitudes of both are the same. Is possible. For example, when there is a long-time drift phenomenon in the threshold voltage in a MOS type gas sensor, removal of the fluctuation drift component by this method is effective.
- FIG. 8 is an enlarged schematic cross-sectional view showing a gate structure portion of the catalyst gate CMOS type hydrogen sensor.
- the hydrogen atom excitation dipole is denoted by reference numeral 6.
- a gate insulating film 4 (for example, a SiO 2 film) is formed on the Si substrate 5, and a Ti modified film 2 is formed on the gate insulating film 4.
- the Ti-modified film 2 is a film in which TiO (titanium oxide) microcrystals and an oxygen-doped amorphous Ti film are mixed.
- the mixing ratio, thickness, and production conditions are described in, for example, Patent Documents 1, 2, and 3.
- a film made of (111) -oriented Pt crystal grains (or Pt grains or microcrystals) 3 is formed on the Ti modified film 2.
- a crystal grain boundary 1 is formed between adjacent Pt crystal grains 3, and Ti, O, and Pt are formed in a region near the grain boundary. Oxygen-doped Ti or TiO fine particles are further formed on the surface in the vicinity of the grain boundary, but these are not always necessary.
- a region composed of the Pt crystal grains 3 and the Ti modified film 2 is called a Pt—Ti—O structure, and is used for each gate electrode of the nMOS transistor and the pMOS transistor.
- the Pt—Ti—O structure is produced, for example, by successively laminating Ti and Pt on the gate insulating film 4 and performing a heat treatment in an oxygen atmosphere gas.
- FIG. 9 is an example of a plan view of a CMOS inverter.
- FIG. 10 is a cross-sectional view of a main part of an nMOS transistor constituting the CMOS inverter (a cross-sectional view of the main part along the line AA ′ in FIG. 9).
- FIG. 11 is a cross-sectional view of a main part of a pMOS transistor constituting the CMOS inverter (a cross-sectional view of the main part along the line BB ′ in FIG. 9).
- CMOS inverter design An example of a CMOS inverter design will be described.
- the gate electrode and the gate insulating film of the Pt—Ti—O structure are the same in the nMOS transistor and the pMOS transistor.
- the length Lg (n) can be designed to be 20 ⁇ m, the gate width Wg (n) is 75 ⁇ m, the gate length Lg (p) of the pMOS transistor is 20 ⁇ m, and the gate width Wg (p) is 250 ⁇ m.
- the threshold voltage Vtn of the nMOS transistor is defined as a voltage when the source-drain voltage Vds is 3.0 V and the source-drain current Ids is 10 ⁇ A, and is set to 1.3 V, for example.
- the threshold voltage Vtp of the pMOS transistor is defined as a voltage when the source-drain voltage Vds is 3.0 V and the source-drain current Ids is 10 ⁇ A, for example, ⁇ 1.3 V.
- control electrode 29 and the source electrode 21 connected to the p-type Si substrate 43 and the p contact layer 41 of the nMOS transistor NTr are connected to each other, and the low potential terminal (described above) of the CMOS inverter is connected.
- Vss terminal shown in FIG. the control electrode 30 and the source electrode 31 connected to the n well 44 and the n contact layer 45 of the pMOS transistor PTr are connected to each other and connected to the high potential terminal (Vdd terminal shown in FIG. 4 described above).
- the drain region 27d of the nMOS transistor NTr and the drain region 42d of the pMOS transistor PTr are electrically connected via the drain electrode 22 and are connected to the output terminal of the CMOS inverter (Vout terminal shown in FIG. 4 described above). Connected.
- the gate electrode 20 of the nMOS transistor NTr and the gate electrode 20 of the pMOS transistor PTr are connected to each other and connected to the input terminal of the CMOS inverter (the Vout terminal shown in FIG. 4 described above).
- the CMOS inverter the Vout terminal shown in FIG. 4 described above.
- an opening 19 is formed from which the protective film made of a laminated film of PSG (phosphorus doped glass) 24 and silicon nitride film 23 is removed.
- the high potential of the CMOS inverter (Vdd shown in FIG. 4 described above) is set to 3.0 V, for example.
- a local oxide film 40 is formed on the main surface of the p-type Si substrate 43 by local oxidation.
- the local oxide film 40 is made of, for example, a SiO 2 film, and has a thickness of about 250 nm, for example.
- n-type impurity for example, phosphorus (P)
- P phosphorus
- the gate insulating film 25 is formed on the main surface of the Si substrate 43 by a wet thermal oxidation method.
- the gate insulating film 25 is made of, for example, a SiO 2 film, and the thickness thereof is, for example, about 18 nm.
- a local oxide film 28 having a thickness of about 80 nm is formed on the surface of the n-type channel region 47 of the source region 27s and the drain region 27d by this wet thermal oxidation method.
- a gate electrode 20 made of a Ti film (not shown) and a Pt film is formed on the gate insulating film 25 by, for example, a lift-off method.
- the thickness of the Ti film is, for example, about 5 nm
- the thickness of the Pt film is, for example, about 15 nm.
- the source region 27 s and the drain region 27 d are formed in accordance with the local oxide film 28 that defines the formation region of the gate electrode 20, and the gate electrode 20 is formed only on the gate insulating film 25. Instead, it is formed so as to cover the upper surface of the local oxide film 40. Therefore, the gate electrode 20 is formed so that the end of the gate electrode 20 overlaps the end of the source region 27s and the end of the drain region 27d.
- the Ti film and the Pt film constituting the gate electrode 20 are formed by, for example, an electron beam irradiation vapor deposition method.
- the gate structure shown in FIG. 8 is formed by performing annealing in a high-purity air atmosphere at a heat treatment temperature of 400 ° C. and a heat treatment time of 2 hours.
- an insulating film 26 made of PSG (phosphorus-doped glass) is formed on the Si substrate 43 including the gate electrode 20. Then, a contact hole penetrating the insulating film 26 is formed, and a process such as surface treatment is performed. Then, the source electrode 21, the drain electrode 22, and the control electrode 29 made of an Al (aluminum) film containing Si are formed on the insulating film 26 including the inside of the contact hole.
- the thicknesses of the source electrode 21, the drain electrode 22, and the control electrode 29 are, for example, about 500 nm.
- a wiring composed of an Al film containing the same Si as the source electrode 21 or the drain electrode 22 is also formed as a heater for heating the lead wire of the gate electrode 20 and the chip.
- the wiring width of the wiring heater is, for example, about 20 ⁇ m, and the wiring length is, for example, about 30,000 ⁇ m.
- a protective film is formed on the main surface of the Si substrate 43 in order to protect the source electrode 21, the drain electrode 22, the control electrode 29, and the chip.
- This protective film is composed of, for example, a laminated film of PSG (phosphorus-doped glass) 24 and silicon nitride film 23.
- the silicon nitride film 24 is formed by a low temperature plasma CVD method, and the thickness of the protective film is, for example, about 700 nm.
- a contact hole 46 is formed on an electrode pad (not shown), and an opening 19 is formed so as to expose the gate electrode 20 as a sensor portion.
- the manufacturing method of the pMOS transistor PTr is the same as the manufacturing method of the nMOS transistor NTr described above, and only different portions will be described.
- n-well 44 on the p-type Si substrate 43 After forming the n-well 44 on the p-type Si substrate 43, local oxidation is performed to form the local oxide film 40.
- the thickness of the local oxide film 40 is, for example, about 250 nm.
- ion implantation of a p-type impurity for example, boron (B)
- p-type impurity ions are implanted to form an active layer of the pMOS transistor PTr.
- a gate insulating film 25, a gate electrode 20, a source electrode 21, a drain electrode 22 and the like are formed in the same manner as the nMOS transistor NTr.
- hydrogen termination is performed by performing hydrogen annealing at 400 ° C. for 30 minutes with 1% hydrogen gas when forming PSG (phosphorus-doped glass).
- the sensor chip temperature is set to 100 ° C. or higher due to the problem of response speed and water vapor desorption in the environment.
- This method makes it possible to easily determine a desired threshold hydrogen concentration without using an analog circuit and an AD converter.
- the input setting gate potential Vin (D) may be determined from the equation (12) in consideration of the threshold input potential Vtc. In that case, since there are three types of sensor response threshold strength ⁇ Vgth, three catalyst gate CMOS type hydrogen sensors are required. At that time, three sensor chips are prepared, or three catalyst gate CMOS hydrogen sensors are formed in the same chip, and a desired input setting gate potential Vin (D) is set by each catalyst gate CMOS hydrogen sensor. It can also be set.
- ⁇ Vgth is a sensor response threshold strength corresponding to a desired gas concentration at which an alarm or warning is desired
- Vtc is a threshold input voltage of the CMOS inverter.
- ⁇ Vgth is a sensor response threshold strength corresponding to a desired gas concentration at which an alarm or warning is desired
- Vtc is a threshold input voltage of the CMOS inverter. Then, the input setting gate potential Vin (D) can be made variable according to the desired sensor response threshold strength ⁇ Vgth.
- the sensor response strength ⁇ Vg of the nMOS transistor and the pMOS transistor is slightly different in the strict sense because of manufacturing variations and the like.
- the sensor response intensity ⁇ Vg has a different value.
- ⁇ Vgav [ ⁇ Vg (n) + ⁇ Vg (p)] / 2 Formula (19)
- a difference ⁇ Vgdif between ⁇ Vg (n) and ⁇ Vg (p) is defined by the following equation.
- ⁇ Vgdif [ ⁇ Vg (n) ⁇ Vg (p)] / 2
- Formula (20) ⁇ Vgeff can be generally expressed by the following equation using the average value ⁇ Vgav and the difference ⁇ Vgdif (including when ⁇ R ⁇ 1).
- ⁇ Vgeff ⁇ Vgav + [ ⁇ ( ⁇ R ) ⁇ 1] ⁇ Vgdif / (1 + ⁇ ( ⁇ R )) (21)
- ⁇ Vgeffth [ ⁇ ( ⁇ R ) ⁇ Vgth (n) + ⁇ Vgth (p)] / (1 + ⁇ ( ⁇ R )) (22)
- Vin (D) Vtc ⁇ Vgeffth (23) Is used.
- the effective hydrogen response intensity ⁇ Vgeff can be approximated by the average ⁇ Vgav of sensor response intensity of the sensor response strength [Delta] Vg (n) and the pMOS transistor of the nMOS transistor [Delta] Vg (p), this
- the average value ⁇ Vgav may be replaced with the sensor response intensity ⁇ Vg discussed so far.
- the catalyst gate structure is a structure suitable for alcohol gas, and the catalyst gate structure is different, and the sensor response intensity ⁇ Vg according to the alcohol gas concentration is different.
- the threshold strength ⁇ Vgth is different.
- Example 2 an example of a catalyst gate structure capable of determining an alcohol gas concentration of about 70 ppm in air diluted ethanol will be described.
- An n-channel MOSFET type gas sensor according to Example 2 is disclosed in, for example, Patent Document 2 described above.
- the catalyst gate structure is different from the catalyst gate structure of Example 1, and the sensor operating temperature needs to be increased. Since the circuit configuration is the same as the circuit configuration of the first embodiment, only the parts specific to the alcohol sensor will be disclosed below.
- FIG. 12 is a schematic cross-sectional view showing an enlarged gate structure portion of the Si-MISFET type gas sensor according to the second embodiment.
- a gate insulating film 4 for example, SiO 2 film
- a mixed film here, Ti modified
- a membrane 2 a mixed film of the TiOx nanocrystal 2a and the amorphous Ti film 2b doped with oxygen at a high concentration
- It is referred to as a membrane 2).
- (111) oriented Pt crystal grains 3 that are effectively surrounded by the TiOx nanostructures 7 are formed on the Ti modified film 2.
- the polarization of the adsorbed polar molecule is indicated by reference numeral 8 and the carrier inversion layer is indicated by reference numeral 9.
- the feature of this structure is that, unlike the Pt—Ti—O gate structure shown in FIG. 8 described above, the average interval between adjacent Pt crystal grains 3 is wide, and the Pt crystal grains 3 and the Pt crystal grains 3 are spaced apart from each other. Is a structure in which Pt crystal grains 3 and Pt crystal grains 3 are electrically short-circuited.
- the amount of molecular adsorption can be sensed by using the change in potential ⁇ V of the MOS structure threshold voltage (or flat band voltage) as the change in potential due to the change in surface potential ⁇ s due to the adsorbed gas shown in equation (24).
- the average distance between adjacent Pt crystal grains 3 is preferably about several nm.
- the dielectric constant is large as in the TiOx nanostructure 7 and that almost no carriers are present in the TiOx nanostructure 7. In this case, free carriers such as electrons or holes are not effectively present in the TiOx nanostructure 7, or few exist.
- the reason for reducing the average distance between adjacent Pt crystal grains 3 is to increase the electric capacity and to completely deplete the TiOx nanostructure 7.
- the TiOx nanostructure 7 is an insulator that is completely depleted at the operating temperature or has no carriers.
- the change amount ⁇ V of the gate potential can be observed with respect to the gas adsorption.
- the gas sensor can detect the gas concentration as the change amount ⁇ Vt of the gate potential. That is, the gas sensor can detect any gas that changes the surface potential ⁇ s of the Pt crystal grains 3 based on the above-described operating principle.
- the change amount ⁇ V of the gate potential may be considered as a shift amount of the threshold voltage Vth, and can be applied to a catalyst gate CMOS type gas sensor.
- a Pt film and a Ti film formed by an electron beam irradiation deposition method are heated in a nitrogen atmosphere at 400 ° C. for about 2 hours, and then further heated in air at 400 ° C. for 1 hour. Heated to a degree.
- the thickness of the Pt film is, for example, about 7 nm
- the thickness of the Ti film is, for example, about 3 nm. Thereafter, annealing using a 1% hydrogen concentration is performed.
- FIG. 13 is a graph showing the dependence of the sensor response intensity ( ⁇ Vg) on the ethanol gas concentration.
- ⁇ Vg sensor response intensity
- This method makes it possible to easily determine a desired threshold ethanol gas concentration without using an analog circuit and an AD converter, thereby providing a simple alcohol checker.
- the sensor response threshold strength ⁇ Vgth is 200 mV, which is lower than the sensor response threshold strength ⁇ Vgth of the first embodiment. Therefore, the reduction in temperature drift is effective in improving the measurement accuracy.
- the threshold input potential Vtc of the logic inversion characteristic can realize a stable (non-drift) inverter characteristic regardless of the temperature change. .
- the gate electrode is different between the catalyst gate structure of the second embodiment and the catalyst gate structure of the first embodiment, and accordingly, the threshold voltage Vtn of the nMOS transistor and the threshold voltage Vtp of the pMOS transistor are shifted.
- An nMOS transistor and a pMOS transistor having the same catalyst gate structure may be formed in the same manner as in the first embodiment to realize the circuit configuration shown in FIG. As a result, it is possible to eliminate the factor that fluctuates in the opposite phase due to the fluctuation of the threshold voltage of the nMOS transistor and the pMOS transistor.
- connection as a CMOS inverter was performed (the gates of the nMOS transistor and the pMOS transistor are both catalytic gates).
- the nMOS transistor and the pMOS transistor were formed independently, and the respective sensor response intensities were obtained.
- FIG. 14 shows an example of a plan view of a pMOS transistor and an nMOS transistor constituting the gas sensor.
- each of the pMOS transistor PTr and the nMOS transistor NTr are the same as those of the CMOS inverter shown in the first embodiment.
- a Si semiconductor was used.
- a catalyst gate CMOS type gas sensor that uses a SiC semiconductor and can be used in a high temperature environment of about 300 to 700 ° C. will be described.
- FIG. 15 is a schematic cross-sectional view showing an enlarged gate structure portion of the catalyst gate CMOS type hydrogen sensor according to the fourth embodiment.
- the catalyst gate has a modified Pt—Ti—O gate structure, and has a structure in which the proportion of the TiOx crystal portion in the modified Ti film is larger than that in the oxygen-doped amorphous Ti portion.
- This Pt film is composed of a plurality of Pt crystal grains 3, and O and Ti exist in the crystal grain boundary gaps 7 a between the plurality of Pt crystal grains 3. TiOx nanocrystals are formed (modified Pt film).
- FIG. 15 shows an example in which the carrier inversion layer 9 depending on the gate voltage exists at the interface between the SiC channel layer 98 and the gate insulating film 4.
- a Ti film is formed on the gate insulating film (SiO 2 film) 4 and further a Pt film is formed on the Ti film.
- the thickness of the Ti film is, for example, about 5 nm, and the thickness of the Pt film is, for example, about 15 nm.
- annealing is performed in air at 400 ° C. for 68 days. Alternatively, annealing in air at 600 ° C. for about 12 hours may be performed.
- Pt-Ti-O gate structure modified Pt-Ti-O / SiO 2 / SiC substrate structure adopting the points is stable, and a direct gate insulating film 4 formed was Pt / SiO 2 / SiC substrate structure on Pt It is a different point.
- the improved Pt—Ti—O / SiO 2 / SiC substrate structure is suitable for applications operating at 400 to 600 ° C. for a long time.
- Example 4 the circuit configuration of the catalyst gate CMOS inverter is the same as that of Example 1, but its performance is different from that of the catalyst gate CMOS type hydrogen sensor of Example 1.
- FIG. 16 is an example of a plan view of a CMOS inverter.
- FIG. 17 is a cross-sectional view of a main part of an nMOS transistor constituting the CMOS inverter (a cross-sectional view of the main part along the line AA ′ in FIG. 16).
- 18 is a cross-sectional view of main parts of the pMOS transistor constituting the CMOS inverter (main-part cross-sectional view along the line BB ′ in FIG. 16).
- an n-type 4H—SiC 8 ° off semiconductor substrate (2 ⁇ 10 18 / cm 3 ) is prepared.
- An n-type semiconductor layer 83 having a thickness of, for example, about 10 ⁇ m is formed on the semiconductor substrate by homoepitaxial technology.
- the electron concentration of the n-type semiconductor layer 83 is, for example, 1 ⁇ 10 17 / cm 3 .
- a p-type impurity for example, Al (aluminum) is ion-implanted with a dose energy of, for example, 250 kV.
- B boron
- the local oxide film 90 is formed on the main surface of the n-type semiconductor layer 83 by local oxidation.
- the local oxide film 90 is composed of, for example, a SiO 2 film, and the thickness thereof is, for example, about 250 nm.
- an n-type impurity for example, N (nitrogen) is ion-implanted into the p-well 84 using the oxide film as a mask to define the N-channel region, and an n-type semiconductor layer (Vth adjusted n-ion implantation layer) 87 is formed.
- an n-type impurity for example, N (nitrogen) is formed in a source region 77s and a drain region 77d having an impurity concentration of 1 ⁇ 10 20 / cm 3 and a depth from the surface of the n-type semiconductor layer 87 of about 200 nm.
- P phosphorus
- a p contact layer 81 is formed in order to control the substrate potential of the p well 84.
- Al aluminum
- the dose energy is, for example, 70 keV, and the dose amount is, for example, 5 ⁇ 10 14 / cm 2 .
- Ar annealing is performed at 1300 ° C. for 20 minutes in an Ar (argon) atmosphere. The annealing process may be performed individually after each ion implantation. Further, a flash annealing method for about 1 to 5 minutes may be used for the annealing treatment.
- a gate insulating film 75 is formed by a wet oxidation method.
- the gate insulating film 75 is made of, for example, a SiO 2 film, and has a thickness of, for example, about 30 nm.
- thermal oxidation at 850 ° C. for 30 minutes and thermal oxidation at 1100 ° C. for 6 hours are performed.
- a local oxide film 78 having a thickness of about 80 nm is also formed on the surface of the n-type semiconductor layer 87 in the source region 77s and the drain region 77d.
- hydrogen annealing is performed in an Ar atmosphere diluted with a hydrogen concentration of 1% (Ar diluted 1% hydrogen) at a heat treatment temperature of 800 to 1000 ° C. and a heat treatment time of 30 minutes.
- a hydrogen concentration of 1% Ar diluted 1% hydrogen
- the retention of hydrogen termination is improved as in Example 1.
- hydrogen gas having a hydrogen concentration of 0.1 to 3.5% is used.
- a gate electrode 70 made of a Ti film (not shown) and a Pt film is formed on the gate insulating film 75 by, for example, a lift-off method.
- the Ti film and the Pt film are continuously formed.
- the thickness of the Ti film is, for example, about 5 nm, and the thickness of the Pt film is, for example, about 15 nm.
- the thickness of the Ti film is often selected in the range of 2 to 10 nm, for example, and the thickness of the Pt film is often selected in the range of 5 to 90 nm, for example.
- the thickness of the Pt film is increased, for example, about 90 nm. This is because as the film thickness is increased, the sensitivity in the low concentration region is lost, and conversely, the sensitivity begins to be high in the high concentration region.
- the source region 77 s and the drain region 77 d are formed in accordance with the local oxide film 78 that defines the formation region of the gate electrode 75, and the gate electrode 70 is formed only on the gate insulating film 75. And formed so as to cover the upper surface of the local oxide film 78. Accordingly, the gate electrode 75 is formed so that the end of the gate electrode 70 overlaps the end of the source region 77s and the end of the drain region 77d. This is because the technique of forming the source region 77s and the drain region 77d in a self-aligned manner with respect to the gate electrode 70 cannot be used in the fourth embodiment.
- the Ti film and the Pt film are formed by, for example, an electron beam irradiation deposition method, and the film formation rate is, for example, about 10 nm / 1 minute.
- annealing is performed in an air atmosphere at a heat treatment temperature of 400 ° C. and a heat treatment period of 68 days, or by annealing in an air atmosphere at 600 ° C. for about 12 hours. Can be realized. Thereafter, hydrogen annealing may be performed in a nitrogen atmosphere having a hydrogen or deuterium concentration of about 0.1 to 3.5% and a heat treatment temperature of about 400 to 630 ° C. and a heat treatment time of 30 minutes.
- an insulating film 76 made of PSG (phosphorus-doped glass) or TEOS is formed on the n-type semiconductor layer 83 including the gate electrode 70. Then, a contact hole penetrating the insulating film 76 is formed, and a process such as surface treatment is performed.
- a Ti film, a TiN film, and a Pt film are sequentially deposited on the n-type semiconductor layer 83 by the EB vapor deposition lift-off method, and these are processed to form the source electrode 71, the drain electrode 72, and the control electrode 79.
- the thickness of the Ti film is, for example, about 50 nm
- the thickness of the TiN film is, for example, about 50 nm
- the thickness of the Pt film is, for example, about 300 nm.
- a protective film is formed on the main surface of the n-type semiconductor layer 83 in order to protect the source electrode 71, the drain electrode 72, the control electrode 79, and the chip.
- This protective film is composed of a laminated film of PSG (phosphorus doped glass) 74 and silicon nitride film 73, for example.
- a contact hole 86 is formed on an electrode pad (not shown), and an opening 99 is formed so as to expose the gate electrode 70 which is a sensor portion.
- a p-type semiconductor layer is formed by ion-implanting a p-type impurity, for example, Al (aluminum), into an n-type semiconductor layer 83 using an oxide film as a mask to define a P-channel region.
- a p-type impurity for example, Al (aluminum)
- Vth adjustment p ion implantation layer 88 is formed.
- a source region 82s and a drain region 82d having an impurity concentration of 1 ⁇ 10 20 / cm 3 and a depth of about 200 nm from the surface of the p-type semiconductor layer 88 are formed using a p-type impurity such as Al (aluminum).
- an n contact layer 85 is formed in order to control the substrate potential of the n-type semiconductor layer 83.
- N nitrogen
- the dose energy is, for example, 20 keV, and the dose amount is, for example, 5 ⁇ 10 14 / cm 2 .
- annealing is performed in the same manner as the nMOS transistor NTr.
- the insulating layer made of PSG (phosphorus doped glass) or TEOS is formed on the n-type semiconductor layer 83 including the gate electrode 70.
- a film 76 is formed.
- a contact hole penetrating the insulating film 76 is formed, and a process such as surface treatment is performed.
- the source electrode 91, the drain electrode 72, and the control electrode 80 are formed on the n-type semiconductor layer 83 in the same manner as the nMOS transistor NTr.
- a wiring heater may be formed using a laminated film made of a Ti film, a TiN film, and a Pt film constituting the source electrodes 71 and 91 and the like as a heater for heating the chip.
- the wiring heater has a wiring width of, for example, about 20 ⁇ m and a wiring length of, for example, about 29,000 ⁇ m.
- the gate electrode and the gate insulating film of the Pt—Ti—O structure are the same in the nMOS transistor and the pMOS transistor.
- the length Lg (n) and the gate length Lg (p) of the pMOS transistor are set to 10 ⁇ m, the gate width Wg (n) of the nMOS transistor is 200 ⁇ m, and the gate width Wg (p) of the pMOS transistor is 500 ⁇ m. .
- the threshold voltage Vtn of the nMOS transistor is defined as a voltage when the source-drain voltage Vds is 3.0 V and the source-drain current Ids is 10 ⁇ A, and is set to 1.3 V, for example.
- the threshold voltage Vtp of the pMOS transistor is defined as a voltage when the source-drain voltage Vds is ⁇ 3.0 V and the source-drain current Ids is 10 ⁇ A, for example, ⁇ 1.3 V.
- the other circuit configuration is the same as that of the first embodiment, and is omitted.
- This method makes it possible to easily determine a desired threshold hydrogen gas concentration without using an analog circuit and an AD converter, and it is possible to easily measure a hydrogen concentration threshold at a high temperature.
- the gate electrode is different between the catalyst gate structure of the fourth embodiment and the catalyst gate structure of the first embodiment, and accordingly, the threshold voltage Vtn of the nMOS transistor and the threshold voltage Vthp of the pMOS transistor are shifted.
- the gas sensor may be configured using a field effect transistor other than the MOS structure described in the first to fourth embodiments.
- a TFT Thin Film Transistor
- the TFT has been mainly applied to an image element so far, but an nMOS transistor and a pMOS transistor can be fabricated on the same substrate. Therefore, by applying a catalyst gate structure suitable for a desired gas, a gas sensor can be used. It goes without saying that it can be realized. That is, it suffices if a catalyst gate structure is formed and an nMOS transistor and a pMOS transistor applicable to a CMOS inverter can be realized.
- the nMOS transistor and the pMOS transistor are formed in the same chip, and the gates are placed as close as possible in order to avoid the influence of process variation.
- the present invention is not limited to this. Absent.
- the nMOS transistor and the pMOS transistor may be fabricated on separate chips.
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Abstract
Description
ΔVg=ΔVgmax×√(C/C0)/(1+√(C/C0))
・・・式(1)
と表すことができる。ここで、ΔVgmaxはセンサ応答強度ΔVgの最大値、Cはガスセンサ近傍の水素ガス濃度、C0はガスセンサの水素吸着サイトの半分を埋める時の水素濃度である(例えばT. Usagawa 他、IEEE Sensors Journal、12(2012)2243-2248参照)。従って、センサ応答強度ΔVgを測定することにより、水素ガス濃度を検知することができる。
・・・式(2)
Vtn=Vtn0-Kn(T-T0)・・・式(3)
Vtp=Vtp0+Kp(T-T0)・・・式(4)
と表される。Vtn0およびVtp0は、基準温度T0の時のしきい値電圧であり、基準温度近傍でのKnおよびKpは、
Kn≒Kp=2~3mV/℃・・・式(5)
である。KnおよびKpの具体的な値は、半導体材料であるSi、SiC、GaC(炭化ガリウム)、またはダイヤモンド(炭素)に依存するが、しきい値電圧Vtn,Vtpの温度特性およびKn≒Kpの関係は維持される。
Ids=βn(Vin-Vtn)2/2・・・式(6)
βn=Wg(n)μnCOx(n)/Lg(n)・・・式(7)
と表わされる。
Ids=βp(Vin-Vdd-Vtp)2/2・・・式(8)
βp=Wg(p)μpCOx(p)/Lg(p)・・・式(9)
と表される。
Vtc=[Vdd+√(βR)Vtn+Vtp]/(1+√(βR))
・・・式(10)
と表わされる。absは絶対値信号であり、
βR=βn/βp・・・式(11)
である。ゲート長Lg(n),Lg(p)、ゲート幅Wg(n),Wg(p)、および単位面積当たりのゲート容量COx(n),COx(p)は設計パラメータであり、nチャネル実効電子移動度μnおよびpチャネル実効電子移動度をμpが測定できれば、論理反転特性のしきい値入力電位Vtcを設計することができる。
pMOSトランジスタの触媒ゲートおよびnMOSトランジスタの触媒ゲートが水素ガス、水素化合物ガス、または極性分子ガス等の検知対象ガスに暴露されると、ガス濃度に応じて、pMOSトランジスタのしきい値電圧Vtpは負の方向へ、nMOSトランジスタのしきい値電圧Vtnも負の方向にシフトする(同位相変化)。ゲート構造(触媒ゲートおよびゲート絶縁膜)を同じに設計すれば、センサ応答強度ΔVgは両者で同じになる。ゲート絶縁膜の物質および構造が同じ場合、半導体に接するゲート絶縁膜の厚さが多少変わっても触媒ゲートが同じであれば、センサ応答強度ΔVgは両者でほぼ同じになる。
つまり、前述の図5に示すように、入力電位Vinを入力設定ゲート電位(入力電位Vinの初期値)Vin(D)(Vin<Vtc)に設定し、暴露させるガス濃度を上げていくと、(Vin(D)+ΔVg)がしきい値入力電位Vtcを超えたところで、CMOSインバータを反転させることが可能になる。つまり、検知対象ガスのないCMOSインバータの初期状態(Vin=Vin(D))から、暴露させるガス濃度を上げていくと、センサ応答強度ΔVgが徐々に大きくなり、あるしきい値濃度のガス環境で出力電位Voutが反転してVout=Vss(Vss=0V)となる。前述の図1に示すステップ型ガス応答SGRに近い応答を実現できるようになる(ここでは、上下反転しているが問題はない)。
この時、図6に示すように、センサ応答強度ΔVgに対する出力電位Voutは、入力電位VinをΔVgとするCMOSインバータ(前述の図4参照)の動作と類似の関数型になる。
ΔVthN=ΔVg(n)+ΔVth(n)・・・式(13)
ΔVthP=ΔVg(p)-ΔVth(p)・・・式(14)
と表される。センサ応答強度ΔVgはΔVg(n)=ΔVg(p)であり、また、ΔVth(n)≒ΔVth(p)である。
触媒ゲート電極を有するCMOSインバータを導入し、CMOSインバータの入力設定ゲート電位Vin(D)をΔVgth=Vtc-Vin(D)を満足するようにする。ここで、ΔVgthは警報または警告を出したい所望のガス濃度に対応するセンサ応答しきい値強度、VtcはCMOSインバータのしきい値入力電圧である。警報または警告を出したい所望のしきい値濃度が複数ある場合には、それぞれのガス濃度に対応したセンサ応答しきい値強度ΔVgthを複数用意して、それぞれのCMOSインバータにおいて、ΔVgth=Vtc-Vin(D)を満足するように入力設定ゲート電位Vin(D)を設計する。
触媒ゲート電極を有するCMOSインバータを導入し、CMOSインバータの入力設定ゲート電位Vin(D)をΔVgth=Vtc-Vin(D)を満足するようにする。ここで、ΔVgthは警報または警告を出したい所望のガス濃度に対応するセンサ応答しきい値強度、VtcはCMOSインバータのしきい値入力電圧である。そして、所望のセンサ応答しきい値強度ΔVgthに応じて、入力設定ゲート電位Vin(D)を可変にできるようにする。
CMOSインバータのしきい値入力電圧VtcをβR=βn/βp=1にし、所望の基準動作温度で、nMOSトランジスタのしきい値電圧Vtn0とpMOSトランジスタのしきい値電圧Vtp0とがVtn0=-Vtp0となるようにする。また、後述する実施例3で説明する様に、同じ触媒ゲート構造を有するnMOSトランジスタとpMOSトランジスタにおいて、それぞれのセンサ応答強度の和をとり、その1/2をセンサ信号とする。
Ids=βp(Vin+ΔVg(p)-Vdd-Vtp)2/2
・・・式(16)
式(15)と式(16)のソース-ドレイン間電流Idsが等しいとおくと、式(10)の論理反転特性のしきい値入力電位Vtcを用いて、
ΔVgeff=Vtc-Vin・・・式(17)
が求まる。ただし、ΔVgeffは次式で定義される触媒ゲートCMOS型ガスセンサの実効的な水素応答強度である。
(1+√(βR))・・・式(18)
ΔVgeffは、βR=1なら、ΔVg(n)とΔVg(p)の平均値ΔVgavになる。
ΔVg(n)とΔVg(p)の差分ΔVgdifを次式で定義する。
ΔVgeffは、一般には(βR≠1の時も含めて)、平均値ΔVgavと差分ΔVgdifを用いて、次式で表わすこともできる。
(1+√(βR))・・・式(21)
同一水素ガス濃度をnMOSトランジスタとpMOSトランジスタに照射した時、それぞれが互いに異なるセンサ応答強度ΔVg(n)とセンサ応答強度ΔVg(p)を持つ場合を考える。この場合、nMOSトランジスタのセンサ応答しきい値強度ΔVgth(n)とpMOSトランジスタのセンサ応答しきい値強度ΔVgth(p)が異なるので、センサ応答しきい値強度ΔVgthは、式(18)を用いて、新たなセンサ応答しきい値強度ΔVgeffthを次式で定義する。
(1+√(βR))・・・式(22)
この場合、CMOSインバータの入力設定ゲート電位Vin(D)は、式(12)の代わりに、
Vin(D)=Vtc-ΔVgeffth・・・式(23)
を用いる。これにより、nMOSトランジスタとpMOSトランジスタのセンサ応答強度ΔVgが互いに異なる値を持つ場合でも、センサ応答しきい値強度ΔVgthをΔVgeffth(式(22))で読み替えることにより、本発明を実現することができる。そのため、実施例1では、nMOSトランジスタのセンサ応答強度ΔVg(n)とpMOSトランジスタのセンサ応答強度ΔVg(p)が同じ場合についてのみ説明した。
ΔV=ΔφsCS・CE/[CS・CE+CM(CS+CE)] ・・・式(24)
の関係があり、ガス吸着に対してゲート電位の変化量ΔVを観測することができる。
+0.5]・・・式(25)
2 Ti改質膜
2a TiOxナノ結晶
2b アモルファスTi膜
3 Pt結晶粒
4 ゲート絶縁膜
5 シリコン基板
6 水素原子励起双極子
7 TiOxナノ構造体
7a 結晶粒界間隙
8 吸着極性分子の分極
9 キャリア反転層
19 開口部
20 ゲート電極
21 ソース電極
22 ドレイン電極
23 窒化シリコン膜
24 PSG(リンドープガラス)
25 ゲート絶縁膜
26 絶縁膜
27d ドレイン領域
27s ソース領域
28 局所酸化膜
29,30 制御電極
31 ソース電極
40 局所酸化膜
41 pコンタクト層
42d ドレイン領域
42s ソース領域
43 シリコン基板
44 nウェル
45 nコンタクト層
46 コンタクト孔
47 n型チャネル領域
48 p型チャネル領域
49 コンタクト孔
50,51反転加算増幅回路
52 加算回路部
53 nMOSトランジスタ
54 pMOSトランジスタ
56 出力
70 ゲート電極
71 ソース電極
72 ドレイン電極
73 PSG(リンドープガラス)
74 窒化シリコン膜
75 ゲート絶縁膜
76 絶縁膜
77d ドレイン領域
77s ソース領域
78 局所酸化膜
79,80 制御電極
81 pコンタクト層
82d ドレイン領域
82s ソース領域
83 半導体層
84 pウェル
85 nコンタクト層
86 コンタクト孔
87 半導体層
88 半導体層
89 コンタクト孔
90 局所酸化膜
98 SiCチャネル層
99 開口部
NTr nMOSトランジスタ
PTr pMOSトランジスタ
SGR ステップ型ガス応答
Claims (18)
- 触媒作用を有する第1ゲートを備えるnチャネル型電界効果トランジスタと、
触媒作用を有する第2ゲートを備えるpチャネル型電界効果トランジスタと、
を有し、
前記nチャネル型電界効果トランジスタのしきい値電圧のシフト量を示す第1センサ応答強度、および前記pチャネル電界効果トランジスタのしきい値電圧のシフト量を示す第2センサ応答強度を用いてガスの濃度を検知する、半導体ガスセンサ。 - 請求項1記載の半導体ガスセンサにおいて、
前記ガスは、水素ガス、水素化合物ガス、または極性分子ガスである、半導体ガスセンサ。 - 請求項1記載の半導体ガスセンサにおいて、
前記nチャネル型電界効果トランジスタの前記第1ゲートの構成と、前記pチャネル型電界効果トランジスタの前記第2ゲートの構成が同じである、半導体ガスセンサ。 - 請求項1記載の半導体ガスセンサにおいて、
前記nチャネル型電界効果トランジスタの前記第1センサ応答強度と、前記pチャネル型電界効果トランジスタの前記第2センサ応答強度との和の1/2を、センサ信号とする、半導体ガスセンサ。 - 請求項1記載の半導体ガスセンサにおいて、
前記nチャネル型電界効果トランジスタと前記pチャネル型電界効果トランジスタとがCMOSインバータを構成する、半導体ガスセンサ。 - 請求項1記載の半導体ガスセンサにおいて、
前記nチャネル型電界効果トランジスタと前記pチャネル型電界効果トランジスタとがCMOSインバータを構成し、前記nチャネル型電界効果トランジスタの前記第1ゲートの構成と、前記pチャネル型電界効果トランジスタの前記第2ゲートの構成が同じである、半導体ガスセンサ。 - 請求項5記載の半導体ガスセンサにおいて、
前記nチャネル型電界効果トランジスタの前記第1ゲートおよび前記pチャネル型電界効果トランジスタの第2ゲートは保護膜に覆われていない、半導体ガスセンサ。 - 請求項5記載の半導体ガスセンサにおいて、
前記CMOSインバータのしきい値入力電位がVtcであり、
検知したいガス濃度により生じる前記nチャネル型電界効果トランジスタの前記第1センサ応答強度がΔVgth(n)および前記pチャネル型電界効果トランジスタの前記第2センサ応答強度がΔVgth(p)である場合、
前記nチャネル型電界効果トランジスタの特性係数をβn、
前記pチャネル型電界効果トランジスタの特性係数をβp、
としたとき、
Vtn=-Vtp>0、
βR=βn/βp
であり、
前記CMOSインバータの入力設定ゲート電位であるVin(D)は、
ΔVgeffth=[√(βR)ΔVgth(n)+ΔVgth(p)]/(1+√(βR))と定義されたΔVgeffthを用いて、
Vin(D)=Vtc-ΔVgeffth
に設定される、半導体ガスセンサ。 - 請求項5記載の半導体ガスセンサにおいて、
前記CMOSインバータのしきい値入力電位がVtcであり、
検知したいガス濃度により生じる前記nチャネル型電界効果トランジスタの前記第1センサ応答強度および前記pチャネル型電界効果トランジスタの前記第2センサ応答強度がΔVgthである場合、
前記CMOSインバータの入力設定ゲート電位であるVin(D)は、
Vin(D)=Vtc-ΔVgth
に設定される、半導体ガスセンサ。 - 請求項5記載の半導体ガスセンサにおいて、
前記CMOSインバータのしきい値入力電位がVtcであり、
検知したい第1ガス濃度により生じる前記nチャネル型電界効果トランジスタの前記第1センサ応答強度および前記pチャネル型電界効果トランジスタの前記第2センサ応答強度がそれぞれΔVgth1であり、
前記第1ガス濃度と異なる検知したい第2ガス濃度により生じる前記nチャネル型電界効果トランジスタの前記第1センサ応答強度および前記pチャネル型電界効果トランジスタの前記第2センサ応答強度がそれぞれΔVgth2である場合、
前記第1ガス濃度を検知するときには、
前記CMOSインバータの第1入力設定ゲート電位であるVin(D)1は、
Vin(D)1=Vtc-ΔVgth1
に設定され、
前記第2ガス濃度を検知するときには、
前記CMOSインバータの第2入力設定ゲート電位であるVin(D)2は、
Vin(D)2=Vtc-ΔVgth2
に設定される、半導体ガスセンサ。 - 請求項5記載の半導体ガスセンサにおいて、
検知したいN個のガス濃度により生じる前記nチャネル型電界効果トランジスタの前記第1センサ応答強度および前記pチャネル型電界効果トランジスタの前記第2センサ応答強度が、N個の条件に応じて、それぞれΔVgth(N)である場合、
前記CMOSインバータのしきい値入力電位がVtc(I)、前記第1センサ応答強度および前記第2センサ応答強度がΔVgth(I)である、第I番目のガス濃度を検知するときには、
前記CMOSインバータの前記第I番目の入力設定ゲート電位であるVin(D)Iは、
Vin(D)I=Vtc(I)-ΔVgth(I)
に設定され、
N個の前記CMOSインバータから構成される、半導体ガスセンサ。 - 請求項11記載の半導体ガスセンサにおいて、
N個の前記CMOSインバータが同一基板上に構成される、半導体ガスセンサ。 - 請求項5記載の半導体ガスセンサにおいて、
前記CMOSインバータの低電位側の電位をVss、
前記CMOSインバータの高電位側の電位をVdd、
前記nチャネル型電界効果トランジスタのしきい値電位をVtn、
前記pチャネル型電界効果トランジスタのしきい値電位をVtp、
前記CMOSインバータのしきい値入力電位をVtc、
としたとき、
Vtn>0、
Vtp<0、
Vdd+Vtp>Vtc>Vtn
の関係を有する、半導体ガスセンサ。 - 請求項5記載の半導体ガスセンサにおいて、
前記nチャネル型電界効果トランジスタのしきい値電位をVtn、
前記pチャネル型電界効果トランジスタのしきい値電位をVtp、
前記CMOSインバータのしきい値入力電位をVtc、
前記nチャネル型電界効果トランジスタの特性係数をβn、
前記pチャネル型電界効果トランジスタの特性係数をβp、
としたとき、
Vtn=-Vtp>0、
βn/βp=1
の関係を有する、半導体ガスセンサ。 - 請求項1記載の半導体ガスセンサにおいて、
前記nチャネル型電界効果トランジスタおよび前記pチャネル型電界効果トランジスタは半導体基板の主面の互いに異なる領域に形成され、
前記nチャネル型電界効果トランジスタは、
(a)前記半導体基板上に形成された第1ゲート絶縁膜、
(b)前記第1ゲート絶縁膜上に形成された第1ゲート電極、
(c)前記半導体基板に形成された第1ソース領域、
(d)前記半導体基板に形成された第1ドレイン領域
を備え、
前記pチャネル型電界効果トランジスタは、
(e)前記半導体基板上に形成された第2ゲート絶縁膜、
(f)前記第2ゲート絶縁膜上に形成された第2ゲート電極、
(g)前記半導体基板に形成された第2ソース領域、
(h)前記半導体基板に形成された第2ドレイン領域、
を備え、
前記nチャネル型電界効果トランジスタの前記第1ゲート電極および前記pチャネル型電界効果トランジスタの前記第2ゲート電極は、
(i)酸素を含有する酸素ドープチタン膜とチタン微結晶が混合したチタン改質膜、
(j)前記チタン改質膜上に形成されたプラチナ膜、
から構成される、半導体ガスセンサ。 - 請求項15記載の半導体ガスセンサにおいて、
前記プラチナ膜は、複数の結晶粒から構成され、前記複数の結晶粒の間にある粒界領域には酸素とチタンが存在する、半導体ガスセンサ。 - 請求項15記載の半導体ガスセンサにおいて、
前記nチャネル型電界効果トランジスタの前記第1ドレイン領域と、前記pチャネル型電界効果トランジスタの前記第2ドレイン領域とは電気的に接続され、
前記nチャネル型電界効果トランジスタの前記第1ゲート電極と、前記pチャネル型電界効果トランジスタの前記第2ゲート電極とは電気的に接続されている、半導体ガスセンサ。 - 請求項1または5記載の半導体ガスセンサにおいて、
前記nチャネル型電界効果トランジスタおよび前記pチャネル型電界効果トランジスタが配置された領域に近接してヒータ領域が配置されている、半導体ガスセンサ。
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JPH06249826A (ja) * | 1993-02-26 | 1994-09-09 | Tokyo Gas Co Ltd | Fetセンサ |
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US9897569B2 (en) * | 2010-07-08 | 2018-02-20 | The Johns Hopkins University | Circuits, devices and sensors for fluid detection |
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