WO2014181565A1 - Dispositif à semi-conducteur et dispositif de protection esd - Google Patents

Dispositif à semi-conducteur et dispositif de protection esd Download PDF

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Publication number
WO2014181565A1
WO2014181565A1 PCT/JP2014/054405 JP2014054405W WO2014181565A1 WO 2014181565 A1 WO2014181565 A1 WO 2014181565A1 JP 2014054405 W JP2014054405 W JP 2014054405W WO 2014181565 A1 WO2014181565 A1 WO 2014181565A1
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WO
WIPO (PCT)
Prior art keywords
layer
semiconductor substrate
formation layer
element formation
trench
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Application number
PCT/JP2014/054405
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English (en)
Japanese (ja)
Inventor
中磯俊幸
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株式会社村田製作所
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Publication date
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Publication of WO2014181565A1 publication Critical patent/WO2014181565A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/8611—Planar PN junction diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/0814—Diodes only

Definitions

  • the present invention relates to a semiconductor device in which an element formation layer is provided on the surface of a semiconductor substrate and an element isolation region for separating elements of the element formation layer is formed, and an ESD protection device including the structure thereof.
  • Patent Document 1 discloses an ESD protection element configured by forming a plurality of elements on a semiconductor substrate such as a silicon (Si) substrate.
  • Patent Document 1 includes a structure in which a horizontal element, a vertical element, and an element isolation region for insulating and separating the horizontal element and the vertical element are formed.
  • the element isolation region shown in Patent Document 1 is a trench filled with an insulator.
  • the method of forming an element isolation region having a structure in which a trench is filled with an insulator has a difficulty in terms of manufacturing efficiency and manufacturing cost, and the trench is filled with a conductor such as polysilicon (Poly-Si). May take structure.
  • FIG. 9 is a schematic cross-sectional view of a semiconductor device showing an example thereof.
  • a SiOx insulating film 111 is formed on the surface of the element formation layer 10L of the semiconductor substrate, an Al electrode film 20 is formed in the contact hole, and a silicon nitride film (SiNx) 21 as a protective film is formed on the surface.
  • SiNx silicon nitride film
  • An object of the present invention is to provide a semiconductor device that eliminates the configuration of parasitic elements due to trench isolation, and an ESD protection device having the structure.
  • an element isolation layer is provided on the surface of the semiconductor substrate, the element formation layer forming a plurality of elements.
  • the element isolation region is a trench isolation in which a Si oxide film is formed on the inner surface of a trench and polysilicon is filled therein, and two elements separated in the element isolation region are
  • the surface of the formation layer is provided with a semiconductor layer opposite to the mold of the semiconductor substrate, and the upper surface of the element formation layer has a charge characteristic (polarity) opposite to that of the semiconductor substrate, or a charge characteristic (polarity).
  • a protective film that does not have a characteristic is formed.
  • the two elements separated by this trench are opposite to the type of the semiconductor substrate on the surface of the element formation layer.
  • a MOSFET structure is constituted by the semiconductor layers of these two elements and trench isolation. That is, the semiconductor layers of the two elements function as a drain and a source, and the polysilicon inside the trench functions as a gate electrode.
  • the polysilicon in the trench has the same potential as the semiconductor substrate, a channel is formed in the semiconductor substrate.
  • the silicon nitride film is positively charged due to its physical properties, if the trench is filled with polysilicon, a channel is formed in the semiconductor substrate through the polysilicon. An unnecessary current path is formed. As a result, a leak current is generated.
  • the protective film since the protective film has a charging characteristic (polarity) opposite to that of the semiconductor type on the surface of the element forming layer or does not have a charging characteristic (polarity), a potential is applied to the polysilicon inside the trench. Therefore, the channel in the MOSFET structure is not formed, and an unnecessary energization path is not formed.
  • one of the two elements is a Zener diode, and the other is a diode conducting to the Zener diode.
  • one of the two elements is a diode having a vertical structure using a junction layer between the semiconductor substrate and the well of the element formation layer, and the other is in a well formed in the element formation layer. This is a horizontal structure diode.
  • An ESD protection device of the present invention includes the semiconductor device according to any one of (1) to (3), and has a structure in which the diode is connected in series to the Zener diode.
  • the protective film has a charging characteristic (polarity) opposite to that of the semiconductor substrate or does not have a charging characteristic (polarity)
  • no potential is applied to the polysilicon inside the trench.
  • FIG. 1 is a cross-sectional view of a main part of the semiconductor device according to the first embodiment.
  • FIG. 2 is a schematic cross-sectional view showing a MOSFET structure constituted by a semiconductor layer of two elements separated by a trench and trench isolation.
  • FIG. 3 is a schematic cross-sectional view showing the structure of the rewiring layer of the semiconductor device.
  • FIG. 4 is a diagram showing a structure of an ESD protection circuit configured in a semiconductor substrate and an element formation layer according to the second embodiment.
  • FIG. 5 is a plan view of each layer of the ESD protection device according to the second embodiment.
  • 6A is a circuit diagram of the ESD protection device shown in FIG.
  • FIG. 6B is a diagram illustrating an example of an unnecessary current path generated by the conventional structure.
  • FIG. 7 is a diagram showing voltage / current characteristics of the ESD protection device.
  • FIG. 8A is a diagram showing a connection example of the ESD protection device according to the present embodiment.
  • FIG. 8B is a diagram showing a connection example of the ESD protection device according to the present embodiment.
  • FIG. 9 is a schematic cross-sectional view of a semiconductor device on which a silicon nitride film (SiNx) is formed.
  • FIG. 10 is a diagram illustrating a state in which a channel is configured in a MOSFET configured by a semiconductor layer of two elements separated by a trench and trench isolation.
  • FIG. 1 is a cross-sectional view of a main part of a semiconductor device according to an embodiment of the present invention.
  • an element formation layer 10L for forming a plurality of elements is provided on the surface of a p + Si semiconductor substrate 10, and a plurality of elements deeper than the element formation layer 10L from the surface of the element formation layer 10L into the semiconductor substrate 10 are provided.
  • An isolation region 110 is formed.
  • These element isolation regions 110 are trench isolations in which a Si oxide film (SiOx) is formed on the inner surface of a trench and polysilicon is filled therein.
  • Two elements separated by the element isolation region 110 are n epitaxial layers that are opposite to the type (p +) of the semiconductor substrate 10 on the surface of the element formation layer 10L. I have.
  • the protective film 22 is a polyimide resin or epoxy resin film.
  • the manufacturing process of the semiconductor device shown in FIG. 1 is as follows.
  • an n-type epitaxial layer is grown on the p + semiconductor substrate 10.
  • a trench is formed by an STI (Shallow Trench Isolation) method. Specifically, first, the p + semiconductor substrate 10 is thermally oxidized to form a SiOx film on the surface, and then a SiNx film is formed by CVD. Next, a photoresist is applied, exposed, and developed to form a pattern, which is used as a mask to etch in the order of SiNx / SiOx / Si to form a trench. Next, after forming the SiOx layer 110S on the inner wall surface of the trench by the CVD method, the polysilicon 110P is filled by the CVD method. Since polysilicon is formed on the entire surface of the substrate, it is deleted by the CMP method. At this time, the SiNx film acts as a polishing stopper. Thereafter, the SiNx film is removed. In this way, trench isolation is formed.
  • STI Silicon Trench Isolation
  • An n-type well and a p-type well are formed in a predetermined region of the n-type epitaxial layer by an ion implantation method or a diffusion method.
  • n + region or a p + region is formed by ion implantation or diffusion in a predetermined region of the n-type epitaxial layer, a predetermined region of the n-type well or the p-type well.
  • a SiOx film is formed on the surface of the element formation layer 10L by the CVD method.
  • a contact hole is opened in the SiO 2 film, and then an Al electrode film is formed by sputtering.
  • the Al electrode film is patterned into a predetermined wiring pattern.
  • the protective film 22 is applied to the surface by spin coating and baked.
  • a rewiring layer made of Cu is formed by a plurality of steps.
  • FIG. 1 the cross section in the state in which the protective film 22 was formed is shown.
  • the trench isolation may be formed after the element is formed.
  • FIG. 2 is a schematic cross-sectional view showing a MOSFET structure constituted by a semiconductor layer of two elements separated by a trench and trench isolation.
  • the n epitaxial layer is a semiconductor layer of two elements separated by a trench.
  • a SiOx layer 110S and a polysilicon 110P are arranged so as to cover the two semiconductor layers with the p + substrate 10 interposed therebetween.
  • This structure can be called a MOSFET structure. That is, the semiconductor layer (n epitaxial layer) of the two elements functions as a drain and a source, and the polysilicon 110P inside the trench functions as a gate electrode.
  • the SiNx film 21 is positively charged due to the physical properties of SiNx.
  • the polysilicon 110P as a conductor is also positively charged. Since this charge is the same type as that of the p + semiconductor substrate 10, an n channel (n ⁇ ch) is formed in the p + semiconductor substrate 10. In this state, the two n epitaxial layers 100-100 separated by the trench are electrically connected.
  • the SiOx film 111 and the protective film 22 are both insulating layers having no charging characteristics (polarity), the polysilicon 110P is not charged, and the channel is not formed on the p + substrate 10. Not formed. Therefore, an unnecessary energization path is not formed.
  • FIG. 3 is a schematic cross-sectional view showing the structure of the rewiring layer of the semiconductor device.
  • the rewiring layer 30 is formed on the surface of the element formation layer 10L of the semiconductor substrate.
  • a Cu film pattern 24 for rewiring is formed on the protective film 22.
  • External connection electrodes 25 are formed at predetermined positions of the Cu film pattern 24.
  • An opening for exposing the external connection electrode 25 is formed in the protective film 23 on the outermost surface. In this way, the rewiring layer 30 is configured.
  • the film formation cost can be reduced by forming a polyimide resin or an epoxy resin as a protective film without forming a SiNx film as a conventional general passivation film.
  • the Al electrode film is not damaged by forming the SiNx film. Therefore, the SiOx film and the Al electrode film function as a passivation film that suppresses moisture intrusion.
  • the protective films 22 and 23 ensure the mechanical strength of the element formation layer 10L and the rewiring layer 30.
  • the second embodiment shows an example applied to an ESD protection device.
  • FIG. 4 is a diagram showing the structure of an ESD protection circuit configured on the semiconductor substrate 10 and the element formation layer 10L.
  • the semiconductor device shown in FIG. 1 in the first embodiment is already an ESD protection device.
  • the diodes D1 to D4 and the Zener diode Dz shown in FIG. 4 are elements configured in regions indicated by D1 to D4 and Dz in FIG.
  • the electrodes P1 and P2 correspond to the electrodes indicated by P1 and P2 in the Al electrode film 20 in FIG.
  • FIG. 5 is a plan view of each layer of the ESD protection device of the present embodiment.
  • An opening is formed in the resin layer 22 included in the rewiring layer 30 formed in the semiconductor substrate 10.
  • the electrodes P1 and P2 are electrically connected to the Cu film pattern 24 through the opening.
  • the external connection electrode 25 on the Cu film pattern 24 is exposed to the opening formed in the protective film 23.
  • FIG. 6A is a circuit diagram of the ESD protection device shown in FIG.
  • This ESD protection device is a device that allows an ESD current to flow between ports P1 and P2.
  • a positive high voltage surge voltage exceeding the Zener voltage of the Zener diode Dz
  • a surge current flows through the path P2.
  • FIG. 7 is a diagram showing the voltage / current characteristics of the ESD protection device.
  • the characteristic curve A shows the characteristic when the protective film 22 is a polyimide resin or an epoxy resin in the structure shown in FIG.
  • a characteristic curve B shows the characteristics when the protective film is a SiNx film.
  • the protective film is a SiNx film
  • no leakage current flows even when ⁇ 7 V is reached, and energization is performed at a time exceeding ⁇ 10 V, and ESD protection is performed.
  • FIGS. 8A and 8B are diagrams showing a connection example of the ESD protection device 1 according to the present embodiment.
  • the ESD protection device 1 is mounted on an electronic device. Examples of electronic devices include notebook PCs, tablet terminal devices, mobile phones, digital cameras, and portable music players.
  • FIG. 8A shows an example in which the ESD protection device 1 is connected to the shunt with respect to the signal line between the IC 101 to be protected and the port Po.
  • the port Po is a port to which an antenna is connected, for example.
  • FIG. 8B shows an example in which a plurality of ESD protection devices 1 are connected between the signal line connecting the connector 102 and the IC 101 and the GND line.
  • the signal line in this example is, for example, a high-speed transmission line (differential transmission line), and the ESD protection device 1 is connected between each of the plurality of signal lines and the GND line.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

La présente invention concerne une couche de formation d'un élément sur la surface d'un substrat semi-conducteur dans laquelle une pluralité d'éléments sont formés, une région d'isolement d'un élément plus profonde que la couche de formation de l'élément étant formée à partir de la surface de la couche de formation de l'élément vers l'intérieur du substrat semi-conducteur, la région d'isolement de l'élément étant un isolement par tranchée présentant un film de SiOx formé sur la surface intérieure de la tranchée, l'intérieur de l'isolement par tranchée étant rempli de polysilicium. Deux éléments isolés par la région d'isolement de l'élément, sur la surface de la couche de formation de l'élément, sont pourvus d'une couche semi-conductrice d'un type opposé à celui du substrat semi-conducteur, un film de protection présentant une caractéristique de charge (polarité) opposée à celle du substrat semi-conducteur ou ne présentant pas de caractéristique de charge (polarité) étant formé sur la face supérieure de la couche de formation de l'élément. Ceci permet de fournir un dispositif à semi-conducteur éliminant la configuration d'un élément parasite à l'aide d'un isolement par tranchée et un dispositif de protection ESD pourvu d'une structure associée.
PCT/JP2014/054405 2013-05-07 2014-02-25 Dispositif à semi-conducteur et dispositif de protection esd WO2014181565A1 (fr)

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JP2013097494 2013-05-07
JP2013-097494 2013-05-07

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023058553A1 (fr) * 2021-10-04 2023-04-13 株式会社村田製作所 Élément d'absorption de surtension

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002176106A (ja) * 2000-09-14 2002-06-21 Vishay Intertechnology Inc 半導体基板上に形成される高精度高周波数キャパシタ
JP2004221569A (ja) * 2003-01-09 2004-08-05 Internatl Business Mach Corp <Ibm> トリプル・ウェル半導体デバイスの静電放電保護回路
JP2008098479A (ja) * 2006-10-13 2008-04-24 Toyota Central R&D Labs Inc 静電気保護用半導体装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002176106A (ja) * 2000-09-14 2002-06-21 Vishay Intertechnology Inc 半導体基板上に形成される高精度高周波数キャパシタ
JP2004221569A (ja) * 2003-01-09 2004-08-05 Internatl Business Mach Corp <Ibm> トリプル・ウェル半導体デバイスの静電放電保護回路
JP2008098479A (ja) * 2006-10-13 2008-04-24 Toyota Central R&D Labs Inc 静電気保護用半導体装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023058553A1 (fr) * 2021-10-04 2023-04-13 株式会社村田製作所 Élément d'absorption de surtension

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