WO2014181565A1 - Semiconductor device and esd protection device - Google Patents

Semiconductor device and esd protection device Download PDF

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WO2014181565A1
WO2014181565A1 PCT/JP2014/054405 JP2014054405W WO2014181565A1 WO 2014181565 A1 WO2014181565 A1 WO 2014181565A1 JP 2014054405 W JP2014054405 W JP 2014054405W WO 2014181565 A1 WO2014181565 A1 WO 2014181565A1
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layer
semiconductor substrate
formation layer
element formation
trench
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French (fr)
Japanese (ja)
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中磯俊幸
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株式会社村田製作所
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/8611—Planar PN junction diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/0814—Diodes only

Definitions

  • the present invention relates to a semiconductor device in which an element formation layer is provided on the surface of a semiconductor substrate and an element isolation region for separating elements of the element formation layer is formed, and an ESD protection device including the structure thereof.
  • Patent Document 1 discloses an ESD protection element configured by forming a plurality of elements on a semiconductor substrate such as a silicon (Si) substrate.
  • Patent Document 1 includes a structure in which a horizontal element, a vertical element, and an element isolation region for insulating and separating the horizontal element and the vertical element are formed.
  • the element isolation region shown in Patent Document 1 is a trench filled with an insulator.
  • the method of forming an element isolation region having a structure in which a trench is filled with an insulator has a difficulty in terms of manufacturing efficiency and manufacturing cost, and the trench is filled with a conductor such as polysilicon (Poly-Si). May take structure.
  • FIG. 9 is a schematic cross-sectional view of a semiconductor device showing an example thereof.
  • a SiOx insulating film 111 is formed on the surface of the element formation layer 10L of the semiconductor substrate, an Al electrode film 20 is formed in the contact hole, and a silicon nitride film (SiNx) 21 as a protective film is formed on the surface.
  • SiNx silicon nitride film
  • An object of the present invention is to provide a semiconductor device that eliminates the configuration of parasitic elements due to trench isolation, and an ESD protection device having the structure.
  • an element isolation layer is provided on the surface of the semiconductor substrate, the element formation layer forming a plurality of elements.
  • the element isolation region is a trench isolation in which a Si oxide film is formed on the inner surface of a trench and polysilicon is filled therein, and two elements separated in the element isolation region are
  • the surface of the formation layer is provided with a semiconductor layer opposite to the mold of the semiconductor substrate, and the upper surface of the element formation layer has a charge characteristic (polarity) opposite to that of the semiconductor substrate, or a charge characteristic (polarity).
  • a protective film that does not have a characteristic is formed.
  • the two elements separated by this trench are opposite to the type of the semiconductor substrate on the surface of the element formation layer.
  • a MOSFET structure is constituted by the semiconductor layers of these two elements and trench isolation. That is, the semiconductor layers of the two elements function as a drain and a source, and the polysilicon inside the trench functions as a gate electrode.
  • the polysilicon in the trench has the same potential as the semiconductor substrate, a channel is formed in the semiconductor substrate.
  • the silicon nitride film is positively charged due to its physical properties, if the trench is filled with polysilicon, a channel is formed in the semiconductor substrate through the polysilicon. An unnecessary current path is formed. As a result, a leak current is generated.
  • the protective film since the protective film has a charging characteristic (polarity) opposite to that of the semiconductor type on the surface of the element forming layer or does not have a charging characteristic (polarity), a potential is applied to the polysilicon inside the trench. Therefore, the channel in the MOSFET structure is not formed, and an unnecessary energization path is not formed.
  • one of the two elements is a Zener diode, and the other is a diode conducting to the Zener diode.
  • one of the two elements is a diode having a vertical structure using a junction layer between the semiconductor substrate and the well of the element formation layer, and the other is in a well formed in the element formation layer. This is a horizontal structure diode.
  • An ESD protection device of the present invention includes the semiconductor device according to any one of (1) to (3), and has a structure in which the diode is connected in series to the Zener diode.
  • the protective film has a charging characteristic (polarity) opposite to that of the semiconductor substrate or does not have a charging characteristic (polarity)
  • no potential is applied to the polysilicon inside the trench.
  • FIG. 1 is a cross-sectional view of a main part of the semiconductor device according to the first embodiment.
  • FIG. 2 is a schematic cross-sectional view showing a MOSFET structure constituted by a semiconductor layer of two elements separated by a trench and trench isolation.
  • FIG. 3 is a schematic cross-sectional view showing the structure of the rewiring layer of the semiconductor device.
  • FIG. 4 is a diagram showing a structure of an ESD protection circuit configured in a semiconductor substrate and an element formation layer according to the second embodiment.
  • FIG. 5 is a plan view of each layer of the ESD protection device according to the second embodiment.
  • 6A is a circuit diagram of the ESD protection device shown in FIG.
  • FIG. 6B is a diagram illustrating an example of an unnecessary current path generated by the conventional structure.
  • FIG. 7 is a diagram showing voltage / current characteristics of the ESD protection device.
  • FIG. 8A is a diagram showing a connection example of the ESD protection device according to the present embodiment.
  • FIG. 8B is a diagram showing a connection example of the ESD protection device according to the present embodiment.
  • FIG. 9 is a schematic cross-sectional view of a semiconductor device on which a silicon nitride film (SiNx) is formed.
  • FIG. 10 is a diagram illustrating a state in which a channel is configured in a MOSFET configured by a semiconductor layer of two elements separated by a trench and trench isolation.
  • FIG. 1 is a cross-sectional view of a main part of a semiconductor device according to an embodiment of the present invention.
  • an element formation layer 10L for forming a plurality of elements is provided on the surface of a p + Si semiconductor substrate 10, and a plurality of elements deeper than the element formation layer 10L from the surface of the element formation layer 10L into the semiconductor substrate 10 are provided.
  • An isolation region 110 is formed.
  • These element isolation regions 110 are trench isolations in which a Si oxide film (SiOx) is formed on the inner surface of a trench and polysilicon is filled therein.
  • Two elements separated by the element isolation region 110 are n epitaxial layers that are opposite to the type (p +) of the semiconductor substrate 10 on the surface of the element formation layer 10L. I have.
  • the protective film 22 is a polyimide resin or epoxy resin film.
  • the manufacturing process of the semiconductor device shown in FIG. 1 is as follows.
  • an n-type epitaxial layer is grown on the p + semiconductor substrate 10.
  • a trench is formed by an STI (Shallow Trench Isolation) method. Specifically, first, the p + semiconductor substrate 10 is thermally oxidized to form a SiOx film on the surface, and then a SiNx film is formed by CVD. Next, a photoresist is applied, exposed, and developed to form a pattern, which is used as a mask to etch in the order of SiNx / SiOx / Si to form a trench. Next, after forming the SiOx layer 110S on the inner wall surface of the trench by the CVD method, the polysilicon 110P is filled by the CVD method. Since polysilicon is formed on the entire surface of the substrate, it is deleted by the CMP method. At this time, the SiNx film acts as a polishing stopper. Thereafter, the SiNx film is removed. In this way, trench isolation is formed.
  • STI Silicon Trench Isolation
  • An n-type well and a p-type well are formed in a predetermined region of the n-type epitaxial layer by an ion implantation method or a diffusion method.
  • n + region or a p + region is formed by ion implantation or diffusion in a predetermined region of the n-type epitaxial layer, a predetermined region of the n-type well or the p-type well.
  • a SiOx film is formed on the surface of the element formation layer 10L by the CVD method.
  • a contact hole is opened in the SiO 2 film, and then an Al electrode film is formed by sputtering.
  • the Al electrode film is patterned into a predetermined wiring pattern.
  • the protective film 22 is applied to the surface by spin coating and baked.
  • a rewiring layer made of Cu is formed by a plurality of steps.
  • FIG. 1 the cross section in the state in which the protective film 22 was formed is shown.
  • the trench isolation may be formed after the element is formed.
  • FIG. 2 is a schematic cross-sectional view showing a MOSFET structure constituted by a semiconductor layer of two elements separated by a trench and trench isolation.
  • the n epitaxial layer is a semiconductor layer of two elements separated by a trench.
  • a SiOx layer 110S and a polysilicon 110P are arranged so as to cover the two semiconductor layers with the p + substrate 10 interposed therebetween.
  • This structure can be called a MOSFET structure. That is, the semiconductor layer (n epitaxial layer) of the two elements functions as a drain and a source, and the polysilicon 110P inside the trench functions as a gate electrode.
  • the SiNx film 21 is positively charged due to the physical properties of SiNx.
  • the polysilicon 110P as a conductor is also positively charged. Since this charge is the same type as that of the p + semiconductor substrate 10, an n channel (n ⁇ ch) is formed in the p + semiconductor substrate 10. In this state, the two n epitaxial layers 100-100 separated by the trench are electrically connected.
  • the SiOx film 111 and the protective film 22 are both insulating layers having no charging characteristics (polarity), the polysilicon 110P is not charged, and the channel is not formed on the p + substrate 10. Not formed. Therefore, an unnecessary energization path is not formed.
  • FIG. 3 is a schematic cross-sectional view showing the structure of the rewiring layer of the semiconductor device.
  • the rewiring layer 30 is formed on the surface of the element formation layer 10L of the semiconductor substrate.
  • a Cu film pattern 24 for rewiring is formed on the protective film 22.
  • External connection electrodes 25 are formed at predetermined positions of the Cu film pattern 24.
  • An opening for exposing the external connection electrode 25 is formed in the protective film 23 on the outermost surface. In this way, the rewiring layer 30 is configured.
  • the film formation cost can be reduced by forming a polyimide resin or an epoxy resin as a protective film without forming a SiNx film as a conventional general passivation film.
  • the Al electrode film is not damaged by forming the SiNx film. Therefore, the SiOx film and the Al electrode film function as a passivation film that suppresses moisture intrusion.
  • the protective films 22 and 23 ensure the mechanical strength of the element formation layer 10L and the rewiring layer 30.
  • the second embodiment shows an example applied to an ESD protection device.
  • FIG. 4 is a diagram showing the structure of an ESD protection circuit configured on the semiconductor substrate 10 and the element formation layer 10L.
  • the semiconductor device shown in FIG. 1 in the first embodiment is already an ESD protection device.
  • the diodes D1 to D4 and the Zener diode Dz shown in FIG. 4 are elements configured in regions indicated by D1 to D4 and Dz in FIG.
  • the electrodes P1 and P2 correspond to the electrodes indicated by P1 and P2 in the Al electrode film 20 in FIG.
  • FIG. 5 is a plan view of each layer of the ESD protection device of the present embodiment.
  • An opening is formed in the resin layer 22 included in the rewiring layer 30 formed in the semiconductor substrate 10.
  • the electrodes P1 and P2 are electrically connected to the Cu film pattern 24 through the opening.
  • the external connection electrode 25 on the Cu film pattern 24 is exposed to the opening formed in the protective film 23.
  • FIG. 6A is a circuit diagram of the ESD protection device shown in FIG.
  • This ESD protection device is a device that allows an ESD current to flow between ports P1 and P2.
  • a positive high voltage surge voltage exceeding the Zener voltage of the Zener diode Dz
  • a surge current flows through the path P2.
  • FIG. 7 is a diagram showing the voltage / current characteristics of the ESD protection device.
  • the characteristic curve A shows the characteristic when the protective film 22 is a polyimide resin or an epoxy resin in the structure shown in FIG.
  • a characteristic curve B shows the characteristics when the protective film is a SiNx film.
  • the protective film is a SiNx film
  • no leakage current flows even when ⁇ 7 V is reached, and energization is performed at a time exceeding ⁇ 10 V, and ESD protection is performed.
  • FIGS. 8A and 8B are diagrams showing a connection example of the ESD protection device 1 according to the present embodiment.
  • the ESD protection device 1 is mounted on an electronic device. Examples of electronic devices include notebook PCs, tablet terminal devices, mobile phones, digital cameras, and portable music players.
  • FIG. 8A shows an example in which the ESD protection device 1 is connected to the shunt with respect to the signal line between the IC 101 to be protected and the port Po.
  • the port Po is a port to which an antenna is connected, for example.
  • FIG. 8B shows an example in which a plurality of ESD protection devices 1 are connected between the signal line connecting the connector 102 and the IC 101 and the GND line.
  • the signal line in this example is, for example, a high-speed transmission line (differential transmission line), and the ESD protection device 1 is connected between each of the plurality of signal lines and the GND line.

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Abstract

On the surface of a semiconductor substrate is provided an element formation layer in which a plurality of elements are formed, an element isolation region deeper than the element formation layer being formed from the surface of the element formation layer to the interior of the semiconductor substrate, the element isolation region being a trench isolation having an SiOx film formed on the inner surface of the trench, the inside of the trench isolation being filled with polysilicon. Two elements isolated by the element isolation region, on the surface of the element formation layer, are provided with a semiconductor layer of a type opposite that of the semiconductor substrate, a protective film having a charging characteristic (polarity) opposite that of the semiconductor substrate or having no charging characteristic (polarity) being formed on the top face of the element formation layer. There are thereby provided a semiconductor device eliminating the configuration of a parasitic element by using a trench isolation, and an ESD protection device provided with a structure thereof.

Description

半導体装置およびＥＳＤ保護デバイスSemiconductor device and ESD protection device
　本発明は、半導体基板の表面に素子形成層が設けられ、素子形成層の素子間を分離する素子分離領域が形成された、半導体装置およびその構造を備えるＥＳＤ保護デバイスに関するものである。 The present invention relates to a semiconductor device in which an element formation layer is provided on the surface of a semiconductor substrate and an element isolation region for separating elements of the element formation layer is formed, and an ESD protection device including the structure thereof.
　シリコン（Si）基板などの半導体基板に複数の素子を形成することで構成されたＥＳＤ保護素子が特許文献１に示されている。特許文献１には、横型素子、縦型素子、および横型素子と縦型素子とを絶縁分離する素子分離領域が形成された構造を備えている。 Patent Document 1 discloses an ESD protection element configured by forming a plurality of elements on a semiconductor substrate such as a silicon (Si) substrate. Patent Document 1 includes a structure in which a horizontal element, a vertical element, and an element isolation region for insulating and separating the horizontal element and the vertical element are formed.
特開２００６－１７９６３２号公報JP 2006-179632 A
　特許文献１に示されている素子分離領域は絶縁体が充填されたトレンチである。しかし、トレンチを絶縁体で充填した構造の素子分離領域を形成する工法には、製造効率・製造コストの点で難点があり、トレンチ内をポリシリコン（Poly-Si）などの導電体で充填する構造をとることがある。 The element isolation region shown in Patent Document 1 is a trench filled with an insulator. However, the method of forming an element isolation region having a structure in which a trench is filled with an insulator has a difficulty in terms of manufacturing efficiency and manufacturing cost, and the trench is filled with a conductor such as polysilicon (Poly-Si). May take structure.
　一方、半導体基板の素子形成層の表面には、主に耐湿性および機械的強度の確保を目的として窒化シリコン膜（SiNx）が形成される。図９はその例を示す半導体装置の概略断面図である。半導体基板の素子形成層１０Ｌの表面にはSiOx 絶縁膜１１１が形成されていて、コンタクトホールにAl電極膜２０が形成されて、さらに、表面に保護膜としての窒化シリコン膜（SiNx）２１が形成されている。 On the other hand, a silicon nitride film (SiNx) is formed on the surface of the element forming layer of the semiconductor substrate mainly for the purpose of securing moisture resistance and mechanical strength. FIG. 9 is a schematic cross-sectional view of a semiconductor device showing an example thereof. A SiOx insulating film 111 is formed on the surface of the element formation layer 10L of the semiconductor substrate, an Al electrode film 20 is formed in the contact hole, and a silicon nitride film (SiNx) 21 as a protective film is formed on the surface. Has been.
　発明者の実験によれば、内部にポリシリコンが充填されたトレンチアイソレーションを備え、且つ窒化シリコン膜でパッシベーションしたデバイスにおいて、意図しない不都合な特性が生じる場合があることが判った。その上で素子構造と回路特性との関係を解析した結果、トレンチアイソレーションが寄生素子を構成することが明らかとなった。 According to the experiments by the inventors, it has been found that unintended and undesired characteristics may occur in a device having trench isolation filled with polysilicon and being passivated with a silicon nitride film. As a result of analyzing the relationship between the element structure and circuit characteristics, it became clear that trench isolation constitutes a parasitic element.
　本発明の目的は、トレンチアイソレーションによる寄生素子の構成を無くした半導体装置およびその構造を備えたＥＳＤ保護デバイスを提供することにある。 An object of the present invention is to provide a semiconductor device that eliminates the configuration of parasitic elements due to trench isolation, and an ESD protection device having the structure.
（１）本発明の半導体装置は、半導体基板の表面に、複数の素子を形成する素子形成層が設けられ、前記素子形成層の表面から半導体基板内部へ前記素子形成層より深い、素子分離領域が形成され、前記素子分離領域は、トレンチの内面に酸化Ｓｉ膜が形成され、内部にポリシリコンが充填されたトレンチアイソレーションであり、前記素子分離領域で分離された２つの素子は、前記素子形成層表面に前記半導体基板の型とは逆型の半導体層を備え、前記素子形成層の上面に、前記半導体基板の型とは逆の帯電特性（極性）をもつ、または帯電特性（極性）をもたない、保護膜が形成されていることを特徴とする。 (1) In the semiconductor device of the present invention, an element isolation layer is provided on the surface of the semiconductor substrate, the element formation layer forming a plurality of elements. The element isolation region is a trench isolation in which a Si oxide film is formed on the inner surface of a trench and polysilicon is filled therein, and two elements separated in the element isolation region are The surface of the formation layer is provided with a semiconductor layer opposite to the mold of the semiconductor substrate, and the upper surface of the element formation layer has a charge characteristic (polarity) opposite to that of the semiconductor substrate, or a charge characteristic (polarity). A protective film that does not have a characteristic is formed.
　トレンチの内面に酸化Ｓｉ膜（SiOx）が形成され、内部にポリシリコンが充填されたトレンチアイソレーションにおいては、このトレンチで分離された２つの素子が素子形成層表面に半導体基板の型とは逆型の半導体層を備える場合に、この２つの素子の半導体層とトレンチアイソレーションとによってMOSFET構造が構成される。すなわち、上記２つの素子の半導体層がドレインおよびソースとして作用し、トレンチの内部のポリシリコンがゲート電極として作用する。そして、トレンチ内部のポリシリコンが半導体基板とは同型の電位になると半導体基板にチャンネルが形成される。 In trench isolation in which a Si oxide film (SiOx) is formed on the inner surface of the trench and the inside is filled with polysilicon, the two elements separated by this trench are opposite to the type of the semiconductor substrate on the surface of the element formation layer. When a semiconductor layer of a type is provided, a MOSFET structure is constituted by the semiconductor layers of these two elements and trench isolation. That is, the semiconductor layers of the two elements function as a drain and a source, and the polysilicon inside the trench functions as a gate electrode. When the polysilicon in the trench has the same potential as the semiconductor substrate, a channel is formed in the semiconductor substrate.
　窒化シリコン膜は物性上、正に帯電するため、トレンチ内にポリシリコンが充填されていると、ポリシリコンを介して半導体基板にチャンネルが形成されるため、上記MOSFET構造が導通して回路内に不要な電流パスが形成される。その結果、リーク電流が発生する原因となる。 Since the silicon nitride film is positively charged due to its physical properties, if the trench is filled with polysilicon, a channel is formed in the semiconductor substrate through the polysilicon. An unnecessary current path is formed. As a result, a leak current is generated.
　本発明によれば、保護膜は素子形成層表面の半導体の型とは逆の帯電特性（極性）をもつ、または帯電特性（極性）をもたないので、トレンチの内部のポリシリコンに電位が掛からず、上記MOSFET構造におけるチャンネルが形成されることはなく、不要な通電経路が形成されない。 According to the present invention, since the protective film has a charging characteristic (polarity) opposite to that of the semiconductor type on the surface of the element forming layer or does not have a charging characteristic (polarity), a potential is applied to the polysilicon inside the trench. Therefore, the channel in the MOSFET structure is not formed, and an unnecessary energization path is not formed.
（２）例えば、前記２つの素子の一方はツェナーダイオードであり、他方は前記ツェナーダイオードに導通するダイオードである。 (2) For example, one of the two elements is a Zener diode, and the other is a diode conducting to the Zener diode.
（３）また、例えば前記２つの素子の一方は前記半導体基板と前記素子形成層のウェルとの接合層を利用する縦型構造のダイオードであり、他方は前記素子形成層に形成されたウェル内に構成された横型構造のダイオードである。 (3) Further, for example, one of the two elements is a diode having a vertical structure using a junction layer between the semiconductor substrate and the well of the element formation layer, and the other is in a well formed in the element formation layer. This is a horizontal structure diode.
（４）本発明のＥＳＤ保護デバイスは、上記（１）～（３）のいずれかに記載の半導体装置を備え、前記ツェナーダイオードに対し、前記ダイオードが直列に接続された構造である。 (4) An ESD protection device of the present invention includes the semiconductor device according to any one of (1) to (3), and has a structure in which the diode is connected in series to the Zener diode.
　本発明によれば、保護膜は半導体基板の型とは逆の帯電特性（極性）をもつ、または帯電特性（極性）をもたないので、トレンチの内部のポリシリコンに電位が掛からず、トレンチで分離された２つの素子が素子形成層表面に半導体基板の型とは逆型の半導体層を備える場合に、この２つの素子の半導体層とトレンチアイソレーションとによってMOSFET構造におけるチャンネルに相当する不要な通電経路が形成されない。 According to the present invention, since the protective film has a charging characteristic (polarity) opposite to that of the semiconductor substrate or does not have a charging characteristic (polarity), no potential is applied to the polysilicon inside the trench. When the two elements separated by (1) have a semiconductor layer opposite to the type of the semiconductor substrate on the surface of the element formation layer, the semiconductor layer of these two elements and the trench isolation eliminate the need for a channel in the MOSFET structure. Is not formed.
図１は実施形態１に係る半導体装置の要部断面図である。FIG. 1 is a cross-sectional view of a main part of the semiconductor device according to the first embodiment. 図２は、トレンチで分離された２つの素子の半導体層とトレンチアイソレーションとによって構成されるMOSFET構造を示す模式断面図である。FIG. 2 is a schematic cross-sectional view showing a MOSFET structure constituted by a semiconductor layer of two elements separated by a trench and trench isolation. 図３は半導体装置の再配線層の構造を示す概略断面図である。FIG. 3 is a schematic cross-sectional view showing the structure of the rewiring layer of the semiconductor device. 図４は、第２の実施形態に係る、半導体基板および素子形成層に構成したＥＳＤ保護回路の構造を示す図である。FIG. 4 is a diagram showing a structure of an ESD protection circuit configured in a semiconductor substrate and an element formation layer according to the second embodiment. 図５は、第２の実施形態に係るＥＳＤ保護デバイスの各層の平面図である。FIG. 5 is a plan view of each layer of the ESD protection device according to the second embodiment. 図６Ａは図４に示したＥＳＤ保護デバイスの回路図である。6A is a circuit diagram of the ESD protection device shown in FIG. 図６Ｂは従来構造により生じる不要な電流パスの例を示す図である。FIG. 6B is a diagram illustrating an example of an unnecessary current path generated by the conventional structure. 図７はＥＳＤ保護デバイスの電圧・電流特性を示す図である。FIG. 7 is a diagram showing voltage / current characteristics of the ESD protection device. 図８Ａは本実施形態に係るＥＳＤ保護デバイスの接続例を示す図である。FIG. 8A is a diagram showing a connection example of the ESD protection device according to the present embodiment. 図８Ｂは本実施形態に係るＥＳＤ保護デバイスの接続例を示す図である。FIG. 8B is a diagram showing a connection example of the ESD protection device according to the present embodiment. 図９は、窒化シリコン膜（SiNx）が形成された半導体装置の概略断面図である。FIG. 9 is a schematic cross-sectional view of a semiconductor device on which a silicon nitride film (SiNx) is formed. 図１０は、トレンチで分離された２つの素子の半導体層とトレンチアイソレーションとによって構成されるMOSFETにおいて、チャンネルが構成される様子を示す図である。FIG. 10 is a diagram illustrating a state in which a channel is configured in a MOSFET configured by a semiconductor layer of two elements separated by a trench and trench isolation.
《第１の実施形態》
　図１は本発明の実施形態に係る半導体装置の要部断面図である。この半導体装置は、ｐ＋のＳｉ半導体基板１０の表面に、複数の素子を形成する素子形成層１０Ｌが設けられ、素子形成層１０Ｌの表面から半導体基板１０内部へ素子形成層１０Ｌより深い複数の素子分離領域１１０が形成されている。これらの素子分離領域１１０は、トレンチの内面に酸化Ｓｉ膜（SiOx）が形成され、内部にポリシリコンが充填されたトレンチアイソレーションである。素子分離領域１１０で分離された２つの素子（素子分離領域１１０を挟む２つの素子）は、素子形成層１０Ｌの表面において、半導体基板１０の型（ｐ＋）とは逆型であるｎエピタキシャル層を備えている。 << First Embodiment >>
FIG. 1 is a cross-sectional view of a main part of a semiconductor device according to an embodiment of the present invention. In this semiconductor device, an element formation layer 10L for forming a plurality of elements is provided on the surface of a p + Si semiconductor substrate 10, and a plurality of elements deeper than the element formation layer 10L from the surface of the element formation layer 10L into the semiconductor substrate 10 are provided. An isolation region 110 is formed. These element isolation regions 110 are trench isolations in which a Si oxide film (SiOx) is formed on the inner surface of a trench and polysilicon is filled therein. Two elements separated by the element isolation region 110 (two elements sandwiching the element isolation region 110) are n epitaxial layers that are opposite to the type (p +) of the semiconductor substrate 10 on the surface of the element formation layer 10L. I have.
　素子形成層１０Ｌの上面には、帯電特性（極性）をもたない、SiOx膜および保護膜２２が形成されている。この保護膜２２はポリイミド系樹脂またはエポキシ系樹脂の膜である。 On the upper surface of the element forming layer 10L, a SiOx film and a protective film 22 having no charging characteristics (polarity) are formed. The protective film 22 is a polyimide resin or epoxy resin film.
　図１に示す半導体装置の製造工程は次のとおりである。 The manufacturing process of the semiconductor device shown in FIG. 1 is as follows.
（１）先ず、ｐ＋半導体基板１０にｎ型のエピタキシャル層を成長させる。 (1) First, an n-type epitaxial layer is grown on the p + semiconductor substrate 10.
（２）STI（Shallow Trench Isolation）法により、トレンチを形成する。具体的には、まず、ｐ＋半導体基板１０を熱酸化して、表面にSiOx膜を形成し、次いで、SiNx膜をCVDで形成する。次にフォトレジストを塗布・露光・現像してパターンを形成し、それをマスクにしてSiNx/SiOx/Siの順にエッチングし、トレンチを形成する。次いで、トレンチの内壁面にSiOx層１１０ＳをCVD法で形成した後に、ポリシリコン１１０ＰをCVD法で充填する。ポリシリコンは基板表面の全面に形成されるので、これをCMP法で削除する。この時、上記SiNx膜が研磨のストッパとして作用させる。その後、SiNx膜を除去する。このようにしてトレンチアイソレーションを形成する。 (2) A trench is formed by an STI (Shallow Trench Isolation) method. Specifically, first, the p + semiconductor substrate 10 is thermally oxidized to form a SiOx film on the surface, and then a SiNx film is formed by CVD. Next, a photoresist is applied, exposed, and developed to form a pattern, which is used as a mask to etch in the order of SiNx / SiOx / Si to form a trench. Next, after forming the SiOx layer 110S on the inner wall surface of the trench by the CVD method, the polysilicon 110P is filled by the CVD method. Since polysilicon is formed on the entire surface of the substrate, it is deleted by the CMP method. At this time, the SiNx film acts as a polishing stopper. Thereafter, the SiNx film is removed. In this way, trench isolation is formed.
（３）ｎ型エピタキシャル層の所定領域にｎ型のウェルおよびｐ型のウェルをイオン注入法または拡散法により形成する。 (3) An n-type well and a p-type well are formed in a predetermined region of the n-type epitaxial layer by an ion implantation method or a diffusion method.
（４）ｎ型エピタキシャル層の所定領域、ｎ型ウェルまたはｐ型ウェルの所定領域にイオン注入法または拡散法によりｎ＋領域またはｐ＋領域を形成する。 (4) An n + region or a p + region is formed by ion implantation or diffusion in a predetermined region of the n-type epitaxial layer, a predetermined region of the n-type well or the p-type well.
（５）素子形成層１０Ｌの表面にCVD法によりSiOx膜を成膜する。 (5) A SiOx film is formed on the surface of the element formation layer 10L by the CVD method.
（６）上記SiO2膜にコンタクトホールを開口し、続いてAl電極膜をスパッタリング法により形成する。 (6) A contact hole is opened in the SiO 2 film, and then an Al electrode film is formed by sputtering.
（７）上記Al電極膜を所定の配線パターンにパターンニングする。 (7) The Al electrode film is patterned into a predetermined wiring pattern.
（８）表面に保護膜２２をスピンコート法で塗布し、ベークする。 (8) The protective film 22 is applied to the surface by spin coating and baked.
（９）その後、複数の工程により、Ｃｕによる再配線層を形成する。（図１においては、保護膜２２が形成された状態での断面を示している。）
　なお、素子を形成した後に上記トレンチアイソレーションを形成してもよい。 (9) Thereafter, a rewiring layer made of Cu is formed by a plurality of steps. (In FIG. 1, the cross section in the state in which the protective film 22 was formed is shown.)
Note that the trench isolation may be formed after the element is formed.
　図２は、トレンチで分離された２つの素子の半導体層とトレンチアイソレーションとによって構成されるMOSFET構造を示す模式断面図である。ここで、ｎエピタキシャル層はトレンチで分離された２つの素子の半導体層である。ｐ＋基板１０を挟んで上記２つの半導体層を覆うようにSiOx層１１０Ｓおよびポリシリコン１１０Ｐが配置されている。この構造はMOSFET構造ということができる。すなわち、上記２つの素子の半導体層（ｎエピタキシャル層）がドレインおよびソースとして作用し、トレンチの内部のポリシリコン１１０Ｐがゲート電極として作用する。 FIG. 2 is a schematic cross-sectional view showing a MOSFET structure constituted by a semiconductor layer of two elements separated by a trench and trench isolation. Here, the n epitaxial layer is a semiconductor layer of two elements separated by a trench. A SiOx layer 110S and a polysilicon 110P are arranged so as to cover the two semiconductor layers with the p + substrate 10 interposed therebetween. This structure can be called a MOSFET structure. That is, the semiconductor layer (n epitaxial layer) of the two elements functions as a drain and a source, and the polysilicon 110P inside the trench functions as a gate electrode.
　ここで、先ず、保護膜としてSiNx膜２１を形成した場合の作用について、図１０を参照して説明する。SiNx膜２１はSiNxの物性により正に帯電する。これに伴い、導電体であるポリシリコン１１０Ｐも正に帯電される。この電荷はｐ＋半導体基板１０とは同型であるので、ｐ＋半導体基板１０にｎチャンネル（ｎ－ｃｈ）が形成される。この状態で、トレンチで分離された２つのｎエピタキシャル層１００－１００間が導通してしまう。 Here, first, the operation when the SiNx film 21 is formed as a protective film will be described with reference to FIG. The SiNx film 21 is positively charged due to the physical properties of SiNx. Along with this, the polysilicon 110P as a conductor is also positively charged. Since this charge is the same type as that of the p + semiconductor substrate 10, an n channel (n−ch) is formed in the p + semiconductor substrate 10. In this state, the two n epitaxial layers 100-100 separated by the trench are electrically connected.
　一方、本発明の実施形態によれば、SiOx膜１１１および保護膜２２はいずれも帯電特性（極性）をもたない絶縁層であるので、ポリシリコン１１０Ｐは帯電されず、ｐ＋基板１０にチャンネルは形成されない。そのため、不要な通電経路が形成されることはない。 On the other hand, according to the embodiment of the present invention, since the SiOx film 111 and the protective film 22 are both insulating layers having no charging characteristics (polarity), the polysilicon 110P is not charged, and the channel is not formed on the p + substrate 10. Not formed. Therefore, an unnecessary energization path is not formed.
　図３は半導体装置の再配線層の構造を示す概略断面図である。再配線層３０は半導体基板の素子形成層１０Ｌの表面に形成されている。保護膜２２には再配線のＣｕ膜パターン２４が形成されている。このＣｕ膜パターン２４の所定位置に外部接続電極２５が形成されている。最表面の保護膜２３には外部接続電極２５を露出させる開口が形成されている。このようにして再配線層３０が構成される。 FIG. 3 is a schematic cross-sectional view showing the structure of the rewiring layer of the semiconductor device. The rewiring layer 30 is formed on the surface of the element formation layer 10L of the semiconductor substrate. A Cu film pattern 24 for rewiring is formed on the protective film 22. External connection electrodes 25 are formed at predetermined positions of the Cu film pattern 24. An opening for exposing the external connection electrode 25 is formed in the protective film 23 on the outermost surface. In this way, the rewiring layer 30 is configured.
　本実施形態によれば、従来の一般的なパッシベーション膜としてのSiNx膜を形成せず、ポリイミド系樹脂またはエポキシ系樹脂を保護膜として形成することで、膜形成コストが低減できる。また、SiNx膜を形成することによるAl電極膜へのダメージがなくなる。そのため、SiOx膜およびAl電極膜が水分浸入を抑制するパッシベーション膜として作用する。そして、保護膜２２，２３は素子形成層１０Ｌおよび再配線層３０の機械的強度を確保する。 According to the present embodiment, the film formation cost can be reduced by forming a polyimide resin or an epoxy resin as a protective film without forming a SiNx film as a conventional general passivation film. Further, the Al electrode film is not damaged by forming the SiNx film. Therefore, the SiOx film and the Al electrode film function as a passivation film that suppresses moisture intrusion. The protective films 22 and 23 ensure the mechanical strength of the element formation layer 10L and the rewiring layer 30.
《第２の実施形態》
　第２の実施形態ではＥＳＤ保護デバイスに適用した例を示す。 << Second Embodiment >>
The second embodiment shows an example applied to an ESD protection device.
　図４は、半導体基板１０および素子形成層１０Ｌに構成したＥＳＤ保護回路の構造を示す図である。第１の実施形態で図１に示した半導体装置は既にＥＳＤ保護デバイスである。図４に示すダイオードＤ１～Ｄ４およびツェナーダイオードＤｚは図１においてＤ１～Ｄ４およびＤｚで示す領域に構成された素子である。また、電極Ｐ１，Ｐ２は図１においてAl電極膜２０のうち、Ｐ１，Ｐ２で示す電極に相当する。 FIG. 4 is a diagram showing the structure of an ESD protection circuit configured on the semiconductor substrate 10 and the element formation layer 10L. The semiconductor device shown in FIG. 1 in the first embodiment is already an ESD protection device. The diodes D1 to D4 and the Zener diode Dz shown in FIG. 4 are elements configured in regions indicated by D1 to D4 and Dz in FIG. The electrodes P1 and P2 correspond to the electrodes indicated by P1 and P2 in the Al electrode film 20 in FIG.
　図５は、本実施形態のＥＳＤ保護デバイスの各層の平面図である。半導体基板１０に形成された再配線層３０に含まれる樹脂層２２には、開口（コンタクトホール）が形成されている。電極Ｐ１，Ｐ２は、上記開口を経由してＣｕ膜パターン２４と導通する。Ｃｕ膜パターン２４上の外部接続電極２５は、保護膜２３に形成された開口に露出する。 FIG. 5 is a plan view of each layer of the ESD protection device of the present embodiment. An opening (contact hole) is formed in the resin layer 22 included in the rewiring layer 30 formed in the semiconductor substrate 10. The electrodes P1 and P2 are electrically connected to the Cu film pattern 24 through the opening. The external connection electrode 25 on the Cu film pattern 24 is exposed to the opening formed in the protective film 23.
　図６Ａは図４に示したＥＳＤ保護デバイスの回路図である。このＥＳＤ保護デバイスはポートＰ１－Ｐ２間にＥＳＤ電流を流すデバイスである。ポートＰ１にポートＰ２より正の高電圧（ツェナーダイオードＤｚのツェナー電圧を超えるサージ電圧）が印加されると、図中破線で示すように、ポートＰ１→ダイオードＤ１→ツェナーダイオードＤｚ→ダイオードＤ４→ポートＰ２の経路でサージ電流が流れる。逆に、ポートＰ２にポートＰ１より正の高電圧（ツェナーダイオードＤｚのツェナー電圧を超えるサージ電圧）が印加されると、ポートＰ２→ダイオードＤ３→ツェナーダイオードＤｚ→ダイオードＤ２→ポートＰ１の経路でサージ電流が流れる。 FIG. 6A is a circuit diagram of the ESD protection device shown in FIG. This ESD protection device is a device that allows an ESD current to flow between ports P1 and P2. When a positive high voltage (surge voltage exceeding the Zener voltage of the Zener diode Dz) is applied to the port P1 from the port P2, the port P1 → the diode D1 → the Zener diode Dz → the diode D4 → the port as shown by the broken line in the figure. A surge current flows through the path P2. Conversely, when a positive high voltage (surge voltage exceeding the Zener voltage of the Zener diode Dz) is applied to the port P2 from the port P1, a surge occurs along the path of the port P2, the diode D3, the Zener diode Dz, the diode D2, and the port P1. Current flows.
　ここで、比較例として、図１に示した構造で、保護膜２２に代えてSiNx膜を形成すると、ポートＰ１にポートＰ２より正の電圧が印加されると、ツェナーダイオードＤｚのツェナー電圧より低い電圧で、本来であればトレンチで分離されなければならない、ツェナーダイオードＤｚおよびダイオードＤ３のｎエピタキシャル層と、ダイオードＤ４のｎエピタキシャル層が導通する。ダイオードＤ４のｎエピタキシャル層はポートＰ２に接続されているため、図６Ｂに破線で示すような不要な電流パスが形成される。その結果、ポートＰ１－Ｐ２間にリーク電流が発生してしまう。これに対して、本実施形態によれば、不要な電流パスは形成されず、ポートＰ１－Ｐ２間にリーク電流が発生しない。 Here, as a comparative example, when a SiNx film is formed instead of the protective film 22 in the structure shown in FIG. 1, when a positive voltage is applied to the port P1 from the port P2, it is lower than the Zener voltage of the Zener diode Dz. With voltage, the n epitaxial layer of the Zener diode Dz and the diode D3, which would otherwise have to be separated by a trench, and the n epitaxial layer of the diode D4 conduct. Since the n epitaxial layer of the diode D4 is connected to the port P2, an unnecessary current path as shown by a broken line in FIG. 6B is formed. As a result, a leak current is generated between the ports P1 and P2. On the other hand, according to this embodiment, an unnecessary current path is not formed, and no leak current is generated between the ports P1 and P2.
　図７は上記ＥＳＤ保護デバイスの電圧・電流特性を示す図である。ここで特性曲線Ａは、図１に示した構造で、保護膜２２がポリイミド系樹脂またはエポキシ系樹脂である場合の特性を示している。特性曲線Ｂは上記保護膜がSiNx膜である場合の特性を示している。保護膜がSiNx膜である場合、印加電圧が±１Ｖを超えると通電していまい、不要な電流（リーク電流）が流れる。これに対し、本実施形態に係るＥＳＤ保護デバイスにおいては、±７Ｖに達してもリーク電流は流れず、±１０Ｖを超える時点で通電し、ＥＳＤ保護がなされる。 FIG. 7 is a diagram showing the voltage / current characteristics of the ESD protection device. Here, the characteristic curve A shows the characteristic when the protective film 22 is a polyimide resin or an epoxy resin in the structure shown in FIG. A characteristic curve B shows the characteristics when the protective film is a SiNx film. In the case where the protective film is a SiNx film, when the applied voltage exceeds ± 1 V, current is not supplied and an unnecessary current (leakage current) flows. On the other hand, in the ESD protection device according to the present embodiment, no leakage current flows even when ± 7 V is reached, and energization is performed at a time exceeding ± 10 V, and ESD protection is performed.
　図８Ａおよび図８Ｂは本実施形態に係るＥＳＤ保護デバイス１の接続例を示す図である。ＥＳＤ保護デバイス１は電子機器に搭載される。電子機器の例として、ノートＰＣ、タブレット型端末装置、携帯電話機、デジタルカメラ、携帯型音楽プレーヤなどが挙げられる。 8A and 8B are diagrams showing a connection example of the ESD protection device 1 according to the present embodiment. The ESD protection device 1 is mounted on an electronic device. Examples of electronic devices include notebook PCs, tablet terminal devices, mobile phones, digital cameras, and portable music players.
　図８Ａは、保護すべきＩＣ１０１とポートＰｏとの間の信号ラインに対してＥＳＤ保護デバイス１がシャントに接続された例を示す。ポートＰｏは例えばアンテナが接続されるポートである。 FIG. 8A shows an example in which the ESD protection device 1 is connected to the shunt with respect to the signal line between the IC 101 to be protected and the port Po. The port Po is a port to which an antenna is connected, for example.
　図８Ｂは、コネクタ１０２とＩＣ１０１とを接続する信号ラインと、ＧＮＤラインとの間に複数のＥＳＤ保護デバイス１を接続した例を示す。この例の信号ラインは、例えば、高速伝送線路（差動伝送線路）であって、複数の信号ラインそれぞれと、ＧＮＤラインとの間にＥＳＤ保護デバイス１が接続されている。 FIG. 8B shows an example in which a plurality of ESD protection devices 1 are connected between the signal line connecting the connector 102 and the IC 101 and the GND line. The signal line in this example is, for example, a high-speed transmission line (differential transmission line), and the ESD protection device 1 is connected between each of the plurality of signal lines and the GND line.
　以上に示した実施形態では、素子形成層１０Ｌの上面に、帯電特性（極性）をもたない保護膜を形成した例を示したが、素子形成層１０Ｌの上面に、半導体基板の型とは逆の帯電特性（極性）をもつ層を形成してもよい。 In the embodiment described above, an example in which a protective film having no charging characteristic (polarity) is formed on the upper surface of the element forming layer 10L is shown. However, what is the type of the semiconductor substrate on the upper surface of the element forming layer 10L? A layer having reverse charging characteristics (polarity) may be formed.
Ｄ１～Ｄ４…ダイオード
Ｄｚ…ツェナーダイオード
Ｐ１，Ｐ２…電極（ポート）
Ｐｏ…ポート
１…ＥＳＤ保護デバイス
１０…半導体基板
１０Ｌ…素子形成層
２０…Al電極膜
２１…SiNx膜
２２，２３…保護膜
２４…Ｃｕ膜パターン
２５…外部接続電極
３０…再配線層
１００…ｎエピタキシャル層
１０１…ＩＣ
１０２…コネクタ
１１０…素子分離領域
１１０Ｐ…ポリシリコン
１１０Ｓ…SiOx層
１１１…SiOx膜 D1 to D4 ... Diode Dz ... Zener diodes P1, P2 ... Electrodes (ports)
Po ... Port 1 ... ESD protection device 10 ... Semiconductor substrate 10L ... Element formation layer 20 ... Al electrode film 21 ... SiNx film 22, 23 ... Protection film 24 ... Cu film pattern 25 ... External connection electrode 30 ... Redistribution layer 100 ... n Epitaxial layer 101 ... IC
102 ... Connector 110 ... Element isolation region 110P ... Polysilicon 110S ... SiOx layer 111 ... SiOx film

Claims (4)

  1. 　半導体基板の表面に、複数の素子を形成する素子形成層が設けられ、前記素子形成層の表面から半導体基板内部へ前記素子形成層より深い、素子分離領域が形成された半導体装置において、
    　前記素子分離領域は、トレンチの内面に酸化Ｓｉ膜が形成され、内部にポリシリコンが充填されたトレンチアイソレーションであり、
    　前記素子分離領域で分離された２つの素子は、前記素子形成層表面に前記半導体基板の型とは逆型の半導体層を備え、
    　前記素子形成層の上面に、前記半導体基板の型とは逆の帯電特性をもつ、または帯電特性をもたない、保護膜が形成されていることを特徴とする半導体装置。     In a semiconductor device in which an element formation layer for forming a plurality of elements is provided on a surface of a semiconductor substrate, and an element isolation region is formed deeper than the element formation layer from the surface of the element formation layer to the inside of the semiconductor substrate.
    The element isolation region is a trench isolation in which a Si oxide film is formed on the inner surface of a trench and polysilicon is filled therein.
    The two elements separated in the element isolation region include a semiconductor layer opposite to the type of the semiconductor substrate on the surface of the element formation layer,
    A semiconductor device, wherein a protective film having a charging characteristic opposite to a mold of the semiconductor substrate or having no charging characteristic is formed on an upper surface of the element formation layer.
  2. 　前記２つの素子の一方は前記半導体基板と前記素子形成層のウェルとの接合層を利用する縦型構造のダイオードであり、他方は前記素子形成層に形成されたウェル内に構成された横型構造のダイオードである、請求項１に記載の半導体装置。 One of the two elements is a diode having a vertical structure using a junction layer between the semiconductor substrate and the well of the element formation layer, and the other is a lateral structure configured in a well formed in the element formation layer. The semiconductor device according to claim 1, which is a diode.
  3. 　前記２つの素子の一方はツェナーダイオードであり、他方は前記ツェナーダイオードに導通するダイオードである、請求項１または２に記載の半導体装置。 3. The semiconductor device according to claim 1, wherein one of the two elements is a Zener diode, and the other is a diode conducting to the Zener diode.
  4. 　請求項３に記載の半導体装置を備え、前記ツェナーダイオードに対し、前記ダイオードが直列に接続された、ＥＳＤ保護デバイス。 An ESD protection device comprising the semiconductor device according to claim 3, wherein the diode is connected in series to the Zener diode.
PCT/JP2014/054405 2013-05-07 2014-02-25 Semiconductor device and esd protection device WO2014181565A1 (en)

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JP2002176106A (en) * 2000-09-14 2002-06-21 Vishay Intertechnology Inc High-accuracy high-frequency capacitor formed on semiconductor board
JP2004221569A (en) * 2003-01-09 2004-08-05 Internatl Business Mach Corp <Ibm> Electrostatic discharge protective circuit of triple well semiconductor device
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