WO2014180404A1 - 时钟恢复方法和装置 - Google Patents
时钟恢复方法和装置 Download PDFInfo
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- WO2014180404A1 WO2014180404A1 PCT/CN2014/078655 CN2014078655W WO2014180404A1 WO 2014180404 A1 WO2014180404 A1 WO 2014180404A1 CN 2014078655 W CN2014078655 W CN 2014078655W WO 2014180404 A1 WO2014180404 A1 WO 2014180404A1
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- 238000000034 method Methods 0.000 title claims abstract description 54
- 238000011084 recovery Methods 0.000 title claims abstract description 38
- 230000010287 polarization Effects 0.000 claims abstract description 48
- 238000005070 sampling Methods 0.000 claims abstract description 36
- 238000004364 calculation method Methods 0.000 claims description 50
- 238000001514 detection method Methods 0.000 claims description 38
- 238000012217 deletion Methods 0.000 claims description 31
- 230000037430 deletion Effects 0.000 claims description 31
- 238000001914 filtration Methods 0.000 claims description 28
- 238000012545 processing Methods 0.000 claims description 17
- 230000003139 buffering effect Effects 0.000 claims description 4
- 230000009466 transformation Effects 0.000 claims 1
- 230000001360 synchronised effect Effects 0.000 abstract description 8
- 230000001427 coherent effect Effects 0.000 abstract description 3
- 238000004891 communication Methods 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 9
- 239000006185 dispersion Substances 0.000 description 6
- 230000006870 function Effects 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 238000004590 computer program Methods 0.000 description 1
- 230000006735 deficit Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000004321 preservation Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/26—Systems using multi-frequency codes
- H04L27/2601—Multicarrier modulation systems
- H04L27/2647—Arrangements specific to the receiver only
- H04L27/2649—Demodulators
- H04L27/26524—Fast Fourier transform [FFT] or discrete Fourier transform [DFT] demodulators in combination with other circuits for demodulation
- H04L27/26526—Fast Fourier transform [FFT] or discrete Fourier transform [DFT] demodulators in combination with other circuits for demodulation with inverse FFT [IFFT] or inverse DFT [IDFT] demodulators, e.g. standard single-carrier frequency-division multiple access [SC-FDMA] receiver or DFT spread orthogonal frequency division multiplexing [DFT-SOFDM]
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/60—Receivers
- H04B10/61—Coherent receivers
- H04B10/616—Details of the electronic signal processing in coherent optical receivers
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/60—Receivers
- H04B10/61—Coherent receivers
- H04B10/616—Details of the electronic signal processing in coherent optical receivers
- H04B10/6161—Compensation of chromatic dispersion
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/60—Receivers
- H04B10/61—Coherent receivers
- H04B10/616—Details of the electronic signal processing in coherent optical receivers
- H04B10/6162—Compensation of polarization related effects, e.g., PMD, PDL
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/60—Receivers
- H04B10/61—Coherent receivers
- H04B10/616—Details of the electronic signal processing in coherent optical receivers
- H04B10/6164—Estimation or correction of the frequency offset between the received optical signal and the optical local oscillator
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/60—Receivers
- H04B10/61—Coherent receivers
- H04B10/616—Details of the electronic signal processing in coherent optical receivers
- H04B10/6165—Estimation of the phase of the received optical signal, phase error estimation or phase error correction
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/60—Receivers
- H04B10/61—Coherent receivers
- H04B10/616—Details of the electronic signal processing in coherent optical receivers
- H04B10/6166—Polarisation demultiplexing, tracking or alignment of orthogonal polarisation components
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L5/00—Arrangements affording multiple use of the transmission path
- H04L5/02—Channels characterised by the type of signal
- H04L5/04—Channels characterised by the type of signal the signals being represented by different amplitudes or polarities, e.g. quadriplex
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
- H04L7/0033—Correction by delay
- H04L7/0037—Delay of clock signal
Definitions
- the present invention relates to the field of clock recovery technologies, and in particular, to a clock recovery method and apparatus.
- the sample clocks of the transmitter and receiver in the communication system are not completely synchronized. In order to correctly obtain the transmitted signal at the receiving end, it is necessary to solve the problem that the transmitter and receiver clocks are not synchronized.
- the clock recovery is to solve the transmitter and the receiver. The problem that the clock is not synchronized.
- Coherent digital receivers are commonly used in modern communication digital receivers.
- the coherent digital receiver can compensate for transmission impairments in the received signal in the digital domain, such as chromatic dispersion compensation, polarization mode dispersion compensation, clock recovery, frequency offset compensation, and phase. Compensation, etc.
- the clock recovery module can correctly extract the sample clock frequency and the sample phase from the digital signal and compensate the signal for error. Thereby, the transmitted signal can be correctly demodulated.
- the embodiment of the invention provides a clock recovery method and device, which solves the problem that the sample clocks of the transmitter and the receiver are not synchronized.
- a clock recovery method includes:
- a second phase adjustment is performed based on the residual phase error compensation value.
- the steps of calculating the clock sample error, the signal phase error compensation value, and the residual phase error compensation value according to the polarization demultiplexing and the equalized data include:
- T(m) angle (e(m)) / ⁇ ⁇
- ⁇ is the phase discrimination value
- ⁇ represents the phase angle operation
- the phase discrimination value is used to calculate the filtering process of the clock sample error, Clock sampling error
- the filtering process of calculating the residual phase error compensation value is performed on the phase discrimination value to obtain the residual phase error compensation value.
- the step of adjusting the sample clock according to the clock sample error comprises:
- the sampling frequency of the analog-to-digital converter ADC is changed according to the clock sampling error.
- the step of performing the first phase adjustment according to the signal phase error compensation value includes:
- the first phase adjustment is performed using the following expression: ⁇ ⁇ ) ⁇ (cos ⁇ ⁇ ) +J -sm ⁇ ⁇ )) l ⁇ n ⁇ x f (n) . (cos d .
- the step of performing the second phase adjustment according to the residual phase error compensation value includes: According to the residual phase error compensation value, the second phase adjustment is performed using the following expression: ⁇ ⁇ ) ⁇ (cos ⁇ ⁇ ) +J -sm ⁇ ⁇ )) l ⁇ n ⁇ x f (n) . (cos d .
- the method before the step of performing the first phase adjustment according to the signal phase error compensation value, the method further includes:
- the digital signal is sampled according to the changed ADC sampling frequency
- the data processed by the front end data signal is converted into data of the frequency domain signal.
- the method before the step of performing the second phase adjustment according to the residual phase error compensation value, the method further includes:
- the digital signal data after the first phase adjustment is performed is subjected to polarization separation, and the signal is equalized.
- the method further includes:
- the frequency domain data obtained after the second phase adjustment is converted into time domain data for subsequent buffering.
- the method further includes:
- the phase-detection value is calculated to interpolate or delete the value, or the filtering process of the instruction is maintained, to obtain an interpolation or a value, or to hold the instruction.
- the method further includes:
- the embodiment of the invention further provides a clock recovery device, comprising: a clock error calculation module, an analog-to-digital converter ADC module, a first sample phase adjustment module, and a second sample phase adjustment module, wherein
- the clock error calculation module is configured to: calculate a clock sample error, a signal phase error compensation value, and a residual phase error compensation value according to the polarization demultiplexing and the equalized data;
- the ADC module is configured to: adjust a sample clock according to the clock sample error; the first sample phase adjustment module is configured to: perform a first phase adjustment according to the signal phase error compensation value;
- the second sample phase adjustment module is configured to: perform a second phase adjustment according to the residual phase error compensation value.
- the clock error calculation module includes:
- a clock error phase-detecting unit configured to calculate a phase-detection error according to the following expression:
- e(m) ⁇ conj(x e - OMt (/)) ⁇ ⁇ - 0 ⁇ (i + N/2) + conj(y e - mt (/)) f (i + N/ 2)
- i the frequency domain index value
- conj the conjugate operation
- N the FT point of the Fourier transform module
- m The index of the phase discrimination result
- ) is the phase error, where N is a positive integer;
- T(m) angle (e(m) ) / ⁇ ⁇
- ⁇ is the phase-detection value
- ⁇ represents the phase angle operation
- the first clock error calculation unit is configured to calculate the phase-detection value Filtering the clock sample error to obtain the clock sample error
- a second clock error calculation unit configured to perform a filtering process for calculating the signal phase error compensation value for the phase discrimination value to obtain the signal phase error compensation value
- a third clock error calculation unit configured to calculate the residual phase for the phase-detection value
- the filtering process of the error compensation value obtains the residual phase error compensation value.
- the clock error calculation module further includes:
- a fourth clock error calculation unit configured to calculate or interpolate the value of the phase-detection value, or to maintain a filtering process of the instruction, to obtain an interpolation or a value, or to hold the instruction.
- the device further includes:
- the buffer BUFFER module is configured to buffer the received time domain data, and perform corresponding interpolation or deletion, or hold operation, on the received time domain data according to the interpolation or the deletion or hold instruction.
- the device further includes:
- the polarization demultiplexing and equalization module is configured to perform polarization separation of the digital signal data after the first phase adjustment is performed, and equalize the signal.
- Embodiments of the present invention provide a clock recovery method and apparatus, and according to polarization demultiplexing and equalized data, calculate a clock sample error, a signal phase error compensation value, and a residual phase error compensation value, according to the clock sample error Adjusting the sample clock, performing the first phase adjustment according to the signal phase error compensation value, and performing the second phase adjustment according to the residual phase error compensation value, realizing a three-stage error compensation mechanism for the clock, and solving the transmission The problem that the sampling clock of the machine and the receiver are not synchronized.
- FIG. 1 is a schematic structural diagram of a clock recovery apparatus according to Embodiment 1 of the present invention
- FIG. 2 is a schematic structural diagram of a clock error calculation module of FIG.
- FIG. 3 is a schematic diagram showing the implementation principle of the first sample phase adjustment module and the second sample phase adjustment module in the first embodiment of the present invention
- FIG. 4 is a schematic diagram showing the principle of the frequency adjustment of the ADC module in the first embodiment of the present invention
- FIG. 5 is a diagram showing sample hold and sample interpolation using the BUFFER module in the first embodiment of the present invention. And a sample deletion operation diagram;
- FIG. 6 is a flowchart of a clock recovery method according to Embodiment 2 of the present invention.
- Embodiments of the present invention provide a clock recovery method and apparatus. Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that, in the case of no conflict, the features in the embodiments and the embodiments of the present application may be arbitrarily combined with each other.
- a clock recovery device has a structure as shown in FIG. 1 , including: an analog-to-digital converter (ADC) module 11 , a front-end digital signal processing module 12 , and a Fourier transform module (FT ) 13 .
- the ADC module 11 converts the received analog signal into a digital signal, and sends the digital signal to the front end digital signal processing module, and adjusts the sample clock according to the clock sample error calculated by the clock error calculation module;
- the front-end digital signal processing module performs digital signal processing on the front end of the received digital signal, including delay adjustment, de-DC and other digital signal processing.
- the module then sends the processed signal to the subsequent IFT module;
- the IFT module 18 changes the received time domain signal to the frequency domain.
- the module then sends the processed frequency domain signal to the subsequent first sample phase adjustment module.
- the clock error calculation module 16 is configured to calculate a clock sample error, a signal phase error compensation value, and a residual phase error compensation value according to the polarization demultiplexing and the equalized data, and calculate the calculated clock error and signal phase error.
- the compensation value and the residual phase error compensation value are transmitted to the first sample phase adjustment module 14, the second sample phase adjustment module 17 and the ADC module 11, and the sample hold, the sample interpolation and the sample value deletion command are transmitted to the BUFFER. Module.
- the first sample phase adjustment module 14 is configured to perform a first phase adjustment according to the signal phase error compensation value, and adjust a phase of the received signal. Then the module sends the processed signal Subsequent polarization demultiplexing and equalization modules;
- the polarization demultiplexing and equalization module 15 is configured to perform polarization separation of the digital signal data after the first phase adjustment is performed, and equalize the signal. Correspondingly, the polarization state of the received digital signal is separated, and the signal is equalized to eliminate the colored noise of the signal (including residual chromatic dispersion and polarization mode dispersion). The module then sends the processed signal to a subsequent second sample phase adjustment module and a clock error calculation module;
- the second sample phase adjustment module 17 is arranged to perform a second phase adjustment based on the residual phase error compensation value.
- the clock error calculation module 16 is the core module of the entire device. Since chromatic dispersion, polarization mode dispersion, and other noises have a large impact on error calculations, this module is placed after the polarization demultiplexing and equalization modules, thus eliminating the effect of these noises on the error calculation.
- the clock error calculation module 16 calculates three levels of clock errors.
- the module passes a relatively fixed clock error compensation value to the ADC module, changing the sampling frequency of the ADC module, so that the sampling clock of the ADC is as close as possible to the sampling clock of the DAC. .
- the clock error appears as a phase change in the data because the clock error calculation module and the first sample phase adjustment module are a feedback loop, so the calculated phase error is ⁇ before the data of several clocks, There is still a certain deviation from the current phase error, so the first sample phase adjustment module only processes the phase error that changes slowly.
- the clock error calculation module and the second sample phase adjustment module are a feedforward loop, which can process the phase error of the current data in real time. Therefore, the remaining phase of the first sample phase adjustment module is processed by the second sample phase adjustment module. error. Through such a three-stage error compensation mechanism, various types of clock errors can be effectively compensated.
- the clock error calculation module simultaneously calculates the interpolation or deletion command and passes this command to The buffer (BUFFER) after the IFT is interpolated or deleted.
- the second sample phase adjustment module 17 adjusts the phase of the sample signal according to the residual phase error compensation value calculated by the clock error calculation module. Then, the module sends the processed signal to the subsequent IIFT module;
- the IIFT module 18 receives data from the second sample phase adjustment module and converts the frequency domain data Change to time domain data. The module then sends the processed signal to the subsequent buffer module.
- the BUFFER module 19 is configured to buffer the received time domain data (receive data from the IFT module), perform corresponding operations on the received time domain data according to the interpolation or deletion command transmitted by the clock error calculation module (eg, Perform interpolation or deletion operations). The module then sends the processed signal to subsequent digital signal processing modules.
- the structure of the clock error calculation module is as shown in FIG. 2, including:
- the clock error phase detecting unit 161 is configured to calculate the phase error according to the following expression:
- e(m) ⁇ conj(x e - OMt (/)) ⁇ ⁇ - 0 ⁇ (i + N/2) + conj(y e - mt (/)) f (i + N/ 2)
- i the frequency domain index value
- conj the conjugate operation
- N the FT point of the Fourier transform module
- m The index of the phase result, ) is the phase discrimination error, where N is a positive integer;
- T(m) angle (e(m) ) / ⁇ ⁇
- ⁇ is the phase-detection value
- ⁇ represents the phase angle operation
- the first clock error calculation unit 162 is configured to calculate the phase-detection value Decoding the clock sample error to obtain the clock sample error
- a second clock error calculation unit 163 configured to perform a filtering process for calculating the signal phase error compensation value for the phase-detection value to obtain the signal phase error compensation value
- a third clock error calculation unit 164 configured to perform a filtering process for calculating the residual phase error compensation value for the phase-detection value to obtain the residual phase error compensation value
- the fourth clock error calculating unit 165 is configured to calculate the interpolation or deletion of the phase-detection value, or to maintain the instruction filtering process, to obtain an interpolation or a value, or to hold the instruction.
- the embodiment of the invention also provides a method for clock recovery.
- the parameters for clock recovery are calculated based on the data after polarization demultiplexing and equalization.
- the ADC module, the first sample phase adjustment module, the second sample phase adjustment module, and the buffer module perform the sample clock and the sample phase according to the calculated clock error parameter. Adjustments and sample hold, sample deletion, and sample interpolation.
- the ADC module 11 calculates a sample clock error value based on the clock error calculation module Adjusting, and converting the analog signal into a digital signal, and transmitting it to the subsequent front-end digital signal processing module; performing fixed delay compensation, DC offset compensation and other digital signal processing in the front-end digital signal processing module, and then transmitting the signal to
- the IFT module changes the time domain data into the frequency domain, and then transfers the data to the first sample phase adjustment module 14; the first sample phase adjustment module performs data on the data according to the signal phase error compensation value calculated by the clock error calculation module.
- phase adjustment and then pass the phase-adjusted data to the polarization demultiplexing and equalization module; the polarization demultiplexing and equalization module separates and equalizes the two polarization states, and then passes the processed data to the clock error calculation The module and the second sample phase adjustment module 17; the clock error calculation module calculates the clock sample error, the signal phase error compensation value, the residual phase error compensation value, and the sample hold according to the data after the polarization demultiplexing and the equalization module.
- Point interpolation and sample deletion commands are passed separately
- the second sample phase adjustment module calculates the residual phase error compensation value according to the clock error calculation module, and the polarization solution
- the multiplexed and equalized data is further phase adjusted, and then the data is passed to the IIFT module;
- the IIFT module converts the frequency domain data into time domain data and passes the data to the buffer;
- the buffer calculates the module based on the clock error
- the instructions are to perform sample preservation, sample interpolation or sample deletion, and then pass the data to subsequent modules of the receiver.
- the clock error calculation module calculates the clock error based on the polarization demultiplexing and the data after the equalization.
- the clock error phase discrimination module calculates the phase error:
- phase-detection value is output as the phase-detection result, where, for the phase-detection value, angle represents the phase angle operation.
- phase detection result is sent to the second clock error calculation unit, and the signal phase error compensation value suitable for the first sample phase adjustment module is calculated through the filtering process; the clock error suitable for the relatively fast change, the filter coefficient It can be set according to this condition.
- phase detection result is sent to the third clock error calculation unit, and the residual phase error compensation value suitable for the second sample phase adjustment module is calculated through the filtering process; the clock error suitable for the very fast change, the filter coefficient It can be set according to this condition.
- the phase detection result is sent to the fourth clock error calculation unit, and the interpolation or deletion value of the BUFFER module is calculated by the filtering process, or the instruction is held.
- the interpolation/deletion instruction indicates that the difference in the data sample caused by the sample clock error has reached a sample point
- the hold instruction indicates that the difference in data sample points caused by the sample clock error is within one sample point.
- FIG. 3 is a schematic diagram of a phase adjustment principle of a first sample phase adjustment module and a second sample phase adjustment module according to an embodiment of the present invention, and the generation of cos and sin may be performed by using a look-up table method, or may be other Way to achieve.
- the first sample phase adjustment module and the second sample phase adjustment module are implemented in the same manner, and the phase adjustment value is adjusted according to the phase adjustment value sent by the clock error calculation module, and correspondingly, the following expression can be used for adjustment:
- n is the frequency domain index
- N is the FT point number
- u is the phase difference to be adjusted (the result of the clock error filtering)
- XW ' W is the frequency domain data before the phase adjustment, which is the frequency domain data after the phase adjustment, wherein , ⁇ is a positive integer.
- FIG. 4 is a schematic diagram of an implementation principle of a sampling frequency adjustment of an ADC module according to an embodiment of the present invention.
- the sample clock of the ADC module 11 is also based on the sample clock sent from the clock error calculation module 16.
- the error value is used to adjust the sample clock.
- the sample clock error module is in the state of deletion for a long time, indicating
- the sample clock of the ADC module is too fast and needs to be reduced. Conversely, the interpolated state for a long time indicates that the sampling clock of the ADC module is too slow and the clock needs to be increased.
- FIG. 5 is a schematic diagram of the sample hold, the sample interpolation, and the sample deletion operation using the BUFFER module according to the embodiment of the invention.
- N is the number of FT points
- L is the number of redundant data points
- D is the number of samples that need to be interpolated or deleted according to the error calculation module.
- the BUFFER module performs sample hold, sample interpolation or sample deletion according to the sample hold, sample interpolation or sample cut command calculated by the clock error calculation module.
- the embodiment of the present invention provides a clock recovery method.
- the clock recovery device in the first embodiment of the present invention, the recovery process of the sample clock is as shown in FIG. 6, and includes:
- Step 601 Calculate a clock sample error, a signal phase error compensation value, a residual phase error compensation value, and an interpolation or deletion value or a hold command according to the polarization demultiplexing and the equalized data;
- This step includes:
- e(m) ⁇ conj(x e - OMt (/)) ⁇ ⁇ - 0 ⁇ (i + N/ 2) + conj(y e - mt (/)) f (i + N/ 2) where ⁇ 7—°"' and the data representing the polarization states of x,y after polarization demultiplexing and equalization, i is the frequency domain index value, conj is the conjugate operation, N is the FT point number, and the index of the m phase discrimination result is ) is the phase error, where N is a positive integer;
- T(m) angle (e(m) ) / ⁇ ⁇ where ⁇ ) is the phase-detection value and ⁇ is the phase angle operation;
- Step 602 Adjust a sample clock according to the clock sample error
- the sampling frequency of the ADC is changed according to the clock sampling error.
- the digital signal is first sampled according to the changed ADC sample frequency, and then the digital signal processed by the digital signal is processed by the front end, and then the data is processed after the front end data signal is processed.
- Data for the frequency domain signal is sent to the first sample phase adjustment module.
- Step 603 Perform a first phase adjustment according to the signal phase error compensation value.
- this step according to the signal phase error compensation value, use the following expression to perform the first phase adjustment:
- the digital signal data after the first phase adjustment is separated into polarization states, and the signal is equalized, and the equalized data can be sent to the second sample phase adjustment module for the second phase adjustment.
- Step 604 Perform a second phase adjustment according to the residual phase error compensation value.
- Step 604 according to the residual phase error compensation value, perform the second phase adjustment by using the following expression:
- the frequency domain data obtained after the second phase adjustment can then be converted by the BUFFER module into time domain data for subsequent buffering.
- Step 605 Cache the received time domain data, and perform corresponding interpolation or deletion on the received time domain data according to the interpolation or deletion or hold instruction, or keep the operation;
- the interpolation or deletion value calculated by the BUFFER module according to the clock error calculation module, or the hold instruction, the corresponding interpolation or deletion, or the hold operation is calculated by the BUFFER module according to the clock error calculation module, or the hold instruction, the corresponding interpolation or deletion, or the hold operation.
- Embodiments of the present invention provide a clock recovery method and apparatus for calculating a clock sample error, a signal phase error compensation value, and a residual phase error compensation value according to polarization demultiplexing and equalized data, according to the clock
- the error adjustment sample clock performs the first phase adjustment according to the signal phase error compensation value, and performs the second phase adjustment according to the residual phase error compensation value, thereby realizing a three-stage error compensation mechanism for the clock, and solving The problem that the sample clocks of the transmitter and receiver are not synchronized.
- all or part of the steps of the foregoing embodiments may also be implemented by using an integrated circuit. These steps may be separately fabricated into individual integrated circuit modules, or multiple modules or steps may be fabricated into a single integrated circuit module. achieve.
- the invention is not limited to any particular combination of hardware and software.
- the devices/function modules/functional units in the above embodiments may be implemented by a general-purpose computing device, which may be centralized on a single computing device or distributed over a network of multiple computing devices.
- each device/function module/functional unit in the above embodiment is implemented in the form of a software function module and sold or used as a stand-alone product, it can be stored in a computer readable storage medium.
- the above mentioned computer readable storage medium may be a read only memory, a magnetic disk or an optical disk or the like.
- the embodiment of the invention implements a three-level error compensation mechanism for the clock, and solves the problem that the sample clocks of the transmitter and the receiver are not synchronized. Therefore, it has strong industrial applicability.
Abstract
Description
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Priority Applications (3)
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EP14795343.4A EP3046300B1 (en) | 2013-10-15 | 2014-05-28 | Clock recovery method and device |
JP2016547210A JP6194122B2 (ja) | 2013-10-15 | 2014-05-28 | クロック回復方法及び装置 |
US15/029,249 US9948448B2 (en) | 2013-10-15 | 2014-05-28 | Clock recovery method and device |
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CN201310482054.1 | 2013-10-15 | ||
CN201310482054.1A CN104579621B (zh) | 2013-10-15 | 2013-10-15 | 时钟恢复方法和装置 |
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EP (1) | EP3046300B1 (zh) |
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CN114554525A (zh) * | 2022-02-22 | 2022-05-27 | 上海星思半导体有限责任公司 | 信号处理方法、装置、电子设备、存储介质及程序产品 |
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CN108141282B (zh) * | 2015-10-26 | 2019-12-13 | 华为技术有限公司 | 一种时钟性能监控系统、方法及装置 |
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