WO2014180091A1 - 像素结构及其驱动方法、显示装置 - Google Patents

像素结构及其驱动方法、显示装置 Download PDF

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Publication number
WO2014180091A1
WO2014180091A1 PCT/CN2013/085284 CN2013085284W WO2014180091A1 WO 2014180091 A1 WO2014180091 A1 WO 2014180091A1 CN 2013085284 W CN2013085284 W CN 2013085284W WO 2014180091 A1 WO2014180091 A1 WO 2014180091A1
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Prior art keywords
line
signal line
additional
driving signal
pixel
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PCT/CN2013/085284
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English (en)
French (fr)
Inventor
张明
郝昭慧
尹雄宣
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Publication of WO2014180091A1 publication Critical patent/WO2014180091A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/13606—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit having means for reducing parasitic capacitance
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136259—Repairing; Defects
    • G02F1/136272—Auxiliary lines
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0219—Reducing feedthrough effects in active matrix panels, i.e. voltage changes on the scan electrode influencing the pixel voltage due to capacitive coupling

Definitions

  • Embodiments of the present invention relate to a pixel structure, a driving method thereof, and a display device. Background technique
  • TFT-LCDs Thin film transistor liquid crystal displays
  • a typical TFT-LCD typically has a plurality of pixel structures arranged in a matrix.
  • a typical unit pixel structure as shown in Fig. 1, includes a horizontally intersecting gate line 11 and a data line 12, and a thin film transistor (TFT) is disposed at a position where the gate line 11 and the data line 12 intersect.
  • the gate of the TFT is a part of the gate line 11, the source 1312 is connected to the data line 12, and the drain 1311 is connected to the pixel electrode 132 to maintain the voltage of the pixel electrode 132.
  • the pixel structure may also be provided with a common electrode line 10 parallel to the gate line 11, and the pixel electrode 132 has a storage capacitor between a common electrode (not shown) electrically connected to the common electrode line 10.
  • the pixel structure can achieve effective control of the liquid crystal display by using a common electrode voltage (Vcom) to maintain the constant and line flip driving mode.
  • Vcom common electrode voltage
  • Embodiments of the present invention provide a pixel structure, a driving method thereof, and a display device, which can avoid the influence of a hopping voltage on a pixel electrode voltage and improve the display effect of the display device.
  • An aspect of the present invention provides a pixel structure including: a common electrode line, a gate line, a data line, an additional driving signal line, at least one pixel unit defined by horizontally intersecting gate lines and data lines,
  • the pixel unit includes a thin film transistor and a pixel electrode; the additional driving signal line is formed
  • An additional capacitor for compensating for parasitic capacitance within the pixel structure; an input signal of the additional drive signal line is opposite to an input signal of the gate line.
  • a display device including the pixel structure as described above is provided.
  • a pixel structure driving method is provided.
  • the pixel structure includes: a common electrode line, a gate line, a data line, an additional driving signal line, and a gate line and a data line intersected by a horizontally and vertically intersecting At least one pixel unit, the pixel unit includes a thin film transistor and a pixel electrode; the method includes: turning on the thin film transistor row by row through the gate line input gate line signal; inputting a data line signal through the data line, When the thin film transistor is turned on, power is supplied to the pixel electrode through a drain of the thin film transistor; an additional driving signal is input through the additional driving signal line, and the additional driving signal is opposite in phase to the gate line signal.
  • the additional drive signal line forms an additional capacitance that compensates for parasitic capacitance within the pixel structure.
  • FIG. 1 is a schematic diagram of a conventional pixel structure
  • FIG. 2 is a schematic structural diagram of a pixel according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of another pixel according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of another pixel according to an embodiment of the present invention.
  • FIG. 5 is a waveform diagram of a driving signal according to an embodiment of the present invention.
  • FIG. 6 is a waveform diagram of another driving signal according to an embodiment of the present invention.
  • FIG. 7 is a waveform diagram of another driving signal according to an embodiment of the present invention.
  • FIG. 8 is a waveform diagram of still another driving signal according to an embodiment of the present invention.
  • FIG. 9 is a schematic structural diagram of another pixel according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic structural diagram of another pixel according to an embodiment of the present disclosure.
  • FIG. 11 is a schematic structural diagram of another pixel according to an embodiment of the present disclosure.
  • FIG. 12 is a schematic structural diagram of another pixel according to an embodiment of the present disclosure.
  • FIG. 13 is a schematic diagram of still another pixel structure according to an embodiment of the present disclosure.
  • FIG. 14 is a schematic structural diagram of a circuit area according to an embodiment of the present invention
  • FIG. 15 is a schematic structural diagram of a pixel according to an embodiment of the present invention. detailed description
  • An embodiment of the present invention provides an array substrate having a pixel structure.
  • the pixel structure includes: a common electrode line 10, a gate line 11 and a data line 12, which are crossed by a horizontal and vertical
  • the gate line 11 and the data line 12 define at least one pixel unit 13.
  • the pixel unit 13 further includes a TFT 131 and a pixel electrode 132. These pixel cells are arranged in a certain array (for example, a matrix).
  • the pixel structure of this embodiment may further include an additional driving signal line 14.
  • the additional drive signal line 14 can provide an additional capacitance for compensating for the parasitic capacitance (Cgd) charge formed between the gate and drain of the TFT in the pixel structure.
  • the input signal (additional driving signal) on the additional driving signal line 14 and the input signal (gate line signal) on the gate line 11 may be the same timing as each other, but the phases are opposite.
  • the additional capacitance may include: a first capacitor 21 formed by the additional driving signal line 14 and the drain 1311 of the TFT 131, or a second capacitor 22 formed by the additional driving signal line 14 and the pixel electrode 132.
  • the additional driving signal line 14 parallel to the gate line 11 may overlap with the drain 1311 of the TFT 131 in a direction perpendicular to the plane of the paper to form the first capacitor 21.
  • the pixel structure provided by the embodiment of the present invention may further include the additional driving signal line 14 parallel to the data line 12 and the pixel electrode 132 overlapping in the direction perpendicular to the paper surface to form the second capacitor 22, as shown in FIG. 3 or FIG. .
  • the pixel structure provided by the embodiment of the present invention may further have a first capacitor 21 and a second capacitor 22.
  • the pixel structure having the first capacitor 21 and/or the second capacitor 22 is also exemplified.
  • Other pixel structure designs capable of forming the first capacitor 21 and/or the second capacitor 22 are not listed here, but All should be included in the scope of protection of the present invention.
  • the additional driving signal line 14 and the drain 1311 of the TFT 131 form a first capacitor 21 or a charge of the second capacitor 22 formed by the additional driving signal line 14 and the pixel electrode 132, and the charge variation of the parasitic capacitance can be performed.
  • Compensation that is, the additional drive signal line 14 is implemented to compensate for the charge change of the parasitic capacitance. This compensation can avoid the influence of the jump voltage on the pixel electrode voltage, thereby improving the display effect of the display device.
  • Embodiments of the present invention provide a pixel structure by adding an additional driving signal line parallel to a gate line and/or a data line in a pixel structure, the additional driving signal line forming a capacitance with a drain or a pixel electrode of the TFT, and
  • the input signal on the additional driving signal line is opposite to the phase of the input signal on the gate line, so that the charge of the capacitor formed by the driving signal line and the drain or pixel electrode of the TFT can compensate for the charge variation of the parasitic capacitance, avoiding The influence of the jump voltage on the pixel electrode voltage is improved, thereby improving the display effect of the display device.
  • the ADSDS technology forms a multi-dimensional electric field by a parallel electric field generated by the edge of the pixel electrode in the same plane and a longitudinal electric field generated between the pixel electrode layer and the common electrode layer, so that all the aligned liquid crystal molecules directly between the pixel electrodes in the liquid crystal cell and above the electrodes can be generated.
  • the rotation conversion increases the working efficiency of the plane-oriented liquid crystal and increases the light transmission efficiency.
  • a liquid crystal display device includes an array substrate and a counter substrate.
  • the array substrate and the opposite substrate face each other and form a liquid crystal cell by, for example, a sealant, and the liquid crystal cell is filled with a liquid crystal material.
  • the opposite substrate is, for example, a color filter substrate.
  • the pixel electrode of each pixel unit of the array substrate is used to apply an electric field to control the degree of rotation of the liquid crystal material to perform a display operation.
  • the liquid crystal display device may further include a backlight that provides backlighting for the array substrate.
  • Each pixel of the array substrate of the ADSDS mode includes a first electrode (not shown in FIG. 2) connected to the common electrode line 10 and a second electrode connected to the drain of the TFT.
  • the second electrode may be a pixel electrode 132 connected to the drain 1311 of the TFT through the via hole 16.
  • the additional driving signal line 14 may be disposed in the same layer as the pixel electrode 132 but not connected to each other, and the materials of the two may be the same; if the source electrode and the drain metal layer where the pixel electrode 132 and the drain are located at different levels, the additional driving signal line 14 That is, the first capacitor 21 can be formed with the drain 1311 of the TFT 131.
  • an additional driving signal line 14 can be produced without adding a new manufacturing process, thereby reducing the production difficulty of the product.
  • the embodiment of the present invention is not limited to the liquid crystal display device of the ADSDS mode. In other liquid crystal display devices of the same structure, such an additional driving signal line design can also be adopted, which is not enumerated here.
  • the waveform of the input signal of the additional driving signal line 14 and the waveform of the input signal of the gate line 11 can be as shown in FIG. Additional drive signal line 14
  • the waveform of the input signal Va is the same as the waveform period (timing) of the gate line 11 input signal Vg, but the transition direction is opposite (ie, inverted from each other).
  • the additional driving signal line 14 inputs the low voltage signal Val accordingly; when the gate line 11 inputs the low voltage signal Vgl, the additional driving signal line 14 inputs the high voltage signal Vah accordingly.
  • the input signal on the additional driving signal line 14 can also be used to compensate the voltage of the pixel electrode 132 such that the voltage of the pixel electrode 132 and the voltage of the input signal on the common electrode line 10 (ie, The absolute value of the difference between the voltages applied to the common electrode is within a predetermined range.
  • the conventional charging process of the pixel is as shown in the upper part of Fig. 6, for example.
  • the TFT switch connected to the gate line 11 is turned on, whereby the current on the data line 12 is input to the pixel electrode 14, and the gate line 11 is completed after the charging is completed.
  • the signal becomes a low voltage, and the TFT switch is turned off, whereby the charging process of the pixel electrode 14 is completed.
  • Vpixel voltage of the pixel electrode 14 and the common electrode line in this frame period.
  • the difference of 10 voltage (Vcom) ie, I Vpixel-Vcom
  • the input signal of the additional drive signal line 14 compensates for the pixel electrode
  • the process of the voltage of 132 is as follows. As shown in FIG. 6, in the positive frame, the voltage (Vpixel) of the pixel electrode 132 is greater than the voltage (Vcom) of the common electrode line 10, and the voltage Val input to the additional driving signal line 14 is pulled up to Va2. Then, the voltage (Vpixel) of the corresponding pixel electrode 132 is also pulled upward, so that
  • the voltage (Vcom) is pulled down by the voltage Val input to the additional driving signal line 14 to Va2 in the opposite direction, and the voltage (Vpixel) of the corresponding pixel electrode 132 is also pulled down, so that
  • the signal input from the additional driving signal line 14 compensates the voltage of the pixel electrode 132 such that the absolute value of the difference between the voltage of the pixel electrode 132 and the voltage of the common electrode line 10 is within a predetermined interval.
  • the preset interval may be a range selected according to actual needs. For example, in a positive period as shown in FIG. 7, since the voltage Vcom input from the common electrode line 10 does not change, the voltage of the pixel electrode 132 that has undergone compensation once is between VI and V2, and thus the voltage of the pixel electrode 132 is The absolute value of the difference between the voltages Vcom input to the common electrode line 10 is within the preset interval
  • the preset value of the difference between the voltage (Vpixel) of the pixel electrode 132 and the voltage (Vcom) input by the common electrode line 10 may also be a specific As shown in FIG. 8, the signal Va input through the additional driving signal line 14 is adjusted a plurality of times in each period to compensate the voltage of the pixel electrode 132 in real time, so that the voltage of the pixel electrode 132 tends to be fixed.
  • the additional driving signal line 14 may be parallel to the gate line 11; or, the additional driving signal line 14 may be parallel to the data line 12.
  • the additional driving signal line 14 is parallel to the gate line 11; in the pixel structure shown in Fig. 4, the additional driving signal line 14 is parallel to the data line 12.
  • an additional driving signal line 41 parallel to the gate line 11 and an additional driving signal line 42 parallel to the data line 12 may be simultaneously added.
  • the portion 14-1 of the additional driving signal line 14 and the pixel electrode 132 forming the second capacitor 22 is formed in the same layer as the gate line 11, and the two are formed of the same material but not each other.
  • the remaining portion 14-2 of the additional drive signal line 14 is electrically coupled by a material in the same layer as the pixel electrode 132, which portion 14-2 spans the data line 12, for example, from above.
  • Portions 14-1 and 14-2 of the additional drive signal line 14 are connected by vias 18.
  • the portion 14-1 of the additional capacitor signal line 14 and the pixel electrode 132 forming the second capacitor 22 is formed in the same layer as the data line 12, and the two are formed of the same material but are not connected to each other;
  • the remaining portion 14-2 of the additional driving signal line 14 is electrically connected by a material in the same layer as the pixel electrode 132, which portion 14-2 spans, for example, the gate line 11 and the common electrode line 10 from above.
  • Portions 14-1 and 14-2 of the additional drive signal line 14 are connected through vias 19.
  • the structure of the additional driving signal lines 41, 42 can be referred to the structure of the corresponding driving signal lines in Figs. 2 and 4.
  • the segmented portions of the laterally extending additional drive signal line 41 are connected by a connecting line that spans the data line 12 from above, which is slightly different from the embodiment shown in Fig. 2.
  • the additional driving signal line 14 when the additional driving signal line 14 is parallel to the gate line 11, the additional driving signal line 14 and the gate line 11 may be formed of the same layer of metal material; or the additional driving signal line 14 and the gate line 11 may be disposed in different layers. .
  • the additional driving signal line 14 when the additional driving signal line 14 is parallel to the data line 12, the additional driving signal line 14 and the data line 12 may be formed of the same layer of metal material; or the additional driving signal line 14 and the data line 12 may be disposed in different layers. .
  • the additional driving signal line 14 is parallel to the gate line 11 and is processed in the same layer using the same metal material.
  • the pattern of the additional driving signal line 14 and the gate line 11 can be formed by one patterning process using a mask having a corresponding exposed area. In this way, the production process can be completed, the production cost is effectively saved, and the production difficulty is reduced.
  • the additional driving signal line 14 and the gate line 11 may be made of different materials and are formed at different levels.
  • the additional driving signal line 14 may include a first sub-addition driving signal line 141 and a second sub-addition driving signal line 142.
  • the first sub-addition driving signal line 141 may be parallel to the gate line 11 or the data line 12, and the first sub-addition driving signal line 141 is located outside the area of the gate line 11 or the data line 12. In the pixel structure shown in FIG. 11, the first sub-addition driving signal line 141 is parallel to the gate line 11 and outside the area of the gate line 11.
  • the second sub-addition drive signal line 142 is located in the area of the gate line 11 or the data line 12 (in the projection area of the gate line 11 or the data line 12 in the direction perpendicular to the substrate). It should be noted that when the second sub-addition driving signal line 142 is located in the area of the gate line 11 or the data line 12, it is disposed in a different layer from the gate line 11 or the data line 12.
  • the first sub-addition drive signal line 141 and the second sub-addition drive signal line 142 are connected to each other through the via hole 17.
  • the first sub-addition driving signal line 141 is parallel to the gate line 11 and located outside the area of the gate line 11, and the second sub-addition The drive signal line 142 is located in the area of the gate line 11.
  • the first additional driving signal line 141 may be disposed in the same layer as the pixel electrode 132 (not shown in Fig. 11).
  • the additional driving signal line 14 is designed in such a polygonal line structure.
  • the second sub-addition driving signal line 142 Since the second sub-addition driving signal line 142 is located in the area of the gate line 11 or the data line 12, the second sub-addition driving signal line 142 does not need to occupy the pixel unit 13 The display area is effectively displayed, thereby increasing the aperture ratio of the display device.
  • the drain 1311 of the TFT 131 may also be electrically connected to the extension electrode 30.
  • the extension electrode 30 is a portion in which the drain electrode 1311 of the TFT 131 extends in the direction of the driving signal line 14, and the extension electrode 30 is electrically connected to the drain of the TFT 131.
  • the additional driving signal line 14 forms a first capacitance 21 with the drain 1311 of the TFT 131 and the extension electrode 30. In this way, by the electrical connection method, the area of the upper and lower substrates of the first capacitor 21 is increased, and the storage capacity of the first capacitor 21 is improved, so that the driving power of the additional driving signal line 14 to the pixel electrode 132 is enabled. Increases and lowers the drive voltage.
  • the additional driving signal line 14 when the additional driving signal line 14 is disposed in the same layer as the gate line 11, the additional driving signal line 14 may include the first sub-addition driving signal line 141 and the second sub-addition driving. Signal line 142.
  • the first sub-addition driving signal line 141 is parallel to the gate line 11 and outside the area of the gate line 11, and the second sub-addition driving signal line 142 is located in the area of the gate line 11.
  • the first sub-addition drive signal line 141 forms an overlap region with the pixel electrode 132, and the overlap region is the second capacitor 22.
  • the first sub-addition driving signal line 141 may be disposed in the same layer as the gate line 11, and may eventually lead to an additional driving signal line from the gate line direction.
  • the additional driving signal line 14 when the additional driving signal line 14 is parallel to the data line 12, the additional driving signal line 14 may include the first sub-addition driving signal line 141 and the second sub-addition driving signal line 142.
  • the first sub-addition drive signal line 141 is parallel to the data line 12 and outside the area of the data line 12, and the second sub-addition drive signal line 142 is located in the area of the data line 12.
  • the first sub-addition drive signal line 141 will form an overlap region with the pixel electrode 132, which is the second capacitor 22.
  • the first sub-addition drive signal line 141 may be disposed in the same layer as the data line 12, and may eventually draw additional drive signal lines from the data line direction.
  • the second sub-addition driving signal line 142 since the second sub-addition driving signal line 142 is located in the gate line or the data line area, the second sub-addition driving signal line 142 does not need to occupy the effective in the pixel unit.
  • the display area is such that these structures increase the aperture ratio of the display device.
  • the design of the additional driving signal lines 14 of the above-mentioned several broken line structures is also merely an example. Other designing of additional driving signal lines having a broken line structure is not listed here, but should be included in the protection scope of the present invention.
  • the pixel structure of the display device provided by the embodiment of the present invention further includes at least one set of parallel lead regions, and each set of lead regions 10 includes a first port 101 and a second port 102.
  • the first port 101 is for introducing a signal input by the additional driving signal line 14, and the second port 102 is for introducing a signal input by the gate line 11 or the data line 12.
  • the display device also includes a first circuit region 50 and a second circuit region 51.
  • a first circuit region 50 electrically connected to the first port 101 is used to drive the additional drive signal line 14, and a second circuit region 51 electrically connected to the second port 102 is used to drive the gate line 11 or the data line 12.
  • the first circuit region 50 and the second circuit region 51 can be fabricated by using a flexible circuit board.
  • the first circuit region 50 and the second circuit region 51 may be an integrated structure, or the first circuit region 50 and the second circuit region 51 may be separately fabricated on different circuit boards, in the circuit shown in FIG. A circuit region 50 and a second circuit region 51 are separately fabricated. Since the processing cost is considered, the first circuit region 50 and the second circuit region 51 can be formed in two non-communicated regions of the same circuit board.
  • the additional driving signal line 14 in the pixel structure provided by the embodiment of the present invention may be Made of transparent conductive material.
  • the additional driving signal line 14 can be made to improve the aperture ratio of the display device while satisfying the conductivity.
  • the additional driving signal line 14 may need to pass through the lead crossing region 60 in the pixel structure unit.
  • the connection line 15 is used to turn on the common electrode in each pixel unit on both sides of the gate line 11.
  • a via connection as shown.
  • such a connecting line 15 may also exist in the pixel structure of the liquid crystal display device adopting other modes, and a similar additional signal line bridging structure is also reserved in FIG. 11 , FIG. 12 and the like, and only the above Figure 15 shows an example, no longer - enumerated.
  • transition voltage AVp the process of the transition voltage AVp will be described in detail by taking the existing pixel structure as an example.
  • a storage capacitor is provided between the pixel electrode 132 and the common electrode (not shown), and the voltage signal of the common electrode line 10 electrically connected to the common electrode is kept constant. mode. Since the thin film transistor (TFT) channel is located on the gate line 11, there is a parasitic capacitance (Cgd). Thus, after the gate line 11 is input with a low voltage, the pixel electrode 14 is completely charged. However, the total amount of charge stored in the liquid crystal capacitor Clc (not shown in Fig. 1), the storage capacitor Cst (not shown in Fig. 1), and the parasitic capacitance is equal before and after the TFT is turned off.
  • TFT thin film transistor
  • Vp2-Vpl C ⁇ (yg/ - Vgh) I (Cgd + Clc + Cst)
  • the hopping voltage is:
  • Vgl is a low voltage input to the gate line 11 (gate voltage when the TFT is turned off)
  • Vgh is a high voltage input from the gate line 11 (gate voltage when the TFT is turned on)
  • Vpl is the voltage of the corresponding pixel electrode 14 when the gate line 11 is input with a high voltage (when the TFT is turned on)
  • Vp2 is the voltage of the pixel electrode 14 corresponding to the low voltage of the gate line 11 (when the TFT is turned off)
  • the pixel structure shown in FIG. 2 proposed by the embodiment of the present invention is taken as an example, and the specific working process of the pixel structure is as follows:
  • the input signal of the additional driving signal line 14 is the same as the timing of the input signal of the gate line 11, but the direction of the transition of the input signal of the additional driving signal line 14 is opposite to the direction of the transition of the input signal of the gate line 11.
  • the charge and voltage changes caused by the additional driving signal line 14 to the first capacitor 21 (Cad) and the charge and voltage changes caused by the gate line 11 input signal passing through the parasitic capacitance (Cgd) are positively and negatively offset by inputting a reasonable signal. , thus achieving the solution of the AVp problem.
  • the calculation process is as follows:
  • AVp can be reduced or eliminated by controlling the Val, Vah, first capacitance 21 (Cad) of the signal in the additional drive signal line 14, and its transition timing.
  • the key positions of the signal hopping sequence in the additional driving signal line 14 are mainly concentrated on the corresponding process in which the gate voltage signal is hopped from Vgh to Vgl, that is, the process in which the signal on the additional driving signal line 14 is changed from Val to Vah, where Val
  • the time point of transition to Vah and the voltage difference from Val to Vah are the main control parameters that need to be met:
  • the waveform diagram is shown in Figure 5.
  • the position of the dotted line ⁇ is the output of the gate voltage signal Vg.
  • the key position of the AVp is generated, and the solid line position is the key time point at which the additional drive signal line 14 is input to the corresponding signal Va.
  • the TFT switch since the TFT switch is turned on, the current on the data line 12 continues to charge the pixel, so the transition position will also generate charge redistribution.
  • the influence on the voltage of the final pixel electrode 132 is small, and the problem of generating AVp or the like in the liquid crystal voltage is not caused, and it is not necessary to consider it in general calculation.
  • the absolute value of the difference between the voltage of the pixel electrode 132 and the voltage of the common electrode line 10 is within a predetermined interval.
  • the gate voltage is Vgl (when the TFT is turned off), the gate voltage is the low voltage Vgl, and remains unchanged in one frame period, and Val is an additional driving signal line.
  • 14 is the voltage before pulling up
  • Vpl is the voltage before the pixel electrode 132 is pulled up
  • Va2 is the voltage after the additional driving signal line 14 is pulled up
  • Vp2 is the voltage after the pixel electrode 132 is pulled up
  • Vp2-Vpl (Va2-Val) x Cad/(Cgd + Cad + Clc + Cst)
  • Va2-Val ⁇ 0 can be selected to achieve
  • the following calculation can be referred to. Taking a positive cycle as an example, due to the presence of leakage current,
  • Vpl is the pixel electrode voltage before the power loss Q
  • Vgl is the gate voltage
  • Val is the signal line voltage
  • Vp3 is The pixel electrode voltage after the power loss Q
  • Vp3 [V/7l(Cgd + Cad + Clc + Cst)-Q]/(Cgd + Cad + Clc + Cst)
  • Vpl - Vp3 Q/(Cgd + Cad + Clc + Cst)
  • Vp ⁇ - Vcom / 2" AVpixel/ m m is the falling grayscale value.
  • FIG. 6 and FIG. 7 only show Va2 and Val, that is, only the voltage of the pixel electrode 132 is raised once in one positive or negative period, and the voltage of the pixel electrode 132 can be improved by using a multi-step driving or the like (eg, in one frame).
  • Va3, Va4, Van, etc. are continuously added during the period; if the number of Van or n is sufficiently large, real-time compensation for the voltage of the pixel electrode 132 can be realized, that is, the waveform shown in FIG.
  • the relationship between Val and Va2 is shown in Figure 7:
  • Va2 Val + Q / Cad
  • the Q value is positive in the positive cycle and negative in the negative cycle.
  • the problem that the voltage of the pixel electrode 132 is lowered due to the presence of leakage current can be solved, thereby improving the display quality of the liquid crystal display.
  • the pixel structure exemplified above is described by adopting a structure in which the additional driving signal line 14 is parallel to the gate line 11 and forms a parasitic capacitance with the drain 1311 of the TFT 131. 3 or the pixel structure shown in FIG. 12, when the additional driving signal line 14 is parallel to the gate line 11 and forms a second capacitor 22 with the pixel electrode, or as shown in FIG. 4 or FIG.
  • the additional driving signal line 14 is When the data line 12 is parallel structure, in order to reduce or eliminate the hopping voltage and solve the problem of the decrease of I Vpixel-Vcom
  • the relevant calculation formula (as calculated above) In the results (2), (3), (4), (5)), the value of the first capacitor (Cad) is replaced by the value of the second capacitor (Cap), and the driving signal is changed to be related to Cap.
  • the pixel structure shown in FIG. 9 when the pixel structure has the structure of the additional driving signal line 41 parallel to the gate line 11 and the additional driving signal line 42 parallel to the data line 12, the same can be reduced or The display voltage quality of the liquid crystal display is improved by eliminating the jump voltage and solving the problem of the reduction of the I Vpixel-Vcom
  • the detailed principle can also be referred to the foregoing embodiment, and details are not described herein again.
  • Embodiments of the present invention provide a display device including any of the pixel structures as described above, which has the same advantageous effects as the pixel structure provided by the foregoing embodiments of the present invention, since the pixel structure has been performed in the foregoing embodiments. Detailed description will not be repeated here.
  • a display device provided by an embodiment of the invention includes a pixel structure.
  • the additional driving signal line and the TFT are added by adding an additional driving signal line parallel to the gate line and/or the data line in the pixel structure
  • the drain or pixel electrode forms a capacitance, and the additional drive signal line input signal is opposite in phase to the gate line input signal.
  • the charge of the capacitor formed by the additional driving signal line and the drain or the pixel electrode of the TFT can compensate for the charge change of the parasitic capacitance, thereby avoiding the influence of the hopping voltage on the voltage of the pixel electrode, thereby improving the display of the display device. effect.
  • the pixel structure driving method provided by the embodiment of the present invention can be applied to the pixel structure provided in the foregoing embodiment.
  • the pixel structure includes: a common electrode line 10, a gate line 11 and a data line 12, and at least one pixel unit 13 is defined by the horizontally intersecting gate line 11 and the data line 12, and the pixel unit 13 further includes a TFT 131 and Pixel electrode 132.
  • the pixel structure driving method provided by the embodiment of the present invention can be performed as follows.
  • Step S101 inputting a signal from the gate line 11 for turning on the TFT 131 row by row.
  • Step S102 inputting a signal from the data line 12 for supplying power to the pixel electrode 132 through the drain 1311 of the TFT when the TFT 131 is turned on.
  • Step S103 inputting a signal from the additional driving signal line 14, the signal and the gate line 11 inputting a signal ⁇ ;
  • the additional drive signal line 14 forms an additional capacitance for compensating for parasitic capacitance within the pixel structure.
  • the additional capacitor may include a first capacitor formed by the additional driving signal line 14 and the drain 1311 of the TFT, or, as shown in FIGS. 3 and 4, the additional capacitor may include an additional driving signal line.
  • a pixel structure driving method provided by an embodiment of the present invention.
  • the additional driving signal line forms a capacitance with the drain or pixel electrode of the TFT by adding an additional driving signal line parallel to the gate line and/or the data line in the pixel structure, and the additional driving signal line input signal and the gate line input signal The opposite phase.
  • the charge of the capacitor formed by the additional driving signal line and the drain or the pixel electrode of the TFT can compensate for the charge change of the parasitic capacitance, thereby avoiding the influence of the hopping voltage on the voltage of the pixel electrode, thereby improving the display of the display device. effect.
  • the waveform of the input signal of the additional driving signal line 14 and the waveform of the input signal of the gate line 11 are exemplified. As shown in Fig. 5, the input signal Va of the additional driving signal line 14 is opposite to the phase of the input signal Vg of the gate line 11.
  • the driving method of the pixel structure provided by the embodiment of the present invention may further include: Step S104:
  • the additional driving signal line 14 inputs a signal for compensating for the voltage of the pixel electrode 132. This causes a difference between the voltage of the pixel electrode 132 and the voltage of the input signal of the common electrode line 10. The absolute value of the value is within the preset interval, thereby improving the display quality of the liquid crystal display.
  • the preset interval may be a range selected according to actual needs. For example, in a positive period as shown in FIG. 7, since the voltage Vcom input from the common electrode line 10 does not change, the voltage of the pixel electrode 132 that has undergone compensation once is between VI and V2, and thus the voltage of the pixel electrode 132 is The absolute value of the difference between the voltages Vcom input to the common electrode line 10 is within the preset interval
  • may also be a specific value.
  • the voltage input by the additional driving signal line 14 is adjusted a plurality of times to compensate the voltage of the pixel electrode 132 in real time, so that the voltage of the pixel electrode 132 tends to a fixed value Vpq due to the voltage input from the common electrode line 10.
  • Vcom is constant, so that the absolute value I Vpixel-Vcom
  • the pixel structure shown in FIG. 2 proposed by the embodiment of the present invention is taken as an example, and the detailed description of the driving method of the pixel structure is as described above, and is not repeated here.
  • the absolute value of the difference between the voltage of the pixel electrode 132 and the voltage of the common electrode line 10 is within a preset interval, and the existing pixel structure as shown in FIG. 1 is the common electrode line 10.
  • the driving method of the existing pixel structure is as follows.
  • the calculation of the trip voltage can also be based on the formula:
  • Vp2-Vp ⁇ (Vcom2-Vcoml) x (Clc + Cs) / (Cgd + Clc + Cst) ( 6 )
  • Vcom2>Vcoml needs to be satisfied.
  • the voltage of the pixel electrode 132 can be changed by Vp2>Vpl.
  • the relationship between Vcoml and Vcom2 is:
  • the driving method can be applied not only to the existing pixel structure as shown in FIG. 1 but also to the pixel structure provided by the embodiment of the present invention.
  • the calculation method is the same as above, and will not be described herein.
  • the absolute value of the difference between the voltage of the pixel electrode 132 and the voltage of the common electrode line 10 is within a preset interval,
  • the pixel structure shown in FIG. 2 is taken as an example in the embodiment of the present invention. The detailed description of the driving method of the pixel structure is as described above, and is not repeated here.

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Abstract

一种像素结构包括公共电极线（10）、栅线（11）、数据线（12）、附加驱动信号线（14）、由横纵交叉的栅线（11）和数据线（12）划分成的至少一个像素单元（13）。所述像素单元（13）包括薄膜晶体管（131）和像素电极（132）。所述附加驱动信号线（14）形成用于补偿所述像素结构内寄生电容（Cgd）电荷的附加电容。所述附加驱动信号线（14）输入信号与所述栅线（11）输入信号的相位相反。该像素结构可避免跳变电压对像素电极（132）电压产生的影响，提高显示装置的显示效果。还提供了一种驱动方法和显示装置。

Description

像素结构及其驱动方法、 显示装置 技术领域
本发明的实施例涉及一种像素结构及其驱动方法、 显示装置。 背景技术
薄膜晶体管液晶显示器（TFT-LCD ) 因具有环保特性良好、 适用温度范 围宽、制造技术自动化程度高、 易于集成化等优点， 已成为主流的显示产品。
典型的 TFT-LCD通常具有以矩阵形式排列的多个像素结构。 典型的单 位像素结构， 如图 1所示， 包括横纵交叉的栅线 11以及数据线 12, 在栅线 11与数据线 12的交叉位置处设置有薄膜晶体管 （TFT ) 。 该 TFT的栅极为 栅线 11的一部分， 源极 1312与数据线 12相连接， 漏极 1311连接像素电极 132以维持像素电极 132的电压。该像素结构还可以设置有与栅线 11平行的 公共电极线 10, 像素电极 132与和公共电极线 10相电连接的公共电极（未 示出）之间具有存储电容。 该像素结构可通过采用公共电极电压（ Vcom )保 持不变以及行翻转的驱动方式， 以实现对液晶显示器的有效控制。
但是， 这样的像素结构的不足之处在于： TFT的栅极与漏极 1311 由于 位于不同层上， 在它们之间会产生寄生电容（Cgd )。 在栅线 11通过电压控 制 TFT开关的瞬间， 由于该寄生电容的存在， TFT关闭时栅电压信号由高到 低的变化， 会使得漏极 1311输出跳变电压（AVp )。 该跳变电压引起相应的 像素中液晶电压（Vic ) 的突然降低， 从而影响像素电极 132 上施加的电压 ( Vpixel ) 的准确性， 使得显示画面闪烁。 发明内容
本发明的实施例提供了一种像素结构及其驱动方法、 显示装置， 可避免 跳变电压对像素电极电压产生的影响， 提高显示装置的显示效果。
本发明的一方面提供了一种像素结构， 其包括： 公共电极线、 栅线、 数 据线、 附加驱动信号线、 由横纵交叉的栅线和数据线界定出的至少一个像素 单元， 所述像素单元包括薄膜晶体管和像素电极； 所述附加驱动信号线形成 用于补偿所述像素结构内寄生电容电荷的附加电容； 所述附加驱动信号线的 输入信号与所述栅线的输入信号的相位相反。
本发明实施例的另一方面，提供一种显示装置， 包括如上所述像素结构。 本发明实施例的另一方面， 提供一种像素结构驱动方法， 所述像素结构 包括： 公共电极线、 栅线、 数据线、 附加驱动信号线、 由横纵交叉的栅线和 数据线界定出的至少一个像素单元， 所述像素单元包括薄膜晶体管和像素电 极； 所述方法包括： 通过所述栅线输入栅线信号，逐行开启所述薄膜晶体管； 通过所述数据线输入数据线信号， 当所述薄膜晶体管开启时， 通过所述薄膜 晶体管的漏极向所述像素电极供电； 通过所述附加驱动信号线输入附加驱动 信号， 该附加驱动信号与所述栅线信号的相位相反。 所述附加驱动信号线形 成补偿所述像素结构内寄生电容电荷的附加电容。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 筒单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为现有的像素结构示意图；
图 2为本发明实施例提供的一种像素结构示意图；
图 3为本发明实施例提供的另一种像素结构示意图；
图 4为本发明实施例提供的另一种像素结构示意图；
图 5为本发明实施例提供的一种驱动信号的波形图；
图 6为本发明实施例提供的另一种驱动信号波形图；
图 7为本发明实施例提供的另一种驱动信号波形图；
图 8为本发明实施例提供的又一种驱动信号波形图；
图 9为本发明实施例提供的另一种像素结构示意图；
图 10为本发明实施例提供的另一种像素结构示意图；
图 11为本发明实施例提供的另一种像素结构示意图；
图 12为本发明实施例提供的另一种像素结构示意图；
图 13为本发明实施例提供的又一种像素结构示意图；
图 14为本发明实施例提供的电路区域结构示意图； 图 15为本发明实施例提供的一种像素结构示意图。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
除非另作定义， 此处使用的技术术语或者科学术语应当为本发明所属领 域内具有一般技能的人士所理解的通常意义。本公开中使用的 "第一"、 "第 二" 以及类似的词语并不表示任何顺序、 数量或者重要性， 而只是用来区分 不同的组成部分。 同样， "一个" 、 "一" 或者 "该" 等类似词语也不表示 数量限制， 而是表示存在至少一个。 "包括" 或者 "包含" 等类似的词语意 指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及 其等同， 而不排除其他元件或者物件。 "连接" 或者 "相连" 等类似的词语 并非限定于物理的或者机械的连接， 而是可以包括电性的连接， 不管是直接 的还是间接的。 "上" 、 "下" 、 "左" 、 "右" 等仅用于表示相对位置关 系， 当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
本发明的实施例提供了一种阵列基板， 该阵列基板具有一种像素结构， 如图 2所示， 该像素结构包括： 公共电极线 10、 栅线 11和数据线 12, 由横 纵交叉的栅线 11和数据线 12界定出的至少一个像素单元 13。 像素单元 13 又包括 TFT 131和像素电极 132。 这些像素单元按照一定的阵列（例如矩阵） 排列。
另外， 该实施例的像素结构还可以包括附加驱动信号线 14。 附加驱动信 号线 14可以提供用于补偿所述像素结构中 TFT的栅极和漏极之间形成的寄 生电容（Cgd ) 电荷的附加电容。 附加驱动信号线 14上的输入信号（附加驱 动信号 )与栅线 11上的输入信号（栅线信号 )可以彼此时序相同， 但是相位 相反。
该附加电容可以包括： 附加驱动信号线 14与 TFT 131的漏极 1311形成 的第一电容 21 ,或者附加驱动信号线 14与像素电极 132形成的第二电容 22。 如图 2所示，与栅线 11平行的附加驱动信号线 14可以与 TFT131的漏极 1311 在垂直于纸面的方向上重叠而形成第一电容 21。 或者， 本发明实施例提供的 像素结构还可以如图 3或图 4所示， 与数据线 12平行的附加驱动信号线 14 与像素电极 132在垂直于纸面的方向上重叠形成第二电容 22。 或者， 本发明 实施例提供的像素结构还可以同时具有第一电容 21和第二电容 22。
当然，上述具有第一电容 21和 /或第二电容 22的像素结构也仅是举例说 明，其他能够形成第一电容 21和 /或第二电容 22的像素结构设计在此不一一 列举， 但都应当纳入本发明的保护范围。 在这样的像素结构中， 附加驱动信 号线 14与 TFT131的漏极 1311形成第一电容 21或者附加驱动信号线 14与 像素电极 132所形成第二电容 22的电荷，可以对寄生电容的电荷变化进行补 偿， 即， 实现附加驱动信号线 14对寄生电容的电荷变化进行补偿。 该补偿可 避免跳变电压对像素电极电压的影响， 从而提高了显示装置的显示效果。
本发明实施例提供一种像素结构， 其通过在像素结构中添加平行于栅线 和 /或数据线的附加驱动信号线， 该附加驱动信号线与 TFT 的漏极或者像素 电极形成电容， 并且该附加驱动信号线上的输入信号与栅线上的输入信号的 相位相反，这样一来附加驱动信号线与 TFT的漏极或者像素电极所形成电容 的电荷可以对寄生电容的电荷变化进行补偿， 避免了跳变电压对像素电极电 压的影响， 从而提高了显示装置的显示效果。
需要说明的是， 本发明的实施例以高级超维场开关 （ ADvanced-Super Dimensional Switching, ADSDS )模式的液晶显示装置为例进行的说明， 但 是本发明不限于此。
ADSDS 技术通过同一平面内像素电极边缘所产生的平行电场以及像素 电极层与公共电极层间产生的纵向电场形成多维电场， 使液晶盒内像素电极 间、 各电极正上方所有取向液晶分子都能够产生旋转转换， 从而提高了平面 取向液晶的工作效率并增大了透光效率。
根据本发明实施例的液晶显示装置包括阵列基板和对置基板。 阵列基板 与对置基板彼此对置并通过例如封框胶形成液晶盒， 在液晶盒中填充有液晶 材料。 该对置基板例如为彩膜基板。 阵列基板的每个像素单元的像素电极用 于施加电场对液晶材料的旋转的程度进行控制从而进行显示操作。 在一些示 例中， 该液晶显示装置还可以包括为阵列基板提供背光的背光源。 ADSDS模式的阵列基板的每个像素包括与公共电极线 10相连的第一电 极（图 2中未示出）以及与 TFT的漏极相连的第二电极。 在如图 1所示的像 素结构中， 该第二电极可以为像素电极 132, 其通过过孔 16与 TFT的漏极 1311相连。 附加驱动信号线 14可以与像素电极 132同层设置但不相连接， 二者制作材料可以相同； 如果此时像素电极 132与漏极所在的源漏金属层处 于不同的层级， 附加驱动信号线 14即可以与 TFT131的漏极 1311形成第一 电容 21。 采用这样的像素结构， 无需增加新的制作工序即可以制作出附加驱 动信号线 14 , 从而降低了产品的生产难度。 当然本发明实施例并不限于 ADSDS模式的液晶显示装置， 在其他结构的液晶显示装置中， 同样可以采 用这样的附加驱动信号线设计， 在此不——列举。
在本实施例当中， 附加驱动信号线 14输入信号的波形与栅线 11输入信 号的波形可以如图 5所示。附加驱动信号线 14输入信号 Va的波形与栅线 11 输入信号 Vg的波形周期（时序）相同， 但跳变方向相反（即彼此反相 ) 。 具体的， 当栅线 11输入高电压信号 Vgh时， 附加驱动信号线 14相应地输入 低电压信号 Val; 当栅线 11输入低电压信号 Vgl时， 附加驱动信号线 14相 应地输入高电压信号 Vah。
进一步地，如图 2所示，附加驱动信号线 14上的输入信号还可以用于补 偿所述像素电极 132的电压， 以使得像素电极 132的电压与公共电极线 10 上输入信号的电压 （即施加到公共电极上的电压）之间差值的绝对值在预设 区间范围内。
需要说明的是， 像素传统的充电过程例如如图 6的上半部分所示。 在一 个帧周期时间内，当栅线 11的信号以高电压输入后，与该栅线 11相连的 TFT 开关打开， 由此数据线 12上的电流输入像素电极 14中， 充电完成后栅线 11 的信号变成低电压， 则 TFT开关关闭， 由此像素电极 14充电过程完成。 但 是， 到下次像素充电开始前还需要经过一段时间， 在这段时间内， 由于多种 原因引起的漏电流的存在，导致在这个帧周期中像素电极 14的电压（Vpixel ) 与公共电极线 10电压（Vcom ) 的差值（即 I Vpixel- Vcom| )会逐渐降低， 因 此像素灰度值也会随之变化， 不能维持原来设定的灰度值， 从而导致像素显 示效果变差。
在本发明的实施例中，附加驱动信号线 14的输入信号补偿所述像素电极 132的电压的过程如下所述。 如图 6所示， 在正周期（ positive frame )中， 像 素电极 132的电压 （Vpixel ) 大于公共电极线 10的电压（Vcom), 通过将附 加驱动信号线 14输入的电压 Val向上拉升为 Va2, 则相应的像素电极 132 的电压 （Vpixel )也会向上拉升， 从而实现 |Vpixel-Vcom|不降低； 在负周期 ( Negative frame ) 中， 像素电极 132 的电压 （Vpixel ) 小于公共电极线 10 的电压（Vcom),通过将附加驱动信号线 14输入的电压 Val下拉为反方向的 Va2 , 相应的像素电极 132 的电压 （Vpixel ) 也会受到下拉， 从而实现 |Vpixel-Vcom|不降低。
进一步地，附加驱动信号线 14输入的信号补偿像素电极 132的电压，可 以使得像素电极 132电压与公共电极线 10电压之间差值的绝对值在一个预设 区间范围内。 该预设区间可以是根据实际需要选取的范围。 例如， 在如图 7 所示的一个正周期内， 由于公共电极线 10输入的电压 Vcom不变，经过一次 补偿的像素电极 132的电压在 VI与 V2之间，因此像素电极 132的电压与所 述公共电极线 10输入的电压 Vcom之间差值的绝对值处在预设区间 |V1-V2| 之内。
或者， 进一步地， 像素电极 132的电压（Vpixel )与公共电极线 10输入 的电压（Vcom )之间差值的绝对值 ( (Vpixel- Vcom| )所处的预设区间还可以 是一个具体的值。 如图 8所示， 在每个周期内多次调整通过附加驱动信号线 14输入的信号 Va, 以对像素电极 132的电压以进行实时补偿， 使得像素电 极 132的电压趋于一个固定的数值 Vpq。由于公共电极线 10输入的电压 Vcom 不变， 因此可以保证像素电极 132的电压 Vpixel与公共电极线 10输入的电 压 Vcom之间差值的绝对值（ I Vpixel- Vcom| )为 |Vpq-Vcom|。
需要说明的是， 附加驱动信号线 14可以与栅线 11平行； 或者， 附加驱 动信号线 14还可以与数据线 12平行。在如图 2、 3所示的像素结构中， 附加 驱动信号线 14与栅线 11平行； 在如图 4所示的像素结构中， 附加驱动信号 线 14与数据线 12平行。 或者， 如图 9所示， 本发明实施例提供的像素结构 中可以同时添加与栅线 11平行的附加驱动信号线 41以及与数据线 12平行的 附加驱动信号线 42。
例如， 在如图 3所示的像素结构中， 附加驱动信号线 14与像素电极 132 形成第二电容 22的部分 14-1与栅线 11同层形成，二者形成材料相同但互不 连接； 附加驱动信号线 14的其余部分 14-2则由与像素电极 132同层的材料 电连接， 该部分 14-2例如从上方跨越了数据线 12。 附加驱动信号线 14的部 分 14-1和 14-2则通过过孔 18连接。
例如， 在如图 4所示的像素结构中， 附加驱动信号线 14与像素电极 132 形成第二电容 22的部分 14-1与数据线 12同层形成，二者形成材料相同但互 不连接； 附加驱动信号线 14的其余部分 14-2则由与像素电极 132同层的材 料电连接， 该部分 14-2例如从上方跨越了栅线 11和公共电极线 10。 附加驱 动信号线 14的部分 14-1和 14-2则通过过孔 19连接。
在图 9所示的像素结构中， 附加驱动信号线 41、 42的结构可以参照图 2 及图 4中相应的驱动信号线的结构。 在图 9中， 横向延伸的附加驱动信号线 41的各分段部分通过从上方跨越数据线 12的连接线连接， 与图 2所示的实 施例略 不同。
进一步地， 例如， 当附加驱动信号线 14与栅线 11平行时， 附加驱动信 号线 14与栅线 11可以为同层金属材料形成；或者附加驱动信号线 14与栅线 11还可以异层设置。
进一步地， 例如， 当附加驱动信号线 14与数据线 12平行时， 附加驱动 信号线 14与数据线 12可以为同层金属材料形成； 或者附加驱动信号线 14 与数据线 12还可以异层设置。
如图 10所示，附加驱动信号线 14与栅线 11平行并且采用同一种金属材 料在同一层加工而成。 例如， 当在基板的表面形成栅金属膜层之后， 可以采 用具有相应曝光区域的掩膜板通过一次构图工艺形成附加驱动信号线 14 与 栅线 11的图案。 这样一来， 可以筒化制作工序， 有效节约了生产成本， 降低 了生产难度。
或者， 附加驱动信号线 14与栅线 11还可以采用不同的材料， 在不同的 层面上力口工而成。
进一步地，附加驱动信号线 14可以包括第一子附加驱动信号线 141和第 二子附加驱动信号线 142。第一子附加驱动信号线 141可以与栅线 11或数据 线 12平行，并且该第一子附加驱动信号线 141位于栅线 11或数据线 12的区 域之外。 如图 11所示的像素结构中， 第一子附加驱动信号线 141与栅线 11 平行且位于栅线 11区域外。可以看到， 当第一子附加驱动信号线 141与栅线 11平行且位于栅线 11区域外时， 第一子附加驱动信号线 141的一部分区域 将与 TFT131的漏极 1311形成交叠区域， 该交叠区域即为第一电容 21。 第 二子附加驱动信号线 142位于栅线 11或数据线 12区域内 （在垂直于基板的 方向上位于栅线 11或数据线 12的投影区域内） 。 需要说明的是， 当第二子 附加驱动信号线 142位于栅线 11或数据线 12区域内时，与栅线 11或数据线 12不同层设置。 该第一子附加驱动信号线 141和第二子附加驱动信号线 142 通过过孔 17彼此连接。
如图 11所示的像素结构中，当附加驱动信号线 14与栅线 11异层设置时， 第一子附加驱动信号线 141与栅线 11平行且位于栅线 11区域外， 第二子附 加驱动信号线 142位于栅线 11的区域内。第一附加驱动信号线 141可以与像 素电极 132 (图 11中未示出）同层设置。 采用这种折线结构的附加驱动信号 线 14设计，由于第二子附加驱动信号线 142位于栅线 11或数据线 12区域内， 因此该第二子附加驱动信号线 142无需占用像素单元 13内的有效显示区域， 从而提高了显示装置的开口率。
更进一步的， 在一个示例中， TFT131的漏极 1311还可以与延伸电极 30 电连接。 如图 11所示， 延伸电极 30为 TFT131的漏极 1311沿驱动信号线 14方向相延伸的部分， 且延伸电极 30与 TFT131的漏极电连接。 附加驱动 信号线 14与 TFT131的漏极 1311以及延伸电极 30形成第一电容 21。 这样 一来， 通过这种电连接方式， 增大了第一电容 21的上、 下基板的面积， 提高 了第一电容 21的存储能力， 使得附加驱动信号线 14对像素电极 132电压的 带动能力增大， 并且降低了驱动电压。
需要说明的是， 在加工过程中， 本领域技术人员可以根据具体对开口率 和寄生电容的存储能力的不同要求来调节延伸电极 30的长度或宽度。
又例如， 在如图 12所示的像素结构中， 当附加驱动信号线 14与栅线 11 同层设置时，附加驱动信号线 14可以包括第一子附加驱动信号线 141和第二 子附加驱动信号线 142。如图 12所示，第一子附加驱动信号线 141与栅线 11 平行且位于栅线 11区域外， 第二子附加驱动信号线 142位于栅线 11的区域 内。 第一子附加驱动信号线 141与像素电极 132形成交叠区域， 该交叠区域 即为第二电容 22。 第一子附加驱动信号线 141可以与栅线 11同层设置， 并 最终可以从沿栅线方向引出附加驱动信号线。 另外， 或者如图 13所示， 当附加驱动信号线 14与数据线 12平行时， 附 加驱动信号线 14可以包括第一子附加驱动信号线 141和第二子附加驱动信号 线 142。 如图 13所示， 第一子附加驱动信号线 141与数据线 12平行且位于 数据线 12区域外， 第二子附加驱动信号线 142位于数据线 12的区域内。 第 一子附加驱动信号线 141将与像素电极 132形成交叠区域， 该交叠区域即为 第二电容 22。 第一子附加驱动信号线 141可以与数据线 12同层设置， 并最 终可以从沿数据线方向引出附加驱动信号线。
在以上几种折线结构的附加驱动信号线 14设计中，由于第二子附加驱动 信号线 142位于栅线或数据线区域内， 因此该第二子附加驱动信号线 142无 需占用像素单元内的有效显示区域,从而这些结构提高了显示装置的开口率。 当然，以上几种折线结构的附加驱动信号线 14设计也仅是举例说明，其他具 有折线结构的附加驱动信号线设计在此不——列举， 但都应当纳入本发明的 保护范围。
需要说明的是，如图 14所示，本发明实施例提供的显示装置的像素结构 还包括至少一组平行的引线区域,每一组引线区域 10包括第一端口 101和第 二端口 102。 第一端口 101用于引入附加驱动信号线 14输入的信号， 第二端 口 102用于引入栅线 11或数据线 12输入的信号。
该显示装置还包括第一电路区域 50与第二电路区域 51。与第一端口 101 电连接的第一电路区域 50用于驱动附加驱动信号线 14,与所述第二端口 102 电连接的第二电路区域 51用于驱动栅线 11或数据线 12。
这样一来， 通过将用于向附加驱动信号线 14输入信号的第一端口 101 与用于向栅线 11或数据线 12输入信号的第二端口 102制作在同一组引线区 域内， 可以无需额外制作新的引线区域， 这大大筒化了电路结构。
需要说明的是，在本发明的实施例中，第一电路区域 50以及第二电路区 域 51均可以采用软性电路板制作而成。第一电路区域 50和第二电路区域 51 可以为一体结构， 或者第一电路区域 50和第二电路区域 51也可以分别制作 在不同的电路板上， 在如图 14所示的电路中， 第一电路区域 50和第二电路 区域 51为分别制作的。 由于考虑到加工成本， 可以将第一电路区域 50和第 二电路区域 51制作在同一个电路板的两块不相通的区域内。
需要说明的是,本发明实施例提供的像素结构中附加驱动信号线 14可以 采用透明导电材料制成。
采用透明导电材料并利用如图 1 1 所示与栅线或者数据线与附加驱动信 号线在同一位置的异层设置，可以使得附加驱动信号线 14在满足导电性的同 时提高显示装置的开口率。
在本发明所涉及的全部实施例中， 需要说明的是， 如图 15所示， 例如在
ADSDS模式下的液晶显示装置的像素中， 附加驱动信号线 14可能需要穿越 像素结构单元中引线交叉区域 60。 在该引线交叉区域 60中， 连接线 15用来 导通在栅线 1 1两侧的各像素单元中的公共电极。 这样， 当附加驱动线 14需 要穿越引线交叉区域 60时则需要采用如图所示过孔连接的方式跨接穿越。当 然这样的连接线 15 在采用其他模式的液晶显示装置的像素结构中也可以存 在， 而在图 1 1 , 图 12等也预留了类似的附加信号线的跨接结构， 在此仅以 上述图 15所示为例， 不再——列举。
以下以现有的像素结构为例，对跳变电压 AVp产生的过程进行详细的说 明。
如图 1所示， 现有的像素结构中， 像素电极 132与公共电极（未示出） 之间具有存储电容,且采用与公共电极电连接的公共电极线 10的电压信号保 持不变的驱动模式。 由于薄膜晶体管（TFT )沟道位于栅线 1 1上， 故存在寄 生电容（Cgd ) 。 这样在栅线 1 1输入低电压后， 像素电极 14完成充电。 但 该液晶电容 Clc (图 1中未示出 ) 、 存储电容 Cst (图 1中未示出）、 寄生电容 三者存储的电荷总量在 TFT关闭前后相等。 在栅线 1 1电压变化前后， 以上 三个电容存储的总电荷之和相等， 但是由于在 TFT关闭的同时， 栅线 1 1电 压也在这个过程中产生电压跳变， 故会产生跳变电压（AVp ) , 其产生的过 程如下：
(Vpl-Vgh) x Cgd+(Vpl-Vcom) x (Clc+Cst)
=(Vp2-Vgl) x Cgd+(Vp2-Vcom) x (Clc+Cst) 兆变电压为：
Vp2-Vpl=C^(yg/ - Vgh) I (Cgd + Clc + Cst)
具体的， 在如图 1所示的像素中， 跳变电压为：
Δ Vp = Cgd (Vgl - Vgh) I {Cgd + Clc + Cst) ( i、 其中， Vgl为栅线 11输入的低电压（TFT关闭时的栅电压）， Vgh为栅 线 11输入的高电压（TFT打开时的栅电压）。 Vpl为栅线 11输入高电压（TFT 打开时 )对应的像素电极 14的电压， Vp2为栅线 11输入低电压 (TFT关闭 时）对应的像素电极 14电压； 漏极 133电压与像素电极 14电压保持一致。 由于栅电压变化， 由上述计算公式（1)可以看出来， 由于 Vg Vgh, 则 Vp2<VpK 在 Vgh变化到 Vgl时就会产生一个降低像素电极 132的电压的 AVp。
针对跳变电压产生的原因， 以本发明实施例提出的如图 2所示的像素结 构为例， 其像素结构的具体工作过程如下所述：
如图 2所示，附加驱动信号线 14输入信号与栅线 11输入信号时序相同， 但该附加驱动信号线 14输入信号的跳变方向与栅线 11输入信号的跳变方向 相反。并且，通过输入合理的信号使附加驱动信号线 14对第一电容 21 (Cad) 所引起的电荷和电压变化与栅线 11输入信号通过寄生电容（Cgd)所引起的 电荷和电压变化正负抵消， 从而实现 AVp问题的解决。 其计算过程如下：
(Vpl-Vgh)x Cgd+(Vpl-Val)x Cad+(V l-Vcom) x (Clc+Cst) =(Vp2-Vgl) x Cgd+(Vp2-Vah ) x Cad+(Vp2-Vcom) x (Clc+Cst) 跳变电压为：
Vp2-Vpl=[C^(y^/ -y^i) + (Vah-Val)Cad] I (Cgd + Clc + Cst + Cad) (2) 其中， Vah为附加驱动信号线 14输入的高电压， Val为附加驱动信号线 14输入的低电压。 在此时若想实现 AVp=Vp2-Vpl=0, 则需满足：
Cgd (Vgh -Vgl)^ (Vah - Val)Cad
即可消除 AVp。 通过控制附加驱动信号线 14中信号的 Val、 Vah, 第一 电容 21 (Cad)以及其跳变时序就可以减小或消除 AVp。 附加驱动信号线 14 中信号跳变顺序的关键位置主要集中在栅电压信号由 Vgh跳变到 Vgl的对应 过程， 也即附加驱动信号线 14上的信号由 Val跳变到 Vah的过程， 这里 Val 跳变到 Vah的时间点以及 Val到 Vah的电压差值是主要控制的参数，需要满 足：
Cgd (Vgh -Vgl) = (Vah-Val)Cad
波形示意图如图 5所示， 标示虚线圏位置即为栅电压信号 Vg跳变时产 生 AVp的关键位置， 而实线圏位置就是在附加驱动信号线 14输入对应信号 Va跳变的关键时间点。 而相对的， 在 Vgl上升到 Vgh以及 Vah下降到 Val 的过程中， 由于 TFT开关开启， 数据线 12上的电流还在持续为像素充电， 故该跃变位置虽然也会产生电荷重新分配。 但是， 由于数据线 12还在充电， 故对于最终像素电极 132 的电压的影响较小， 也不会导致液晶电压中产生 AVp等问题， 在一般的计算中不需要考虑。
进一步地，为了在减小或消除跳变电压的同时能够对像素电极进行补偿， 使得像素电极 132电压与公共电极线 10电压之间差值的绝对值在预设区间范 围内。 以本发明实施例提出的如图 2所示的像素结构为例， 这样一种像素结 构的具体工作过程如下所述。
在 TFT131开关关闭后， 如图 6所示， 栅电压为 Vgl ( TFT断开时） ， 栅电压为低电压 Vgl, 且在一个帧周期（frame period ) 内保持不变， Val为 附加驱动信号线 14拉升前电压， Vpl 为像素电极 132被拉升前电压， Va2 为附加驱动信号线 14拉升后的电压， Vp2为像素电极 132被拉升后电压， 同 样的由于电荷守恒：
(Vpl - Vgl) X Cgd + (Vpl - Va\) x Cad + (Vpl - Vcom) x (Clc + Cst)
= (Vp2 - Vgl) x Cgd + (Vp2 - Va2) x Cad + (Vp2 - Vcom) x (Clc + Cst) 所以跳变电压为：
Vp2-Vpl = (Va2-Val) x Cad/(Cgd + Cad + Clc + Cst)
在正周期中， 当选择调整附加驱动信号线 14输入的电压信号，让该信号 在合适时间段时满足 Va2-Val>0 , 则 Vp2>Vpl , 由于在正周期中， 像素电极 132的电压（ Vpixel )大于公共电极线 10的电压（ Vcom ) ,即 Vpixel > Vcom, 那么使得像素电极 132 的电压相对于公共电极线 10 的电压的差值 |Vp2-Vcom|>|Vpl-Vcom| , 这样将像素电极 132的电压从 Vpl提升到 Vp2 , 灰度值就不会由于漏电流的存在而降低， 从而液晶电压得到了保持， 在负周 期范围内， 可以采用类似的方法实现 |Vpixel-Vcom|保持不变， 只是在负周期 范围内， 由于 Vpixel 小于 Vcom , 可以选择 Va2-Val<0 , 从而实现 |Vp2-Vcom|>|Vpl-Vcom| , 这样显示灰度质量不会出现降低，从而改善了液晶 显示器的显示质量。 对于漏电流电荷的多少与灰度值的关系， 可以参考以下计算。 以正周期 为例， 由于漏电流的存在， 会导致 |Vpixel-Vcom|降低。 首先， 假定漏电流为 i, 在时间 t内的电荷流失量为 Q, 则满足以下关系 （此处 Vpl为电量流失 Q 前像素电极电压， Vgl为栅极电压， Val为信号线电压， Vp3为电量流失 Q 后的像素电极电压） ：
Figure imgf000015_0001
若时间 t后电荷流失量为 Q , 则
(Vpl - Vgl) X Cgd + (Vpl - Va\)Cad + (Vpl - Vcom) x (Clc + Cst) - Q
= (Vp3― Vgl) x Cgd + (Vp3― Va\)Cad + (Vp3― Vcom) x (Clc + Cst) 则漏电流电荷达到 Q后， 其电压为：
Vp3 = [V/7l(Cgd + Cad + Clc + Cst)-Q]/(Cgd + Cad + Clc + Cst)
即在时间 t内， 像素电极 132的电压的下降值 ( Δ Vp下降值 ) 为： Vpl - Vp3 = Q/(Cgd + Cad + Clc + Cst)
对应灰度的下降量为， （ n为 bit数） ： Vp\ - Vcom / 2" = AVpixel/ m m即为下降的灰阶值。
而当调整 Val至 Va2时， 为保持 Vpl电压在电荷 Q流出后不降低， 则 需要满足以下条件：
(Vpl - Vgl) X Cgd + (Vpl - Va\)Cad + (Vpl - Vcom) x (Clc + Cst) - Q
= (Vpl - Vgl) x Cgd + (Vpl - Va2)Cad + (Vpl - Vcom) x (Clc + Cst) 即：
Val = Val + β / Cad (5) 通过以上方法， 可见即便由于漏电流存在使得电荷 Q流失， 当通过测量 或者计算准确掌握了流失的电荷 Q,就可以通过调整 Va2与 Val依然能将像 素电极 132的电压维持在 |Vpl-Vcom|的水平， 从而保持显示效果不降低。 与 前文表述相同： 在正周期中， 由于 Vpixel大于 Vcom, 通过将 Vpixel向上拉 升来实现 |Vpixel-Vcom|不降低， 在负周期中， 由于 Vpixel小于 Vcom, 通过 将 Vpixel向下拉来实现 |Vpixel-Vcom|不降低。 通过以上方法即可实现了显示 器件显示效果的提升。 具体波形可如图 6和图 7所示。
图 6、 图 7只显示了 Va2 和 Val , 即在一个正周期或者负周期中只提升 一次像素电极 132的电压， 还可以采用多阶驱动等方式来改良像素电极 132 的电压 (如在一个帧周期内继续添加 Va3、 Va4、 Van等等)； 若 Van或 n数量 足够多， 就可以实现对于像素电极 132的电压的实时补偿， 即如图 8所示波 形。 关于 Val与 Va2之间的关系， 以图 7所示：
Va2 = Val + Q / Cad
在正周期中 Q值为正， 在负周期中 Q值为负。 即可解决像素电极 132 的电压由于漏电流的存在而导致的灰度降低的问题， 从而提升了液晶显示器 的显示品质。
需要说明的是， 以上举例说明的像素结构如图 2所示， 均是采用附加驱 动信号线 14平行于栅线 11并且与 TFT131的漏极 1311形成寄生电容的结构 进行的说明， 当采用如图 3或图 12所示的像素结构， 附加驱动信号线 14与 栅线 11平行并且与像素电极形成第二电容 22的结构时， 或采用如图 4或图 13所示， 附加驱动信号线 14与数据线 12平行的结构时， 这样的像素结构在 工作过程中， 为了减小或消除跳变电压以及解决由于漏电流引起的 I Vpixel- Vcom|降低的问题时，其相关计算公式（如上文计算结果（ 2 ) , ( 3 ) , ( 4 ) , ( 5 ) ) 中将第一电容（Cad )值换成第二电容（Cap )值即可， 驱动 信号改为与 Cap相关。 详细原理参见前述实施例， 这里不再赘述。
进一步地， 采用如图 9所示的像素结构时， 像素结构同时存在与栅线 11 平行的附加驱动信号线 41和与数据线 12平行的附加驱动信号线 42的结构 时， 同样可以减小或消除跳变电压以及解决由于漏电流引起的 I Vpixel- Vcom| 降低的问题， 从而提升了液晶显示器的显示品质。 其详细原理同样可以参见 前述实施例， 这里不再赘述。
本发明实施例提供了一种显示装置， 其包括如上所述的任意一种像素结 构， 具有与本发明前述实施例提供的像素结构相同的有益效果， 由于像素结 构在前述实施例中已经进行了详细说明， 此处不再赘述。
本发明实施例提供的一种显示装置包括像素结构。 通过在该像素结构中 添加平行于栅线和 /或数据线的附加驱动信号线， 该附加驱动信号线与 TFT 的漏极或像素电极形成电容， 并且该附加驱动信号线输入信号与栅线输入信 号的相位相反。 这样一来， 附加驱动信号线与 TFT的漏极或像素电极所形成 电容的电荷可以对寄生电容的电荷变化进行补偿， 避免了跳变电压对像素电 极电压的影响， 从而提高了显示装置的显示效果。
本发明实施例提供的像素结构驱动方法， 可以应用于前述实施例中所提 供的像素结构。 如图 2所示， 该像素结构包括： 公共电极线 10、 栅线 11和 数据线 12, 由横纵交叉的栅线 11和数据线 12界定至少一个像素单元 13,像 素单元 13又包括 TFT131和像素电极 132。 本发明实施例提供的像素结构驱 动方法可如下进行。
步骤 S101、 从栅线 11输入信号， 该信号用于逐行开启 TFT131。
步骤 S102、 从数据线 12输入信号， 该信号用于当 TFT131开启时， 通 过 TFT的漏极 1311向像素电极 132供电。
步骤 S103、从附加驱动信号线 14输入信号， 该信号与栅线 11输入信号 ^； 目 目 。
附加驱动信号线 14形成用于补偿像素结构内寄生电容电荷的附加电容。 例如， 如图 1所示， 该附加电容可以包括附加驱动信号线 14与 TFT的漏极 1311形成的第一电容， 或者， 如图 3和图 4所示， 该附加电容可以包括附加 驱动信号线 14与像素电极 132形成的第二电容 22。
本发明实施例提供的一种像素结构驱动方法。 通过在像素结构中添加平 行于栅线和 /或数据线的附加驱动信号线， 该附加驱动信号线与 TFT 的漏极 或像素电极形成电容， 并且该附加驱动信号线输入信号与栅线输入信号的相 位相反。 这样一来， 附加驱动信号线与 TFT的漏极或像素电极所形成电容的 电荷可以对寄生电容的电荷变化进行补偿， 避免了跳变电压对像素电极电压 的影响， 从而提高了显示装置的显示效果。
进一步地， 对附加驱动信号线 14输入信号的波形与栅线 11输入信号的 波形进行举例说明，如图 5所示， 附加驱动信号线 14输入信号 Va与栅线 11 输入信号 Vg的相位相反。
进一步地， 本发明实施例提供的像素结构的驱动方法还可以包括： 步骤 S104、附加驱动信号线 14输入用于补偿像素电极 132电压的信号。 这使得所述像素电极 132的电压与所述公共电极线 10输入信号的电压之间差 值的绝对值在预设区间范围内， 从而改善了液晶显示器的显示质量。
如图 6所示， 在正周期中， 由于像素电极电压（Vpixel ) 大于公共电极 电压（Vcom), 采用将附加驱动信号线输入的电压 Val向上拉升为 Va2, 相 应的像素电极电压（Vpixel )也会向上拉升， 从而实现 |Vpixel-Vcom|不降低； 在负周期， 由于像素电极电压（Vpixel )小于公共电极电压（Vcom), 采用将 附加驱动信号线输入的电压 Val下拉为 Va2, 相应的像素电极电压（Vpixel ) 也会受到下拉， 从而实现 |Vpixel-Vcom|不降低， 从而提升了液晶显示器的显 示品质。
例如， 预设区间可以是根据实际需要选取的范围。 例如， 在如图 7所示 的一个正周期内， 由于公共电极线 10输入的电压 Vcom不变，经过一次补偿 的像素电极 132的电压在 VI与 V2之间，因此像素电极 132的电压与所述公 共电极线 10输入的电压 Vcom之间差值的绝对值处在预设区间 |V1-V2|之内。
或者， 例如， 进一步地， 像素电极 132的电压（Vpixel )与公共电极线 10输入的电压 （Vcom )之间差值的绝对值 |Vpixel-Vcom|所处的预设区间还 可以是一个具体的值。如图 8所示，多次调整通过附加驱动信号线 14输入的 信号对像素电极 132的电压进行实时补偿， 使得像素电极 132的电压趋于一 个固定的数值 Vpq, 由于公共电极线 10输入的电压 Vcom不变， 因此可以保 证像素电极 132的电压 Vpixel与公共电极线 10输入的电压 Vcom之间差值 的绝对值 I Vpixel- Vcom|为 | Vpq- Vcom|。
针对跳变电压产生的原因， 以本发明实施例提出的如图 2所示的像素结 构为例， 对像素结构的驱动方法的详细说明如前所述， 这里不再重复。
进一步地， 为了对像素电极进行补偿， 使得像素电极 132电压与公共电 极线 10电压之间差值的绝对值在预设区间范围内，如图 1所示的现有像素结 构当公共电极线 10输入可变化的电压时，该现有的像素结构的驱动方法如下 所述。
当公共电极线 10输入可变化的电压时，跳变电压的计算过程同样可以根 据公式：
(Vpl - Vgl) X Cgd + (Vpl - VcomX) x (Clc + Cst)
= (Vp2 - Vgl) x Cgd + (Vp2 - Vcoml) x (Clc + Cst) 所以跳变电压为：
Vp2-Vp\ = (Vcom2-Vcoml) x (Clc + Cs)/(Cgd + Clc + Cst) ( 6 ) 在像素电极 132 的电压变化的过程中， 如在正周期中， 只需要满足 Vcom2>Vcoml ,就能实现像素电极 132电压的变化 Vp2>Vpl ,像素电极 132 的电压提升后，此时还需要满足 |Vp2-Vcom2|>|Vpl-Vcoml|就能达到防止像素 电极 132的电压降低的目的， 具体的在流失电荷 Q后， Vcoml与 Vcom2关 系为：
(Vpl - V^ X Cgd + (Vpl - Vcoml) x (Clc + Cst) - Q
= (Vp2 -Vgl) x Cgd + (Vp2 -Vcoml) x (Clc + Cst) 即：
(Vpl - Vcoml) - (Vp\ - Vcoml) = ((Vp\ - Vp2)Cgd + Q) I (Clc + Cst) ( 7 ) 如上式所示， 不管在正周期还是在负周期内， 也只需控制计算 I Vp2-Vcom21>| Vp 1 -Vcoml | , 且其计算关系满足（ 6 ) 式， 就能实现液晶电压 |Vpixel-Vcom|的维持与稳定， 从而提升了液晶显示器的显示品质。
需要说明的是，该驱动方法不仅可以应用于如图 1所示的现有像素结构， 还可以应用于本发明实施例提供的像素结构， 其计算方法同上， 此处不再赘 述。
进一步地， 为了在减小或消除跳变电压的同时能够对像素电极 132进行 补偿，使得像素电极 132的电压与公共电极线 10的电压之间差值的绝对值在 预设区间范围内， 以本发明实施例提出的如图 2所示的像素结构为例， 对该 像素结构的驱动方法的详细如前所述， 这里不再重复。
本领域普通技术人员可以理解： 实现上述方法实施例的全部或部分步骤 可以通过程序指令相关的硬件来完成， 前述的程序可以存储于一计算机可读 取存储介质中， 该程序在执行时， 执行包括上述方法实施例的步骤； 而前述 的存储介质包括： ROM、 RAM, 磁碟或者光盘等各种可以存储程序代码的 介质。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。

Claims

权利要求书
1、一种像素结构， 包括： 公共电极线、栅线、数据线、 附加驱动信号线、 由横纵交叉的栅线和数据线界定出的至少一个像素单元， 其中，
所述像素单元包括薄膜晶体管和像素电极；
所述附加驱动信号线形成补偿所述像素结构内寄生电容电荷的附加电 容；
所述附加驱动信号线的输入信号与所述栅线的输入信号的相位相反。
2、 根据权利要求 1所述的像素结构， 其中， 所述附加电容包括： 所述附加驱动信号线与所述薄膜晶体管的漏极形成的第一电容； 和 /或， 所述附加驱动信号线与所述像素电极形成的第二电容。
3、根据权利要求 1或 2所述的像素结构， 其中， 所述附加驱动信号线输 入信号用于补偿所述像素电极的电压。
4、 根据权利要求 1-3任一所述的像素结构， 其中，
所述附加驱动信号线与所述栅线平行； 和 /或，
所述附加驱动信号线与所述数据线平行。
5、根据权利要求 4所述的像素结构， 其中， 所述附加驱动信号线与所述 栅线平行包括：
所述附加驱动信号线与所述栅线为同层金属材料形成； 或
所述附加驱动信号线与所述栅线异层设置。
6、根据权利要求 5所述的像素结构， 其中， 当所述附加驱动信号线与所 述栅线异层设置时， 所述附加驱动信号线与所述薄膜晶体管的漏极以及延伸 电极形成所述第一电容， 所述延伸电极为所述薄膜晶体管的漏极沿所述驱动 信号线方向延伸的部分， 所述延伸电极与所述薄膜晶体管的漏极电连接。
7、根据权利要求 4所述的像素结构， 其中， 所述附加驱动信号线与所述 数据线平行包括：
所述附加驱动信号线与所述数据线为同层金属材料形成； 或
所述附加驱动信号线与所述数据线异层设置。
8、 根据权利要求 1-3任一所述的像素结构， 其中， 所述附加驱动信号线 包括： 第一子附加驱动信号线和第二子附加驱动信号线； 所述第一子附加驱动信号线与所述栅线或所述数据线平行， 且所述第一 子附加驱动信号线位于所述栅线或所述数据线区域之外；
所述第二子附加驱动信号线位于所述栅线或所述数据线区域内。
9、根据权利要求 1-8任一所述的像素结构，还包括至少一组平行的引线 区域， 每一组所述引线区域包括第一端口和第二端口；
所述第一端口用于引入所述附加驱动信号线输入的信号， 所述第二端口 用于引入所述栅线或所述数据线输入的信号。
10、 根据权利要求 9所述的像素结构， 还包括：
与所述第一端口电连接的第一电路区域,用于驱动所述附加驱动信号线； 与所述第二端口电连接的第二电路区域， 用于驱动所述栅线或所述数据 线。
11、 根据权利要求 1-10任一所述的像素结构， 其中， 所述附加驱动信号 线采用透明导电材料制成。
12、 一种显示装置， 包括权利要求 1-11中任一所述像素结构。
13、 一种像素结构驱动方法， 所述像素结构包括公共电极线、 栅线、 数 据线、 附加驱动信号线、 由横纵交叉的栅线和数据线界定出的至少一个像素 单元， 所述像素单元包括薄膜晶体管和像素电极， 所述方法包括：
通过所述栅线输入栅线信号， 逐行开启所述薄膜晶体管；
通过所述数据线输入数据线信号， 当所述薄膜晶体管开启时， 通过所述 薄膜晶体管的漏极向所述像素电极供电；
通过所述附加驱动信号线输入附加驱动信号， 该附加驱动信号与所述栅 线信号的相位相反；
其中， 所述附加驱动信号线形成补偿所述像素结构内寄生电容电荷的附 加电容。
14、根据权利要求 13所述的像素结构驱动方法， 其中， 所述附加电容包 括：
所述附加驱动信号线与所述薄膜晶体管的漏极形成的第一电容； 和 /或， 所述附加驱动信号线与所述像素电极形成的第二电容。
15、 根据权利要求 13所述的像素结构驱动方法， 还包括：
所述附加驱动信号补偿所述像素电极电压。
PCT/CN2013/085284 2013-05-07 2013-10-16 像素结构及其驱动方法、显示装置 WO2014180091A1 (zh)

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