WO2014176806A1 - Dispositif semi-conducteur et son procédé de fabrication - Google Patents

Dispositif semi-conducteur et son procédé de fabrication Download PDF

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Publication number
WO2014176806A1
WO2014176806A1 PCT/CN2013/076475 CN2013076475W WO2014176806A1 WO 2014176806 A1 WO2014176806 A1 WO 2014176806A1 CN 2013076475 W CN2013076475 W CN 2013076475W WO 2014176806 A1 WO2014176806 A1 WO 2014176806A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
metallic material
semiconductor device
gate
metal
Prior art date
Application number
PCT/CN2013/076475
Other languages
English (en)
Chinese (zh)
Inventor
杨红
王文武
闫江
马雪丽
Original Assignee
中国科学院微电子研究所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 中国科学院微电子研究所 filed Critical 中国科学院微电子研究所
Publication of WO2014176806A1 publication Critical patent/WO2014176806A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2

Definitions

  • the present disclosure relates to the field of semiconductors, and more particularly to a semiconductor device and a method of fabricating the same. Background technique
  • the design of the double metal gate structure is generally adopted. That is, the NMOSFET and the PMOSFET are made of a metallic material having different work functions, so that the effective work function of the metal gate electrode is close to the conduction band edge ( ⁇ 4.2 eV) and the valence band edge ( ⁇ 5.1 eV) of the silicon substrate, respectively.
  • a semiconductor device comprising: a substrate; and a gate stack formed on the substrate, the gate stack including a high-k gate dielectric layer and a gate conductor layer, wherein the gate conductor layer includes A first layer of metallic material and a second layer of metallic material and an aluminum A1 layer sandwiched therebetween or a laminate of A1 and other metals or metal compounds.
  • a method of fabricating a semiconductor device comprising: sequentially forming a high-k gate dielectric layer and a gate conductor layer on a substrate, and patterning them to form a gate stack, wherein the gate conductor
  • the layer comprises a first layer of metallic material and a second layer of metallic material and an aluminum A1 layer sandwiched between them or a laminate of A1 and other metals or metal compounds.
  • an A1 layer is inserted in a gate stack, particularly a gate conductor layer or A laminate of Al and other metals or metal compounds.
  • a gate stack particularly a gate conductor layer or A laminate of Al and other metals or metal compounds.
  • FIGS. 1-2 are schematic diagrams showing a flow of manufacturing a semiconductor device in accordance with an embodiment of the present disclosure. detailed description
  • a layer/element when a layer/element is referred to as being "on" another layer/element, the layer/element may be located directly on the other layer/element, or a central layer may be present between them. element. In addition, if a layer/element is "on” another layer/element, the layer/element may be "under” the other layer/element when the orientation is reversed.
  • a semiconductor device can include a gate stack formed on a substrate.
  • the gate stack can be a configuration of a high K gate dielectric layer/metallic gate conductor layer.
  • an aluminum (Al) layer or a stack of A1 and other metals or metal compounds is interposed in the metallic gate conductor layer to effectively adjust the effective work function of the gate stack.
  • the "effective work function" refers to a work function exhibited by the gate stack (in particular, the gate conductor layer) as a whole in electrical performance.
  • the gate conductor layer may include a first metallic material layer under the A1 layer or laminate (which may have a corresponding a work function and/or a material capable of preventing A1 from diffusing downward) and a second metallic material layer on the A1 layer or stack (may have a corresponding second work function and/or can prevent A1 from rising Diffused material).
  • metallic material means a material exhibiting the same or similar electrical properties as a metal (for example, a work function close to a metal material), such as a metal material, a nitride of some metals such as TiN, or the like.
  • the first metallic material layer and the second metallic material layer may comprise the same or different materials (and thus have the same or different work functions, and those skilled in the art may select their respective work function and/or work function combination to Expand the adjustment range of the work function).
  • the gate stack can also include other layers.
  • the gate stack can include a gate dielectric protection layer and/or an etch stop layer disposed between the high K gate dielectric layer and the gate conductor layer. This layer or layers are particularly advantageous in CMOS integrated processes.
  • a method of fabricating a semiconductor device can include sequentially forming a high K gate dielectric layer and a gate conductor layer on the substrate and patterning them to form a gate stack.
  • the gate conductor layer is, for example, a structure in which the first metal material layer and the second metal material layer are laminated with an A1 layer or a layer of A1 and another metal or metal compound.
  • the technology of the present disclosure can be applied to a gate-first process as well as a back gate process.
  • the high-k gate dielectric layer and the gate conductor layer can be directly formed on the surface of the substrate by a process such as deposition, and their patterning can be realized, for example, by lithography.
  • the high-k gate dielectric layer and the gate conductor layer may be formed on the substrate, for example, by a deposition process or the like to fill a space between the gate spacers due to the removal of the sacrificial gate stack, and their composition may pass, for example, A planarization process such as chemical mechanical polishing (CMP) is performed to remain in the space.
  • CMP chemical mechanical polishing
  • the material and/or thickness of the first metallic material layer and/or the second metallic material layer, the thickness of the A1 layer or the laminate of A1 and other metal or metal compounds, and/or may be selected. Parameters such as material and/or thickness of the other metal or metal compound to achieve adjustment of the effective work function of the gate stack. Due to various combinations of these parameters, a variety of effective work functions can be realized, and thus multi-threshold adjustment of the semiconductor device is realized.
  • the semiconductor device can be heat treated.
  • the temperature and/or time of the heat treatment can be selected based on the desired effective work function.
  • This heat treatment can be carried out at various suitable stages. For example, it may be performed after forming each layer in the gate conductor layer, or at other timings after patterning.
  • a substrate 1000 is provided.
  • the substrate 1000 may be a suitable substrate in various forms, such as a bulk semiconductor substrate such as Si, Ge, etc., a compound semiconductor substrate such as SiGe, GaAs, GaSb, AlAs, InAs, InP, GaN, SiC, InGaAs, InSb, InGaSb Etc., a semiconductor-on-insulator (SOI), etc.
  • a bulk silicon substrate and a silicon-based material will be described as an example. However, it should be noted that the present disclosure is not limited thereto.
  • a high-k gate dielectric layer 1004 On the substrate 1000, for example, by deposition, a high-k gate dielectric layer 1004, a first metallic material layer 1010, an Al layer or a laminate 1012 of A1 and other metals or metal compounds, and a second metallic material layer may be sequentially formed. 1014.
  • the high-k gate dielectric layer 1004 may include Hf0 2 or the like having a thickness of about 10-40 A; the first metallic material layer 1010 may include TiN or the like having a thickness of about 0.5-20 nm; the A1 layer or the A1 and other metals or metal compounds.
  • the thickness of the laminate 1012 may be about 0.5-20 nm, the other metal may include Ti or the like, the metal compound may include TiN, TaN, etc.; the second metallic material layer 1014 may include the first metallic material layer 1010
  • the same or different materials, such as TiN have a thickness of about 0.5-20 nm.
  • the work function of the first metallic material and/or the second metallic material itself can be close to the desired effective work function, so that the required effective work function can be achieved with a small amount of adjustment.
  • the interface layer 1002 can be formed by deposition or thermal oxidation on the surface of the substrate 1000.
  • Interfacial layer 1002 can include an oxide (e.g., silicon oxide) having a thickness of between about 5A and 2 nm.
  • a gate dielectric protection layer 1006 and/or an etch etch stop layer 1008 may also be formed.
  • the gate dielectric protection layer 1006 may include TiN having a thickness of about 0.5-5 nm; the etch stop layer 1008 may include TaN having a thickness of about 0.5-8 nm.
  • the gate dielectric protective layer 1006 and the etch stop layer 1008 are integrated in a CMOS process. Especially useful.
  • the gate dielectric protective layer 1006 can prevent the above metal/metal material from diffusing into the gate dielectric layer 1004 and thus causing problems such as a change in dielectric constant and an increase in gate leakage.
  • the etch stop layer 1008 can be used to function in etching a layer of PFET material in the NFET region in a CMOS integrated process that forms NFETs and PFETs.
  • other layers such as polysilicon or the like (not shown) may be formed over the gate conductor layer. One or more of these layers can be set as desired, as desired.
  • the above layers are patterned into a pattern corresponding to the gate stack, for example, by photolithography, and thus a gate stack is formed.
  • the gate stack can be used as a mask for halo and extension implants.
  • side walls 1016 can be formed on both sides of the gate stack.
  • the spacers 1016 can be formed by conformally depositing a layer of nitride (e.g., silicon nitride) on the substrate and selectively etching the nitride layer, such as reactive ion etching (RIE).
  • RIE reactive ion etching
  • source/drain implantation can be performed using the gate stack and spacers 1016 as a mask. Annealing can also be performed to activate the implanted ions and form source/drain regions.
  • the semiconductor device is formed as an n-type device.
  • A1 in the laminate 1012 of the A1 layer or A1 and other metals or metal compounds may diffuse toward the first metallic material layer 1010 and the second metallic material layer 1014.
  • the structure shown in Fig. 2 can also be heat treated.
  • heat treatment may be carried out at about 100 to 900 ° C for about 10 seconds to 60 minutes.
  • the specific temperature and/or specific time of the heat treatment can be selected according to the desired effective work function.
  • the material and/or thickness of the first metallic material layer and the second metallic material layer, the thickness of the A1 layer or the laminate of A1 and other metals or metal compounds, and/or the other metal or metal compound may be selected.
  • the first metallic material layer 1010 and the second metallic material layer 1014 of different materials may be selected according to different diffusion coefficients of A1 between different materials to control the diffusion direction and depth of A1.
  • first metallic material layer 1010 and/or the second metallic material layer 1014 may also be selected. It should be noted here that although the above describes an example of the gate-first process, the present disclosure is not limited to This. The techniques of the present disclosure may also be applied to a back gate process.
  • the techniques of the present disclosure are compatible with conventional CMOS processes. Therefore, effective work function adjustment of semiconductor devices (especially NMOS) can be achieved without introducing new materials and processes.
  • the work function can be adjusted simply by adjusting the material and/or thickness of each layer in the gate conductor, and/or the temperature and/or time of subsequent heat treatment.
  • the fabrication of a multi-threshold device can be achieved by the material and/or thickness of the first metallic material layer and the second metallic material layer.
  • the technique according to the present disclosure is highly scalable. For example, a more flexible work function adjustment can be achieved by inserting another metal or metal compound layer between the A1 layer and the first metallic material layer and/or the A1 layer and the second metallic material layer.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • General Physics & Mathematics (AREA)
  • Composite Materials (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Materials Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

L'invention concerne un dispositif semi-conducteur et son procédé de fabrication. Un dispositif d'exemple peut comprendre : un substrat; et un empilement de grille formé sur le substrat. L'empilement de grille comprend une couche diélectrique de grille à fort k et une couche conductrice de grille, la couche conductrice de grille comprenant une couche de premier matériau en métal et une couche de second matériau en métal ainsi qu'une couche d'aluminium (Al) ou une couche couvrante d'Al et d'autre métal ou composé de métal intercalée entre elles.
PCT/CN2013/076475 2013-05-03 2013-05-30 Dispositif semi-conducteur et son procédé de fabrication WO2014176806A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201310160772.7 2013-05-03
CN201310160772.7A CN104134691B (zh) 2013-05-03 2013-05-03 半导体器件及其制造方法

Publications (1)

Publication Number Publication Date
WO2014176806A1 true WO2014176806A1 (fr) 2014-11-06

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WO (1) WO2014176806A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106711040B (zh) * 2015-07-23 2020-11-27 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101877311A (zh) * 2010-06-30 2010-11-03 复旦大学 一种有效调节TiN金属栅功函数的方法
CN101930996A (zh) * 2009-06-18 2010-12-29 国际商业机器公司 半导体结构及其形成方法
CN102651313A (zh) * 2011-02-25 2012-08-29 中国科学院微电子研究所 Pmos器件叠层结构的制备和栅功函数调节方法
US20120223397A1 (en) * 2011-03-01 2012-09-06 Chan-Lon Yang Metal gate structure and manufacturing method thereof

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6873048B2 (en) * 2003-02-27 2005-03-29 Sharp Laboratories Of America, Inc. System and method for integrating multiple metal gates for CMOS applications
KR100662850B1 (ko) * 2006-02-02 2007-01-02 삼성전자주식회사 복수 개의 금속층을 적층한 반도체 소자
CN102237398B (zh) * 2010-04-20 2013-09-04 中国科学院微电子研究所 半导体结构及其形成方法
TW201242018A (en) * 2011-04-07 2012-10-16 United Microelectronics Corp Metal gate structure and manufacturing method thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101930996A (zh) * 2009-06-18 2010-12-29 国际商业机器公司 半导体结构及其形成方法
CN101877311A (zh) * 2010-06-30 2010-11-03 复旦大学 一种有效调节TiN金属栅功函数的方法
CN102651313A (zh) * 2011-02-25 2012-08-29 中国科学院微电子研究所 Pmos器件叠层结构的制备和栅功函数调节方法
US20120223397A1 (en) * 2011-03-01 2012-09-06 Chan-Lon Yang Metal gate structure and manufacturing method thereof

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Publication number Publication date
CN104134691A (zh) 2014-11-05
CN104134691B (zh) 2017-09-08

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